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-rw-r--r--lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp139
1 files changed, 85 insertions, 54 deletions
diff --git a/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 36200c03f703..15943ba42156 100644
--- a/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -13,6 +13,7 @@
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "Utils/RISCVBaseInfo.h"
+#include "llvm/CodeGen/Register.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
@@ -56,17 +57,6 @@ extern "C" void LLVMInitializeRISCVDisassembler() {
createRISCVDisassembler);
}
-static const unsigned GPRDecoderTable[] = {
- RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3,
- RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7,
- RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11,
- RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
- RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19,
- RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23,
- RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27,
- RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31
-};
-
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
@@ -76,38 +66,21 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
.getFeatureBits();
bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
- if (RegNo > array_lengthof(GPRDecoderTable) || (IsRV32E && RegNo > 15))
+ if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
return MCDisassembler::Fail;
- // We must define our own mapping from RegNo to register identifier.
- // Accessing index RegNo in the register class will work in the case that
- // registers were added in ascending order, but not in general.
- unsigned Reg = GPRDecoderTable[RegNo];
+ Register Reg = RISCV::X0 + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
-static const unsigned FPR32DecoderTable[] = {
- RISCV::F0_32, RISCV::F1_32, RISCV::F2_32, RISCV::F3_32,
- RISCV::F4_32, RISCV::F5_32, RISCV::F6_32, RISCV::F7_32,
- RISCV::F8_32, RISCV::F9_32, RISCV::F10_32, RISCV::F11_32,
- RISCV::F12_32, RISCV::F13_32, RISCV::F14_32, RISCV::F15_32,
- RISCV::F16_32, RISCV::F17_32, RISCV::F18_32, RISCV::F19_32,
- RISCV::F20_32, RISCV::F21_32, RISCV::F22_32, RISCV::F23_32,
- RISCV::F24_32, RISCV::F25_32, RISCV::F26_32, RISCV::F27_32,
- RISCV::F28_32, RISCV::F29_32, RISCV::F30_32, RISCV::F31_32
-};
-
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > array_lengthof(FPR32DecoderTable))
+ if (RegNo >= 32)
return MCDisassembler::Fail;
- // We must define our own mapping from RegNo to register identifier.
- // Accessing index RegNo in the register class will work in the case that
- // registers were added in ascending order, but not in general.
- unsigned Reg = FPR32DecoderTable[RegNo];
+ Register Reg = RISCV::F0_F + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -115,35 +88,21 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > 8) {
+ if (RegNo >= 8) {
return MCDisassembler::Fail;
}
- unsigned Reg = FPR32DecoderTable[RegNo + 8];
+ Register Reg = RISCV::F8_F + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
-static const unsigned FPR64DecoderTable[] = {
- RISCV::F0_64, RISCV::F1_64, RISCV::F2_64, RISCV::F3_64,
- RISCV::F4_64, RISCV::F5_64, RISCV::F6_64, RISCV::F7_64,
- RISCV::F8_64, RISCV::F9_64, RISCV::F10_64, RISCV::F11_64,
- RISCV::F12_64, RISCV::F13_64, RISCV::F14_64, RISCV::F15_64,
- RISCV::F16_64, RISCV::F17_64, RISCV::F18_64, RISCV::F19_64,
- RISCV::F20_64, RISCV::F21_64, RISCV::F22_64, RISCV::F23_64,
- RISCV::F24_64, RISCV::F25_64, RISCV::F26_64, RISCV::F27_64,
- RISCV::F28_64, RISCV::F29_64, RISCV::F30_64, RISCV::F31_64
-};
-
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > array_lengthof(FPR64DecoderTable))
+ if (RegNo >= 32)
return MCDisassembler::Fail;
- // We must define our own mapping from RegNo to register identifier.
- // Accessing index RegNo in the register class will work in the case that
- // registers were added in ascending order, but not in general.
- unsigned Reg = FPR64DecoderTable[RegNo];
+ Register Reg = RISCV::F0_D + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -151,10 +110,10 @@ static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > 8) {
+ if (RegNo >= 8) {
return MCDisassembler::Fail;
}
- unsigned Reg = FPR64DecoderTable[RegNo + 8];
+ Register Reg = RISCV::F8_D + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -182,10 +141,10 @@ static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > 8)
+ if (RegNo >= 8)
return MCDisassembler::Fail;
- unsigned Reg = GPRDecoderTable[RegNo + 8];
+ Register Reg = RISCV::X8 + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -279,8 +238,80 @@ static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
return MCDisassembler::Success;
}
+static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+
+static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+
+static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
+static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+
+static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
#include "RISCVGenDisassemblerTables.inc"
+static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ uint64_t SImm6 =
+ fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
+ DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
+ (void)Result;
+ assert(Result == MCDisassembler::Success && "Invalid immediate");
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
+ uint64_t SImm6 =
+ fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
+ DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
+ (void)Result;
+ assert(Result == MCDisassembler::Success && "Invalid immediate");
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
+ Inst.addOperand(Inst.getOperand(0));
+ uint64_t UImm6 =
+ fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
+ DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
+ (void)Result;
+ assert(Result == MCDisassembler::Success && "Invalid immediate");
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Rd = fieldFromInstruction(Insn, 7, 5);
+ unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
+ DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
+ DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ unsigned Rd = fieldFromInstruction(Insn, 7, 5);
+ unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
+ DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
+ Inst.addOperand(Inst.getOperand(0));
+ DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
+ return MCDisassembler::Success;
+}
+
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 04:50:57 +0000