diff options
Diffstat (limited to 'lib/Target/SystemZ/SystemZISelLowering.h')
| -rw-r--r-- | lib/Target/SystemZ/SystemZISelLowering.h | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/lib/Target/SystemZ/SystemZISelLowering.h b/lib/Target/SystemZ/SystemZISelLowering.h index abe8b7233e60..2cdc88db5a4d 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.h +++ b/lib/Target/SystemZ/SystemZISelLowering.h @@ -18,7 +18,7 @@ #include "SystemZ.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Target/TargetLowering.h" +#include "llvm/CodeGen/TargetLowering.h" namespace llvm { namespace SystemZISD { @@ -308,6 +308,22 @@ enum NodeType : unsigned { // Operand 5: the width of the field in bits (8 or 16) ATOMIC_CMP_SWAPW, + // Atomic compare-and-swap returning glue (condition code). + // Val, OUTCHAIN, glue = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) + ATOMIC_CMP_SWAP, + + // 128-bit atomic load. + // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr) + ATOMIC_LOAD_128, + + // 128-bit atomic store. + // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr) + ATOMIC_STORE_128, + + // 128-bit atomic compare-and-swap. + // Val, OUTCHAIN, glue = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) + ATOMIC_CMP_SWAP_128, + // Byte swapping load. // // Operand 0: the address to load from @@ -384,8 +400,8 @@ public: bool isLegalICmpImmediate(int64_t Imm) const override; bool isLegalAddImmediate(int64_t Imm) const override; bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, - unsigned AS) const override; - bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) const override; + unsigned AS, + Instruction *I = nullptr) const override; bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const override; @@ -410,6 +426,8 @@ public: switch(ConstraintCode[0]) { default: break; + case 'o': + return InlineAsm::Constraint_o; case 'Q': return InlineAsm::Constraint_Q; case 'R': @@ -448,6 +466,10 @@ public: EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; + void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, + SelectionDAG &DAG) const override; + void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, + SelectionDAG &DAG) const override; bool allowTruncateForTailCall(Type *, Type *) const override; bool mayBeEmittedAsTailCall(const CallInst *CI) const override; SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, @@ -565,6 +587,8 @@ private: MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB, unsigned StoreOpcode, unsigned STOCOpcode, bool Invert) const; + MachineBasicBlock *emitPair128(MachineInstr &MI, + MachineBasicBlock *MBB) const; MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB, bool ClearEven) const; MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI, |