diff options
Diffstat (limited to 'lib/Target/WebAssembly/WebAssemblyRegisterInfo.td')
| -rw-r--r-- | lib/Target/WebAssembly/WebAssemblyRegisterInfo.td | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td b/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td index 90888100be17..29f42b96b249 100644 --- a/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td +++ b/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// /// /// \file -/// \brief This file describes the WebAssembly register classes and some nominal +/// This file describes the WebAssembly register classes and some nominal /// physical registers. /// //===----------------------------------------------------------------------===// @@ -34,13 +34,18 @@ def SP32 : WebAssemblyReg<"%SP32">; def SP64 : WebAssemblyReg<"%SP64">; // The register allocation framework requires register classes have at least -// one register, so we define a few for the floating point register classes -// since we otherwise don't need a physical register in those classes. +// one register, so we define a few for the integer / floating point register +// classes since we otherwise don't need a physical register in those classes. +// These are also used a "types" in the generated assembly matcher. +def I32_0 : WebAssemblyReg<"%i32.0">; +def I64_0 : WebAssemblyReg<"%i64.0">; def F32_0 : WebAssemblyReg<"%f32.0">; def F64_0 : WebAssemblyReg<"%f64.0">; def V128_0: WebAssemblyReg<"%v128">; +def EXCEPT_REF_0 : WebAssemblyReg<"%except_ref.0">; + // The value stack "register". This is an opaque entity which serves to order // uses and defs that must remain in LIFO order. def VALUE_STACK : WebAssemblyReg<"STACK">; @@ -54,9 +59,10 @@ def ARGUMENTS : WebAssemblyReg<"ARGUMENTS">; // Register classes //===----------------------------------------------------------------------===// -def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>; -def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>; +def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>; +def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>; def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>; def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>; def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>; +def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>; |