diff options
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.cpp')
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 52 |
1 files changed, 41 insertions, 11 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 274b56688558..86750633aecc 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -52,7 +52,7 @@ X86RegisterInfo::X86RegisterInfo(const Triple &TT) X86_MC::getDwarfRegFlavour(TT, false), X86_MC::getDwarfRegFlavour(TT, true), (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { - X86_MC::InitLLVM2SEHRegisterMapping(this); + X86_MC::initLLVMToSEHAndCVRegMapping(this); // Cache some information. Is64Bit = TT.isArch64Bit(); @@ -162,10 +162,23 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, case 0: // Normal GPRs. if (Subtarget.isTarget64BitLP64()) return &X86::GR64RegClass; + // If the target is 64bit but we have been told to use 32bit addresses, + // we can still use 64-bit register as long as we know the high bits + // are zeros. + // Reflect that in the returned register class. + if (Is64Bit) { + // When the target also allows 64-bit frame pointer and we do have a + // frame, this is fine to use it for the address accesses as well. + const X86FrameLowering *TFI = getFrameLowering(MF); + return TFI->hasFP(MF) && TFI->Uses64BitFramePtr + ? &X86::LOW32_ADDR_ACCESS_RBPRegClass + : &X86::LOW32_ADDR_ACCESSRegClass; + } return &X86::GR32RegClass; case 1: // Normal GPRs except the stack pointer (for encoding reasons). if (Subtarget.isTarget64BitLP64()) return &X86::GR64_NOSPRegClass; + // NOSP does not contain RIP, so no special case here. return &X86::GR32_NOSPRegClass; case 2: // NOREX GPRs. if (Subtarget.isTarget64BitLP64()) @@ -174,6 +187,7 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, case 3: // NOREX GPRs except the stack pointer (for encoding reasons). if (Subtarget.isTarget64BitLP64()) return &X86::GR64_NOREX_NOSPRegClass; + // NOSP does not contain RIP, so no special case here. return &X86::GR32_NOREX_NOSPRegClass; case 4: // Available for tailcall (not callee-saved GPRs). return getGPRsForTailCall(MF); @@ -280,15 +294,19 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { return CSR_64_SaveList; case CallingConv::X86_INTR: if (Is64Bit) { + if (HasAVX512) + return CSR_64_AllRegs_AVX512_SaveList; if (HasAVX) return CSR_64_AllRegs_AVX_SaveList; - else - return CSR_64_AllRegs_SaveList; + return CSR_64_AllRegs_SaveList; } else { + if (HasAVX512) + return CSR_32_AllRegs_AVX512_SaveList; + if (HasAVX) + return CSR_32_AllRegs_AVX_SaveList; if (HasSSE) return CSR_32_AllRegs_SSE_SaveList; - else - return CSR_32_AllRegs_SaveList; + return CSR_32_AllRegs_SaveList; } default: break; @@ -299,6 +317,10 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { return CSR_Win64_SaveList; if (CallsEHReturn) return CSR_64EHRet_SaveList; + if (Subtarget.getTargetLowering()->supportSwiftError() && + MF->getFunction()->getAttributes().hasAttrSomewhere( + Attribute::SwiftError)) + return CSR_64_SwiftError_SaveList; return CSR_64_SaveList; } if (CallsEHReturn) @@ -366,18 +388,22 @@ X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF, return CSR_64_RegMask; case CallingConv::X86_INTR: if (Is64Bit) { + if (HasAVX512) + return CSR_64_AllRegs_AVX512_RegMask; if (HasAVX) return CSR_64_AllRegs_AVX_RegMask; - else - return CSR_64_AllRegs_RegMask; + return CSR_64_AllRegs_RegMask; } else { + if (HasAVX512) + return CSR_32_AllRegs_AVX512_RegMask; + if (HasAVX) + return CSR_32_AllRegs_AVX_RegMask; if (HasSSE) return CSR_32_AllRegs_SSE_RegMask; - else - return CSR_32_AllRegs_RegMask; + return CSR_32_AllRegs_RegMask; } - default: - break; + default: + break; } // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check @@ -385,6 +411,10 @@ X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF, if (Is64Bit) { if (IsWin64) return CSR_Win64_RegMask; + if (Subtarget.getTargetLowering()->supportSwiftError() && + MF.getFunction()->getAttributes().hasAttrSomewhere( + Attribute::SwiftError)) + return CSR_64_SwiftError_RegMask; return CSR_64_RegMask; } return CSR_32_RegMask; |