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path: root/lib/Target/XCore/XCoreInstrInfo.td
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Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.td')
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.td16
1 files changed, 7 insertions, 9 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index b25a08d25c1a..ae646a248524 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -741,14 +741,12 @@ let isCall=1,
// All calls clobber the link register and the non-callee-saved registers:
Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
def BL_u10 : _FU10<
- (outs),
- (ins calltarget:$target, variable_ops),
+ (outs), (ins calltarget:$target),
"bl $target",
[(XCoreBranchLink immU10:$target)]>;
def BL_lu10 : _FLU10<
- (outs),
- (ins calltarget:$target, variable_ops),
+ (outs), (ins calltarget:$target),
"bl $target",
[(XCoreBranchLink immU20:$target)]>;
}
@@ -796,7 +794,7 @@ def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
"mkmsk $dst, $size",
- [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>;
+ [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type),
"getr $dst, $type",
@@ -950,10 +948,10 @@ def ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
// dgetreg
def MSYNC_1r : _F1R<(outs), (ins GRRegs:$i),
"msync res[$i]",
- [(int_xcore_msync GRRegs:$i)]>;
+ [(int_xcore_msync GRRegs:$i)]>;
def MJOIN_1r : _F1R<(outs), (ins GRRegs:$i),
"mjoin res[$i]",
- [(int_xcore_mjoin GRRegs:$i)]>;
+ [(int_xcore_mjoin GRRegs:$i)]>;
let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
@@ -988,7 +986,7 @@ def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
let isCall=1,
// All calls clobber the link register and the non-callee-saved registers:
Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
-def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
+def BLA_1r : _F1R<(outs), (ins GRRegs:$addr),
"bla $addr",
[(XCoreBranchLink GRRegs:$addr)]>;
}
@@ -1038,7 +1036,7 @@ def GETET_0R : _F0R<(outs), (ins),
def SSYNC_0r : _F0R<(outs), (ins),
"ssync",
- [(int_xcore_ssync)]>;
+ [(int_xcore_ssync)]>;
let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
hasSideEffects = 1 in