diff options
Diffstat (limited to 'lib/Target/XCore')
35 files changed, 2253 insertions, 850 deletions
diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt index ca94f03a6496..099ad390d2a7 100644 --- a/lib/Target/XCore/CMakeLists.txt +++ b/lib/Target/XCore/CMakeLists.txt @@ -2,6 +2,7 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info) tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info) +tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel) tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv) @@ -15,6 +16,7 @@ add_llvm_target(XCoreCodeGen XCoreISelDAGToDAG.cpp XCoreISelLowering.cpp XCoreMachineFunctionInfo.cpp + XCoreMCInstLower.cpp XCoreRegisterInfo.cpp XCoreSubtarget.cpp XCoreTargetMachine.cpp @@ -24,5 +26,7 @@ add_llvm_target(XCoreCodeGen add_dependencies(LLVMXCoreCodeGen intrinsics_gen) +add_subdirectory(Disassembler) +add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) add_subdirectory(MCTargetDesc) diff --git a/lib/Target/XCore/Disassembler/CMakeLists.txt b/lib/Target/XCore/Disassembler/CMakeLists.txt new file mode 100644 index 000000000000..cdc5d993b8bf --- /dev/null +++ b/lib/Target/XCore/Disassembler/CMakeLists.txt @@ -0,0 +1,5 @@ +add_llvm_library(LLVMXCoreDisassembler + XCoreDisassembler.cpp + ) + +add_dependencies(LLVMXCoreDisassembler XCoreCommonTableGen) diff --git a/lib/Target/XCore/Disassembler/LLVMBuild.txt b/lib/Target/XCore/Disassembler/LLVMBuild.txt new file mode 100644 index 000000000000..028de2cb3433 --- /dev/null +++ b/lib/Target/XCore/Disassembler/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/XCore/Disassembler/LLVMBuild.txt ------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = XCoreDisassembler +parent = XCore +required_libraries = MC Support XCoreInfo +add_to_library_groups = XCore diff --git a/lib/Target/XCore/Disassembler/Makefile b/lib/Target/XCore/Disassembler/Makefile new file mode 100644 index 000000000000..4caffdd1da6a --- /dev/null +++ b/lib/Target/XCore/Disassembler/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/XCore/Disassembler/Makefile --------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMXCoreDisassembler + +# Hack: we need to include 'main' XCore target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp new file mode 100644 index 000000000000..7b99967c4f32 --- /dev/null +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -0,0 +1,800 @@ +//===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief This file is part of the XCore Disassembler. +/// +//===----------------------------------------------------------------------===// + +#include "XCore.h" +#include "XCoreRegisterInfo.h" +#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +typedef MCDisassembler::DecodeStatus DecodeStatus; + +namespace { + +/// \brief A disassembler class for XCore. +class XCoreDisassembler : public MCDisassembler { + const MCRegisterInfo *RegInfo; +public: + XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) : + MCDisassembler(STI), RegInfo(Info) {} + + /// \brief See MCDisassembler. + virtual DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const; + + const MCRegisterInfo *getRegInfo() const { return RegInfo; } +}; +} + +static bool readInstruction16(const MemoryObject ®ion, + uint64_t address, + uint64_t &size, + uint16_t &insn) { + uint8_t Bytes[4]; + + // We want to read exactly 2 Bytes of data. + if (region.readBytes(address, 2, Bytes, NULL) == -1) { + size = 0; + return false; + } + // Encoded as a little-endian 16-bit word in the stream. + insn = (Bytes[0] << 0) | (Bytes[1] << 8); + return true; +} + +static bool readInstruction32(const MemoryObject ®ion, + uint64_t address, + uint64_t &size, + uint32_t &insn) { + uint8_t Bytes[4]; + + // We want to read exactly 4 Bytes of data. + if (region.readBytes(address, 4, Bytes, NULL) == -1) { + size = 0; + return false; + } + // Encoded as a little-endian 32-bit word in the stream. + insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | + (Bytes[3] << 24); + return true; +} + +static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { + const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D); + return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); +} + +static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); + +static DecodeStatus Decode2RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode2RImmInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeR2RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRUSInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL2RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode3RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode3RImmInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode2RUSInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL3RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL6RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL5RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +#include "XCoreGenDisassemblerTables.inc" + +static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 11) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); + Inst.addOperand(MCOperand::CreateReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 15) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); + Inst.addOperand(MCOperand::CreateReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + if (Val > 11) + return MCDisassembler::Fail; + static unsigned Values[] = { + 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 + }; + Inst.addOperand(MCOperand::CreateImm(Values[Val])); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::CreateImm(0)); + return MCDisassembler::Success; +} + +static DecodeStatus +Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { + unsigned Combined = fieldFromInstruction(Insn, 6, 5); + if (Combined < 27) + return MCDisassembler::Fail; + if (fieldFromInstruction(Insn, 5, 1)) { + if (Combined == 31) + return MCDisassembler::Fail; + Combined += 5; + } + Combined -= 27; + unsigned Op1High = Combined % 3; + unsigned Op2High = Combined / 3; + Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); + Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); + return MCDisassembler::Success; +} + +static DecodeStatus +Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, + unsigned &Op3) { + unsigned Combined = fieldFromInstruction(Insn, 6, 5); + if (Combined >= 27) + return MCDisassembler::Fail; + + unsigned Op1High = Combined % 3; + unsigned Op2High = (Combined / 3) % 3; + unsigned Op3High = Combined / 9; + Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); + Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); + Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); + return MCDisassembler::Success; +} + +static DecodeStatus +Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + // Try and decode as a 3R instruction. + unsigned Opcode = fieldFromInstruction(Insn, 11, 5); + switch (Opcode) { + case 0x0: + Inst.setOpcode(XCore::STW_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x1: + Inst.setOpcode(XCore::LDW_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x2: + Inst.setOpcode(XCore::ADD_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x3: + Inst.setOpcode(XCore::SUB_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x4: + Inst.setOpcode(XCore::SHL_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x5: + Inst.setOpcode(XCore::SHR_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x6: + Inst.setOpcode(XCore::EQ_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x7: + Inst.setOpcode(XCore::AND_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x8: + Inst.setOpcode(XCore::OR_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x9: + Inst.setOpcode(XCore::LDW_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x10: + Inst.setOpcode(XCore::LD16S_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x11: + Inst.setOpcode(XCore::LD8U_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x12: + Inst.setOpcode(XCore::ADD_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x13: + Inst.setOpcode(XCore::SUB_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x14: + Inst.setOpcode(XCore::SHL_2rus); + return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x15: + Inst.setOpcode(XCore::SHR_2rus); + return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x16: + Inst.setOpcode(XCore::EQ_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x17: + Inst.setOpcode(XCore::TSETR_3r); + return Decode3RImmInstruction(Inst, Insn, Address, Decoder); + case 0x18: + Inst.setOpcode(XCore::LSS_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x19: + Inst.setOpcode(XCore::LSU_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + } + return MCDisassembler::Fail; +} + +static DecodeStatus +Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S != MCDisassembler::Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus +Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S != MCDisassembler::Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + Inst.addOperand(MCOperand::CreateImm(Op1)); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus +DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); + if (S != MCDisassembler::Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus +Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S != MCDisassembler::Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus +DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S != MCDisassembler::Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + Inst.addOperand(MCOperand::CreateImm(Op2)); + return S; +} + +static DecodeStatus +DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S != MCDisassembler::Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus +DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S != MCDisassembler::Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus +DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + // Try and decode as a L3R / L2RUS instruction. + unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | + fieldFromInstruction(Insn, 27, 5) << 4; + switch (Opcode) { + case 0x0c: + Inst.setOpcode(XCore::STW_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x1c: + Inst.setOpcode(XCore::XOR_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x2c: + Inst.setOpcode(XCore::ASHR_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x3c: + Inst.setOpcode(XCore::LDAWF_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x4c: + Inst.setOpcode(XCore::LDAWB_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x5c: + Inst.setOpcode(XCore::LDA16F_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x6c: + Inst.setOpcode(XCore::LDA16B_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x7c: + Inst.setOpcode(XCore::MUL_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x8c: + Inst.setOpcode(XCore::DIVS_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x9c: + Inst.setOpcode(XCore::DIVU_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x10c: + Inst.setOpcode(XCore::ST16_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x11c: + Inst.setOpcode(XCore::ST8_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x12c: + Inst.setOpcode(XCore::ASHR_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12d: + Inst.setOpcode(XCore::OUTPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12e: + Inst.setOpcode(XCore::INPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x13c: + Inst.setOpcode(XCore::LDAWF_l2rus); + return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x14c: + Inst.setOpcode(XCore::LDAWB_l2rus); + return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x15c: + Inst.setOpcode(XCore::CRC_l3r); + return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); + case 0x18c: + Inst.setOpcode(XCore::REMS_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x19c: + Inst.setOpcode(XCore::REMU_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + } + return MCDisassembler::Fail; +} + +static DecodeStatus +DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), + Op1, Op2); + if (S != MCDisassembler::Success) + return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus +DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), + Op1, Op2); + if (S != MCDisassembler::Success) + return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + return S; +} + +static DecodeStatus +Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus +Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + Inst.addOperand(MCOperand::CreateImm(Op1)); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus +Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + Inst.addOperand(MCOperand::CreateImm(Op3)); + } + return S; +} + +static DecodeStatus +Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeBitpOperand(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + Inst.addOperand(MCOperand::CreateImm(Op3)); + } + return S; +} + +static DecodeStatus +DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeBitpOperand(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3, Op4, Op5, Op6; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S != MCDisassembler::Success) + return S; + S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); + if (S != MCDisassembler::Success) + return S; + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); + return S; +} + +static DecodeStatus +DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + // Try and decode as a L6R instruction. + Inst.clear(); + unsigned Opcode = fieldFromInstruction(Insn, 27, 5); + switch (Opcode) { + case 0x00: + Inst.setOpcode(XCore::LMUL_l6r); + return DecodeL6RInstruction(Inst, Insn, Address, Decoder); + } + return MCDisassembler::Fail; +} + +static DecodeStatus +DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3, Op4, Op5; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S != MCDisassembler::Success) + return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); + S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); + if (S != MCDisassembler::Success) + return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + return S; +} + +static DecodeStatus +DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + unsigned Op4 = fieldFromInstruction(Insn, 16, 4); + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + } + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3; + unsigned Op4 = fieldFromInstruction(Insn, 16, 4); + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + } + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +MCDisassembler::DecodeStatus +XCoreDisassembler::getInstruction(MCInst &instr, + uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &vStream, + raw_ostream &cStream) const { + uint16_t insn16; + + if (!readInstruction16(Region, Address, Size, insn16)) { + return Fail; + } + + // Calling the auto-generated decoder function. + DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16, + Address, this, STI); + if (Result != Fail) { + Size = 2; + return Result; + } + + uint32_t insn32; + + if (!readInstruction32(Region, Address, Size, insn32)) { + return Fail; + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI); + if (Result != Fail) { + Size = 4; + return Result; + } + + return Fail; +} + +namespace llvm { + extern Target TheXCoreTarget; +} + +static MCDisassembler *createXCoreDisassembler(const Target &T, + const MCSubtargetInfo &STI) { + return new XCoreDisassembler(STI, T.createMCRegInfo("")); +} + +extern "C" void LLVMInitializeXCoreDisassembler() { + // Register the disassembler. + TargetRegistry::RegisterMCDisassembler(TheXCoreTarget, + createXCoreDisassembler); +} diff --git a/lib/Target/XCore/InstPrinter/CMakeLists.txt b/lib/Target/XCore/InstPrinter/CMakeLists.txt new file mode 100644 index 000000000000..930e733cd7f1 --- /dev/null +++ b/lib/Target/XCore/InstPrinter/CMakeLists.txt @@ -0,0 +1,7 @@ +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) + +add_llvm_library(LLVMXCoreAsmPrinter + XCoreInstPrinter.cpp + ) + +add_dependencies(LLVMXCoreAsmPrinter XCoreCommonTableGen) diff --git a/lib/Target/XCore/InstPrinter/LLVMBuild.txt b/lib/Target/XCore/InstPrinter/LLVMBuild.txt new file mode 100644 index 000000000000..8750bc7acedc --- /dev/null +++ b/lib/Target/XCore/InstPrinter/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/XCore/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = XCoreAsmPrinter +parent = XCore +required_libraries = MC Support +add_to_library_groups = XCore diff --git a/lib/Target/XCore/InstPrinter/Makefile b/lib/Target/XCore/InstPrinter/Makefile new file mode 100644 index 000000000000..1c1c61299c39 --- /dev/null +++ b/lib/Target/XCore/InstPrinter/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/XCore/AsmPrinter/Makefile ----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMXCoreAsmPrinter + +# Hack: we need to include 'main' xcore target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/XCore/InstPrinter/XCoreInstPrinter.cpp b/lib/Target/XCore/InstPrinter/XCoreInstPrinter.cpp new file mode 100644 index 000000000000..1592351c3861 --- /dev/null +++ b/lib/Target/XCore/InstPrinter/XCoreInstPrinter.cpp @@ -0,0 +1,97 @@ +//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax ----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an XCore MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "asm-printer" +#include "XCoreInstPrinter.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +#include "XCoreGenAsmWriter.inc" + +void XCoreInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << StringRef(getRegisterName(RegNo)).lower(); +} + +void XCoreInstPrinter::printInst(const MCInst *MI, raw_ostream &O, + StringRef Annot) { + printInstruction(MI, O); + printAnnotation(O, Annot); +} + +void XCoreInstPrinter:: +printInlineJT(const MCInst *MI, int opNum, raw_ostream &O) { + report_fatal_error("can't handle InlineJT"); +} + +void XCoreInstPrinter:: +printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O) { + report_fatal_error("can't handle InlineJT32"); +} + +static void printExpr(const MCExpr *Expr, raw_ostream &OS) { + int Offset = 0; + const MCSymbolRefExpr *SRE; + + if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) { + SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS()); + const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(BE->getRHS()); + assert(SRE && CE && "Binary expression must be sym+const."); + Offset = CE->getValue(); + } else { + SRE = dyn_cast<MCSymbolRefExpr>(Expr); + assert(SRE && "Unexpected MCExpr type."); + } + assert(SRE->getKind() == MCSymbolRefExpr::VK_None); + + OS << SRE->getSymbol(); + + if (Offset) { + if (Offset > 0) + OS << '+'; + OS << Offset; + } +} + +void XCoreInstPrinter:: +printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isReg()) { + printRegName(O, Op.getReg()); + return; + } + + if (Op.isImm()) { + O << Op.getImm(); + return; + } + + assert(Op.isExpr() && "unknown operand kind in printOperand"); + printExpr(Op.getExpr(), O); +} + +void XCoreInstPrinter:: +printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) { + printOperand(MI, opNum, O); + + if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0) + return; + + O << "+"; + printOperand(MI, opNum+1, O); +} diff --git a/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h b/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h new file mode 100644 index 000000000000..772c515b5c9e --- /dev/null +++ b/lib/Target/XCore/InstPrinter/XCoreInstPrinter.h @@ -0,0 +1,44 @@ +//== XCoreInstPrinter.h - Convert XCore MCInst to assembly syntax -*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief This file contains the declaration of the XCoreInstPrinter class, +/// which is used to print XCore MCInst to a .s file. +/// +//===----------------------------------------------------------------------===// + +#ifndef XCOREINSTPRINTER_H +#define XCOREINSTPRINTER_H +#include "llvm/MC/MCInstPrinter.h" + +namespace llvm { + +class TargetMachine; + +class XCoreInstPrinter : public MCInstPrinter { +public: + XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, + const MCRegisterInfo &MRI) + : MCInstPrinter(MAI, MII, MRI) {} + + // Autogenerated by tblgen. + void printInstruction(const MCInst *MI, raw_ostream &O); + static const char *getRegisterName(unsigned RegNo); + + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; + virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); +private: + void printInlineJT(const MCInst *MI, int opNum, raw_ostream &O); + void printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O); + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); +}; +} // end namespace llvm + +#endif diff --git a/lib/Target/XCore/LLVMBuild.txt b/lib/Target/XCore/LLVMBuild.txt index 53b4a9e3f5f7..59e64ad0855c 100644 --- a/lib/Target/XCore/LLVMBuild.txt +++ b/lib/Target/XCore/LLVMBuild.txt @@ -16,13 +16,14 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = MCTargetDesc TargetInfo +subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo [component_0] type = TargetGroup name = XCore parent = Target has_asmprinter = 1 +has_disassembler = 1 [component_1] type = Library diff --git a/lib/Target/XCore/MCTargetDesc/LLVMBuild.txt b/lib/Target/XCore/MCTargetDesc/LLVMBuild.txt index a80c939b4372..8213f9e42883 100644 --- a/lib/Target/XCore/MCTargetDesc/LLVMBuild.txt +++ b/lib/Target/XCore/MCTargetDesc/LLVMBuild.txt @@ -19,5 +19,5 @@ type = Library name = XCoreDesc parent = XCore -required_libraries = MC XCoreInfo +required_libraries = MC XCoreAsmPrinter XCoreInfo add_to_library_groups = XCore diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index bbfdd4356f2a..b5b072dcbda6 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "XCoreMCTargetDesc.h" +#include "InstPrinter/XCoreInstPrinter.h" #include "XCoreMCAsmInfo.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" @@ -69,6 +70,15 @@ static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, return X; } +static MCInstPrinter *createXCoreMCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI, + const MCInstrInfo &MII, + const MCRegisterInfo &MRI, + const MCSubtargetInfo &STI) { + return new XCoreInstPrinter(MAI, MII, MRI); +} + // Force static initialization. extern "C" void LLVMInitializeXCoreTargetMC() { // Register the MC asm info. @@ -87,4 +97,8 @@ extern "C" void LLVMInitializeXCoreTargetMC() { // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget, createXCoreMCSubtargetInfo); + + // Register the MCInstPrinter + TargetRegistry::RegisterMCInstPrinter(TheXCoreTarget, + createXCoreMCInstPrinter); } diff --git a/lib/Target/XCore/Makefile b/lib/Target/XCore/Makefile index b823c4ed37e9..92ddc8860876 100644 --- a/lib/Target/XCore/Makefile +++ b/lib/Target/XCore/Makefile @@ -14,10 +14,10 @@ TARGET = XCore # Make sure that tblgen is run, first thing. BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \ XCoreGenAsmWriter.inc \ - XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ - XCoreGenSubtargetInfo.inc + XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ + XCoreGenDisassemblerTables.inc XCoreGenSubtargetInfo.inc -DIRS = TargetInfo MCTargetDesc +DIRS = Disassembler InstPrinter TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp b/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp index 9a0971d1e45f..00e34e04fbe5 100644 --- a/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp +++ b/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// #include "XCore.h" -#include "llvm/Module.h" +#include "llvm/IR/Module.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; diff --git a/lib/Target/XCore/XCore.td b/lib/Target/XCore/XCore.td index 04a1dd5e95be..e9a6d88fd68e 100644 --- a/lib/Target/XCore/XCore.td +++ b/lib/Target/XCore/XCore.td @@ -41,7 +41,13 @@ def : Proc<"xs1b-generic", []>; // Declare the target which we are implementing //===----------------------------------------------------------------------===// +def XCoreAsmWriter : AsmWriter { + string AsmWriterClassName = "InstPrinter"; + bit isMCAsmWriter = 1; +} + def XCore : Target { // Pull in Instruction Info: let InstructionSet = XCoreInstrInfo; + let AssemblyWriters = [XCoreAsmWriter]; } diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp index caae56227214..0d146ba4d98d 100644 --- a/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -14,31 +14,34 @@ #define DEBUG_TYPE "asm-printer" #include "XCore.h" +#include "InstPrinter/XCoreInstPrinter.h" #include "XCoreInstrInfo.h" +#include "XCoreMCInstLower.h" #include "XCoreSubtarget.h" #include "XCoreTargetMachine.h" -#include "llvm/Constants.h" -#include "llvm/DebugInfo.h" -#include "llvm/DerivedTypes.h" -#include "llvm/Module.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/DebugInfo.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Module.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCInst.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/Target/Mangler.h" -#include "llvm/DataLayout.h" -#include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/ADT/SmallString.h" -#include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/Mangler.h" +#include "llvm/Target/TargetLoweringObjectFile.h" #include <algorithm> #include <cctype> using namespace llvm; @@ -52,16 +55,17 @@ static cl::opt<unsigned> MaxThreads("xcore-max-threads", cl::Optional, namespace { class XCoreAsmPrinter : public AsmPrinter { const XCoreSubtarget &Subtarget; + XCoreMCInstLower MCInstLowering; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); public: explicit XCoreAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) - : AsmPrinter(TM, Streamer), Subtarget(TM.getSubtarget<XCoreSubtarget>()){} + : AsmPrinter(TM, Streamer), Subtarget(TM.getSubtarget<XCoreSubtarget>()), + MCInstLowering(*this) {} virtual const char *getPassName() const { return "XCore Assembly Printer"; } - void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, const std::string &directive = ".jmptable"); void printInlineJT32(const MachineInstr *MI, int opNum, raw_ostream &O) { @@ -75,18 +79,14 @@ namespace { void emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV); virtual void EmitGlobalVariable(const GlobalVariable *GV); - void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd. - static const char *getRegisterName(unsigned RegNo); - void EmitFunctionEntryLabel(); void EmitInstruction(const MachineInstr *MI); + void EmitFunctionBodyStart(); void EmitFunctionBodyEnd(); virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const; }; } // end of anonymous namespace -#include "XCoreGenAsmWriter.inc" - void XCoreAsmPrinter::emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV) { assert(((GV->hasExternalLinkage() || GV->hasWeakLinkage()) || @@ -171,12 +171,16 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { // The ABI requires that unsigned scalar types smaller than 32 bits // are padded to 32 bits. if (Size < 4) - OutStreamer.EmitZeros(4 - Size, 0); + OutStreamer.EmitZeros(4 - Size); // Mark the end of the global OutStreamer.EmitRawText("\t.cc_bottom " + Twine(GVSym->getName()) + ".data"); } +void XCoreAsmPrinter::EmitFunctionBodyStart() { + MCInstLowering.Initialize(Mang, &MF->getContext()); +} + /// EmitFunctionBodyEnd - Targets can override this to emit stuff after /// the last basic block in the function. void XCoreAsmPrinter::EmitFunctionBodyEnd() { @@ -192,17 +196,6 @@ void XCoreAsmPrinter::EmitFunctionEntryLabel() { OutStreamer.EmitLabel(CurrentFnSym); } -void XCoreAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, - raw_ostream &O) { - printOperand(MI, opNum, O); - - if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0) - return; - - O << "+"; - printOperand(MI, opNum+1, O); -} - void XCoreAsmPrinter:: printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, const std::string &directive) { @@ -225,7 +218,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum, const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: - O << getRegisterName(MO.getReg()); + O << XCoreInstPrinter::getRegisterName(MO.getReg()); break; case MachineOperand::MO_Immediate: O << MO.getImm(); @@ -270,7 +263,7 @@ bool XCoreAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O); } -printOperand(MI, OpNo, O); + printOperand(MI, OpNo, O); return false; } @@ -317,15 +310,30 @@ void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case XCore::ADD_2rus: if (MI->getOperand(2).getImm() == 0) { - O << "\tmov " << getRegisterName(MI->getOperand(0).getReg()) << ", " - << getRegisterName(MI->getOperand(1).getReg()); + O << "\tmov " + << XCoreInstPrinter::getRegisterName(MI->getOperand(0).getReg()) << ", " + << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg()); OutStreamer.EmitRawText(O.str()); return; } break; + case XCore::BR_JT: + case XCore::BR_JT32: + O << "\tbru " + << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg()) << '\n'; + if (MI->getOpcode() == XCore::BR_JT) + printInlineJT(MI, 0, O); + else + printInlineJT32(MI, 0, O); + O << '\n'; + OutStreamer.EmitRawText(O.str()); + return; } - printInstruction(MI, O); - OutStreamer.EmitRawText(O.str()); + + MCInst TmpInst; + MCInstLowering.Lower(MI, TmpInst); + + OutStreamer.EmitInstruction(TmpInst); } // Force static initialization. diff --git a/lib/Target/XCore/XCoreFrameLowering.cpp b/lib/Target/XCore/XCoreFrameLowering.cpp index e18d97384d3d..beeb07f831c6 100644 --- a/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/lib/Target/XCore/XCoreFrameLowering.cpp @@ -16,16 +16,16 @@ #include "XCore.h" #include "XCoreInstrInfo.h" #include "XCoreMachineFunctionInfo.h" -#include "llvm/Function.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/DataLayout.h" -#include "llvm/Target/TargetOptions.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/Function.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetOptions.h" using namespace llvm; @@ -98,13 +98,10 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); bool FP = hasFP(MF); - const AttrListPtr &PAL = MF.getFunction()->getAttributes(); + const AttributeSet &PAL = MF.getFunction()->getAttributes(); - for (unsigned I = 0, E = PAL.getNumAttrs(); I != E; ++I) - if (PAL.getAttributesAtIndex(I).hasAttribute(Attributes::Nest)) { - loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); - break; - } + if (PAL.hasAttrSomewhere(Attribute::Nest)) + loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); // Work out frame sizes. int FrameSize = MFI->getStackSize(); @@ -264,7 +261,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); MBB.erase(MBBI); } else { - int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; + int Opcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize); } } @@ -335,6 +332,58 @@ bool XCoreFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, return true; } +// This function eliminates ADJCALLSTACKDOWN, +// ADJCALLSTACKUP pseudo instructions +void XCoreFrameLowering:: +eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + const XCoreInstrInfo &TII = + *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo()); + if (!hasReservedCallFrame(MF)) { + // Turn the adjcallstackdown instruction into 'extsp <amt>' and the + // adjcallstackup instruction into 'ldaw sp, sp[<amt>]' + MachineInstr *Old = I; + uint64_t Amount = Old->getOperand(0).getImm(); + if (Amount != 0) { + // We need to keep the stack aligned properly. To do this, we round the + // amount of space needed for the outgoing arguments up to the next + // alignment boundary. + unsigned Align = getStackAlignment(); + Amount = (Amount+Align-1)/Align*Align; + + assert(Amount%4 == 0); + Amount /= 4; + + bool isU6 = isImmU6(Amount); + if (!isU6 && !isImmU16(Amount)) { + // FIX could emit multiple instructions in this case. +#ifndef NDEBUG + errs() << "eliminateCallFramePseudoInstr size too big: " + << Amount << "\n"; +#endif + llvm_unreachable(0); + } + + MachineInstr *New; + if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) { + int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode)) + .addImm(Amount); + } else { + assert(Old->getOpcode() == XCore::ADJCALLSTACKUP); + int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP) + .addImm(Amount); + } + + // Replace the pseudo instruction with a new instruction... + MBB.insert(I, New); + } + } + + MBB.erase(I); +} + void XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { @@ -360,7 +409,7 @@ XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, } if (RegInfo->requiresRegisterScavenging(MF)) { // Reserve a slot close to SP or frame pointer. - RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), + RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false)); } diff --git a/lib/Target/XCore/XCoreFrameLowering.h b/lib/Target/XCore/XCoreFrameLowering.h index db1bbb60d968..ebad62f2fa53 100644 --- a/lib/Target/XCore/XCoreFrameLowering.h +++ b/lib/Target/XCore/XCoreFrameLowering.h @@ -39,6 +39,10 @@ namespace llvm { const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; + bool hasFP(const MachineFunction &MF) const; void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 7564fbad7d45..fbf86c523054 100644 --- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -13,23 +13,23 @@ #include "XCore.h" #include "XCoreTargetMachine.h" -#include "llvm/DerivedTypes.h" -#include "llvm/Function.h" -#include "llvm/Intrinsics.h" -#include "llvm/CallingConv.h" -#include "llvm/Constants.h" -#include "llvm/LLVMContext.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/Target/TargetLowering.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Intrinsics.h" +#include "llvm/IR/LLVMContext.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetLowering.h" using namespace llvm; /// XCoreDAGToDAGISel - XCore specific code to select XCore machine @@ -211,15 +211,10 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) { return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, Ops, 4); } - case ISD::INTRINSIC_WO_CHAIN: { - unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); - switch (IntNo) { - case Intrinsic::xcore_crc8: - SDValue Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3) }; - return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, - Ops, 3); - } - break; + case XCoreISD::CRC8: { + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; + return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, + Ops, 3); } case ISD::BRIND: if (SDNode *ResNode = SelectBRIND(N)) diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 9e7816e21f80..a5d2be88db7d 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -14,17 +14,11 @@ #define DEBUG_TYPE "xcore-lower" #include "XCoreISelLowering.h" -#include "XCoreMachineFunctionInfo.h" #include "XCore.h" -#include "XCoreTargetObjectFile.h" -#include "XCoreTargetMachine.h" +#include "XCoreMachineFunctionInfo.h" #include "XCoreSubtarget.h" -#include "llvm/DerivedTypes.h" -#include "llvm/Function.h" -#include "llvm/Intrinsics.h" -#include "llvm/CallingConv.h" -#include "llvm/GlobalVariable.h" -#include "llvm/GlobalAlias.h" +#include "XCoreTargetMachine.h" +#include "XCoreTargetObjectFile.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -33,6 +27,12 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/ValueTypes.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/GlobalAlias.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Intrinsics.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -54,6 +54,7 @@ getTargetNodeName(unsigned Opcode) const case XCoreISD::LMUL : return "XCoreISD::LMUL"; case XCoreISD::MACCU : return "XCoreISD::MACCU"; case XCoreISD::MACCS : return "XCoreISD::MACCS"; + case XCoreISD::CRC8 : return "XCoreISD::CRC8"; case XCoreISD::BR_JT : return "XCoreISD::BR_JT"; case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32"; default : return NULL; @@ -83,7 +84,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? // XCore does not have the NodeTypes below. - setOperationAction(ISD::BR_CC, MVT::Other, Expand); + setOperationAction(ISD::BR_CC, MVT::i32, Expand); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); setOperationAction(ISD::ADDC, MVT::i32, Expand); setOperationAction(ISD::ADDE, MVT::i32, Expand); @@ -152,9 +153,12 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); - maxStoresPerMemset = maxStoresPerMemsetOptSize = 4; - maxStoresPerMemmove = maxStoresPerMemmoveOptSize - = maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 2; + // We want to custom lower some of our intrinsics. + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + + MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4; + MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize + = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2; // We have target-specific dag combine patterns for the following nodes: setTargetDAGCombine(ISD::STORE); @@ -167,24 +171,25 @@ SDValue XCoreTargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { - case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); - case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); - case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); - case ISD::ConstantPool: return LowerConstantPool(Op, DAG); - case ISD::BR_JT: return LowerBR_JT(Op, DAG); - case ISD::LOAD: return LowerLOAD(Op, DAG); - case ISD::STORE: return LowerSTORE(Op, DAG); - case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); - case ISD::VAARG: return LowerVAARG(Op, DAG); - case ISD::VASTART: return LowerVASTART(Op, DAG); - case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG); - case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG); + case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); + case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); + case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); + case ISD::ConstantPool: return LowerConstantPool(Op, DAG); + case ISD::BR_JT: return LowerBR_JT(Op, DAG); + case ISD::LOAD: return LowerLOAD(Op, DAG); + case ISD::STORE: return LowerSTORE(Op, DAG); + case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); + case ISD::VAARG: return LowerVAARG(Op, DAG); + case ISD::VASTART: return LowerVASTART(Op, DAG); + case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG); + case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG); // FIXME: Remove these when LegalizeDAGTypes lands. case ISD::ADD: - case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); - case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); - case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); - case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); + case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); + case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); + case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); + case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); + case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); default: llvm_unreachable("unimplemented operand"); } @@ -225,20 +230,16 @@ getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, { // FIXME there is no actual debug info here DebugLoc dl = GA.getDebugLoc(); - if (isa<Function>(GV)) { - return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); + const GlobalValue *UnderlyingGV = GV; + // If GV is an alias then use the aliasee to determine the wrapper type + if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) + UnderlyingGV = GA->resolveAliasedGlobal(); + if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(UnderlyingGV)) { + if (GVar->isConstant()) + return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); + return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); } - const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); - if (!GVar) { - // If GV is an alias then use the aliasee to determine constness - if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) - GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); - } - bool isConst = GVar && GVar->isConstant(); - if (isConst) { - return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); - } - return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); + return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); } SDValue XCoreTargetLowering:: @@ -740,13 +741,13 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : XCoreISD::LSUB; SDValue Zero = DAG.getConstant(0, MVT::i32); - SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), - LHSL, RHSL, Zero); - SDValue Lo(Carry.getNode(), 1); + SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), + LHSL, RHSL, Zero); + SDValue Carry(Lo.getNode(), 1); - SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), - LHSH, RHSH, Carry); - SDValue Hi(Ignored.getNode(), 1); + SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), + LHSH, RHSH, Carry); + SDValue Ignored(Hi.getNode(), 1); // Merge the pieces return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); } @@ -862,6 +863,23 @@ LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5); } +SDValue XCoreTargetLowering:: +LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + DebugLoc DL = Op.getDebugLoc(); + unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); + switch (IntNo) { + case Intrinsic::xcore_crc8: + EVT VT = Op.getValueType(); + SDValue Data = + DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), + Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); + SDValue Crc(Data.getNode(), 1); + SDValue Results[] = { Crc, Data }; + return DAG.getMergeValues(Results, 2, DL); + } + return SDValue(); +} + //===----------------------------------------------------------------------===// // Calling Convention Implementation //===----------------------------------------------------------------------===// @@ -1231,15 +1249,11 @@ XCoreTargetLowering::LowerReturn(SDValue Chain, // Analyze return values. CCInfo.AnalyzeReturn(Outs, RetCC_XCore); - // If this is the first return lowered for this function, add - // the regs to the liveout set for the function. - if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { - for (unsigned i = 0; i != RVLocs.size(); ++i) - if (RVLocs[i].isRegLoc()) - DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); - } - SDValue Flag; + SmallVector<SDValue, 4> RetOps(1, Chain); + + // Return on XCore is always a "retsp 0" + RetOps.push_back(DAG.getConstant(0, MVT::i32)); // Copy the result values into the output registers. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -1252,15 +1266,17 @@ XCoreTargetLowering::LowerReturn(SDValue Chain, // guarantee that all emitted copies are // stuck together, avoiding something bad Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); } - // Return on XCore is always a "retsp 0" + RetOps[0] = Chain; // Update chain. + + // Add the flag if we have it. if (Flag.getNode()) - return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, - Chain, DAG.getConstant(0, MVT::i32), Flag); - else // Return Void - return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, - Chain, DAG.getConstant(0, MVT::i32)); + RetOps.push_back(Flag); + + return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, + &RetOps[0], RetOps.size()); } //===----------------------------------------------------------------------===// @@ -1357,13 +1373,13 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, SDValue Carry = DAG.getConstant(0, VT); SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, DAG.getConstant(1, VT)); - SDValue Ops [] = { Carry, Result }; + SDValue Ops[] = { Result, Carry }; return DAG.getMergeValues(Ops, 2, dl); } // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the // low bit set - if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) { + if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { APInt KnownZero, KnownOne; APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), VT.getSizeInBits() - 1); @@ -1371,7 +1387,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, if ((KnownZero & Mask) == Mask) { SDValue Carry = DAG.getConstant(0, VT); SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); - SDValue Ops [] = { Carry, Result }; + SDValue Ops[] = { Result, Carry }; return DAG.getMergeValues(Ops, 2, dl); } } @@ -1395,14 +1411,14 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, SDValue Borrow = N2; SDValue Result = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), N2); - SDValue Ops [] = { Borrow, Result }; + SDValue Ops[] = { Result, Borrow }; return DAG.getMergeValues(Ops, 2, dl); } } // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the // low bit set - if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) { + if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { APInt KnownZero, KnownOne; APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), VT.getSizeInBits() - 1); @@ -1410,7 +1426,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, if ((KnownZero & Mask) == Mask) { SDValue Borrow = DAG.getConstant(0, VT); SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); - SDValue Ops [] = { Borrow, Result }; + SDValue Ops[] = { Result, Borrow }; return DAG.getMergeValues(Ops, 2, dl); } } @@ -1436,11 +1452,15 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, // If the high result is unused fold to add(a, b) if (N->hasNUsesOfValue(0, 0)) { SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); - SDValue Ops [] = { Lo, Lo }; + SDValue Ops[] = { Lo, Lo }; return DAG.getMergeValues(Ops, 2, dl); } // Otherwise fold to ladd(a, b, 0) - return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1); + SDValue Result = + DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1); + SDValue Carry(Result.getNode(), 1); + SDValue Ops[] = { Carry, Result }; + return DAG.getMergeValues(Ops, 2, dl); } } break; @@ -1534,7 +1554,7 @@ void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, default: break; case XCoreISD::LADD: case XCoreISD::LSUB: - if (Op.getResNo() == 0) { + if (Op.getResNo() == 1) { // Top bits of carry / borrow are clear. KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), KnownZero.getBitWidth() - 1); diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index 2874f00e4763..8d258f5054c1 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -63,6 +63,9 @@ namespace llvm { // Corresponds to MACCS instruction MACCS, + // Corresponds to CRC8 instruction + CRC8, + // Jumptable branch. BR_JT, @@ -81,7 +84,7 @@ namespace llvm { explicit XCoreTargetLowering(XCoreTargetMachine &TM); virtual unsigned getJumpTableEncoding() const; - virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } + virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } /// LowerOperation - Provide custom lowering hooks for some operations. virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; @@ -147,6 +150,7 @@ namespace llvm { SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; // Inline asm support std::pair<unsigned, const TargetRegisterClass*> diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td index 1963a70fb30d..379cc39aa617 100644 --- a/lib/Target/XCore/XCoreInstrFormats.td +++ b/lib/Target/XCore/XCoreInstrFormats.td @@ -10,7 +10,7 @@ //===----------------------------------------------------------------------===// // Instruction format superclass //===----------------------------------------------------------------------===// -class InstXCore<dag outs, dag ins, string asmstr, list<dag> pattern> +class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<32> Inst; @@ -19,102 +19,259 @@ class InstXCore<dag outs, dag ins, string asmstr, list<dag> pattern> dag InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; + let Size = sz; + field bits<32> SoftFail = 0; } // XCore pseudo instructions format class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern>; + : InstXCore<0, outs, ins, asmstr, pattern> { + let isPseudo = 1; +} //===----------------------------------------------------------------------===// // Instruction formats //===----------------------------------------------------------------------===// -class _F3R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + let Inst{15-11} = opc; + let DecoderMethod = "Decode3RInstruction"; +} + +// 3R with first operand as an immediate. Used for TSETR where the first +// operand is treated as an immediate since it refers to a register number in +// another thread. +class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : _F3R<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "Decode3RImmInstruction"; +} + +class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + let Inst{31-27} = opc{8-4}; + let Inst{26-20} = 0b1111110; + let Inst{19-16} = opc{3-0}; + + let Inst{15-11} = 0b11111; + let DecoderMethod = "DecodeL3RInstruction"; +} + +// L3R with first operand as both a source and a destination. +class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr, + list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "DecodeL3RSrcDstInstruction"; +} + +class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + let Inst{15-11} = opc; + let DecoderMethod = "Decode2RUSInstruction"; +} + +// 2RUS with bitp operand +class _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr, + list<dag> pattern> + : _F2RUS<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "Decode2RUSBitpInstruction"; +} + +class _FL2RUS<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + let Inst{31-27} = opc{8-4}; + let Inst{26-20} = 0b1111110; + let Inst{19-16} = opc{3-0}; + + let Inst{15-11} = 0b11111; + let DecoderMethod = "DecodeL2RUSInstruction"; +} + +// L2RUS with bitp operand +class _FL2RUSBitp<bits<9> opc, dag outs, dag ins, string asmstr, + list<dag> pattern> + : _FL2RUS<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "DecodeL2RUSBitpInstruction"; +} + +class _FRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + bits<4> a; + bits<6> b; + + let Inst{15-10} = opc; + let Inst{9-6} = a; + let Inst{5-0} = b; } -class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _FLRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + bits<4> a; + bits<16> b; + + let Inst{31-26} = opc; + let Inst{25-22} = a; + let Inst{21-16} = b{5-0}; + let Inst{15-10} = 0b111100; + let Inst{9-0} = b{15-6}; } -class _F2RUS<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _FU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + bits<6> a; + + let Inst{15-6} = opc; + let Inst{5-0} = a; } -class _FL2RUS<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _FLU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + bits<16> a; + + let Inst{31-22} = opc; + let Inst{21-16} = a{5-0}; + let Inst{15-10} = 0b111100; + let Inst{9-0} = a{15-6}; } -class _FRU6<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _FU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + bits<10> a; + + let Inst{15-10} = opc; + let Inst{9-0} = a; } -class _FLRU6<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _FLU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + bits<20> a; + + let Inst{31-26} = opc; + let Inst{25-16} = a{9-0}; + let Inst{15-10} = 0b111100; + let Inst{9-0} = a{19-10}; } -class _FU6<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + let Inst{15-11} = opc{5-1}; + let Inst{4} = opc{0}; + let DecoderMethod = "Decode2RInstruction"; } -class _FLU6<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +// 2R with first operand as an immediate. Used for TSETMR where the first +// operand is treated as an immediate since it refers to a register number in +// another thread. +class _F2RImm<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : _F2R<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "Decode2RImmInstruction"; } -class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +// 2R with first operand as both a source and a destination. +class _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr, + list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "Decode2RSrcDstInstruction"; } -class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +// Same as 2R with last two operands swapped +class _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : _F2R<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "DecodeR2RInstruction"; } -class _F2R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _FRUS<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + let Inst{15-11} = opc{5-1}; + let Inst{4} = opc{0}; + let DecoderMethod = "DecodeRUSInstruction"; } -class _FRUS<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +// RUS with bitp operand +class _FRUSBitp<bits<6> opc, dag outs, dag ins, string asmstr, + list<dag> pattern> + : _FRUS<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "DecodeRUSBitpInstruction"; } -class _FL2R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +// RUS with first operand as both a source and a destination and a bitp second +// operand +class _FRUSSrcDstBitp<bits<6> opc, dag outs, dag ins, string asmstr, + list<dag> pattern> + : _FRUS<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "DecodeRUSSrcDstBitpInstruction"; } -class _F1R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _FL2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + let Inst{31-27} = opc{9-5}; + let Inst{26-20} = 0b1111110; + let Inst{19-16} = opc{4-1}; + + let Inst{15-11} = 0b11111; + let Inst{4} = opc{0}; + let DecoderMethod = "DecodeL2RInstruction"; } -class _F0R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +// Same as L2R with last two operands swapped +class _FLR2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : _FL2R<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "DecodeLR2RInstruction"; } -class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + bits<4> a; + + let Inst{15-11} = opc{5-1}; + let Inst{10-5} = 0b111111; + let Inst{4} = opc{0}; + let Inst{3-0} = a; } -class _L5R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<2, outs, ins, asmstr, pattern> { + let Inst{15-11} = opc{9-5}; + let Inst{10-5} = 0b111111; + let Inst{4-0} = opc{4-0}; } -class _L6R<dag outs, dag ins, string asmstr, list<dag> pattern> - : InstXCore<outs, ins, asmstr, pattern> { - let Inst{31-0} = 0; +class _FL4R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + bits<4> d; + + let Inst{31-27} = opc{5-1}; + let Inst{26-21} = 0b111111; + let Inst{20} = opc{0}; + let Inst{19-16} = d; + let Inst{15-11} = 0b11111; +} + +// L4R with 4th operand as both a source and a destination. +class _FL4RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr, + list<dag> pattern> + : _FL4R<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "DecodeL4RSrcDstInstruction"; +} + +// L4R with 1st and 4th operand as both a source and a destination. +class _FL4RSrcDstSrcDst<bits<6> opc, dag outs, dag ins, string asmstr, + list<dag> pattern> + : _FL4R<opc, outs, ins, asmstr, pattern> { + let DecoderMethod = "DecodeL4RSrcDstSrcDstInstruction"; +} + +class _FL5R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + let Inst{31-27} = opc{5-1}; + let Inst{20} = opc{0}; + let Inst{15-11} = 0b11111; + + let DecoderMethod = "DecodeL5RInstruction"; +} + +class _FL6R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstXCore<4, outs, ins, asmstr, pattern> { + let Inst{31-27} = opc; + let Inst{15-11} = 0b11111; + + let DecoderMethod = "DecodeL6RInstruction"; } diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 0a3008d7ab33..e457e0dbf027 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -12,12 +12,12 @@ //===----------------------------------------------------------------------===// #include "XCoreInstrInfo.h" -#include "XCoreMachineFunctionInfo.h" #include "XCore.h" -#include "llvm/MC/MCContext.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineFrameInfo.h" +#include "XCoreMachineFunctionInfo.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/MC/MCContext.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 3e7666bdb936..03653cb2b3de 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -32,8 +32,8 @@ def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; -def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, - [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad]>; +def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, + [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>; def SDT_XCoreBR_JT : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; @@ -182,6 +182,7 @@ def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], // Address operands def MEMii : Operand<i32> { let PrintMethod = "printMemOperand"; + let DecoderMethod = "DecodeMEMiiOperand"; let MIOperandInfo = (ops i32imm, i32imm); } @@ -200,154 +201,117 @@ def InlineJT32 : Operand<i32> { // Three operand short -multiclass F3R_2RUS<string OpcStr, SDNode OpNode> { - def _3r: _F3R< - (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; - def _2rus : _F2RUS< - (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; +multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { + def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; + def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; } -multiclass F3R_2RUS_np<string OpcStr> { - def _3r: _F3R< - (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - []>; - def _2rus : _F2RUS< - (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - []>; +multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { + def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), + !strconcat(OpcStr, " $dst, $b, $c"), []>; + def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), + !strconcat(OpcStr, " $dst, $b, $c"), []>; } -multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> { - def _3r: _F3R< - (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; - def _2rus : _F2RUS< - (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; +multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, + SDNode OpNode> { + def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; + def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; } -class F3R<string OpcStr, SDNode OpNode> : _F3R< - (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; +class F3R<bits<5> opc, string OpcStr, SDNode OpNode> : + _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; -class F3R_np<string OpcStr> : _F3R< - (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - []>; +class F3R_np<bits<5> opc, string OpcStr> : + _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), + !strconcat(OpcStr, " $dst, $b, $c"), []>; // Three operand long /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. -multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> { - def _l3r: _FL3R< - (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; - def _l2rus : _FL2RUS< - (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; +multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, + SDNode OpNode> { + def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; + def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; } /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. -multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { - def _l3r: _FL3R< - (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; - def _l2rus : _FL2RUS< - (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; +multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, + SDNode OpNode> { + def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; + def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; } -class FL3R<string OpcStr, SDNode OpNode> : _FL3R< - (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), - !strconcat(OpcStr, " $dst, $b, $c"), - [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; +class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> : + _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), + !strconcat(OpcStr, " $dst, $b, $c"), + [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; // Register - U6 // Operand register - U6 -multiclass FRU6_LRU6_branch<string OpcStr> { - def _ru6: _FRU6< - (outs), (ins GRRegs:$cond, brtarget:$dest), - !strconcat(OpcStr, " $cond, $dest"), - []>; - def _lru6: _FLRU6< - (outs), (ins GRRegs:$cond, brtarget:$dest), - !strconcat(OpcStr, " $cond, $dest"), - []>; +multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> { + def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), + !strconcat(OpcStr, " $a, $b"), []>; + def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), + !strconcat(OpcStr, " $a, $b"), []>; } -multiclass FRU6_LRU6_cp<string OpcStr> { - def _ru6: _FRU6< - (outs GRRegs:$dst), (ins i32imm:$a), - !strconcat(OpcStr, " $dst, cp[$a]"), - []>; - def _lru6: _FLRU6< - (outs GRRegs:$dst), (ins i32imm:$a), - !strconcat(OpcStr, " $dst, cp[$a]"), - []>; +multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { + def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), + !strconcat(OpcStr, " $a, -$b"), []>; + def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), + !strconcat(OpcStr, " $a, -$b"), []>; } -// U6 -multiclass FU6_LU6<string OpcStr, SDNode OpNode> { - def _u6: _FU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - [(OpNode immU6:$b)]>; - def _lu6: _FLU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - [(OpNode immU16:$b)]>; +multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> { + def _ru6: _FRU6<opc, (outs RRegs:$a), (ins i32imm:$b), + !strconcat(OpcStr, " $a, cp[$b]"), []>; + def _lru6: _FLRU6<opc, (outs RRegs:$a), (ins i32imm:$b), + !strconcat(OpcStr, " $a, cp[$b]"), []>; } -multiclass FU6_LU6_int<string OpcStr, Intrinsic Int> { - def _u6: _FU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - [(Int immU6:$b)]>; - def _lu6: _FLU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - [(Int immU16:$b)]>; + +// U6 +multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> { + def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), + [(OpNode immU6:$a)]>; + def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), + [(OpNode immU16:$a)]>; } -multiclass FU6_LU6_np<string OpcStr> { - def _u6: _FU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - []>; - def _lu6: _FLU6< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - []>; +multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> { + def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), + [(Int immU6:$a)]>; + def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), + [(Int immU16:$a)]>; } -// U10 -multiclass FU10_LU10_np<string OpcStr> { - def _u10: _FU10< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - []>; - def _lu10: _FLU10< - (outs), (ins i32imm:$b), - !strconcat(OpcStr, " $b"), - []>; +multiclass FU6_LU6_np<bits<10> opc, string OpcStr> { + def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; + def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; } // Two operand short -class F2R_np<string OpcStr> : _F2R< - (outs GRRegs:$dst), (ins GRRegs:$b), - !strconcat(OpcStr, " $dst, $b"), - []>; +class F2R_np<bits<6> opc, string OpcStr> : + _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), + !strconcat(OpcStr, " $dst, $b"), []>; // Two operand long @@ -357,23 +321,23 @@ class F2R_np<string OpcStr> : _F2R< let Defs = [SP], Uses = [SP] in { def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), - "${:comment} ADJCALLSTACKDOWN $amt", + "# ADJCALLSTACKDOWN $amt", [(callseq_start timm:$amt)]>; def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), - "${:comment} ADJCALLSTACKUP $amt1", + "# ADJCALLSTACKUP $amt1", [(callseq_end timm:$amt1, timm:$amt2)]>; } def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), - "${:comment} LDWFI $dst, $addr", + "# LDWFI $dst, $addr", [(set GRRegs:$dst, (load ADDRspii:$addr))]>; def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), - "${:comment} LDAWFI $dst, $addr", + "# LDAWFI $dst, $addr", [(set GRRegs:$dst, ADDRspii:$addr)]>; def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), - "${:comment} STWFI $src, $addr", + "# STWFI $src, $addr", [(store GRRegs:$src, ADDRspii:$addr)]>; // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after @@ -381,7 +345,7 @@ def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), let usesCustomInserter = 1 in { def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), - "${:comment} SELECT_CC PSEUDO!", + "# SELECT_CC PSEUDO!", [(set GRRegs:$dst, (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; } @@ -391,572 +355,564 @@ let usesCustomInserter = 1 in { //===----------------------------------------------------------------------===// // Three operand short -defm ADD : F3R_2RUS<"add", add>; -defm SUB : F3R_2RUS<"sub", sub>; +defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; +defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; let neverHasSideEffects = 1 in { -defm EQ : F3R_2RUS_np<"eq">; -def LSS_3r : F3R_np<"lss">; -def LSU_3r : F3R_np<"lsu">; +defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; +def LSS_3r : F3R_np<0b11000, "lss">; +def LSU_3r : F3R_np<0b11001, "lsu">; } -def AND_3r : F3R<"and", and>; -def OR_3r : F3R<"or", or>; +def AND_3r : F3R<0b00111, "and", and>; +def OR_3r : F3R<0b01000, "or", or>; let mayLoad=1 in { -def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), - "ldw $dst, $addr[$offset]", - []>; +def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst), + (ins GRRegs:$addr, GRRegs:$offset), + "ldw $dst, $addr[$offset]", []>; -def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), - "ldw $dst, $addr[$offset]", - []>; +def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst), + (ins GRRegs:$addr, i32imm:$offset), + "ldw $dst, $addr[$offset]", []>; -def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), - "ld16s $dst, $addr[$offset]", - []>; +def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst), + (ins GRRegs:$addr, GRRegs:$offset), + "ld16s $dst, $addr[$offset]", []>; -def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), - "ld8u $dst, $addr[$offset]", - []>; +def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), + (ins GRRegs:$addr, GRRegs:$offset), + "ld8u $dst, $addr[$offset]", []>; } let mayStore=1 in { -def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), - "stw $val, $addr[$offset]", - []>; +def STW_l3r : _FL3R<0b000001100, (outs), + (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), + "stw $val, $addr[$offset]", []>; -def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), - "stw $val, $addr[$offset]", - []>; +def STW_2rus : _F2RUS<0b0000, (outs), + (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), + "stw $val, $addr[$offset]", []>; } -defm SHL : F3R_2RBITP<"shl", shl>; -defm SHR : F3R_2RBITP<"shr", srl>; -// TODO tsetr +defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; +defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; + +// The first operand is treated as an immediate since it refers to a register +// number in another thread. +def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), + "set t[$c]:r$a, $b", []>; // Three operand long -def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), - "ldaw $dst, $addr[$offset]", - [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; +def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), + (ins GRRegs:$addr, GRRegs:$offset), + "ldaw $dst, $addr[$offset]", + [(set GRRegs:$dst, + (ldawf GRRegs:$addr, GRRegs:$offset))]>; let neverHasSideEffects = 1 in -def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), - (ins GRRegs:$addr, i32imm:$offset), - "ldaw $dst, $addr[$offset]", - []>; +def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), + (ins GRRegs:$addr, i32imm:$offset), + "ldaw $dst, $addr[$offset]", []>; -def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), - "ldaw $dst, $addr[-$offset]", - [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; +def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), + (ins GRRegs:$addr, GRRegs:$offset), + "ldaw $dst, $addr[-$offset]", + [(set GRRegs:$dst, + (ldawb GRRegs:$addr, GRRegs:$offset))]>; let neverHasSideEffects = 1 in -def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), - (ins GRRegs:$addr, i32imm:$offset), - "ldaw $dst, $addr[-$offset]", - []>; - -def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), - "lda16 $dst, $addr[$offset]", - [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; - -def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), - "lda16 $dst, $addr[-$offset]", - [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; - -def MUL_l3r : FL3R<"mul", mul>; +def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), + (ins GRRegs:$addr, i32imm:$offset), + "ldaw $dst, $addr[-$offset]", []>; + +def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst), + (ins GRRegs:$addr, GRRegs:$offset), + "lda16 $dst, $addr[$offset]", + [(set GRRegs:$dst, + (lda16f GRRegs:$addr, GRRegs:$offset))]>; + +def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst), + (ins GRRegs:$addr, GRRegs:$offset), + "lda16 $dst, $addr[-$offset]", + [(set GRRegs:$dst, + (lda16b GRRegs:$addr, GRRegs:$offset))]>; + +def MUL_l3r : FL3R<0b001111100, "mul", mul>; // Instructions which may trap are marked as side effecting. let hasSideEffects = 1 in { -def DIVS_l3r : FL3R<"divs", sdiv>; -def DIVU_l3r : FL3R<"divu", udiv>; -def REMS_l3r : FL3R<"rems", srem>; -def REMU_l3r : FL3R<"remu", urem>; +def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>; +def DIVU_l3r : FL3R<0b010011100, "divu", udiv>; +def REMS_l3r : FL3R<0b110001100, "rems", srem>; +def REMU_l3r : FL3R<0b110011100, "remu", urem>; } -def XOR_l3r : FL3R<"xor", xor>; -defm ASHR : FL3R_L2RBITP<"ashr", sra>; +def XOR_l3r : FL3R<0b000011100, "xor", xor>; +defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>; let Constraints = "$src1 = $dst" in -def CRC_l3r : _FL3R<(outs GRRegs:$dst), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), - "crc32 $dst, $src2, $src3", - [(set GRRegs:$dst, - (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, - GRRegs:$src3))]>; +def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), + (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), + "crc32 $dst, $src2, $src3", + [(set GRRegs:$dst, + (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, + GRRegs:$src3))]>; -// TODO inpw, outpw let mayStore=1 in { -def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), - "st16 $val, $addr[$offset]", - []>; +def ST16_l3r : _FL3R<0b100001100, (outs), + (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), + "st16 $val, $addr[$offset]", []>; -def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), - "st8 $val, $addr[$offset]", - []>; +def ST8_l3r : _FL3R<0b100011100, (outs), + (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), + "st8 $val, $addr[$offset]", []>; } -// Four operand long -let Constraints = "$src1 = $dst1,$src2 = $dst2" in { -def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, - GRRegs:$src4), - "maccu $dst1, $dst2, $src3, $src4", - []>; +def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), + (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", + []>; -def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, - GRRegs:$src4), - "maccs $dst1, $dst2, $src3, $src4", - []>; +def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), + (ins GRRegs:$a, GRRegs:$b, i32imm:$c), + "outpw res[$b], $a, $c", []>; + +// Four operand long +let Constraints = "$e = $a,$f = $b" in { +def MACCU_l4r : _FL4RSrcDstSrcDst< + 0b000001, (outs GRRegs:$a, GRRegs:$b), + (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; + +def MACCS_l4r : _FL4RSrcDstSrcDst< + 0b000010, (outs GRRegs:$a, GRRegs:$b), + (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; } -let Constraints = "$src1 = $dst1" in -def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), - "crc8 $dst1, $dst2, $src2, $src3", - []>; +let Constraints = "$e = $b" in +def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), + (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), + "crc8 $b, $a, $c, $d", []>; // Five operand long -def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), - "ladd $dst1, $dst2, $src1, $src2, $src3", - []>; +def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2), + (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), + "ladd $dst2, $dst1, $src1, $src2, $src3", + []>; -def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), - "lsub $dst1, $dst2, $src1, $src2, $src3", - []>; +def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2), + (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), + "lsub $dst2, $dst1, $src1, $src2, $src3", []>; -def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), - "ldiv $dst1, $dst2, $src1, $src2, $src3", - []>; +def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2), + (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), + "ldivu $dst1, $dst2, $src3, $src1, $src2", []>; // Six operand long -def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), - (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, - GRRegs:$src4), - "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", - []>; +def LMUL_l6r : _FL6R< + 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2), + (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), + "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>; // Register - U6 //let Uses = [DP] in ... let neverHasSideEffects = 1, isReMaterializable = 1 in -def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), - "ldaw $dst, dp[$a]", - []>; +def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins MEMii:$b), + "ldaw $a, dp[$b]", []>; let isReMaterializable = 1 in -def LDAWDP_lru6: _FLRU6< - (outs GRRegs:$dst), (ins MEMii:$a), - "ldaw $dst, dp[$a]", - [(set GRRegs:$dst, ADDRdpii:$a)]>; +def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins MEMii:$b), + "ldaw $a, dp[$b]", + [(set RRegs:$a, ADDRdpii:$b)]>; let mayLoad=1 in -def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), - "ldw $dst, dp[$a]", - []>; - -def LDWDP_lru6: _FLRU6< - (outs GRRegs:$dst), (ins MEMii:$a), - "ldw $dst, dp[$a]", - [(set GRRegs:$dst, (load ADDRdpii:$a))]>; +def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins MEMii:$b), + "ldw $a, dp[$b]", []>; + +def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins MEMii:$b), + "ldw $a, dp[$b]", + [(set RRegs:$a, (load ADDRdpii:$b))]>; let mayStore=1 in -def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), - "stw $val, dp[$addr]", - []>; +def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, MEMii:$b), + "stw $a, dp[$b]", []>; -def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), - "stw $val, dp[$addr]", - [(store GRRegs:$val, ADDRdpii:$addr)]>; +def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, MEMii:$b), + "stw $a, dp[$b]", + [(store RRegs:$a, ADDRdpii:$b)]>; //let Uses = [CP] in .. let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in -defm LDWCP : FRU6_LRU6_cp<"ldw">; +defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">; let Uses = [SP] in { let mayStore=1 in { -def STWSP_ru6 : _FRU6< - (outs), (ins GRRegs:$val, i32imm:$index), - "stw $val, sp[$index]", - [(XCoreStwsp GRRegs:$val, immU6:$index)]>; - -def STWSP_lru6 : _FLRU6< - (outs), (ins GRRegs:$val, i32imm:$index), - "stw $val, sp[$index]", - [(XCoreStwsp GRRegs:$val, immU16:$index)]>; +def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), + "stw $a, sp[$b]", + [(XCoreStwsp RRegs:$a, immU6:$b)]>; + +def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), + "stw $a, sp[$b]", + [(XCoreStwsp RRegs:$a, immU16:$b)]>; } let mayLoad=1 in { -def LDWSP_ru6 : _FRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldw $dst, sp[$b]", - []>; +def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), + "ldw $a, sp[$b]", []>; -def LDWSP_lru6 : _FLRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldw $dst, sp[$b]", - []>; +def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), + "ldw $a, sp[$b]", []>; } let neverHasSideEffects = 1 in { -def LDAWSP_ru6 : _FRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldaw $dst, sp[$b]", - []>; +def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), + "ldaw $a, sp[$b]", []>; -def LDAWSP_lru6 : _FLRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldaw $dst, sp[$b]", - []>; - -def LDAWSP_ru6_RRegs : _FRU6< - (outs RRegs:$dst), (ins i32imm:$b), - "ldaw $dst, sp[$b]", - []>; - -def LDAWSP_lru6_RRegs : _FLRU6< - (outs RRegs:$dst), (ins i32imm:$b), - "ldaw $dst, sp[$b]", - []>; +def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), + "ldaw $a, sp[$b]", []>; } } let isReMaterializable = 1 in { -def LDC_ru6 : _FRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldc $dst, $b", - [(set GRRegs:$dst, immU6:$b)]>; - -def LDC_lru6 : _FLRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldc $dst, $b", - [(set GRRegs:$dst, immU16:$b)]>; +def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), + "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>; + +def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), + "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>; } -def SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val), - "setc res[$r], $val", - [(int_xcore_setc GRRegs:$r, immU6:$val)]>; +def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), + "setc res[$a], $b", + [(int_xcore_setc GRRegs:$a, immU6:$b)]>; -def SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val), - "setc res[$r], $val", - [(int_xcore_setc GRRegs:$r, immU16:$val)]>; +def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), + "setc res[$a], $b", + [(int_xcore_setc GRRegs:$a, immU16:$b)]>; // Operand register - U6 let isBranch = 1, isTerminator = 1 in { -defm BRFT: FRU6_LRU6_branch<"bt">; -defm BRBT: FRU6_LRU6_branch<"bt">; -defm BRFF: FRU6_LRU6_branch<"bf">; -defm BRBF: FRU6_LRU6_branch<"bf">; +defm BRFT: FRU6_LRU6_branch<0b011100, "bt">; +defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; +defm BRFF: FRU6_LRU6_branch<0b011110, "bf">; +defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; } // U6 let Defs = [SP], Uses = [SP] in { let neverHasSideEffects = 1 in -defm EXTSP : FU6_LU6_np<"extsp">; +defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; + let mayStore = 1 in -defm ENTSP : FU6_LU6_np<"entsp">; +defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { -defm RETSP : FU6_LU6<"retsp", XCoreRetsp>; +defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; } } -// TODO extdp, kentsp, krestsp, blat -// getsr, kalli +let neverHasSideEffects = 1 in +defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; + +let Uses = [R11], isCall=1 in +defm BLAT : FU6_LU6_np<0b0111001101, "blat">; + let isBranch = 1, isTerminator = 1, isBarrier = 1 in { -def BRBU_u6 : _FU6< - (outs), - (ins brtarget:$target), - "bu $target", - []>; +def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; -def BRBU_lu6 : _FLU6< - (outs), - (ins brtarget:$target), - "bu $target", - []>; +def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; -def BRFU_u6 : _FU6< - (outs), - (ins brtarget:$target), - "bu $target", - []>; +def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; -def BRFU_lu6 : _FLU6< - (outs), - (ins brtarget:$target), - "bu $target", - []>; +def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; } //let Uses = [CP] in ... let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in -def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a), - "ldaw r11, cp[$a]", +def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]", []>; let Defs = [R11], isReMaterializable = 1 in -def LDAWCP_lu6: _FLRU6< - (outs), (ins MEMii:$a), - "ldaw r11, cp[$a]", - [(set R11, ADDRcpii:$a)]>; +def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]", + [(set R11, ADDRcpii:$a)]>; + +let Defs = [R11] in +defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">; -defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>; +defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; -defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>; +defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; // setsr may cause a branch if it is used to enable events. clrsr may // branch if it is executed while events are enabled. -let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in { -defm SETSR_branch : FU6_LU6_np<"setsr">; -defm CLRSR_branch : FU6_LU6_np<"clrsr">; +let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, + isCodeGenOnly = 1 in { +defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; +defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; } +defm KCALL : FU6_LU6_np<0b0111001111, "kcall">; + +let Uses = [SP], Defs = [SP], mayStore = 1 in +defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">; + +let Uses = [SP], Defs = [SP], mayLoad = 1 in +defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; + // U10 -// TODO ldwcpl, blacp let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in -def LDAP_u10 : _FU10< - (outs), - (ins i32imm:$addr), - "ldap r11, $addr", - []>; +def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>; let Defs = [R11], isReMaterializable = 1 in -def LDAP_lu10 : _FLU10< - (outs), - (ins i32imm:$addr), - "ldap r11, $addr", - [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; +def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", + [(set R11, (pcrelwrapper tglobaladdr:$a))]>; -let Defs = [R11], isReMaterializable = 1 in -def LDAP_lu10_ba : _FLU10<(outs), - (ins i32imm:$addr), - "ldap r11, $addr", - [(set R11, (pcrelwrapper tblockaddress:$addr))]>; +let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in +def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", + [(set R11, (pcrelwrapper tblockaddress:$a))]>; let isCall=1, // All calls clobber the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { -def BL_u10 : _FU10< - (outs), (ins calltarget:$target), - "bl $target", - [(XCoreBranchLink immU10:$target)]>; - -def BL_lu10 : _FLU10< - (outs), (ins calltarget:$target), - "bl $target", - [(XCoreBranchLink immU20:$target)]>; +def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; + +def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; + +def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a", + [(XCoreBranchLink immU10:$a)]>; + +def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a", + [(XCoreBranchLink immU20:$a)]>; +} + +let Defs = [R11], mayLoad = 1, isReMaterializable = 1, + neverHasSideEffects = 1 in { +def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; + +def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", + []>; } // Two operand short -// TODO eet, eef, tsetmr -def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), - "not $dst, $b", - [(set GRRegs:$dst, (not GRRegs:$b))]>; +def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b), + "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; -def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), - "neg $dst, $b", - [(set GRRegs:$dst, (ineg GRRegs:$b))]>; +def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b), + "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; let Constraints = "$src1 = $dst" in { -def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), - "sext $dst, $src2", - [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, - immBitp:$src2))]>; - -def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), - "sext $dst, $src2", - [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, - GRRegs:$src2))]>; - -def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), - "zext $dst, $src2", - [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, - immBitp:$src2))]>; - -def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), - "zext $dst, $src2", - [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, - GRRegs:$src2))]>; - -def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), - "andnot $dst, $src2", - [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; +def SEXT_rus : + _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), + "sext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, + immBitp:$src2))]>; + +def SEXT_2r : + _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), + "sext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; + +def ZEXT_rus : + _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), + "zext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, + immBitp:$src2))]>; + +def ZEXT_2r : + _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), + "zext $dst, $src2", + [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; + +def ANDNOT_2r : + _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), + "andnot $dst, $src2", + [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; } let isReMaterializable = 1, neverHasSideEffects = 1 in -def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size), - "mkmsk $dst, $size", - []>; +def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), + "mkmsk $dst, $size", []>; -def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), - "mkmsk $dst, $size", - [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; +def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size), + "mkmsk $dst, $size", + [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; -def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type), - "getr $dst, $type", - [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; +def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type), + "getr $dst, $type", + [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; -def GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), - "getts $dst, res[$r]", - [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; +def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r), + "getts $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; -def SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), - "setpt res[$r], $val", - [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; +def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val), + "setpt res[$r], $val", + [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; -def OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), - "outct res[$r], $val", - [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; +def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val), + "outct res[$r], $val", + [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; -def OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), - "outct res[$r], $val", - [(int_xcore_outct GRRegs:$r, immUs:$val)]>; +def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val), + "outct res[$r], $val", + [(int_xcore_outct GRRegs:$r, immUs:$val)]>; -def OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), - "outt res[$r], $val", - [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; +def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val), + "outt res[$r], $val", + [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; -def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), - "out res[$r], $val", - [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; +def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val), + "out res[$r], $val", + [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; let Constraints = "$src = $dst" in -def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), - "outshr res[$r], $src", - [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, - GRRegs:$src))]>; +def OUTSHR_2r : + _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), + "outshr res[$r], $src", + [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; -def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), - "inct $dst, res[$r]", - [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; +def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r), + "inct $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; -def INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), - "int $dst, res[$r]", - [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; +def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r), + "int $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; -def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), +def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r), "in $dst, res[$r]", [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; let Constraints = "$src = $dst" in -def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), - "inshr $dst, res[$r]", - [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, - GRRegs:$src))]>; +def INSHR_2r : + _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), + "inshr $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; -def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), - "chkct res[$r], $val", - [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; +def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val), + "chkct res[$r], $val", + [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; -def CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), - "chkct res[$r], $val", - [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; +def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val), + "chkct res[$r], $val", + [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; -def TESTCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src), +def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src), "testct $dst, res[$src]", [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; -def TESTWCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src), +def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src), "testwct $dst, res[$src]", [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; -def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), - "setd res[$r], $val", - [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; +def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), + "setd res[$r], $val", + [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; -def GETST_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), +def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), + "setpsc res[$src1], $src2", + [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; + +def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), "getst $dst, res[$r]", [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; -def INITSP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), +def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t), "init t[$t]:sp, $src", [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; -def INITPC_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), +def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t), "init t[$t]:pc, $src", [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; -def INITCP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), +def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t), "init t[$t]:cp, $src", [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; -def INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), +def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t), "init t[$t]:dp, $src", [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; +def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src), + "peek $dst, res[$src]", + [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; + +def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src), + "endin $dst, res[$src]", + [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; + +def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b), + "eef $a, res[$b]", []>; + +def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b), + "eet $a, res[$b]", []>; + +def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b), + "tsetmr r$a, $b", []>; + // Two operand long -// getd, testlcl -def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), - "bitrev $dst, $src", - [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; +def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src), + "bitrev $dst, $src", + [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; + +def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), + "byterev $dst, $src", + [(set GRRegs:$dst, (bswap GRRegs:$src))]>; -def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), - "byterev $dst, $src", - [(set GRRegs:$dst, (bswap GRRegs:$src))]>; +def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src), + "clz $dst, $src", + [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; -def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), - "clz $dst, $src", - [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; +def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src), + "getd $dst, res[$src]", []>; -def SETC_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val), - "setc res[$r], $val", - [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; +def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src), + "getn $dst, res[$src]", []>; -def SETTW_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val), - "settw res[$r], $val", - [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; +def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val), + "setc res[$r], $val", + [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; -def GETPS_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), - "get $dst, ps[$src]", - [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; +def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val), + "settw res[$r], $val", + [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; -def SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), - "set ps[$src1], $src2", - [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; +def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src), + "get $dst, ps[$src]", + [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; -def INITLR_l2r : _FL2R<(outs), (ins GRRegs:$t, GRRegs:$src), +def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), + "set ps[$src1], $src2", + [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; + +def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t), "init t[$t]:lr, $src", [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; -def SETCLK_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), - "setclk res[$src1], $src2", - [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; - -def SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), - "setrdy res[$src1], $src2", - [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; +def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2), + "setclk res[$src1], $src2", + [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; -def SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), - "setpsc res[$src1], $src2", - [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; +def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2), + "setn res[$src1], $src2", []>; -def PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), - "peek $dst, res[$src]", - [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; +def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), + "setrdy res[$src1], $src2", + [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; -def ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), - "endin $dst, res[$src]", - [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; +def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src), + "testlcl $dst, res[$src]", []>; // One operand short -// TODO edu, eeu, waitet, waitef, tstart, clrtp -// setdp, setcp, setev, kcall -// dgetreg -def MSYNC_1r : _F1R<(outs), (ins GRRegs:$i), - "msync res[$i]", - [(int_xcore_msync GRRegs:$i)]>; -def MJOIN_1r : _F1R<(outs), (ins GRRegs:$i), - "mjoin res[$i]", - [(int_xcore_mjoin GRRegs:$i)]>; +def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a), + "msync res[$a]", + [(int_xcore_msync GRRegs:$a)]>; +def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a), + "mjoin res[$a]", + [(int_xcore_mjoin GRRegs:$a)]>; let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in -def BAU_1r : _F1R<(outs), (ins GRRegs:$addr), - "bau $addr", - [(brind GRRegs:$addr)]>; +def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a), + "bau $a", + [(brind GRRegs:$a)]>; let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), @@ -968,88 +924,150 @@ def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), "bru $i\n$t", [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; +let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in +def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; + let Defs=[SP], neverHasSideEffects=1 in -def SETSP_1r : _F1R<(outs), (ins GRRegs:$src), - "set sp, $src", - []>; +def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; + +let neverHasSideEffects=1 in +def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; + +let neverHasSideEffects=1 in +def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; let hasCtrlDep = 1 in -def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), - "ecallt $src", +def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), + "ecallt $a", []>; let hasCtrlDep = 1 in -def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), - "ecallf $src", +def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), + "ecallf $a", []>; let isCall=1, // All calls clobber the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { -def BLA_1r : _F1R<(outs), (ins GRRegs:$addr), - "bla $addr", - [(XCoreBranchLink GRRegs:$addr)]>; +def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), + "bla $a", + [(XCoreBranchLink GRRegs:$a)]>; } -def SYNCR_1r : _F1R<(outs), (ins GRRegs:$r), - "syncr res[$r]", - [(int_xcore_syncr GRRegs:$r)]>; +def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a), + "syncr res[$a]", + [(int_xcore_syncr GRRegs:$a)]>; -def FREER_1r : _F1R<(outs), (ins GRRegs:$r), - "freer res[$r]", - [(int_xcore_freer GRRegs:$r)]>; +def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a), + "freer res[$a]", + [(int_xcore_freer GRRegs:$a)]>; let Uses=[R11] in { -def SETV_1r : _F1R<(outs), (ins GRRegs:$r), - "setv res[$r], r11", - [(int_xcore_setv GRRegs:$r, R11)]>; +def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a), + "setv res[$a], r11", + [(int_xcore_setv GRRegs:$a, R11)]>; -def SETEV_1r : _F1R<(outs), (ins GRRegs:$r), - "setev res[$r], r11", - [(int_xcore_setev GRRegs:$r, R11)]>; +def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a), + "setev res[$a], r11", + [(int_xcore_setev GRRegs:$a, R11)]>; } -def EEU_1r : _F1R<(outs), (ins GRRegs:$r), - "eeu res[$r]", - [(int_xcore_eeu GRRegs:$r)]>; +def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>; + +def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>; + +def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a), + "eeu res[$a]", + [(int_xcore_eeu GRRegs:$a)]>; + +def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>; + +def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>; + +def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>; + +def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>; + +def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>; // Zero operand short -// TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, -// stet, getkep, getksp, setkep, getid, kret, dcall, dret, -// dentsp, drestsp -def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>; +def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>; + +def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>; + +let Defs = [SP], Uses = [SP] in +def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>; + +let Defs = [SP] in +def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>; + +def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>; + +def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>; let Defs = [R11] in { -def GETID_0R : _F0R<(outs), (ins), +def GETID_0R : _F0R<0b0001001110, (outs), (ins), "get r11, id", [(set R11, (int_xcore_getid))]>; -def GETED_0R : _F0R<(outs), (ins), +def GETED_0R : _F0R<0b0000111110, (outs), (ins), "get r11, ed", [(set R11, (int_xcore_geted))]>; -def GETET_0R : _F0R<(outs), (ins), +def GETET_0R : _F0R<0b0000111111, (outs), (ins), "get r11, et", [(set R11, (int_xcore_getet))]>; + +def GETKEP_0R : _F0R<0b0001001111, (outs), (ins), + "get r11, kep", []>; + +def GETKSP_0R : _F0R<0b0001011100, (outs), (ins), + "get r11, ksp", []>; +} + +let Defs = [SP] in +def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>; + +let Uses = [SP], mayLoad = 1 in { +def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>; + +def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>; + +def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>; + +def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>; } -def SSYNC_0r : _F0R<(outs), (ins), +let Uses=[R11] in +def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>; + +def SSYNC_0r : _F0R<0b0000001110, (outs), (ins), "ssync", [(int_xcore_ssync)]>; +let Uses = [SP], mayStore = 1 in { +def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>; + +def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>; + +def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>; + +def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>; +} + let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, hasSideEffects = 1 in -def WAITEU_0R : _F0R<(outs), (ins), - "waiteu", - [(brind (int_xcore_waitevent))]>; +def WAITEU_0R : _F0R<0b0000001100, (outs), (ins), + "waiteu", + [(brind (int_xcore_waitevent))]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// -def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; -def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; +def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>; +def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>; /// sext_inreg def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; @@ -1091,7 +1109,7 @@ def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), - (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; + (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; def : Pat<(store GRRegs:$val, GRRegs:$addr), diff --git a/lib/Target/XCore/XCoreMCInstLower.cpp b/lib/Target/XCore/XCoreMCInstLower.cpp new file mode 100644 index 000000000000..f96eda9fcb9f --- /dev/null +++ b/lib/Target/XCore/XCoreMCInstLower.cpp @@ -0,0 +1,117 @@ +//===-- XCoreMCInstLower.cpp - Convert XCore MachineInstr to MCInst -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief This file contains code to lower XCore MachineInstrs to their +/// corresponding MCInst records. +/// +//===----------------------------------------------------------------------===// +#include "XCoreMCInstLower.h" +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Target/Mangler.h" + +using namespace llvm; + +XCoreMCInstLower::XCoreMCInstLower(class AsmPrinter &asmprinter) +: Printer(asmprinter) {} + +void XCoreMCInstLower::Initialize(Mangler *M, MCContext *C) { + Mang = M; + Ctx = C; +} + +MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO, + MachineOperandType MOTy, + unsigned Offset) const { + MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None; + const MCSymbol *Symbol; + + switch (MOTy) { + case MachineOperand::MO_MachineBasicBlock: + Symbol = MO.getMBB()->getSymbol(); + break; + case MachineOperand::MO_GlobalAddress: + Symbol = Mang->getSymbol(MO.getGlobal()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_BlockAddress: + Symbol = Printer.GetBlockAddressSymbol(MO.getBlockAddress()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_ExternalSymbol: + Symbol = Printer.GetExternalSymbolSymbol(MO.getSymbolName()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_JumpTableIndex: + Symbol = Printer.GetJTISymbol(MO.getIndex()); + break; + case MachineOperand::MO_ConstantPoolIndex: + Symbol = Printer.GetCPISymbol(MO.getIndex()); + Offset += MO.getOffset(); + break; + default: + llvm_unreachable("<unknown operand type>"); + } + + const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx); + + if (!Offset) + return MCOperand::CreateExpr(MCSym); + + // Assume offset is never negative. + assert(Offset > 0); + + const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx); + const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx); + return MCOperand::CreateExpr(Add); +} + +MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO, + unsigned offset) const { + MachineOperandType MOTy = MO.getType(); + + switch (MOTy) { + default: llvm_unreachable("unknown operand type"); + case MachineOperand::MO_Register: + // Ignore all implicit register operands. + if (MO.isImplicit()) break; + return MCOperand::CreateReg(MO.getReg()); + case MachineOperand::MO_Immediate: + return MCOperand::CreateImm(MO.getImm() + offset); + case MachineOperand::MO_MachineBasicBlock: + case MachineOperand::MO_GlobalAddress: + case MachineOperand::MO_ExternalSymbol: + case MachineOperand::MO_JumpTableIndex: + case MachineOperand::MO_ConstantPoolIndex: + case MachineOperand::MO_BlockAddress: + return LowerSymbolOperand(MO, MOTy, offset); + case MachineOperand::MO_RegisterMask: + break; + } + + return MCOperand(); +} + +void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { + OutMI.setOpcode(MI->getOpcode()); + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + MCOperand MCOp = LowerOperand(MO); + + if (MCOp.isValid()) + OutMI.addOperand(MCOp); + } +} diff --git a/lib/Target/XCore/XCoreMCInstLower.h b/lib/Target/XCore/XCoreMCInstLower.h new file mode 100644 index 000000000000..28e702bb9884 --- /dev/null +++ b/lib/Target/XCore/XCoreMCInstLower.h @@ -0,0 +1,42 @@ +//===-- XCoreMCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef XCOREMCINSTLOWER_H +#define XCOREMCINSTLOWER_H +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/Support/Compiler.h" + +namespace llvm { + class MCContext; + class MCInst; + class MCOperand; + class MachineInstr; + class MachineFunction; + class Mangler; + class AsmPrinter; + +/// \brief This class is used to lower an MachineInstr into an MCInst. +class LLVM_LIBRARY_VISIBILITY XCoreMCInstLower { + typedef MachineOperand::MachineOperandType MachineOperandType; + MCContext *Ctx; + Mangler *Mang; + AsmPrinter &Printer; +public: + XCoreMCInstLower(class AsmPrinter &asmprinter); + void Initialize(Mangler *mang, MCContext *C); + void Lower(const MachineInstr *MI, MCInst &OutMI) const; + MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const; + +private: + MCOperand LowerSymbolOperand(const MachineOperand &MO, + MachineOperandType MOTy, unsigned Offset) const; +}; +} + +#endif diff --git a/lib/Target/XCore/XCoreMachineFunctionInfo.h b/lib/Target/XCore/XCoreMachineFunctionInfo.h index f869fcf26de3..69d5de3e03ad 100644 --- a/lib/Target/XCore/XCoreMachineFunctionInfo.h +++ b/lib/Target/XCore/XCoreMachineFunctionInfo.h @@ -14,8 +14,8 @@ #ifndef XCOREMACHINEFUNCTIONINFO_H #define XCOREMACHINEFUNCTIONINFO_H -#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" #include <vector> namespace llvm { diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index be5855abcd0b..49b563497c0b 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -12,25 +12,25 @@ //===----------------------------------------------------------------------===// #include "XCoreRegisterInfo.h" -#include "XCoreMachineFunctionInfo.h" #include "XCore.h" -#include "llvm/Type.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineFunction.h" +#include "XCoreMachineFunctionInfo.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetFrameLowering.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/ADT/BitVector.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Type.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetFrameLowering.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" #define GET_REGINFO_TARGET_DESC #include "XCoreGenRegisterInfo.inc" @@ -101,72 +101,14 @@ XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { return false; } -// This function eliminates ADJCALLSTACKDOWN, -// ADJCALLSTACKUP pseudo instructions -void XCoreRegisterInfo:: -eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const { - const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); - - if (!TFI->hasReservedCallFrame(MF)) { - // Turn the adjcallstackdown instruction into 'extsp <amt>' and the - // adjcallstackup instruction into 'ldaw sp, sp[<amt>]' - MachineInstr *Old = I; - uint64_t Amount = Old->getOperand(0).getImm(); - if (Amount != 0) { - // We need to keep the stack aligned properly. To do this, we round the - // amount of space needed for the outgoing arguments up to the next - // alignment boundary. - unsigned Align = TFI->getStackAlignment(); - Amount = (Amount+Align-1)/Align*Align; - - assert(Amount%4 == 0); - Amount /= 4; - - bool isU6 = isImmU6(Amount); - if (!isU6 && !isImmU16(Amount)) { - // FIX could emit multiple instructions in this case. -#ifndef NDEBUG - errs() << "eliminateCallFramePseudoInstr size too big: " - << Amount << "\n"; -#endif - llvm_unreachable(0); - } - - MachineInstr *New; - if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) { - int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; - New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode)) - .addImm(Amount); - } else { - assert(Old->getOpcode() == XCore::ADJCALLSTACKUP); - int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; - New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP) - .addImm(Amount); - } - - // Replace the pseudo instruction with a new instruction... - MBB.insert(I, New); - } - } - - MBB.erase(I); -} - void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, RegScavenger *RS) const { + int SPAdj, unsigned FIOperandNum, + RegScavenger *RS) const { assert(SPAdj == 0 && "Unexpected"); MachineInstr &MI = *II; DebugLoc dl = MI.getDebugLoc(); - unsigned i = 0; - - while (!MI.getOperand(i).isFI()) { - ++i; - assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); - } - - MachineOperand &FrameOp = MI.getOperand(i); + MachineOperand &FrameOp = MI.getOperand(FIOperandNum); int FrameIndex = FrameOp.getIndex(); MachineFunction &MF = *MI.getParent()->getParent(); @@ -190,14 +132,14 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Special handling of DBG_VALUE instructions. if (MI.isDebugValue()) { - MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/); - MI.getOperand(i+1).ChangeToImmediate(Offset); + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); return; } // fold constant into offset. - Offset += MI.getOperand(i + 1).getImm(); - MI.getOperand(i + 1).ChangeToImmediate(0); + Offset += MI.getOperand(FIOperandNum + 1).getImm(); + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0); assert(Offset%4 == 0 && "Misaligned stack offset"); @@ -231,7 +173,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, .addReg(ScratchReg, RegState::Kill); break; case XCore::STWFI: - BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) + BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) .addReg(Reg, getKillRegState(isKill)) .addReg(FrameReg) .addReg(ScratchReg, RegState::Kill); diff --git a/lib/Target/XCore/XCoreRegisterInfo.h b/lib/Target/XCore/XCoreRegisterInfo.h index c4dcb6b533c2..1db32489cf8d 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.h +++ b/lib/Target/XCore/XCoreRegisterInfo.h @@ -54,12 +54,9 @@ public: bool useFPForScavengingIndex(const MachineFunction &MF) const; - void eliminateCallFramePseudoInstr(MachineFunction &MF, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const; - void eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, RegScavenger *RS = NULL) const; + int SPAdj, unsigned FIOperandNum, + RegScavenger *RS = NULL) const; // Debug information queries. unsigned getFrameRegister(const MachineFunction &MF) const; diff --git a/lib/Target/XCore/XCoreRegisterInfo.td b/lib/Target/XCore/XCoreRegisterInfo.td index 9edfda1f5007..6694b2882aca 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.td +++ b/lib/Target/XCore/XCoreRegisterInfo.td @@ -45,12 +45,15 @@ def LR : Ri<15, "lr">, DwarfRegNum<[15]>; def GRRegs : RegisterClass<"XCore", [i32], 32, // Return values and arguments (add R0, R1, R2, R3, - // Not preserved across procedure calls - R11, // Callee save - R4, R5, R6, R7, R8, R9, R10)>; + R4, R5, R6, R7, R8, R9, R10, + // Not preserved across procedure calls + R11)>; // Reserved -def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> { +def RRegs : RegisterClass<"XCore", [i32], 32, + (add R0, R1, R2, R3, + R4, R5, R6, R7, R8, R9, R10, + R11, CP, DP, SP, LR)> { let isAllocatable = 0; } diff --git a/lib/Target/XCore/XCoreSubtarget.h b/lib/Target/XCore/XCoreSubtarget.h index 8d0f254e087a..5ac4dbc4bc07 100644 --- a/lib/Target/XCore/XCoreSubtarget.h +++ b/lib/Target/XCore/XCoreSubtarget.h @@ -14,8 +14,8 @@ #ifndef XCORESUBTARGET_H #define XCORESUBTARGET_H -#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetSubtargetInfo.h" #include <string> #define GET_SUBTARGETINFO_HEADER diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index d5a932c5189d..28c3d12c05fe 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -12,9 +12,9 @@ #include "XCoreTargetMachine.h" #include "XCore.h" -#include "llvm/Module.h" -#include "llvm/PassManager.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/IR/Module.h" +#include "llvm/PassManager.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -32,7 +32,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, InstrInfo(), FrameLowering(Subtarget), TLInfo(*this), - TSInfo(*this), STTI(&TLInfo), VTTI(&TLInfo) { + TSInfo(*this) { } namespace { diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index c60c6a37f95b..eb9a1aa420eb 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -15,13 +15,12 @@ #define XCORETARGETMACHINE_H #include "XCoreFrameLowering.h" -#include "XCoreSubtarget.h" -#include "XCoreInstrInfo.h" #include "XCoreISelLowering.h" +#include "XCoreInstrInfo.h" #include "XCoreSelectionDAGInfo.h" +#include "XCoreSubtarget.h" +#include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetTransformImpl.h" -#include "llvm/DataLayout.h" namespace llvm { @@ -32,8 +31,6 @@ class XCoreTargetMachine : public LLVMTargetMachine { XCoreFrameLowering FrameLowering; XCoreTargetLowering TLInfo; XCoreSelectionDAGInfo TSInfo; - ScalarTargetTransformImpl STTI; - VectorTargetTransformImpl VTTI; public: XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -56,12 +53,6 @@ public: virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } - virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const { - return &STTI; - } - virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const { - return &VTTI; - } virtual const DataLayout *getDataLayout() const { return &DL; } // Pass Pipeline Configuration diff --git a/lib/Target/XCore/XCoreTargetObjectFile.cpp b/lib/Target/XCore/XCoreTargetObjectFile.cpp index 7f4e1c1b4fd7..820389935b38 100644 --- a/lib/Target/XCore/XCoreTargetObjectFile.cpp +++ b/lib/Target/XCore/XCoreTargetObjectFile.cpp @@ -11,8 +11,8 @@ #include "XCoreSubtarget.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSectionELF.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Support/ELF.h" +#include "llvm/Target/TargetMachine.h" using namespace llvm; |