diff options
Diffstat (limited to 'lib/Target/XCore')
31 files changed, 221 insertions, 140 deletions
diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt index 3dc51e1991ed..0d59572a0d57 100644 --- a/lib/Target/XCore/CMakeLists.txt +++ b/lib/Target/XCore/CMakeLists.txt @@ -1,11 +1,11 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) -llvm_tablegen(XCoreGenRegisterInfo.inc -gen-register-info) -llvm_tablegen(XCoreGenInstrInfo.inc -gen-instr-info) -llvm_tablegen(XCoreGenAsmWriter.inc -gen-asm-writer) -llvm_tablegen(XCoreGenDAGISel.inc -gen-dag-isel) -llvm_tablegen(XCoreGenCallingConv.inc -gen-callingconv) -llvm_tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget) +tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info) +tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info) +tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer) +tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel) +tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv) +tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget) add_public_tablegen_target(XCoreCommonTableGen) add_llvm_target(XCoreCodeGen @@ -14,6 +14,7 @@ add_llvm_target(XCoreCodeGen XCoreInstrInfo.cpp XCoreISelDAGToDAG.cpp XCoreISelLowering.cpp + XCoreMachineFunctionInfo.cpp XCoreRegisterInfo.cpp XCoreSubtarget.cpp XCoreTargetMachine.cpp @@ -21,17 +22,5 @@ add_llvm_target(XCoreCodeGen XCoreSelectionDAGInfo.cpp ) -add_llvm_library_dependencies(LLVMXCoreCodeGen - LLVMAsmPrinter - LLVMCodeGen - LLVMCore - LLVMMC - LLVMSelectionDAG - LLVMSupport - LLVMTarget - LLVMXCoreDesc - LLVMXCoreInfo - ) - add_subdirectory(TargetInfo) add_subdirectory(MCTargetDesc) diff --git a/lib/Target/XCore/LLVMBuild.txt b/lib/Target/XCore/LLVMBuild.txt new file mode 100644 index 000000000000..53b4a9e3f5f7 --- /dev/null +++ b/lib/Target/XCore/LLVMBuild.txt @@ -0,0 +1,32 @@ +;===- ./lib/Target/XCore/LLVMBuild.txt -------------------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[common] +subdirectories = MCTargetDesc TargetInfo + +[component_0] +type = TargetGroup +name = XCore +parent = Target +has_asmprinter = 1 + +[component_1] +type = Library +name = XCoreCodeGen +parent = XCore +required_libraries = AsmPrinter CodeGen Core MC SelectionDAG Support Target XCoreDesc XCoreInfo +add_to_library_groups = XCore diff --git a/lib/Target/XCore/MCTargetDesc/CMakeLists.txt b/lib/Target/XCore/MCTargetDesc/CMakeLists.txt index 269822db7113..3a3f5b4cc63e 100644 --- a/lib/Target/XCore/MCTargetDesc/CMakeLists.txt +++ b/lib/Target/XCore/MCTargetDesc/CMakeLists.txt @@ -3,11 +3,6 @@ add_llvm_library(LLVMXCoreDesc XCoreMCAsmInfo.cpp ) -add_llvm_library_dependencies(LLVMXCoreDesc - LLVMMC - LLVMXCoreInfo - ) - add_dependencies(LLVMXCoreDesc XCoreCommonTableGen) # Hack: we need to include 'main' target directory to grab private headers diff --git a/lib/Target/XCore/MCTargetDesc/LLVMBuild.txt b/lib/Target/XCore/MCTargetDesc/LLVMBuild.txt new file mode 100644 index 000000000000..a80c939b4372 --- /dev/null +++ b/lib/Target/XCore/MCTargetDesc/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/XCore/MCTargetDesc/LLVMBuild.txt ------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = XCoreDesc +parent = XCore +required_libraries = MC XCoreInfo +add_to_library_groups = XCore diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp index 42ab1b31d57a..1cfdbda003b5 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp @@ -8,8 +8,11 @@ //===----------------------------------------------------------------------===// #include "XCoreMCAsmInfo.h" +#include "llvm/ADT/StringRef.h" using namespace llvm; +void XCoreMCAsmInfo::anchor() { } + XCoreMCAsmInfo::XCoreMCAsmInfo(const Target &T, StringRef TT) { SupportsDebugInformation = true; Data16bitsDirective = "\t.short\t"; diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h index 840392263881..076777541e33 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h @@ -1,4 +1,4 @@ -//=====-- XCoreMCAsmInfo.h - XCore asm properties -------------*- C++ -*--====// +//===-- XCoreMCAsmInfo.h - XCore asm properties ----------------*- C++ -*--===// // // The LLVM Compiler Infrastructure // @@ -14,13 +14,14 @@ #ifndef XCORETARGETASMINFO_H #define XCORETARGETASMINFO_H -#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { + class StringRef; class Target; class XCoreMCAsmInfo : public MCAsmInfo { + virtual void anchor(); public: explicit XCoreMCAsmInfo(const Target &T, StringRef TT); }; diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index 276e841e6acc..bbfdd4356f2a 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -1,4 +1,4 @@ -//===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -------*- C++ -*-===// +//===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -----------------===// // // The LLVM Compiler Infrastructure // @@ -17,6 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC @@ -61,9 +62,10 @@ static MCAsmInfo *createXCoreMCAsmInfo(const Target &T, StringRef TT) { } static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, - CodeModel::Model CM) { + CodeModel::Model CM, + CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM, CM); + X->InitMCCodeGenInfo(RM, CM, OL); return X; } diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h index 3cfc3764a62c..a255adb2e0f2 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h @@ -15,9 +15,7 @@ #define XCOREMCTARGETDESC_H namespace llvm { -class MCSubtargetInfo; class Target; -class StringRef; extern Target TheXCoreTarget; diff --git a/lib/Target/XCore/TargetInfo/CMakeLists.txt b/lib/Target/XCore/TargetInfo/CMakeLists.txt index 7f84f6904305..2c34b8730c85 100644 --- a/lib/Target/XCore/TargetInfo/CMakeLists.txt +++ b/lib/Target/XCore/TargetInfo/CMakeLists.txt @@ -4,10 +4,4 @@ add_llvm_library(LLVMXCoreInfo XCoreTargetInfo.cpp ) -add_llvm_library_dependencies(LLVMXCoreInfo - LLVMMC - LLVMSupport - LLVMTarget - ) - add_dependencies(LLVMXCoreInfo XCoreCommonTableGen) diff --git a/lib/Target/XCore/TargetInfo/LLVMBuild.txt b/lib/Target/XCore/TargetInfo/LLVMBuild.txt new file mode 100644 index 000000000000..770ba87e4a39 --- /dev/null +++ b/lib/Target/XCore/TargetInfo/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/XCore/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = XCoreInfo +parent = XCore +required_libraries = MC Support Target +add_to_library_groups = XCore diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h index b8fb0cac319b..08f091e5b870 100644 --- a/lib/Target/XCore/XCore.h +++ b/lib/Target/XCore/XCore.h @@ -24,7 +24,8 @@ namespace llvm { class XCoreTargetMachine; class formatted_raw_ostream; - FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM); + FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM, + CodeGenOpt::Level OptLevel); } // end namespace llvm; diff --git a/lib/Target/XCore/XCore.td b/lib/Target/XCore/XCore.td index 38401895e634..04a1dd5e95be 100644 --- a/lib/Target/XCore/XCore.td +++ b/lib/Target/XCore/XCore.td @@ -1,4 +1,4 @@ -//===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===// +//===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -7,6 +7,7 @@ // //===----------------------------------------------------------------------===// // +// This is the top level entry point for the XCore target. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/XCore/XCoreFrameLowering.cpp b/lib/Target/XCore/XCoreFrameLowering.cpp index 7f8b169819a7..50fda58cf574 100644 --- a/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/lib/Target/XCore/XCoreFrameLowering.cpp @@ -1,4 +1,4 @@ -//===-- XCoreFrameLowering.cpp - Frame info for XCore Target -----*- C++ -*-==// +//===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===// // // The LLVM Compiler Infrastructure // @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#include "XCore.h" #include "XCoreFrameLowering.h" +#include "XCore.h" #include "XCoreInstrInfo.h" #include "XCoreMachineFunctionInfo.h" #include "llvm/Function.h" @@ -84,7 +84,8 @@ XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti) } bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const { - return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects(); + return MF.getTarget().Options.DisableFramePointerElim(MF) || + MF.getFrameInfo()->hasVarSizedObjects(); } void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { @@ -92,8 +93,6 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo *MMI = &MF.getMMI(); - const XCoreRegisterInfo *RegInfo = - static_cast<const XCoreRegisterInfo*>(MF.getTarget().getRegisterInfo()); const XCoreInstrInfo &TII = *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo()); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); @@ -118,7 +117,7 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { // FIXME could emit multiple instructions. report_fatal_error("emitPrologue Frame size too big: " + Twine(FrameSize)); } - bool emitFrameMoves = RegInfo->needsFrameMoves(MF); + bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF); // Do we need to allocate space on the stack? if (FrameSize) { diff --git a/lib/Target/XCore/XCoreFrameLowering.h b/lib/Target/XCore/XCoreFrameLowering.h index c591e93780aa..4c51aa5e79cc 100644 --- a/lib/Target/XCore/XCoreFrameLowering.h +++ b/lib/Target/XCore/XCoreFrameLowering.h @@ -1,4 +1,4 @@ -//===-- XCoreFrameLowering.h - Frame info for XCore Target -------*- C++ -*-==// +//===-- XCoreFrameLowering.h - Frame info for XCore Target ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 4dac1cee9827..7564fbad7d45 100644 --- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -41,8 +41,8 @@ namespace { const XCoreSubtarget &Subtarget; public: - XCoreDAGToDAGISel(XCoreTargetMachine &TM) - : SelectionDAGISel(TM), + XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) + : SelectionDAGISel(TM, OptLevel), Lowering(*TM.getTargetLowering()), Subtarget(*TM.getSubtargetImpl()) { } @@ -83,8 +83,9 @@ namespace { /// createXCoreISelDag - This pass converts a legalized DAG into a /// XCore-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM) { - return new XCoreDAGToDAGISel(TM); +FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, + CodeGenOpt::Level OptLevel) { + return new XCoreDAGToDAGISel(TM, OptLevel); } bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, @@ -120,7 +121,7 @@ bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Addr, SDValue &Base, ConstantSDNode *CN = 0; if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) - && (CN->getSExtValue() % 4 == 0)) { + && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { // Constant word offset from a object in the data region Base = Addr.getOperand(0).getOperand(0); Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); @@ -141,7 +142,7 @@ bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Addr, SDValue &Base, ConstantSDNode *CN = 0; if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) - && (CN->getSExtValue() % 4 == 0)) { + && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { // Constant word offset from a object in the data region Base = Addr.getOperand(0).getOperand(0); Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 2afe0e35afb1..fdf2b783241c 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -1,4 +1,4 @@ -//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===// +//===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// // // The LLVM Compiler Infrastructure // @@ -36,7 +36,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/ADT/VectorExtras.h" using namespace llvm; const char *XCoreTargetLowering:: @@ -109,6 +108,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) setOperationAction(ISD::CTPOP, MVT::i32, Expand); setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTR , MVT::i32, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); setOperationAction(ISD::TRAP, MVT::Other, Legal); @@ -186,7 +187,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); default: llvm_unreachable("unimplemented operand"); - return SDValue(); } } @@ -198,7 +198,6 @@ void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, switch (N->getOpcode()) { default: llvm_unreachable("Don't know how to custom expand this!"); - return; case ISD::ADD: case ISD::SUB: Results.push_back(ExpandADDSUB(N, DAG)); @@ -274,9 +273,8 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); } - if (! GVar) { + if (!GVar) { llvm_unreachable("Thread local object not a GlobalVariable?"); - return SDValue(); } Type *Ty = cast<PointerType>(GV->getType())->getElementType(); if (!Ty->isSized() || isZeroLengthArray(Ty)) { @@ -386,6 +384,15 @@ IsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase, Offset = off; return true; } + // Check for an aligned global variable. + if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(*Root)) { + const GlobalValue *GV = GA->getGlobal(); + if (GA->getOffset() == 0 && GV->getAlignment() >= 4) { + AlignedBase = Base; + Offset = off; + return true; + } + } return false; } @@ -418,7 +425,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) const { // return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } // Lower to // ldw low, base[offset >> 2] @@ -435,9 +442,11 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) const { SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset); SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain, - LowAddr, MachinePointerInfo(), false, false, 0); + LowAddr, MachinePointerInfo(), + false, false, false, 0); SDValue High = DAG.getLoad(getPointerTy(), DL, Chain, - HighAddr, MachinePointerInfo(), false, false, 0); + HighAddr, MachinePointerInfo(), + false, false, false, 0); SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift); SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted); @@ -478,8 +487,8 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) const { std::pair<SDValue, SDValue> CallResult = LowerCallTo(Chain, IntPtrTy, false, false, - false, false, 0, CallingConv::C, false, - /*isReturnValueUsed=*/true, + false, false, 0, CallingConv::C, /*isTailCall=*/false, + /*doesNotRet=*/false, /*isReturnValueUsed=*/true, DAG.getExternalSymbol("__misaligned_load", getPointerTy()), Args, DAG, DL); @@ -540,8 +549,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG) const std::pair<SDValue, SDValue> CallResult = LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false, - false, false, 0, CallingConv::C, false, - /*isReturnValueUsed=*/true, + false, false, 0, CallingConv::C, /*isTailCall=*/false, + /*doesNotRet=*/false, /*isReturnValueUsed=*/true, DAG.getExternalSymbol("__misaligned_store", getPointerTy()), Args, DAG, dl); @@ -745,14 +754,14 @@ SDValue XCoreTargetLowering:: LowerVAARG(SDValue Op, SelectionDAG &DAG) const { llvm_unreachable("unimplemented"); - // FIX Arguments passed by reference need a extra dereference. + // FIXME Arguments passed by reference need a extra dereference. SDNode *Node = Op.getNode(); DebugLoc dl = Node->getDebugLoc(); const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); EVT VT = Node->getValueType(0); SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0), Node->getOperand(1), MachinePointerInfo(V), - false, false, 0); + false, false, false, 0); // Increment the pointer, VAList, to the next vararg SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits(), @@ -762,7 +771,7 @@ LowerVAARG(SDValue Op, SelectionDAG &DAG) const MachinePointerInfo(V), false, false, 0); // Load the actual argument out of the pointer VAList return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } SDValue XCoreTargetLowering:: @@ -866,7 +875,7 @@ LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { SDValue XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, @@ -1137,13 +1146,13 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo::getFixedStack(FI), - false, false, 0)); + false, false, false, 0)); } } if (isVarArg) { /* Argument registers */ - static const unsigned ArgRegs[] = { + static const uint16_t ArgRegs[] = { XCore::R0, XCore::R1, XCore::R2, XCore::R3 }; XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); @@ -1354,8 +1363,8 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, APInt KnownZero, KnownOne; APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), VT.getSizeInBits() - 1); - DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne); - if (KnownZero == Mask) { + DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); + if ((KnownZero & Mask) == Mask) { SDValue Carry = DAG.getConstant(0, VT); SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); SDValue Ops [] = { Carry, Result }; @@ -1377,8 +1386,8 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, APInt KnownZero, KnownOne; APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), VT.getSizeInBits() - 1); - DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne); - if (KnownZero == Mask) { + DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); + if ((KnownZero & Mask) == Mask) { SDValue Borrow = N2; SDValue Result = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), N2); @@ -1393,8 +1402,8 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, APInt KnownZero, KnownOne; APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), VT.getSizeInBits() - 1); - DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne); - if (KnownZero == Mask) { + DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); + if ((KnownZero & Mask) == Mask) { SDValue Borrow = DAG.getConstant(0, VT); SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); SDValue Ops [] = { Borrow, Result }; @@ -1512,21 +1521,19 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, } void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, - const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const { - KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); + KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); switch (Op.getOpcode()) { default: break; case XCoreISD::LADD: case XCoreISD::LSUB: if (Op.getResNo() == 0) { // Top bits of carry / borrow are clear. - KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), - Mask.getBitWidth() - 1); - KnownZero &= Mask; + KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), + KnownZero.getBitWidth() - 1); } break; } @@ -1590,8 +1597,6 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, // reg + reg<<2 return AM.Scale == 4 && AM.BaseOffs == 0; } - - return false; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index d6c5b329a0a0..0b63ecd0f78e 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -15,9 +15,9 @@ #ifndef XCOREISELLOWERING_H #define XCOREISELLOWERING_H +#include "XCore.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Target/TargetLowering.h" -#include "XCore.h" namespace llvm { @@ -160,7 +160,6 @@ namespace llvm { virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual void computeMaskedBitsForTargetNode(const SDValue Op, - const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, @@ -175,9 +174,8 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals) const; virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, - CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, + bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td index 8002c993270c..1963a70fb30d 100644 --- a/lib/Target/XCore/XCoreInstrFormats.td +++ b/lib/Target/XCore/XCoreInstrFormats.td @@ -1,4 +1,4 @@ -//===- XCoreInstrFormats.td - XCore Instruction Formats ----*- tablegen -*-===// +//===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index a0946a197a1a..0a3008d7ab33 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -1,4 +1,4 @@ -//===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===// +//===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===// // // The LLVM Compiler Infrastructure // @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#include "XCoreMachineFunctionInfo.h" #include "XCoreInstrInfo.h" +#include "XCoreMachineFunctionInfo.h" #include "XCore.h" #include "llvm/MC/MCContext.h" #include "llvm/CodeGen/MachineInstrBuilder.h" diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h index d354802ee03f..42eeed8370f4 100644 --- a/lib/Target/XCore/XCoreInstrInfo.h +++ b/lib/Target/XCore/XCoreInstrInfo.h @@ -1,4 +1,4 @@ -//===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===// +//===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -14,8 +14,8 @@ #ifndef XCOREINSTRUCTIONINFO_H #define XCOREINSTRUCTIONINFO_H -#include "llvm/Target/TargetInstrInfo.h" #include "XCoreRegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" #define GET_INSTRINFO_HEADER #include "XCoreGenInstrInfo.inc" diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 4d2e93bc7a04..b25a08d25c1a 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -1,4 +1,4 @@ -//===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===// +//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/XCore/XCoreMachineFunctionInfo.cpp b/lib/Target/XCore/XCoreMachineFunctionInfo.cpp new file mode 100644 index 000000000000..7ca06729120e --- /dev/null +++ b/lib/Target/XCore/XCoreMachineFunctionInfo.cpp @@ -0,0 +1,14 @@ +//===-- XCoreMachineFuctionInfo.cpp - XCore machine function info ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "XCoreMachineFunctionInfo.h" + +using namespace llvm; + +void XCoreFunctionInfo::anchor() { } diff --git a/lib/Target/XCore/XCoreMachineFunctionInfo.h b/lib/Target/XCore/XCoreMachineFunctionInfo.h index a575a0f69541..f869fcf26de3 100644 --- a/lib/Target/XCore/XCoreMachineFunctionInfo.h +++ b/lib/Target/XCore/XCoreMachineFunctionInfo.h @@ -1,4 +1,4 @@ -//====- XCoreMachineFuctionInfo.h - XCore machine function info -*- C++ -*-===// +//===-- XCoreMachineFuctionInfo.h - XCore machine function info -*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -26,7 +26,7 @@ class Function; /// XCoreFunctionInfo - This class is derived from MachineFunction private /// XCore target-specific information for each MachineFunction. class XCoreFunctionInfo : public MachineFunctionInfo { -private: + virtual void anchor(); bool UsesLR; int LRSpillSlot; int FPSpillSlot; diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 1b78b373fffa..f3b4b4c4f88a 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -1,4 +1,4 @@ -//===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===// +//===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===// // // The LLVM Compiler Infrastructure // @@ -14,6 +14,8 @@ #include "XCoreRegisterInfo.h" #include "XCoreMachineFunctionInfo.h" #include "XCore.h" +#include "llvm/Type.h" +#include "llvm/Function.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -24,8 +26,6 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Type.h" -#include "llvm/Function.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" @@ -54,28 +54,14 @@ static inline bool isImmU16(unsigned val) { return val < (1 << 16); } -static const unsigned XCore_ArgRegs[] = { - XCore::R0, XCore::R1, XCore::R2, XCore::R3 -}; - -const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF) -{ - return XCore_ArgRegs; -} - -unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF) -{ - return array_lengthof(XCore_ArgRegs); -} - bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) { return MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry(); } -const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) +const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - static const unsigned CalleeSavedRegs[] = { + static const uint16_t CalleeSavedRegs[] = { XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::LR, 0 diff --git a/lib/Target/XCore/XCoreRegisterInfo.h b/lib/Target/XCore/XCoreRegisterInfo.h index 5c28f39d8788..7391cfdf0734 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.h +++ b/lib/Target/XCore/XCoreRegisterInfo.h @@ -1,4 +1,4 @@ -//===- XCoreRegisterInfo.h - XCore Register Information Impl ----*- C++ -*-===// +//===-- XCoreRegisterInfo.h - XCore Register Information Impl ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -44,7 +44,7 @@ public: /// Code Generation virtual methods... - const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; + const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; BitVector getReservedRegs(const MachineFunction &MF) const; @@ -62,15 +62,6 @@ public: // Debug information queries. unsigned getFrameRegister(const MachineFunction &MF) const; - //! Return the array of argument passing registers - /*! - \note The size of this array is returned by getArgRegsSize(). - */ - static const unsigned *getArgRegs(const MachineFunction *MF = 0); - - //! Return the size of the argument passing register array - static unsigned getNumArgRegs(const MachineFunction *MF = 0); - //! Return whether to emit frame moves static bool needsFrameMoves(const MachineFunction &MF); }; diff --git a/lib/Target/XCore/XCoreRegisterInfo.td b/lib/Target/XCore/XCoreRegisterInfo.td index c3542304a4ec..9edfda1f5007 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.td +++ b/lib/Target/XCore/XCoreRegisterInfo.td @@ -1,4 +1,4 @@ -//===- XCoreRegisterInfo.td - XCore Register defs ----------*- tablegen -*-===// +//===-- XCoreRegisterInfo.td - XCore Register defs ---------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/XCore/XCoreSubtarget.cpp b/lib/Target/XCore/XCoreSubtarget.cpp index b4e992710419..8cfb77089f31 100644 --- a/lib/Target/XCore/XCoreSubtarget.cpp +++ b/lib/Target/XCore/XCoreSubtarget.cpp @@ -1,4 +1,4 @@ -//===- XCoreSubtarget.cpp - XCore Subtarget Information -----------*- C++ -*-=// +//===-- XCoreSubtarget.cpp - XCore Subtarget Information ------------------===// // // The LLVM Compiler Infrastructure // @@ -21,6 +21,8 @@ using namespace llvm; +void XCoreSubtarget::anchor() { } + XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) : XCoreGenSubtargetInfo(TT, CPU, FS) diff --git a/lib/Target/XCore/XCoreSubtarget.h b/lib/Target/XCore/XCoreSubtarget.h index 7b29fa236710..8d0f254e087a 100644 --- a/lib/Target/XCore/XCoreSubtarget.h +++ b/lib/Target/XCore/XCoreSubtarget.h @@ -1,4 +1,4 @@ -//=====-- XCoreSubtarget.h - Define Subtarget for the XCore -----*- C++ -*--==// +//===-- XCoreSubtarget.h - Define Subtarget for the XCore -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -25,6 +25,7 @@ namespace llvm { class StringRef; class XCoreSubtarget : public XCoreGenSubtargetInfo { + virtual void anchor(); public: /// This constructor initializes the data members to match that diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index fdc5d35036bb..f65297e54a79 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -14,6 +14,7 @@ #include "XCore.h" #include "llvm/Module.h" #include "llvm/PassManager.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -21,8 +22,10 @@ using namespace llvm; /// XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM) - : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), @@ -32,9 +35,27 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, TSInfo(*this) { } -bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { - PM.add(createXCoreISelDag(*this)); +namespace { +/// XCore Code Generator Pass Configuration Options. +class XCorePassConfig : public TargetPassConfig { +public: + XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + XCoreTargetMachine &getXCoreTargetMachine() const { + return getTM<XCoreTargetMachine>(); + } + + virtual bool addInstSelector(); +}; +} // namespace + +TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) { + return new XCorePassConfig(this, PM); +} + +bool XCorePassConfig::addInstSelector() { + PM.add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel())); return false; } diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index 83d09d6df49d..254668142aaf 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -14,13 +14,13 @@ #ifndef XCORETARGETMACHINE_H #define XCORETARGETMACHINE_H -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetData.h" #include "XCoreFrameLowering.h" #include "XCoreSubtarget.h" #include "XCoreInstrInfo.h" #include "XCoreISelLowering.h" #include "XCoreSelectionDAGInfo.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetData.h" namespace llvm { @@ -33,8 +33,9 @@ class XCoreTargetMachine : public LLVMTargetMachine { XCoreSelectionDAGInfo TSInfo; public: XCoreTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const XCoreFrameLowering *getFrameLowering() const { @@ -55,7 +56,7 @@ public: virtual const TargetData *getTargetData() const { return &DataLayout; } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; } // end namespace llvm diff --git a/lib/Target/XCore/XCoreTargetObjectFile.h b/lib/Target/XCore/XCoreTargetObjectFile.h index 7424c78be305..27875e783b33 100644 --- a/lib/Target/XCore/XCoreTargetObjectFile.h +++ b/lib/Target/XCore/XCoreTargetObjectFile.h @@ -1,4 +1,4 @@ -//===-- llvm/Target/XCoreTargetObjectFile.h - XCore Object Info -*- C++ -*-===// +//===-- XCoreTargetObjectFile.h - XCore Object Info -------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // |