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Diffstat (limited to 'llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp')
-rw-r--r--llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index f8f99b7e87f2..e3c4e86d203b 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -484,6 +484,16 @@ public:
MachineOperand &DefMO = MI.getOperand(I);
assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand");
Register Reg = DefMO.getReg();
+ assert(DefMO.isTied() && "Def is expected to be tied");
+ // We skipped undef uses and did not spill them, so we should not
+ // proceed with defs here.
+ if (MI.getOperand(MI.findTiedOperandIdx(I)).isUndef()) {
+ if (AllowGCPtrInCSR) {
+ NewIndices.push_back(NewMI->getNumOperands());
+ MIB.addReg(Reg, RegState::Define);
+ }
+ continue;
+ }
if (!AllowGCPtrInCSR) {
assert(is_contained(RegsToSpill, Reg));
RegsToReload.push_back(Reg);