diff options
Diffstat (limited to 'llvm/lib/CodeGen/MIRParser/MIParser.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MIRParser/MIParser.cpp | 201 |
1 files changed, 161 insertions, 40 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index e3d6b59c5077..525f49347fc4 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -16,8 +16,6 @@ #include "llvm/ADT/APSInt.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/None.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" @@ -377,10 +375,11 @@ struct ParsedMachineOperand { MachineOperand Operand; StringRef::iterator Begin; StringRef::iterator End; - Optional<unsigned> TiedDefIdx; + std::optional<unsigned> TiedDefIdx; ParsedMachineOperand(const MachineOperand &Operand, StringRef::iterator Begin, - StringRef::iterator End, Optional<unsigned> &TiedDefIdx) + StringRef::iterator End, + std::optional<unsigned> &TiedDefIdx) : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) { if (TiedDefIdx) assert(Operand.isReg() && Operand.isUse() && @@ -449,7 +448,8 @@ public: bool parseSubRegisterIndex(unsigned &SubReg); bool parseRegisterTiedDefIndex(unsigned &TiedDefIdx); bool parseRegisterOperand(MachineOperand &Dest, - Optional<unsigned> &TiedDefIdx, bool IsDef = false); + std::optional<unsigned> &TiedDefIdx, + bool IsDef = false); bool parseImmediateOperand(MachineOperand &Dest); bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, const Constant *&C); @@ -485,19 +485,22 @@ public: bool parsePredicateOperand(MachineOperand &Dest); bool parseShuffleMaskOperand(MachineOperand &Dest); bool parseTargetIndexOperand(MachineOperand &Dest); + bool parseDbgInstrRefOperand(MachineOperand &Dest); bool parseCustomRegisterMaskOperand(MachineOperand &Dest); bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest); bool parseMachineOperand(const unsigned OpCode, const unsigned OpIdx, MachineOperand &Dest, - Optional<unsigned> &TiedDefIdx); + std::optional<unsigned> &TiedDefIdx); bool parseMachineOperandAndTargetFlags(const unsigned OpCode, const unsigned OpIdx, MachineOperand &Dest, - Optional<unsigned> &TiedDefIdx); + std::optional<unsigned> &TiedDefIdx); bool parseOffset(int64_t &Offset); + bool parseIRBlockAddressTaken(BasicBlock *&BB); bool parseAlignment(uint64_t &Alignment); bool parseAddrspace(unsigned &Addrspace); - bool parseSectionID(Optional<MBBSectionID> &SID); + bool parseSectionID(std::optional<MBBSectionID> &SID); + bool parseBBID(std::optional<unsigned> &BBID); bool parseOperandsOffset(MachineOperand &Op); bool parseIRValue(const Value *&V); bool parseMemoryOperandFlag(MachineMemOperand::Flags &Flags); @@ -508,6 +511,7 @@ public: bool parseMachineMemoryOperand(MachineMemOperand *&Dest); bool parsePreOrPostInstrSymbol(MCSymbol *&Symbol); bool parseHeapAllocMarker(MDNode *&Node); + bool parsePCSections(MDNode *&Node); bool parseTargetImmMnemonic(const unsigned OpCode, const unsigned OpIdx, MachineOperand &Dest, const MIRFormatter &MF); @@ -593,7 +597,7 @@ bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) { // Create a diagnostic for a YAML string literal. Error = SMDiagnostic(SM, SMLoc(), Buffer.getBufferIdentifier(), 1, Loc - Source.data(), SourceMgr::DK_Error, Msg.str(), - Source, None, None); + Source, std::nullopt, std::nullopt); return true; } @@ -639,7 +643,7 @@ bool MIParser::consumeIfPresent(MIToken::TokenKind TokenKind) { } // Parse Machine Basic Block Section ID. -bool MIParser::parseSectionID(Optional<MBBSectionID> &SID) { +bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) { assert(Token.is(MIToken::kw_bbsections)); lex(); if (Token.is(MIToken::IntegerLiteral)) { @@ -660,6 +664,18 @@ bool MIParser::parseSectionID(Optional<MBBSectionID> &SID) { return false; } +// Parse Machine Basic Block ID. +bool MIParser::parseBBID(std::optional<unsigned> &BBID) { + assert(Token.is(MIToken::kw_bb_id)); + lex(); + unsigned Value = 0; + if (getUnsigned(Value)) + return error("Unknown BB ID"); + BBID = Value; + lex(); + return false; +} + bool MIParser::parseBasicBlockDefinition( DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) { assert(Token.is(MIToken::MachineBasicBlockLabel)); @@ -669,21 +685,27 @@ bool MIParser::parseBasicBlockDefinition( auto Loc = Token.location(); auto Name = Token.stringValue(); lex(); - bool HasAddressTaken = false; + bool MachineBlockAddressTaken = false; + BasicBlock *AddressTakenIRBlock = nullptr; bool IsLandingPad = false; bool IsInlineAsmBrIndirectTarget = false; bool IsEHFuncletEntry = false; - Optional<MBBSectionID> SectionID; + std::optional<MBBSectionID> SectionID; uint64_t Alignment = 0; + std::optional<unsigned> BBID; BasicBlock *BB = nullptr; if (consumeIfPresent(MIToken::lparen)) { do { // TODO: Report an error when multiple same attributes are specified. switch (Token.kind()) { - case MIToken::kw_address_taken: - HasAddressTaken = true; + case MIToken::kw_machine_block_address_taken: + MachineBlockAddressTaken = true; lex(); break; + case MIToken::kw_ir_block_address_taken: + if (parseIRBlockAddressTaken(AddressTakenIRBlock)) + return true; + break; case MIToken::kw_landing_pad: IsLandingPad = true; lex(); @@ -701,6 +723,7 @@ bool MIParser::parseBasicBlockDefinition( return true; break; case MIToken::IRBlock: + case MIToken::NamedIRBlock: // TODO: Report an error when both name and ir block are specified. if (parseIRBlock(BB, MF.getFunction())) return true; @@ -710,6 +733,10 @@ bool MIParser::parseBasicBlockDefinition( if (parseSectionID(SectionID)) return true; break; + case MIToken::kw_bb_id: + if (parseBBID(BBID)) + return true; + break; default: break; } @@ -736,15 +763,24 @@ bool MIParser::parseBasicBlockDefinition( Twine(ID)); if (Alignment) MBB->setAlignment(Align(Alignment)); - if (HasAddressTaken) - MBB->setHasAddressTaken(); + if (MachineBlockAddressTaken) + MBB->setMachineBlockAddressTaken(); + if (AddressTakenIRBlock) + MBB->setAddressTakenIRBlock(AddressTakenIRBlock); MBB->setIsEHPad(IsLandingPad); MBB->setIsInlineAsmBrIndirectTarget(IsInlineAsmBrIndirectTarget); MBB->setIsEHFuncletEntry(IsEHFuncletEntry); if (SectionID) { - MBB->setSectionID(SectionID.value()); + MBB->setSectionID(*SectionID); MF.setBBSectionsType(BasicBlockSection::List); } + if (BBID.has_value()) { + // BBSectionsType is set to `List` if any basic blocks has `SectionID`. + // Here, we set it to `Labels` if it hasn't been set above. + if (!MF.hasBBSections()) + MF.setBBSectionsType(BasicBlockSection::Labels); + MBB->setBBID(BBID.value()); + } return false; } @@ -987,7 +1023,7 @@ bool MIParser::parse(MachineInstr *&MI) { SmallVector<ParsedMachineOperand, 8> Operands; while (Token.isRegister() || Token.isRegisterFlag()) { auto Loc = Token.location(); - Optional<unsigned> TiedDefIdx; + std::optional<unsigned> TiedDefIdx; if (parseRegisterOperand(MO, TiedDefIdx, /*IsDef=*/true)) return true; Operands.push_back( @@ -1007,11 +1043,13 @@ bool MIParser::parse(MachineInstr *&MI) { while (!Token.isNewlineOrEOF() && Token.isNot(MIToken::kw_pre_instr_symbol) && Token.isNot(MIToken::kw_post_instr_symbol) && Token.isNot(MIToken::kw_heap_alloc_marker) && + Token.isNot(MIToken::kw_pcsections) && + Token.isNot(MIToken::kw_cfi_type) && Token.isNot(MIToken::kw_debug_location) && Token.isNot(MIToken::kw_debug_instr_number) && Token.isNot(MIToken::coloncolon) && Token.isNot(MIToken::lbrace)) { auto Loc = Token.location(); - Optional<unsigned> TiedDefIdx; + std::optional<unsigned> TiedDefIdx; if (parseMachineOperandAndTargetFlags(OpCode, Operands.size(), MO, TiedDefIdx)) return true; Operands.push_back( @@ -1036,6 +1074,24 @@ bool MIParser::parse(MachineInstr *&MI) { if (Token.is(MIToken::kw_heap_alloc_marker)) if (parseHeapAllocMarker(HeapAllocMarker)) return true; + MDNode *PCSections = nullptr; + if (Token.is(MIToken::kw_pcsections)) + if (parsePCSections(PCSections)) + return true; + + unsigned CFIType = 0; + if (Token.is(MIToken::kw_cfi_type)) { + lex(); + if (Token.isNot(MIToken::IntegerLiteral)) + return error("expected an integer literal after 'cfi-type'"); + // getUnsigned is sufficient for 32-bit integers. + if (getUnsigned(CFIType)) + return true; + lex(); + // Lex past trailing comma if present. + if (Token.is(MIToken::comma)) + lex(); + } unsigned InstrNum = 0; if (Token.is(MIToken::kw_debug_instr_number)) { @@ -1116,6 +1172,10 @@ bool MIParser::parse(MachineInstr *&MI) { MI->setPostInstrSymbol(MF, PostInstrSymbol); if (HeapAllocMarker) MI->setHeapAllocMarker(MF, HeapAllocMarker); + if (PCSections) + MI->setPCSections(MF, PCSections); + if (CFIType) + MI->setCFIType(MF, CFIType); if (!MemOperands.empty()) MI->setMemRefs(MF, MemOperands); if (InstrNum) @@ -1322,7 +1382,7 @@ bool MIParser::parseMetadata(Metadata *&MD) { // Forward reference. auto &FwdRef = PFS.MachineForwardRefMDNodes[ID]; FwdRef = std::make_pair( - MDTuple::getTemporary(MF.getFunction().getContext(), None), Loc); + MDTuple::getTemporary(MF.getFunction().getContext(), std::nullopt), Loc); PFS.MachineMetadataNodes[ID].reset(FwdRef.first.get()); MD = FwdRef.first.get(); @@ -1336,7 +1396,7 @@ static const char *printImplicitRegisterFlag(const MachineOperand &MO) { static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg) { - assert(Register::isPhysicalRegister(Reg) && "expected phys reg"); + assert(Reg.isPhysical() && "expected phys reg"); return StringRef(TRI->getName(Reg)).lower(); } @@ -1359,14 +1419,10 @@ bool MIParser::verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands, // Gather all the expected implicit operands. SmallVector<MachineOperand, 4> ImplicitOperands; - if (MCID.ImplicitDefs) - for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs) - ImplicitOperands.push_back( - MachineOperand::CreateReg(*ImpDefs, true, true)); - if (MCID.ImplicitUses) - for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses) - ImplicitOperands.push_back( - MachineOperand::CreateReg(*ImpUses, false, true)); + for (MCPhysReg ImpDef : MCID.implicit_defs()) + ImplicitOperands.push_back(MachineOperand::CreateReg(ImpDef, true, true)); + for (MCPhysReg ImpUse : MCID.implicit_uses()) + ImplicitOperands.push_back(MachineOperand::CreateReg(ImpUse, false, true)); const auto *TRI = MF.getSubtarget().getRegisterInfo(); assert(TRI && "Expected target register info"); @@ -1648,7 +1704,7 @@ bool MIParser::assignRegisterTies(MachineInstr &MI, } bool MIParser::parseRegisterOperand(MachineOperand &Dest, - Optional<unsigned> &TiedDefIdx, + std::optional<unsigned> &TiedDefIdx, bool IsDef) { unsigned Flags = IsDef ? RegState::Define : 0; while (Token.isRegisterFlag()) { @@ -1666,11 +1722,11 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, if (Token.is(MIToken::dot)) { if (parseSubRegisterIndex(SubReg)) return true; - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) return error("subregister index expects a virtual register"); } if (Token.is(MIToken::colon)) { - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) return error("register class specification expects a virtual register"); lex(); if (parseRegisterClassOrBank(*RegInfo)) @@ -1700,7 +1756,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, } } else if (consumeIfPresent(MIToken::lparen)) { // Virtual registers may have a tpe with GlobalISel. - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) return error("unexpected type on physical register"); LLT Ty; @@ -1715,7 +1771,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, MRI.setRegClassOrRegBank(Reg, static_cast<RegisterBank *>(nullptr)); MRI.setType(Reg, Ty); - } else if (Register::isVirtualRegister(Reg)) { + } else if (Reg.isVirtual()) { // Generic virtual registers must have a type. // If we end up here this means the type hasn't been specified and // this is bad! @@ -1744,9 +1800,12 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool MIParser::parseImmediateOperand(MachineOperand &Dest) { assert(Token.is(MIToken::IntegerLiteral)); const APSInt &Int = Token.integerValue(); - if (Int.getMinSignedBits() > 64) + if (auto SImm = Int.trySExtValue(); Int.isSigned() && SImm.has_value()) + Dest = MachineOperand::CreateImm(*SImm); + else if (auto UImm = Int.tryZExtValue(); !Int.isSigned() && UImm.has_value()) + Dest = MachineOperand::CreateImm(*UImm); + else return error("integer literal is too large to be an immediate operand"); - Dest = MachineOperand::CreateImm(Int.getExtValue()); lex(); return false; } @@ -1813,7 +1872,7 @@ bool MIParser::parseIRConstant(StringRef::iterator Loc, const Constant *&C) { return false; } -// See LLT implemntation for bit size limits. +// See LLT implementation for bit size limits. static bool verifyScalarSize(uint64_t Size) { return Size != 0 && isUInt<16>(Size); } @@ -2681,6 +2740,37 @@ bool MIParser::parseShuffleMaskOperand(MachineOperand &Dest) { return false; } +bool MIParser::parseDbgInstrRefOperand(MachineOperand &Dest) { + assert(Token.is(MIToken::kw_dbg_instr_ref)); + + lex(); + if (expectAndConsume(MIToken::lparen)) + return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)"); + + if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isNegative()) + return error("expected unsigned integer for instruction index"); + uint64_t InstrIdx = Token.integerValue().getZExtValue(); + assert(InstrIdx <= std::numeric_limits<unsigned>::max() && + "Instruction reference's instruction index is too large"); + lex(); + + if (expectAndConsume(MIToken::comma)) + return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)"); + + if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isNegative()) + return error("expected unsigned integer for operand index"); + uint64_t OpIdx = Token.integerValue().getZExtValue(); + assert(OpIdx <= std::numeric_limits<unsigned>::max() && + "Instruction reference's operand index is too large"); + lex(); + + if (expectAndConsume(MIToken::rparen)) + return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)"); + + Dest = MachineOperand::CreateDbgInstrRef(InstrIdx, OpIdx); + return false; +} + bool MIParser::parseTargetIndexOperand(MachineOperand &Dest) { assert(Token.is(MIToken::kw_target_index)); lex(); @@ -2754,7 +2844,7 @@ bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) { bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx, MachineOperand &Dest, - Optional<unsigned> &TiedDefIdx) { + std::optional<unsigned> &TiedDefIdx) { switch (Token.kind()) { case MIToken::kw_implicit: case MIToken::kw_implicit_define: @@ -2832,6 +2922,8 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx, return parsePredicateOperand(Dest); case MIToken::kw_shufflemask: return parseShuffleMaskOperand(Dest); + case MIToken::kw_dbg_instr_ref: + return parseDbgInstrRefOperand(Dest); case MIToken::Error: return true; case MIToken::Identifier: @@ -2848,7 +2940,7 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx, if (const auto *Formatter = TII->getMIRFormatter()) { return parseTargetImmMnemonic(OpCode, OpIdx, Dest, *Formatter); } - LLVM_FALLTHROUGH; + [[fallthrough]]; } default: // FIXME: Parse the MCSymbol machine operand. @@ -2859,7 +2951,7 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx, bool MIParser::parseMachineOperandAndTargetFlags( const unsigned OpCode, const unsigned OpIdx, MachineOperand &Dest, - Optional<unsigned> &TiedDefIdx) { + std::optional<unsigned> &TiedDefIdx) { unsigned TF = 0; bool HasTargetFlags = false; if (Token.is(MIToken::kw_target_flags)) { @@ -2918,6 +3010,19 @@ bool MIParser::parseOffset(int64_t &Offset) { return false; } +bool MIParser::parseIRBlockAddressTaken(BasicBlock *&BB) { + assert(Token.is(MIToken::kw_ir_block_address_taken)); + lex(); + if (Token.isNot(MIToken::IRBlock) && Token.isNot(MIToken::NamedIRBlock)) + return error("expected basic block after 'ir_block_address_taken'"); + + if (parseIRBlock(BB, MF.getFunction())) + return true; + + lex(); + return false; +} + bool MIParser::parseAlignment(uint64_t &Alignment) { assert(Token.is(MIToken::kw_align) || Token.is(MIToken::kw_basealign)); lex(); @@ -3378,6 +3483,22 @@ bool MIParser::parseHeapAllocMarker(MDNode *&Node) { return false; } +bool MIParser::parsePCSections(MDNode *&Node) { + assert(Token.is(MIToken::kw_pcsections) && + "Invalid token for a PC sections!"); + lex(); + parseMDNode(Node); + if (!Node) + return error("expected a MDNode after 'pcsections'"); + if (Token.isNewlineOrEOF() || Token.is(MIToken::coloncolon) || + Token.is(MIToken::lbrace)) + return false; + if (Token.isNot(MIToken::comma)) + return error("expected ',' before the next machine operand"); + lex(); + return false; +} + static void initSlots2BasicBlocks( const Function &F, DenseMap<unsigned, const BasicBlock *> &Slots2BasicBlocks) { |