diff options
Diffstat (limited to 'llvm/lib/MCA/InstrBuilder.cpp')
| -rw-r--r-- | llvm/lib/MCA/InstrBuilder.cpp | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp index 24e2a9d2f0ce..2bad13601718 100644 --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -259,8 +259,9 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI, // the opcode descriptor (MCInstrDesc). // 2. Uses start at index #(MCDesc.getNumDefs()). // 3. There can only be a single optional register definition, an it is - // always the last operand of the sequence (excluding extra operands - // contributed by variadic opcodes). + // either the last operand of the sequence (excluding extra operands + // contributed by variadic opcodes) or one of the explicit register + // definitions. The latter occurs for some Thumb1 instructions. // // These assumptions work quite well for most out-of-order in-tree targets // like x86. This is mainly because the vast majority of instructions is @@ -308,12 +309,18 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI, // The first NumExplicitDefs register operands are expected to be register // definitions. unsigned CurrentDef = 0; + unsigned OptionalDefIdx = MCDesc.getNumOperands() - 1; unsigned i = 0; for (; i < MCI.getNumOperands() && CurrentDef < NumExplicitDefs; ++i) { const MCOperand &Op = MCI.getOperand(i); if (!Op.isReg()) continue; + if (MCDesc.OpInfo[CurrentDef].isOptionalDef()) { + OptionalDefIdx = CurrentDef++; + continue; + } + WriteDescriptor &Write = ID.Writes[CurrentDef]; Write.OpIndex = i; if (CurrentDef < NumWriteLatencyEntries) { @@ -369,7 +376,7 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI, if (MCDesc.hasOptionalDef()) { WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; - Write.OpIndex = MCDesc.getNumOperands() - 1; + Write.OpIndex = OptionalDefIdx; // Assign a default latency for this write. Write.Latency = ID.MaxLatency; Write.SClassOrWriteResourceID = 0; @@ -518,7 +525,8 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI) { if (IsVariant) { unsigned CPUID = SM.getProcessorID(); while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant()) - SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID); + SchedClassID = + STI.resolveVariantSchedClass(SchedClassID, &MCI, &MCII, CPUID); if (!SchedClassID) { return make_error<InstructionError<MCInst>>( |