diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64Subtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 51 |
1 files changed, 12 insertions, 39 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 71b2bb196486..b22eb3b154f5 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -47,17 +47,8 @@ static cl::opt<bool> cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden); -static cl::opt<unsigned> SVEVectorBitsMax( - "aarch64-sve-vector-bits-max", - cl::desc("Assume SVE vector registers are at most this big, " - "with zero meaning no maximum size is assumed."), - cl::init(0), cl::Hidden); - -static cl::opt<unsigned> SVEVectorBitsMin( - "aarch64-sve-vector-bits-min", - cl::desc("Assume SVE vector registers are at least this big, " - "with zero meaning no minimum size is assumed."), - cl::init(0), cl::Hidden); +static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true), + cl::desc("Enable the use of AA during codegen.")); AArch64Subtarget & AArch64Subtarget::initializeSubtargetDependencies(StringRef FS, @@ -86,9 +77,8 @@ void AArch64Subtarget::initializeProperties() { case CortexA35: break; case CortexA53: - PrefFunctionLogAlignment = 3; - break; case CortexA55: + PrefFunctionLogAlignment = 4; break; case CortexA57: MaxInterleaveFactor = 4; @@ -208,14 +198,17 @@ void AArch64Subtarget::initializeProperties() { AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, - const TargetMachine &TM, bool LittleEndian) + const TargetMachine &TM, bool LittleEndian, + unsigned MinSVEVectorSizeInBitsOverride, + unsigned MaxSVEVectorSizeInBitsOverride) : AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()), CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()), IsLittle(LittleEndian), - TargetTriple(TT), FrameLowering(), - InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(), - TLInfo(TM, *this) { + MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride), + MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT), + FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS, CPU)), + TSInfo(), TLInfo(TM, *this) { if (AArch64::isX18ReservedByDefault(TT)) ReserveXRegister.set(18); @@ -354,29 +347,9 @@ void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const { MFI.computeMaxCallFrameSize(MF); } -unsigned AArch64Subtarget::getMaxSVEVectorSizeInBits() const { - assert(HasSVE && "Tried to get SVE vector length without SVE support!"); - assert(SVEVectorBitsMax % 128 == 0 && - "SVE requires vector length in multiples of 128!"); - assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) && - "Minimum SVE vector size should not be larger than its maximum!"); - if (SVEVectorBitsMax == 0) - return 0; - return (std::max(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128; -} - -unsigned AArch64Subtarget::getMinSVEVectorSizeInBits() const { - assert(HasSVE && "Tried to get SVE vector length without SVE support!"); - assert(SVEVectorBitsMin % 128 == 0 && - "SVE requires vector length in multiples of 128!"); - assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) && - "Minimum SVE vector size should not be larger than its maximum!"); - if (SVEVectorBitsMax == 0) - return (SVEVectorBitsMin / 128) * 128; - return (std::min(SVEVectorBitsMin, SVEVectorBitsMax) / 128) * 128; -} - bool AArch64Subtarget::useSVEForFixedLengthVectors() const { // Prefer NEON unless larger SVE registers are available. return hasSVE() && getMinSVEVectorSizeInBits() >= 256; } + +bool AArch64Subtarget::useAA() const { return UseAA; } |
