diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64TargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 57 |
1 files changed, 35 insertions, 22 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index a63b9a97ada5..bec1758a931b 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -148,10 +148,10 @@ static cl::opt<int> EnableGlobalISelAtO( cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0)); -static cl::opt<bool> EnableSVEIntrinsicOpts( - "aarch64-sve-intrinsic-opts", cl::Hidden, - cl::desc("Enable SVE intrinsic opts"), - cl::init(true)); +static cl::opt<bool> + EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, + cl::desc("Enable SVE intrinsic opts"), + cl::init(true)); static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden); @@ -184,6 +184,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() { initializeAArch64SIMDInstrOptPass(*PR); initializeAArch64PreLegalizerCombinerPass(*PR); initializeAArch64PostLegalizerCombinerPass(*PR); + initializeAArch64PostLegalizerLoweringPass(*PR); + initializeAArch64PostSelectOptimizePass(*PR); initializeAArch64PromoteConstantPass(*PR); initializeAArch64RedundantCopyEliminationPass(*PR); initializeAArch64StorePairSuppressPass(*PR); @@ -213,8 +215,6 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian) { - if (Options.getABIName() == "ilp32") - return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128"; if (TT.isOSBinFormatMachO()) { if (TT.getArch() == Triple::aarch64_32) return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128"; @@ -222,9 +222,16 @@ static std::string computeDataLayout(const Triple &TT, } if (TT.isOSBinFormatCOFF()) return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"; - if (LittleEndian) - return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"; - return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"; + std::string Endian = LittleEndian ? "e" : "E"; + std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : ""; + return Endian + "-m:e" + Ptr32 + + "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"; +} + +static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) { + if (CPU.empty() && TT.isArm64e()) + return "apple-a12"; + return CPU; } static Reloc::Model getEffectiveRelocModel(const Triple &TT, @@ -274,7 +281,8 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT, bool LittleEndian) : LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions, LittleEndian), - TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), + TT, computeDefaultCPU(TT, CPU), FS, Options, + getEffectiveRelocModel(TT, RM), getEffectiveAArch64CodeModel(TT, CM, JIT), OL), TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) { initAsmInfo(); @@ -309,6 +317,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT, // MachO/CodeModel::Large, which GlobalISel does not support. if (getOptLevel() <= EnableGlobalISelAtO && TT.getArch() != Triple::aarch64_32 && + TT.getEnvironment() != Triple::GNUILP32 && !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) { setGlobalISel(true); setGlobalISelAbort(GlobalISelAbortMode::Disable); @@ -331,12 +340,10 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); Attribute FSAttr = F.getFnAttribute("target-features"); - std::string CPU = !CPUAttr.hasAttribute(Attribute::None) - ? CPUAttr.getValueAsString().str() - : TargetCPU; - std::string FS = !FSAttr.hasAttribute(Attribute::None) - ? FSAttr.getValueAsString().str() - : TargetFS; + std::string CPU = + CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; + std::string FS = + FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; auto &I = SubtargetMap[CPU + FS]; if (!I) { @@ -453,7 +460,12 @@ void AArch64PassConfig::addIRPasses() { // determine whether it succeeded. We can exploit existing control-flow in // ldrex/strex loops to simplify this, but it needs tidying up. if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) - addPass(createCFGSimplificationPass(1, true, true, false, true)); + addPass(createCFGSimplificationPass(SimplifyCFGOptions() + .forwardSwitchCondToPhi(true) + .convertSwitchToLookupTable(true) + .needCanonicalLoops(false) + .hoistCommonInsts(true) + .sinkCommonInsts(true))); // Run LoopDataPrefetch // @@ -541,13 +553,13 @@ bool AArch64PassConfig::addInstSelector() { } bool AArch64PassConfig::addIRTranslator() { - addPass(new IRTranslator()); + addPass(new IRTranslator(getOptLevel())); return false; } void AArch64PassConfig::addPreLegalizeMachineIR() { bool IsOptNone = getOptLevel() == CodeGenOpt::None; - addPass(createAArch64PreLegalizeCombiner(IsOptNone)); + addPass(createAArch64PreLegalizerCombiner(IsOptNone)); } bool AArch64PassConfig::addLegalizeMachineIR() { @@ -556,11 +568,10 @@ bool AArch64PassConfig::addLegalizeMachineIR() { } void AArch64PassConfig::addPreRegBankSelect() { - // For now we don't add this to the pipeline for -O0. We could do in future - // if we split the combines into separate O0/opt groupings. bool IsOptNone = getOptLevel() == CodeGenOpt::None; if (!IsOptNone) - addPass(createAArch64PostLegalizeCombiner(IsOptNone)); + addPass(createAArch64PostLegalizerCombiner(IsOptNone)); + addPass(createAArch64PostLegalizerLowering()); } bool AArch64PassConfig::addRegBankSelect() { @@ -574,6 +585,8 @@ void AArch64PassConfig::addPreGlobalInstructionSelect() { bool AArch64PassConfig::addGlobalInstructionSelect() { addPass(new InstructionSelect()); + if (getOptLevel() != CodeGenOpt::None) + addPass(createAArch64PostSelectOptimize()); return false; } |