diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 122 |
1 files changed, 111 insertions, 11 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index 38ca7fd4104b..1fe80958917d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -31,6 +31,10 @@ namespace { namespace llvm { +namespace AMDGPU { +struct ImageDimIntrinsicInfo; +} + class AMDGPUInstrInfo; class AMDGPURegisterBankInfo; class GCNSubtarget; @@ -80,28 +84,39 @@ private: MachineOperand getSubOperand64(MachineOperand &MO, const TargetRegisterClass &SubRC, unsigned SubIdx) const; + + bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const; bool selectCOPY(MachineInstr &I) const; bool selectPHI(MachineInstr &I) const; bool selectG_TRUNC(MachineInstr &I) const; bool selectG_SZA_EXT(MachineInstr &I) const; bool selectG_CONSTANT(MachineInstr &I) const; + bool selectG_FNEG(MachineInstr &I) const; + bool selectG_FABS(MachineInstr &I) const; bool selectG_AND_OR_XOR(MachineInstr &I) const; bool selectG_ADD_SUB(MachineInstr &I) const; bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const; bool selectG_EXTRACT(MachineInstr &I) const; bool selectG_MERGE_VALUES(MachineInstr &I) const; bool selectG_UNMERGE_VALUES(MachineInstr &I) const; + bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const; bool selectG_PTR_ADD(MachineInstr &I) const; bool selectG_IMPLICIT_DEF(MachineInstr &I) const; bool selectG_INSERT(MachineInstr &I) const; - bool selectG_INTRINSIC(MachineInstr &I) const; - std::tuple<Register, unsigned, unsigned> - splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const; + bool selectInterpP1F16(MachineInstr &MI) const; + bool selectDivScale(MachineInstr &MI) const; + bool selectIntrinsicIcmp(MachineInstr &MI) const; + bool selectBallot(MachineInstr &I) const; + bool selectG_INTRINSIC(MachineInstr &I) const; - bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const; + bool selectEndCfIntrinsic(MachineInstr &MI) const; bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; + bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; + bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const; + bool selectImageIntrinsic(MachineInstr &MI, + const AMDGPU::ImageDimIntrinsicInfo *Intr) const; bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const; int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const; bool selectG_ICMP(MachineInstr &I) const; @@ -112,15 +127,18 @@ private: void initM0(MachineInstr &I) const; bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const; + bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const; bool selectG_STORE(MachineInstr &I) const; bool selectG_SELECT(MachineInstr &I) const; bool selectG_BRCOND(MachineInstr &I) const; - bool selectG_FRAME_INDEX(MachineInstr &I) const; - bool selectG_PTR_MASK(MachineInstr &I) const; + bool selectG_FRAME_INDEX_GLOBAL_VALUE(MachineInstr &I) const; + bool selectG_PTRMASK(MachineInstr &I) const; bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const; + bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const; + bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const; std::pair<Register, unsigned> - selectVOP3ModsImpl(Register Src) const; + selectVOP3ModsImpl(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns selectVCSRC(MachineOperand &Root) const; @@ -134,11 +152,18 @@ private: selectVOP3OMods(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns selectVOP3Mods(MachineOperand &Root) const; + + ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns selectVOP3Mods_nnan(MachineOperand &Root) const; + std::pair<Register, unsigned> + selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const; + InstructionSelector::ComplexRendererFns - selectVOP3OpSelMods0(MachineOperand &Root) const; + selectVOP3PMods(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns selectVOP3OpSelMods(MachineOperand &Root) const; @@ -163,19 +188,86 @@ private: InstructionSelector::ComplexRendererFns selectMUBUFScratchOffset(MachineOperand &Root) const; - bool isDSOffsetLegal(const MachineRegisterInfo &MRI, - const MachineOperand &Base, - int64_t Offset, unsigned OffsetBits) const; + bool isDSOffsetLegal(Register Base, int64_t Offset, + unsigned OffsetBits) const; + std::pair<Register, unsigned> + selectDS1Addr1OffsetImpl(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns selectDS1Addr1Offset(MachineOperand &Root) const; + std::pair<Register, unsigned> + selectDS64Bit4ByteAlignedImpl(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns + selectDS64Bit4ByteAligned(MachineOperand &Root) const; + + std::pair<Register, int64_t> + getPtrBaseWithConstantOffset(Register Root, + const MachineRegisterInfo &MRI) const; + + // Parse out a chain of up to two g_ptr_add instructions. + // g_ptr_add (n0, _) + // g_ptr_add (n0, (n1 = g_ptr_add n2, n3)) + struct MUBUFAddressData { + Register N0, N2, N3; + int64_t Offset = 0; + }; + + bool shouldUseAddr64(MUBUFAddressData AddrData) const; + + void splitIllegalMUBUFOffset(MachineIRBuilder &B, + Register &SOffset, int64_t &ImmOffset) const; + + MUBUFAddressData parseMUBUFAddress(Register Src) const; + + bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr, + Register &RSrcReg, Register &SOffset, + int64_t &Offset) const; + + bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg, + Register &SOffset, int64_t &Offset) const; + + InstructionSelector::ComplexRendererFns + selectMUBUFAddr64(MachineOperand &Root) const; + + InstructionSelector::ComplexRendererFns + selectMUBUFOffset(MachineOperand &Root) const; + + InstructionSelector::ComplexRendererFns + selectMUBUFOffsetAtomic(MachineOperand &Root) const; + + InstructionSelector::ComplexRendererFns + selectMUBUFAddr64Atomic(MachineOperand &Root) const; + + ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const; + ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const; + void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx = -1) const; void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; + void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const { + renderTruncTImm(MIB, MI, OpIdx); + } + + void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const { + renderTruncTImm(MIB, MI, OpIdx); + } + + void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const { + renderTruncTImm(MIB, MI, OpIdx); + } + + void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const { + renderTruncTImm(MIB, MI, OpIdx); + } + void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; @@ -184,6 +276,14 @@ private: void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; + void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const; + void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const; + void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const; + void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const; bool isInlineImmediate16(int64_t Imm) const; bool isInlineImmediate32(int64_t Imm) const; |