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Diffstat (limited to 'llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp77
1 files changed, 34 insertions, 43 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
index 8c4314e6d6cc..2a920f6feb1c 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -13,11 +13,12 @@
#include "llvm/ADT/StringSwitch.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCValue.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/EndianStream.h"
#include "llvm/TargetParser/TargetParser.h"
@@ -31,19 +32,16 @@ class AMDGPUAsmBackend : public MCAsmBackend {
public:
AMDGPUAsmBackend(const Target &T) : MCAsmBackend(llvm::endianness::little) {}
- unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
-
- void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
- const MCValue &Target, MutableArrayRef<char> Data,
- uint64_t Value, bool IsResolved,
- const MCSubtargetInfo *STI) const override;
+ void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,
+ MutableArrayRef<char> Data, uint64_t Value,
+ bool IsResolved) override;
bool fixupNeedsRelaxation(const MCFixup &Fixup,
uint64_t Value) const override;
void relaxInstruction(MCInst &Inst,
const MCSubtargetInfo &STI) const override;
- bool mayNeedRelaxation(const MCInst &Inst,
+ bool mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand> Operands,
const MCSubtargetInfo &STI) const override;
unsigned getMinimumNopSize() const override;
@@ -51,10 +49,7 @@ public:
const MCSubtargetInfo *STI) const override;
std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
- const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
- bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
- const MCValue &Target, uint64_t Value,
- const MCSubtargetInfo *STI) override;
+ MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;
};
} //End anonymous namespace
@@ -76,12 +71,13 @@ bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
return (((int64_t(Value)/4)-1) == 0x3f);
}
-bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst,
- const MCSubtargetInfo &STI) const {
+bool AMDGPUAsmBackend::mayNeedRelaxation(unsigned Opcode,
+ ArrayRef<MCOperand> Operands,
+ const MCSubtargetInfo &STI) const {
if (!STI.hasFeature(AMDGPU::FeatureOffset3fBug))
return false;
- if (AMDGPU::getSOPPWithRelaxation(Inst.getOpcode()) >= 0)
+ if (AMDGPU::getSOPPWithRelaxation(Opcode) >= 0)
return true;
return false;
@@ -99,7 +95,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
return 2;
case FK_SecRel_4:
case FK_Data_4:
- case FK_PCRel_4:
return 4;
case FK_SecRel_8:
case FK_Data_8:
@@ -113,7 +108,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
MCContext *Ctx) {
int64_t SignedValue = static_cast<int64_t>(Value);
- switch (Fixup.getTargetKind()) {
+ switch (Fixup.getKind()) {
case AMDGPU::fixup_si_sopp_br: {
int64_t BrImm = (SignedValue - 4) / 4;
@@ -126,7 +121,6 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
case FK_Data_2:
case FK_Data_4:
case FK_Data_8:
- case FK_PCRel_4:
case FK_SecRel_4:
return Value;
default:
@@ -134,15 +128,17 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
}
}
-void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
+void AMDGPUAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
const MCValue &Target,
MutableArrayRef<char> Data, uint64_t Value,
- bool IsResolved,
- const MCSubtargetInfo *STI) const {
- if (Fixup.getKind() >= FirstLiteralRelocationKind)
+ bool IsResolved) {
+ if (Target.getSpecifier())
+ IsResolved = false;
+ maybeAddReloc(F, Fixup, Target, Value, IsResolved);
+ if (mc::isRelocation(Fixup.getKind()))
return;
- Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
+ Value = adjustFixupValue(Fixup, Value, &getContext());
if (!Value)
return; // Doesn't change encoding.
@@ -176,49 +172,44 @@ AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
return std::nullopt;
}
-const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
- MCFixupKind Kind) const {
+MCFixupKindInfo AMDGPUAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
- // name offset bits flags
- { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
+ // name offset bits flags
+ {"fixup_si_sopp_br", 0, 16, 0},
};
- if (Kind >= FirstLiteralRelocationKind)
- return MCAsmBackend::getFixupKindInfo(FK_NONE);
+ if (mc::isRelocation(Kind))
+ return {};
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
- assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
+ assert(unsigned(Kind - FirstTargetFixupKind) < AMDGPU::NumTargetFixupKinds &&
"Invalid kind!");
return Infos[Kind - FirstTargetFixupKind];
}
-bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &,
- const MCFixup &Fixup,
- const MCValue &, const uint64_t,
- const MCSubtargetInfo *STI) {
- return Fixup.getKind() >= FirstLiteralRelocationKind;
-}
-
unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
return 4;
}
bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
const MCSubtargetInfo *STI) const {
- // If the count is not 4-byte aligned, we must be writing data into the text
- // section (otherwise we have unaligned instructions, and thus have far
- // bigger problems), so just write zeros instead.
- OS.write_zeros(Count % 4);
+ // If the count is not aligned to the minimum instruction alignment, we must
+ // be writing data into the text section (otherwise we have unaligned
+ // instructions, and thus have far bigger problems), so just write zeros
+ // instead.
+ unsigned MinInstAlignment = getContext().getAsmInfo()->getMinInstAlignment();
+ OS.write_zeros(Count % MinInstAlignment);
// We are properly aligned, so write NOPs as requested.
- Count /= 4;
+ Count /= MinInstAlignment;
// FIXME: R600 support.
// s_nop 0
const uint32_t Encoded_S_NOP_0 = 0xbf800000;
+ assert(MinInstAlignment == sizeof(Encoded_S_NOP_0));
for (uint64_t I = 0; I != Count; ++I)
support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian);
@@ -238,7 +229,7 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
public:
ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)
- : AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
+ : AMDGPUAsmBackend(T), Is64Bit(TT.isAMDGCN()),
HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
switch (TT.getOS()) {
case Triple::AMDHSA:
generated by cgit v1.3 (git 2.53.0) at 2026-07-30 02:47:54 +0000