diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp index cec7f563f480..b0620663a230 100644 --- a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -56,9 +56,8 @@ using namespace llvm; #define DEBUG_TYPE "vec-merger" -static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { - assert(MRI.isSSA()); - if (Register::isPhysicalRegister(Reg)) +static bool isImplicitlyDef(MachineRegisterInfo &MRI, Register Reg) { + if (Reg.isPhysical()) return false; const MachineInstr *MI = MRI.getUniqueVRegDef(Reg); return MI && MI->isImplicitDef(); @@ -69,8 +68,8 @@ namespace { class RegSeqInfo { public: MachineInstr *Instr; - DenseMap<unsigned, unsigned> RegToChan; - std::vector<unsigned> UndefReg; + DenseMap<Register, unsigned> RegToChan; + std::vector<Register> UndefReg; RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { assert(MI->getOpcode() == R600::REG_SEQUENCE); @@ -102,7 +101,7 @@ private: InstructionSetMap PreviousRegSeqByUndefCount; bool canSwizzle(const MachineInstr &MI) const; - bool areAllUsesSwizzeable(unsigned Reg) const; + bool areAllUsesSwizzeable(Register Reg) const; void SwizzleInput(MachineInstr &, const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const; bool tryMergeVector(const RegSeqInfo *Untouched, RegSeqInfo *ToMerge, @@ -130,6 +129,11 @@ public: MachineFunctionPass::getAnalysisUsage(AU); } + MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties() + .set(MachineFunctionProperties::Property::IsSSA); + } + StringRef getPassName() const override { return "R600 Vector Registers Merge Pass"; } @@ -165,9 +169,9 @@ bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched, RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned>> &Remap) const { unsigned CurrentUndexIdx = 0; - for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(), + for (DenseMap<Register, unsigned>::iterator It = ToMerge->RegToChan.begin(), E = ToMerge->RegToChan.end(); It != E; ++It) { - DenseMap<unsigned, unsigned>::const_iterator PosInUntouched = + DenseMap<Register, unsigned>::const_iterator PosInUntouched = Untouched->RegToChan.find((*It).first); if (PosInUntouched != Untouched->RegToChan.end()) { Remap.push_back(std::pair<unsigned, unsigned> @@ -203,9 +207,9 @@ MachineInstr *R600VectorRegMerger::RebuildVector( DebugLoc DL = Pos->getDebugLoc(); Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); - DenseMap<unsigned, unsigned> UpdatedRegToChan = BaseRSI->RegToChan; - std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg; - for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(), + DenseMap<Register, unsigned> UpdatedRegToChan = BaseRSI->RegToChan; + std::vector<Register> UpdatedUndef = BaseRSI->UndefReg; + for (DenseMap<Register, unsigned>::iterator It = RSI->RegToChan.begin(), E = RSI->RegToChan.end(); It != E; ++It) { Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass); unsigned SubReg = (*It).first; @@ -218,7 +222,7 @@ MachineInstr *R600VectorRegMerger::RebuildVector( .addReg(SubReg) .addImm(Chan); UpdatedRegToChan[SubReg] = Chan; - std::vector<unsigned>::iterator ChanPos = llvm::find(UpdatedUndef, Chan); + std::vector<Register>::iterator ChanPos = llvm::find(UpdatedUndef, Chan); if (ChanPos != UpdatedUndef.end()) UpdatedUndef.erase(ChanPos); assert(!is_contained(UpdatedUndef, Chan) && @@ -279,7 +283,7 @@ void R600VectorRegMerger::SwizzleInput(MachineInstr &MI, } } -bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const { +bool R600VectorRegMerger::areAllUsesSwizzeable(Register Reg) const { for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), E = MRI->use_instr_end(); It != E; ++It) { if (!canSwizzle(*It)) @@ -322,7 +326,7 @@ bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI, } void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) { - for (DenseMap<unsigned, unsigned>::const_iterator + for (DenseMap<Register, unsigned>::const_iterator It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) { PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr); } |