diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 021d797344c5..a93cf5cad411 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -330,8 +330,10 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST) RegPressureIgnoredUnits.resize(getNumRegUnits()); RegPressureIgnoredUnits.set(*regunits(MCRegister::from(AMDGPU::M0)).begin()); - for (auto Reg : AMDGPU::VGPR_HI16RegClass) - RegPressureIgnoredUnits.set(*regunits(Reg).begin()); + for (auto Reg : AMDGPU::VGPR_16RegClass) { + if (AMDGPU::isHi(Reg, *this)) + RegPressureIgnoredUnits.set(*regunits(Reg).begin()); + } // HACK: Until this is fully tablegen'd. static llvm::once_flag InitializeRegSplitPartsFlag; @@ -2661,7 +2663,7 @@ SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const { if (BitWidth == 1) return &AMDGPU::VReg_1RegClass; if (BitWidth == 16) - return &AMDGPU::VGPR_LO16RegClass; + return &AMDGPU::VGPR_16RegClass; if (BitWidth == 32) return &AMDGPU::VGPR_32RegClass; return ST.needsAlignedVGPRs() ? getAlignedVGPRClassForBitWidth(BitWidth) @@ -2808,8 +2810,6 @@ getAlignedVectorSuperClassForBitWidth(unsigned BitWidth) { const TargetRegisterClass * SIRegisterInfo::getVectorSuperClassForBitWidth(unsigned BitWidth) const { - if (BitWidth == 16) - return &AMDGPU::VGPR_LO16RegClass; if (BitWidth == 32) return &AMDGPU::AV_32RegClass; return ST.needsAlignedVGPRs() @@ -3041,8 +3041,6 @@ unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, default: return AMDGPUGenRegisterInfo::getRegPressureLimit(RC, MF); case AMDGPU::VGPR_32RegClassID: - case AMDGPU::VGPR_LO16RegClassID: - case AMDGPU::VGPR_HI16RegClassID: return std::min(ST.getMaxNumVGPRs(Occupancy), ST.getMaxNumVGPRs(MF)); case AMDGPU::SGPR_32RegClassID: case AMDGPU::SGPR_LO16RegClassID: |