diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/VOPInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOPInstructions.td | 38 |
1 files changed, 26 insertions, 12 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index f8a83e5f74c0..282c1002d3c9 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -8,6 +8,7 @@ // dummies for outer let class LetDummies { + bit TRANS; bit ReadsModeReg; bit mayRaiseFPException; bit isCommutable; @@ -69,7 +70,7 @@ class VOP3Common <dag outs, dag ins, string asm = "", let VOP3 = 1; let AsmVariantName = AMDGPUAsmVariants.VOP3; - let AsmMatchConverter = !if(!eq(HasMods,1), "cvtVOP3", ""); + let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); let isCodeGenOnly = 0; @@ -129,7 +130,7 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], let AsmMatchConverter = !if(isVOP3P, "cvtVOP3P", - !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)), + !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), "cvtVOP3", "")); } @@ -296,7 +297,7 @@ class VOP3be <VOPProfile P> : Enc64 { let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); } -class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 { +class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { bits<8> vdst; // neg, neg_hi, op_sel put in srcN_modifiers bits<4> src0_modifiers; @@ -320,8 +321,8 @@ class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 { let Inst{15} = !if(P.HasClamp, clamp{0}, 0); - let Inst{25-16} = op; - let Inst{31-26} = 0x34; //encoding + let Inst{22-16} = op; + let Inst{31-23} = 0x1a7; //encoding let Inst{40-32} = !if(P.HasSrc0, src0, 0); let Inst{49-41} = !if(P.HasSrc1, src1, 0); let Inst{58-50} = !if(P.HasSrc2, src2, 0); @@ -332,7 +333,7 @@ class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 { let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) } -class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 { +class VOP3Pe_MAI <bits<7> op, VOPProfile P> : Enc64 { bits<8> vdst; bits<10> src0; bits<10> src1; @@ -349,8 +350,8 @@ class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 { let Inst{15} = !if(P.HasClamp, clamp{0}, 0); - let Inst{25-16} = op; - let Inst{31-26} = 0x34; //encoding + let Inst{22-16} = op; + let Inst{31-23} = 0x1a7; //encoding let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); let Inst{58-50} = !if(P.HasSrc2, src2, 0); @@ -362,8 +363,8 @@ class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 { } -class VOP3Pe_gfx10 <bits<10> op, VOPProfile P> : VOP3Pe<op, P> { - let Inst{31-26} = 0x33; //encoding +class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { + let Inst{31-23} = 0x198; //encoding } class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { @@ -626,7 +627,7 @@ class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : string Mnemonic = OpName; string AsmOperands = P.AsmDPP; - let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", ""); + let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); let SubtargetPredicate = HasDPP; let AssemblerPredicate = HasDPP; let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, @@ -681,7 +682,7 @@ class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, let DPP = 1; let Size = 8; - let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", ""); + let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); let SubtargetPredicate = HasDPP; let AssemblerPredicate = HasDPP; let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, @@ -776,6 +777,19 @@ class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); } +class getVSrcOp<ValueType vt> { + RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); +} + +// Class for binary integer operations with the clamp bit set for saturation +// TODO: Add sub with negated inline constant pattern. +class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : + GCNPat<(node vt:$src0, vt:$src1), + (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, + DSTCLAMP.ENABLE) +>; + + include "VOPCInstructions.td" include "VOP1Instructions.td" include "VOP2Instructions.td" |