diff options
Diffstat (limited to 'llvm/lib/Target/ARM/MCTargetDesc')
16 files changed, 252 insertions, 220 deletions
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index 6196881a9b8f..9ad595c016c4 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -48,38 +48,43 @@ public: } // end anonymous namespace Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const { - if (STI.getTargetTriple().isOSBinFormatELF() && Name == "R_ARM_NONE") - return FK_NONE; - - return MCAsmBackend::getFixupKind(Name); + if (!STI.getTargetTriple().isOSBinFormatELF()) + return None; + + unsigned Type = llvm::StringSwitch<unsigned>(Name) +#define ELF_RELOC(X, Y) .Case(#X, Y) +#include "llvm/BinaryFormat/ELFRelocs/ARM.def" +#undef ELF_RELOC + .Default(-1u); + if (Type == -1u) + return None; + return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type); } const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { + unsigned IsPCRelConstant = + MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant; const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { // This table *must* be in the order that the fixup_* kinds are defined in // ARMFixupKinds.h. // // Name Offset (bits) Size (bits) Flags - {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant}, {"fixup_t2_ldst_pcrel_12", 0, 32, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, - {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, - {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant}, + {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant}, {"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_pcrel_9", 0, 32, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_thumb_adr_pcrel_10", 0, 8, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, - {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant}, {"fixup_t2_adr_pcrel_12", 0, 32, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, @@ -118,26 +123,22 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { // ARMFixupKinds.h. // // Name Offset (bits) Size (bits) Flags - {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant}, {"fixup_t2_ldst_pcrel_12", 0, 32, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, - {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, - {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant}, + {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant}, {"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_pcrel_9", 0, 32, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_thumb_adr_pcrel_10", 8, 8, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, - {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant}, {"fixup_t2_adr_pcrel_12", 0, 32, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, @@ -172,6 +173,11 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel} }; + // Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require + // any extra processing. + if (Kind >= FirstLiteralRelocationKind) + return MCAsmBackend::getFixupKindInfo(FK_NONE); + if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); @@ -316,9 +322,8 @@ bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, return reasonForFixupRelaxation(Fixup, Value); } -void ARMAsmBackend::relaxInstruction(const MCInst &Inst, - const MCSubtargetInfo &STI, - MCInst &Res) const { +void ARMAsmBackend::relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const { unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI); // Sanity check w/ diagnostic if we get here w/ a bogus instruction. @@ -334,17 +339,18 @@ void ARMAsmBackend::relaxInstruction(const MCInst &Inst, // have to change the operands too. if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && RelaxedOp == ARM::tHINT) { + MCInst Res; Res.setOpcode(RelaxedOp); Res.addOperand(MCOperand::createImm(0)); Res.addOperand(MCOperand::createImm(14)); Res.addOperand(MCOperand::createReg(0)); + Inst = std::move(Res); return; } // The rest of instructions we're relaxing have the same operands. // We just need to update to the proper opcode. - Res = Inst; - Res.setOpcode(RelaxedOp); + Inst.setOpcode(RelaxedOp); } bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { @@ -438,7 +444,6 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm, default: Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type"); return 0; - case FK_NONE: case FK_Data_1: case FK_Data_2: case FK_Data_4: @@ -871,7 +876,7 @@ bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCSymbolRefExpr *A = Target.getSymA(); const MCSymbol *Sym = A ? &A->getSymbol() : nullptr; const unsigned FixupKind = Fixup.getKind(); - if (FixupKind == FK_NONE) + if (FixupKind >= FirstLiteralRelocationKind) return true; if (FixupKind == ARM::fixup_arm_thumb_bl) { assert(Sym && "How did we resolve this?"); @@ -915,9 +920,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { default: llvm_unreachable("Unknown fixup kind!"); - case FK_NONE: - return 0; - case FK_Data_1: case ARM::fixup_arm_thumb_bcc: case ARM::fixup_arm_thumb_cp: @@ -979,9 +981,6 @@ static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { default: llvm_unreachable("Unknown fixup kind!"); - case FK_NONE: - return 0; - case FK_Data_1: return 1; case FK_Data_2: @@ -1037,7 +1036,10 @@ void ARMAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, MutableArrayRef<char> Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo* STI) const { - unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); + unsigned Kind = Fixup.getKind(); + if (Kind >= FirstLiteralRelocationKind) + return; + unsigned NumBytes = getFixupKindNumBytes(Kind); MCContext &Ctx = Asm.getContext(); Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI); if (!Value) @@ -1049,7 +1051,7 @@ void ARMAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, // Used to point to big endian bytes. unsigned FullSizeBytes; if (Endian == support::big) { - FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); + FullSizeBytes = getFixupKindContainerSizeBytes(Kind); assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!"); assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); } @@ -1116,11 +1118,11 @@ uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding( const MCCFIInstruction &Inst = Instrs[i]; switch (Inst.getOperation()) { case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa - CFARegisterOffset = -Inst.getOffset(); + CFARegisterOffset = Inst.getOffset(); CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); break; case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset - CFARegisterOffset = -Inst.getOffset(); + CFARegisterOffset = Inst.getOffset(); break; case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); @@ -1277,35 +1279,6 @@ uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding( return CompactUnwindEncoding | ((FloatRegCount - 1) << 8); } -static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { - ARM::ArchKind AK = ARM::parseArch(Arch); - switch (AK) { - default: - return MachO::CPU_SUBTYPE_ARM_V7; - case ARM::ArchKind::ARMV4T: - return MachO::CPU_SUBTYPE_ARM_V4T; - case ARM::ArchKind::ARMV5T: - case ARM::ArchKind::ARMV5TE: - case ARM::ArchKind::ARMV5TEJ: - return MachO::CPU_SUBTYPE_ARM_V5; - case ARM::ArchKind::ARMV6: - case ARM::ArchKind::ARMV6K: - return MachO::CPU_SUBTYPE_ARM_V6; - case ARM::ArchKind::ARMV7A: - return MachO::CPU_SUBTYPE_ARM_V7; - case ARM::ArchKind::ARMV7S: - return MachO::CPU_SUBTYPE_ARM_V7S; - case ARM::ArchKind::ARMV7K: - return MachO::CPU_SUBTYPE_ARM_V7K; - case ARM::ArchKind::ARMV6M: - return MachO::CPU_SUBTYPE_ARM_V6M; - case ARM::ArchKind::ARMV7M: - return MachO::CPU_SUBTYPE_ARM_V7M; - case ARM::ArchKind::ARMV7EM: - return MachO::CPU_SUBTYPE_ARM_V7EM; - } -} - static MCAsmBackend *createARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, @@ -1315,10 +1288,8 @@ static MCAsmBackend *createARMAsmBackend(const Target &T, switch (TheTriple.getObjectFormat()) { default: llvm_unreachable("unsupported object format"); - case Triple::MachO: { - MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName()); - return new ARMAsmBackendDarwin(T, STI, MRI, CS); - } + case Triple::MachO: + return new ARMAsmBackendDarwin(T, STI, MRI); case Triple::COFF: assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); return new ARMAsmBackendWinCOFF(T, STI); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h index 67722a5e5b64..38c7b30769b3 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -66,8 +66,8 @@ public: const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override; - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override; + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override; bool writeNopData(raw_ostream &OS, uint64_t Count) const override; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h index 87e56940f46d..e27bb134670f 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h @@ -16,16 +16,20 @@ namespace llvm { class ARMAsmBackendDarwin : public ARMAsmBackend { const MCRegisterInfo &MRI; + Triple TT; public: const MachO::CPUSubTypeARM Subtype; ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI, - const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st) - : ARMAsmBackend(T, STI, support::little), MRI(MRI), Subtype(st) {} + const MCRegisterInfo &MRI) + : ARMAsmBackend(T, STI, support::little), MRI(MRI), + TT(STI.getTargetTriple()), + Subtype((MachO::CPUSubTypeARM)cantFail( + MachO::getCPUSubType(STI.getTargetTriple()))) {} std::unique_ptr<MCObjectTargetWriter> createObjectTargetWriter() const override { - return createARMMachObjectWriter(/*Is64Bit=*/false, MachO::CPU_TYPE_ARM, - Subtype); + return createARMMachObjectWriter( + /*Is64Bit=*/false, cantFail(MachO::getCPUType(TT)), Subtype); } uint32_t generateCompactUnwindEncoding( diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h index 6293a2462306..74cd2e681ded 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h @@ -393,9 +393,21 @@ namespace ARMII { // in an IT block). ThumbArithFlagSetting = 1 << 19, - // Whether an instruction can be included in an MVE tail-predicated loop. + // Whether an instruction can be included in an MVE tail-predicated loop, + // though extra validity checks may need to be performed too. ValidForTailPredication = 1 << 20, + // Whether an instruction writes to the top/bottom half of a vector element + // and leaves the other half untouched. + RetainsPreviousHalfElement = 1 << 21, + + // Whether the instruction produces a scalar result from vector operands. + HorizontalReduction = 1 << 22, + + // Whether this instruction produces a vector result that is larger than + // its input, typically reading from the top/bottom halves of the input(s). + DoubleWidthResult = 1 << 23, + //===------------------------------------------------------------------===// // Code domain. DomainShift = 15, diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp index 2c26dd388c05..37d81e4b0af1 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp @@ -53,8 +53,8 @@ ARMELFObjectWriter::ARMELFObjectWriter(uint8_t OSABI) bool ARMELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, unsigned Type) const { - // FIXME: This is extremely conservative. This really needs to use a - // whitelist with a clear explanation for why each realocation needs to + // FIXME: This is extremely conservative. This really needs to use an + // explicit list with a clear explanation for why each realocation needs to // point to the symbol, not to the section. switch (Type) { default: @@ -79,6 +79,9 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel, MCContext &Ctx) const { + unsigned Kind = Fixup.getTargetKind(); + if (Kind >= FirstLiteralRelocationKind) + return Kind - FirstLiteralRelocationKind; MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant(); if (IsPCRel) { @@ -89,9 +92,18 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, case FK_Data_4: switch (Modifier) { default: - llvm_unreachable("Unsupported Modifier"); - case MCSymbolRefExpr::VK_None: + Ctx.reportError(Fixup.getLoc(), + "invalid fixup for 4-byte pc-relative data relocation"); + return ELF::R_ARM_NONE; + case MCSymbolRefExpr::VK_None: { + if (const MCSymbolRefExpr *SymRef = Target.getSymA()) { + // For GNU AS compatibility expressions such as + // _GLOBAL_OFFSET_TABLE_ - label emit a R_ARM_BASE_PREL relocation. + if (SymRef->getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_") + return ELF::R_ARM_BASE_PREL; + } return ELF::R_ARM_REL32; + } case MCSymbolRefExpr::VK_GOTTPOFF: return ELF::R_ARM_TLS_IE32; case MCSymbolRefExpr::VK_ARM_GOT_PREL: @@ -145,30 +157,34 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, return ELF::R_ARM_THM_BF18; } } - switch (Fixup.getTargetKind()) { + switch (Kind) { default: Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on symbol"); return ELF::R_ARM_NONE; - case FK_NONE: - return ELF::R_ARM_NONE; case FK_Data_1: switch (Modifier) { default: - llvm_unreachable("unsupported Modifier"); + Ctx.reportError(Fixup.getLoc(), + "invalid fixup for 1-byte data relocation"); + return ELF::R_ARM_NONE; case MCSymbolRefExpr::VK_None: return ELF::R_ARM_ABS8; } case FK_Data_2: switch (Modifier) { default: - llvm_unreachable("unsupported modifier"); + Ctx.reportError(Fixup.getLoc(), + "invalid fixup for 2-byte data relocation"); + return ELF::R_ARM_NONE; case MCSymbolRefExpr::VK_None: return ELF::R_ARM_ABS16; } case FK_Data_4: switch (Modifier) { default: - llvm_unreachable("Unsupported Modifier"); + Ctx.reportError(Fixup.getLoc(), + "invalid fixup for 4-byte data relocation"); + return ELF::R_ARM_NONE; case MCSymbolRefExpr::VK_ARM_NONE: return ELF::R_ARM_NONE; case MCSymbolRefExpr::VK_GOT: @@ -210,7 +226,8 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, case ARM::fixup_arm_movt_hi16: switch (Modifier) { default: - llvm_unreachable("Unsupported Modifier"); + Ctx.reportError(Fixup.getLoc(), "invalid fixup for ARM MOVT instruction"); + return ELF::R_ARM_NONE; case MCSymbolRefExpr::VK_None: return ELF::R_ARM_MOVT_ABS; case MCSymbolRefExpr::VK_ARM_SBREL: @@ -219,7 +236,8 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, case ARM::fixup_arm_movw_lo16: switch (Modifier) { default: - llvm_unreachable("Unsupported Modifier"); + Ctx.reportError(Fixup.getLoc(), "invalid fixup for ARM MOVW instruction"); + return ELF::R_ARM_NONE; case MCSymbolRefExpr::VK_None: return ELF::R_ARM_MOVW_ABS_NC; case MCSymbolRefExpr::VK_ARM_SBREL: @@ -228,7 +246,9 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, case ARM::fixup_t2_movt_hi16: switch (Modifier) { default: - llvm_unreachable("Unsupported Modifier"); + Ctx.reportError(Fixup.getLoc(), + "invalid fixup for Thumb MOVT instruction"); + return ELF::R_ARM_NONE; case MCSymbolRefExpr::VK_None: return ELF::R_ARM_THM_MOVT_ABS; case MCSymbolRefExpr::VK_ARM_SBREL: @@ -237,7 +257,9 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, case ARM::fixup_t2_movw_lo16: switch (Modifier) { default: - llvm_unreachable("Unsupported Modifier"); + Ctx.reportError(Fixup.getLoc(), + "invalid fixup for Thumb MOVW instruction"); + return ELF::R_ARM_NONE; case MCSymbolRefExpr::VK_None: return ELF::R_ARM_THM_MOVW_ABS_NC; case MCSymbolRefExpr::VK_ARM_SBREL: diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index f558ca8d2d9f..876741d6c343 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -93,7 +93,7 @@ class ARMTargetAsmStreamer : public ARMTargetStreamer { void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) override; void emitArch(ARM::ArchKind Arch) override; - void emitArchExtension(unsigned ArchExt) override; + void emitArchExtension(uint64_t ArchExt) override; void emitObjectArch(ARM::ArchKind Arch) override; void emitFPU(unsigned FPU) override; void emitInst(uint32_t Inst, char Suffix = '\0') override; @@ -177,7 +177,8 @@ void ARMTargetAsmStreamer::switchVendor(StringRef Vendor) {} void ARMTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) { OS << "\t.eabi_attribute\t" << Attribute << ", " << Twine(Value); if (IsVerboseAsm) { - StringRef Name = ARMBuildAttrs::AttrTypeAsString(Attribute); + StringRef Name = + ELFAttrs::attrTypeAsString(Attribute, ARMBuildAttrs::ARMAttributeTags); if (!Name.empty()) OS << "\t@ " << Name; } @@ -193,7 +194,8 @@ void ARMTargetAsmStreamer::emitTextAttribute(unsigned Attribute, default: OS << "\t.eabi_attribute\t" << Attribute << ", \"" << String << "\""; if (IsVerboseAsm) { - StringRef Name = ARMBuildAttrs::AttrTypeAsString(Attribute); + StringRef Name = ELFAttrs::attrTypeAsString( + Attribute, ARMBuildAttrs::ARMAttributeTags); if (!Name.empty()) OS << "\t@ " << Name; } @@ -212,7 +214,9 @@ void ARMTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute, if (!StringValue.empty()) OS << ", \"" << StringValue << "\""; if (IsVerboseAsm) - OS << "\t@ " << ARMBuildAttrs::AttrTypeAsString(Attribute); + OS << "\t@ " + << ELFAttrs::attrTypeAsString(Attribute, + ARMBuildAttrs::ARMAttributeTags); break; } OS << "\n"; @@ -222,7 +226,7 @@ void ARMTargetAsmStreamer::emitArch(ARM::ArchKind Arch) { OS << "\t.arch\t" << ARM::getArchName(Arch) << "\n"; } -void ARMTargetAsmStreamer::emitArchExtension(unsigned ArchExt) { +void ARMTargetAsmStreamer::emitArchExtension(uint64_t ArchExt) { OS << "\t.arch_extension\t" << ARM::getArchExtName(ArchExt) << "\n"; } @@ -238,7 +242,7 @@ void ARMTargetAsmStreamer::finishAttributeSection() {} void ARMTargetAsmStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *S) { - OS << "\t.tlsdescseq\t" << S->getSymbol().getName(); + OS << "\t.tlsdescseq\t" << S->getSymbol().getName() << "\n"; } void ARMTargetAsmStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) { @@ -328,12 +332,8 @@ private: } // Create new attribute item - AttributeItem Item = { - AttributeItem::NumericAttribute, - Attribute, - Value, - StringRef("") - }; + AttributeItem Item = {AttributeItem::NumericAttribute, Attribute, Value, + std::string(StringRef(""))}; Contents.push_back(Item); } @@ -344,17 +344,13 @@ private: if (!OverwriteExisting) return; Item->Type = AttributeItem::TextAttribute; - Item->StringValue = Value; + Item->StringValue = std::string(Value); return; } // Create new attribute item - AttributeItem Item = { - AttributeItem::TextAttribute, - Attribute, - 0, - Value - }; + AttributeItem Item = {AttributeItem::TextAttribute, Attribute, 0, + std::string(Value)}; Contents.push_back(Item); } @@ -366,17 +362,13 @@ private: return; Item->Type = AttributeItem::NumericAndTextAttributes; Item->IntValue = IntValue; - Item->StringValue = StringValue; + Item->StringValue = std::string(StringValue); return; } // Create new attribute item - AttributeItem Item = { - AttributeItem::NumericAndTextAttributes, - Attribute, - IntValue, - StringValue - }; + AttributeItem Item = {AttributeItem::NumericAndTextAttributes, Attribute, + IntValue, std::string(StringValue)}; Contents.push_back(Item); } @@ -452,7 +444,7 @@ public: ~ARMELFStreamer() override = default; - void FinishImpl() override; + void finishImpl() override; // ARM exception handling directives void emitFnStart(); @@ -468,13 +460,13 @@ public: void emitUnwindRaw(int64_t Offset, const SmallVectorImpl<uint8_t> &Opcodes); void emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc) override { - EmitDataMappingSymbol(); + emitDataMappingSymbol(); MCObjectStreamer::emitFill(NumBytes, FillValue, Loc); } - void ChangeSection(MCSection *Section, const MCExpr *Subsection) override { + void changeSection(MCSection *Section, const MCExpr *Subsection) override { LastMappingSymbols[getCurrentSection().first] = std::move(LastEMSInfo); - MCELFStreamer::ChangeSection(Section, Subsection); + MCELFStreamer::changeSection(Section, Subsection); auto LastMappingSymbol = LastMappingSymbols.find(Section); if (LastMappingSymbol != LastMappingSymbols.end()) { LastEMSInfo = std::move(LastMappingSymbol->second); @@ -486,14 +478,14 @@ public: /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to add the appropriate mapping symbol if /// necessary. - void EmitInstruction(const MCInst &Inst, + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override { if (IsThumb) EmitThumbMappingSymbol(); else EmitARMMappingSymbol(); - MCELFStreamer::EmitInstruction(Inst, STI); + MCELFStreamer::emitInstruction(Inst, STI); } void emitInst(uint32_t Inst, char Suffix) { @@ -533,15 +525,15 @@ public: llvm_unreachable("Invalid Suffix"); } - MCELFStreamer::EmitBytes(StringRef(Buffer, Size)); + MCELFStreamer::emitBytes(StringRef(Buffer, Size)); } /// This is one of the functions used to emit data into an ELF section, so the /// ARM streamer overrides it to add the appropriate mapping symbol ($d) if /// necessary. - void EmitBytes(StringRef Data) override { - EmitDataMappingSymbol(); - MCELFStreamer::EmitBytes(Data); + void emitBytes(StringRef Data) override { + emitDataMappingSymbol(); + MCELFStreamer::emitBytes(Data); } void FlushPendingMappingSymbol() { @@ -555,7 +547,7 @@ public: /// This is one of the functions used to emit data into an ELF section, so the /// ARM streamer overrides it to add the appropriate mapping symbol ($d) if /// necessary. - void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override { + void emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override { if (const MCSymbolRefExpr *SRE = dyn_cast_or_null<MCSymbolRefExpr>(Value)) { if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_SBREL && !(Size == 4)) { getContext().reportError(Loc, "relocated expression must be 32-bit"); @@ -564,12 +556,12 @@ public: getOrCreateDataFragment(); } - EmitDataMappingSymbol(); - MCELFStreamer::EmitValueImpl(Value, Size, Loc); + emitDataMappingSymbol(); + MCELFStreamer::emitValueImpl(Value, Size, Loc); } - void EmitAssemblerFlag(MCAssemblerFlag Flag) override { - MCELFStreamer::EmitAssemblerFlag(Flag); + void emitAssemblerFlag(MCAssemblerFlag Flag) override { + MCELFStreamer::emitAssemblerFlag(Flag); switch (Flag) { case MCAF_SyntaxUnified: @@ -609,7 +601,7 @@ private: ElfMappingSymbol State; }; - void EmitDataMappingSymbol() { + void emitDataMappingSymbol() { if (LastEMSInfo->State == EMS_Data) return; else if (LastEMSInfo->State == EMS_None) { @@ -648,7 +640,7 @@ private: void EmitMappingSymbol(StringRef Name) { auto *Symbol = cast<MCSymbolELF>(getContext().getOrCreateSymbol( Name + "." + Twine(MappingSymbolCounter++))); - EmitLabel(Symbol); + emitLabel(Symbol); Symbol->setType(ELF::STT_NOTYPE); Symbol->setBinding(ELF::STB_LOCAL); @@ -659,15 +651,15 @@ private: uint64_t Offset) { auto *Symbol = cast<MCSymbolELF>(getContext().getOrCreateSymbol( Name + "." + Twine(MappingSymbolCounter++))); - EmitLabelAtPos(Symbol, Loc, F, Offset); + emitLabelAtPos(Symbol, Loc, F, Offset); Symbol->setType(ELF::STT_NOTYPE); Symbol->setBinding(ELF::STB_LOCAL); Symbol->setExternal(false); } - void EmitThumbFunc(MCSymbol *Func) override { + void emitThumbFunc(MCSymbol *Func) override { getAssembler().setIsThumbFunc(Func); - EmitSymbolAttribute(Func, MCSA_ELF_TypeFunction); + emitSymbolAttribute(Func, MCSA_ELF_TypeFunction); } // Helper functions for ARM exception handling directives @@ -868,6 +860,7 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() { case ARM::ArchKind::ARMV8_3A: case ARM::ArchKind::ARMV8_4A: case ARM::ArchKind::ARMV8_5A: + case ARM::ArchKind::ARMV8_6A: setAttributeItem(CPU_arch_profile, ApplicationProfile, false); setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false); @@ -1091,7 +1084,7 @@ void ARMTargetELFStreamer::finishAttributeSection() { Streamer.SwitchSection(AttributeSection); // Format version - Streamer.EmitIntValue(0x41, 1); + Streamer.emitInt8(0x41); } // Vendor size + Vendor name + '\0' @@ -1102,31 +1095,31 @@ void ARMTargetELFStreamer::finishAttributeSection() { const size_t ContentsSize = calculateContentSize(); - Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4); - Streamer.EmitBytes(CurrentVendor); - Streamer.EmitIntValue(0, 1); // '\0' + Streamer.emitInt32(VendorHeaderSize + TagHeaderSize + ContentsSize); + Streamer.emitBytes(CurrentVendor); + Streamer.emitInt8(0); // '\0' - Streamer.EmitIntValue(ARMBuildAttrs::File, 1); - Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4); + Streamer.emitInt8(ARMBuildAttrs::File); + Streamer.emitInt32(TagHeaderSize + ContentsSize); // Size should have been accounted for already, now // emit each field as its type (ULEB or String) for (size_t i = 0; i < Contents.size(); ++i) { AttributeItem item = Contents[i]; - Streamer.EmitULEB128IntValue(item.Tag); + Streamer.emitULEB128IntValue(item.Tag); switch (item.Type) { default: llvm_unreachable("Invalid attribute type"); case AttributeItem::NumericAttribute: - Streamer.EmitULEB128IntValue(item.IntValue); + Streamer.emitULEB128IntValue(item.IntValue); break; case AttributeItem::TextAttribute: - Streamer.EmitBytes(item.StringValue); - Streamer.EmitIntValue(0, 1); // '\0' + Streamer.emitBytes(item.StringValue); + Streamer.emitInt8(0); // '\0' break; case AttributeItem::NumericAndTextAttributes: - Streamer.EmitULEB128IntValue(item.IntValue); - Streamer.EmitBytes(item.StringValue); - Streamer.EmitIntValue(0, 1); // '\0' + Streamer.emitULEB128IntValue(item.IntValue); + Streamer.emitBytes(item.StringValue); + Streamer.emitInt8(0); // '\0' break; } } @@ -1143,7 +1136,7 @@ void ARMTargetELFStreamer::emitLabel(MCSymbol *Symbol) { Streamer.getAssembler().registerSymbol(*Symbol); unsigned Type = cast<MCSymbolELF>(Symbol)->getType(); if (Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC) - Streamer.EmitThumbFunc(Symbol); + Streamer.emitThumbFunc(Symbol); } void @@ -1155,13 +1148,13 @@ void ARMTargetELFStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) { if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Value)) { const MCSymbol &Sym = SRE->getSymbol(); if (!Sym.isDefined()) { - getStreamer().EmitAssignment(Symbol, Value); + getStreamer().emitAssignment(Symbol, Value); return; } } - getStreamer().EmitThumbFunc(Symbol); - getStreamer().EmitAssignment(Symbol, Value); + getStreamer().emitThumbFunc(Symbol); + getStreamer().emitAssignment(Symbol, Value); } void ARMTargetELFStreamer::emitInst(uint32_t Inst, char Suffix) { @@ -1170,12 +1163,12 @@ void ARMTargetELFStreamer::emitInst(uint32_t Inst, char Suffix) { void ARMTargetELFStreamer::reset() { AttributeSection = nullptr; } -void ARMELFStreamer::FinishImpl() { +void ARMELFStreamer::finishImpl() { MCTargetStreamer &TS = *getTargetStreamer(); ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS); ATS.finishAttributeSection(); - MCELFStreamer::FinishImpl(); + MCELFStreamer::finishImpl(); } void ARMELFStreamer::reset() { @@ -1201,7 +1194,7 @@ inline void ARMELFStreamer::SwitchToEHSection(StringRef Prefix, static_cast<const MCSectionELF &>(Fn.getSection()); // Create the name for new section - StringRef FnSecName(FnSection.getSectionName()); + StringRef FnSecName(FnSection.getName()); SmallString<128> EHSecName(Prefix); if (FnSecName != ".text") { EHSecName += FnSecName; @@ -1213,13 +1206,13 @@ inline void ARMELFStreamer::SwitchToEHSection(StringRef Prefix, Flags |= ELF::SHF_GROUP; MCSectionELF *EHSection = getContext().getELFSection( EHSecName, Type, Flags, 0, Group, FnSection.getUniqueID(), - static_cast<const MCSymbolELF *>(&Fn)); + static_cast<const MCSymbolELF *>(FnSection.getBeginSymbol())); assert(EHSection && "Failed to get the required EH section"); // Switch to .ARM.extab or .ARM.exidx section SwitchSection(EHSection); - EmitCodeAlignment(4); + emitCodeAlignment(4); } inline void ARMELFStreamer::SwitchToExTabSection(const MCSymbol &FnStart) { @@ -1258,7 +1251,7 @@ void ARMELFStreamer::EHReset() { void ARMELFStreamer::emitFnStart() { assert(FnStart == nullptr); FnStart = getContext().createTempSymbol(); - EmitLabel(FnStart); + emitLabel(FnStart); } void ARMELFStreamer::emitFnEnd() { @@ -1284,17 +1277,17 @@ void ARMELFStreamer::emitFnEnd() { MCSymbolRefExpr::VK_ARM_PREL31, getContext()); - EmitValue(FnStartRef, 4); + emitValue(FnStartRef, 4); if (CantUnwind) { - EmitIntValue(ARM::EHABI::EXIDX_CANTUNWIND, 4); + emitInt32(ARM::EHABI::EXIDX_CANTUNWIND); } else if (ExTab) { // Emit a reference to the unwind opcodes in the ".ARM.extab" section. const MCSymbolRefExpr *ExTabEntryRef = MCSymbolRefExpr::create(ExTab, MCSymbolRefExpr::VK_ARM_PREL31, getContext()); - EmitValue(ExTabEntryRef, 4); + emitValue(ExTabEntryRef, 4); } else { // For the __aeabi_unwind_cpp_pr0, we have to emit the unwind opcodes in // the second word of exception index table entry. The size of the unwind @@ -1307,7 +1300,7 @@ void ARMELFStreamer::emitFnEnd() { Opcodes[1] << 8 | Opcodes[2] << 16 | Opcodes[3] << 24; - EmitIntValue(Intval, Opcodes.size()); + emitIntValue(Intval, Opcodes.size()); } // Switch to the section containing FnStart @@ -1366,7 +1359,7 @@ void ARMELFStreamer::FlushUnwindOpcodes(bool NoHandlerData) { // Create .ARM.extab label for offset in .ARM.exidx assert(!ExTab); ExTab = getContext().createTempSymbol(); - EmitLabel(ExTab); + emitLabel(ExTab); // Emit personality if (Personality) { @@ -1375,7 +1368,7 @@ void ARMELFStreamer::FlushUnwindOpcodes(bool NoHandlerData) { MCSymbolRefExpr::VK_ARM_PREL31, getContext()); - EmitValue(PersonalityRef, 4); + emitValue(PersonalityRef, 4); } // Emit unwind opcodes @@ -1386,7 +1379,7 @@ void ARMELFStreamer::FlushUnwindOpcodes(bool NoHandlerData) { Opcodes[I + 1] << 8 | Opcodes[I + 2] << 16 | Opcodes[I + 3] << 24; - EmitIntValue(Intval, 4); + emitInt32(Intval); } // According to ARM EHABI section 9.2, if the __aeabi_unwind_cpp_pr1() or @@ -1397,7 +1390,7 @@ void ARMELFStreamer::FlushUnwindOpcodes(bool NoHandlerData) { // In case that the .handlerdata directive is not specified by the // programmer, we should emit zero to terminate the handler data. if (NoHandlerData && !Personality) - EmitIntValue(0, 4); + emitInt32(0); } void ARMELFStreamer::emitHandlerData() { FlushUnwindOpcodes(false); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp index b36106a78b71..744d919f2fd4 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp @@ -288,7 +288,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address, case ARM::t2DSB: switch (MI->getOperand(0).getImm()) { default: - if (!printAliasInstr(MI, STI, O)) + if (!printAliasInstr(MI, Address, STI, O)) printInstruction(MI, Address, STI, O); break; case 0: @@ -302,7 +302,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address, return; } - if (!printAliasInstr(MI, STI, O)) + if (!printAliasInstr(MI, Address, STI, O)) printInstruction(MI, Address, STI, O); printAnnotation(O, Annot); @@ -1669,15 +1669,6 @@ void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum, } } -void ARMInstPrinter::printExpandedImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint32_t Val = MI->getOperand(OpNum).getImm(); - O << markup("<imm:") << "#0x"; - O.write_hex(Val); - O << markup(">"); -} - void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h index 20f901033395..37cb731ff001 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h @@ -32,10 +32,10 @@ public: // Autogenerated by tblgen. void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O); - virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, - raw_ostream &O); - virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, + virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, + const MCSubtargetInfo &STI, raw_ostream &O); + virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo, @@ -43,6 +43,10 @@ public: void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum, + const MCSubtargetInfo &STI, raw_ostream &O) { + printOperand(MI, OpNum, STI, O); + } void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); @@ -109,6 +113,12 @@ public: template <unsigned scale> void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); + template <unsigned scale> + void printAdrLabelOperand(const MCInst *MI, uint64_t /*Address*/, + unsigned OpNum, const MCSubtargetInfo &STI, + raw_ostream &O) { + printAdrLabelOperand<scale>(MI, OpNum, STI, O); + } void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); void printThumbSRImm(const MCInst *MI, unsigned OpNum, @@ -206,6 +216,11 @@ public: const MCSubtargetInfo &STI, raw_ostream &O); void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); + void printThumbLdrLabelOperand(const MCInst *MI, uint64_t /*Address*/, + unsigned OpNum, const MCSubtargetInfo &STI, + raw_ostream &O) { + printThumbLdrLabelOperand(MI, OpNum, STI, O); + } void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); void printFBits32(const MCInst *MI, unsigned OpNum, @@ -260,8 +275,6 @@ public: const MCSubtargetInfo &STI, raw_ostream &O); void printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); - void printExpandedImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); void printMveSaturateOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); private: diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp index d30d15df3d00..765613cf347d 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp @@ -37,8 +37,6 @@ ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) { ExceptionsType = (TheTriple.isOSDarwin() && !TheTriple.isWatchABI()) ? ExceptionHandling::SjLj : ExceptionHandling::DwarfCFI; - - UseIntegratedAssembler = true; } void ARMELFMCAsmInfo::anchor() { } @@ -73,8 +71,6 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) { // foo(plt) instead of foo@plt UseParensForSymbolVariant = true; - - UseIntegratedAssembler = true; } void ARMELFMCAsmInfo::setUseIntegratedAssembler(bool Value) { @@ -116,7 +112,6 @@ ARMCOFFMCAsmInfoGNU::ARMCOFFMCAsmInfoGNU() { ExceptionsType = ExceptionHandling::DwarfCFI; UseParensForSymbolVariant = true; - UseIntegratedAssembler = true; DwarfRegNumForCFI = false; // Conditional Thumb 4-byte instructions can have an implicit IT. diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index 268fe7efd9ce..1cb99534f146 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -413,14 +413,6 @@ public: unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; - template <uint8_t shift, bool invert> - unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups, - const MCSubtargetInfo &STI) const { - static_assert(shift <= 32, "Shift count must be less than or equal to 32."); - const MCOperand MO = MI.getOperand(Op); - return (invert ? (MO.getImm() ^ 0xff) : MO.getImm()) >> shift; - } unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue, diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 9f60e70e0e02..05d73ccf6ff2 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -63,6 +63,25 @@ static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, return true; } } + if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && + ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || + (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { + Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating " + "point instructions"; + return true; + } + return false; +} + +static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, + std::string &Info) { + if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && + ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || + (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { + Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating " + "point instructions"; + return true; + } return false; } @@ -168,7 +187,7 @@ MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, if (!ArchFS.empty()) ArchFS = (Twine(ArchFS) + "," + FS).str(); else - ArchFS = FS; + ArchFS = std::string(FS); } return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS); @@ -200,7 +219,7 @@ static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, MAI = new ARMELFMCAsmInfo(TheTriple); unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); - MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0)); + MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0)); return MAI; } @@ -266,7 +285,9 @@ public: bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override { // We only handle PCRel branches for now. - if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL) + if (Inst.getNumOperands() == 0 || + Info->get(Inst.getOpcode()).OpInfo[0].OperandType != + MCOI::OPERAND_PCREL) return false; int64_t Imm = Inst.getOperand(0).getImm(); @@ -285,8 +306,15 @@ public: switch (Inst.getOpcode()) { default: OpId = 0; + if (Inst.getNumOperands() == 0) + return false; break; + case ARM::MVE_WLSTP_8: + case ARM::MVE_WLSTP_16: + case ARM::MVE_WLSTP_32: + case ARM::MVE_WLSTP_64: case ARM::t2WLS: + case ARM::MVE_LETP: case ARM::t2LEUpdate: OpId = 2; break; @@ -316,6 +344,14 @@ static MCInstrAnalysis *createThumbMCInstrAnalysis(const MCInstrInfo *Info) { return new ThumbMCInstrAnalysis(Info); } +bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) { + // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have + // to rely on feature bits. + if (Coproc >= 8) + return false; + return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc]; +} + // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() { for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(), diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h index 9cbbd56225ef..7cfe6881b456 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -107,6 +107,9 @@ inline bool isVpred(OperandType op) { inline bool isVpred(uint8_t op) { return isVpred(static_cast<OperandType>(op)); } + +bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI); + } // end namespace ARM } // End llvm namespace diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp index 7b30a61e8ccb..1fee354cad93 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp @@ -80,7 +80,7 @@ void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) { default: llvm_unreachable("Invalid Suffix"); } - getStreamer().EmitBytes(StringRef(Buffer, Size)); + getStreamer().emitBytes(StringRef(Buffer, Size)); } // The remaining callbacks should be handled separately by each @@ -108,7 +108,7 @@ void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) {} void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {} -void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {} +void ARMTargetStreamer::emitArchExtension(uint64_t ArchExt) {} void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {} void ARMTargetStreamer::emitFPU(unsigned FPU) {} void ARMTargetStreamer::finishAttributeSection() {} diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp index a9460b70da56..781627c3c425 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp @@ -134,7 +134,7 @@ void UnwindOpcodeAssembler::EmitSPOffset(int64_t Offset) { uint8_t Buff[16]; Buff[0] = ARM::EHABI::UNWIND_OPCODE_INC_VSP_ULEB128; size_t ULEBSize = encodeULEB128((Offset - 0x204) >> 2, Buff + 1); - EmitBytes(Buff, ULEBSize + 1); + emitBytes(Buff, ULEBSize + 1); } else if (Offset > 0) { if (Offset > 0x100) { EmitInt8(ARM::EHABI::UNWIND_OPCODE_INC_VSP | 0x3fu); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h index 5fb7307159d1..ec11a78f8a7a 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h @@ -64,7 +64,7 @@ public: OpBegins.push_back(OpBegins.back() + Opcodes.size()); } - /// Finalize the unwind opcode sequence for EmitBytes() + /// Finalize the unwind opcode sequence for emitBytes() void Finalize(unsigned &PersonalityIndex, SmallVectorImpl<uint8_t> &Result); @@ -80,7 +80,7 @@ private: OpBegins.push_back(OpBegins.back() + 2); } - void EmitBytes(const uint8_t *Opcode, size_t Size) { + void emitBytes(const uint8_t *Opcode, size_t Size) { Ops.insert(Ops.end(), Opcode, Opcode + Size); OpBegins.push_back(OpBegins.back() + Size); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp index b3c8146a9bde..e6f649164a29 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp @@ -22,18 +22,18 @@ public: std::unique_ptr<MCObjectWriter> OW) : MCWinCOFFStreamer(C, std::move(AB), std::move(CE), std::move(OW)) {} - void EmitThumbFunc(MCSymbol *Symbol) override; - void FinishImpl() override; + void emitThumbFunc(MCSymbol *Symbol) override; + void finishImpl() override; }; -void ARMWinCOFFStreamer::EmitThumbFunc(MCSymbol *Symbol) { +void ARMWinCOFFStreamer::emitThumbFunc(MCSymbol *Symbol) { getAssembler().setIsThumbFunc(Symbol); } -void ARMWinCOFFStreamer::FinishImpl() { - EmitFrames(nullptr); +void ARMWinCOFFStreamer::finishImpl() { + emitFrames(nullptr); - MCWinCOFFStreamer::FinishImpl(); + MCWinCOFFStreamer::finishImpl(); } } |