diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonSubtarget.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 51 |
1 files changed, 30 insertions, 21 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 6c706fea096b..2b7e1bcba9a3 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -75,14 +75,14 @@ static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable checking for cache bank conflicts")); - HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()), - CPUString(Hexagon_MC::selectHexagonCPU(CPU)), - InstrInfo(initializeSubtargetDependencies(CPU, FS)), + CPUString(std::string(Hexagon_MC::selectHexagonCPU(CPU))), + TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), RegInfo(getHwMode()), TLInfo(TM, *this), InstrItins(getInstrItineraryForCPU(CPUString)) { + Hexagon_MC::addArchSubtarget(this, FS); // Beware of the default constructor of InstrItineraryData: it will // reset all members to 0. assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized"); @@ -90,24 +90,16 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, HexagonSubtarget & HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { - static std::map<StringRef, Hexagon::ArchEnum> CpuTable{ - {"generic", Hexagon::ArchEnum::V60}, - {"hexagonv5", Hexagon::ArchEnum::V5}, - {"hexagonv55", Hexagon::ArchEnum::V55}, - {"hexagonv60", Hexagon::ArchEnum::V60}, - {"hexagonv62", Hexagon::ArchEnum::V62}, - {"hexagonv65", Hexagon::ArchEnum::V65}, - {"hexagonv66", Hexagon::ArchEnum::V66}, - }; - - auto FoundIt = CpuTable.find(CPUString); - if (FoundIt != CpuTable.end()) - HexagonArchVersion = FoundIt->second; + Optional<Hexagon::ArchEnum> ArchVer = + Hexagon::GetCpu(Hexagon::CpuTable, CPUString); + if (ArchVer) + HexagonArchVersion = *ArchVer; else llvm_unreachable("Unrecognized Hexagon processor version"); UseHVX128BOps = false; UseHVX64BOps = false; + UseAudioOps = false; UseLongCalls = false; UseBSBScheduling = hasV60Ops() && EnableBSBSched; @@ -117,6 +109,13 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { if (OverrideLongCalls.getPosition()) UseLongCalls = OverrideLongCalls; + if (isTinyCore()) { + // Tiny core has a single thread, so back-to-back scheduling is enabled by + // default. + if (!EnableBSBSched.getPosition()) + UseBSBScheduling = false; + } + FeatureBitset Features = getFeatureBits(); if (HexagonDisableDuplex) setFeatureBits(Features.reset(Hexagon::FeatureDuplex)); @@ -316,13 +315,14 @@ bool HexagonSubtarget::useAA() const { /// Perform target specific adjustments to the latency of a schedule /// dependency. -void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst, +void HexagonSubtarget::adjustSchedDependency(SUnit *Src, int SrcOpIdx, + SUnit *Dst, int DstOpIdx, SDep &Dep) const { - MachineInstr *SrcInst = Src->getInstr(); - MachineInstr *DstInst = Dst->getInstr(); if (!Src->isInstr() || !Dst->isInstr()) return; + MachineInstr *SrcInst = Src->getInstr(); + MachineInstr *DstInst = Dst->getInstr(); const HexagonInstrInfo *QII = getInstrInfo(); // Instructions with .new operands have zero latency. @@ -424,8 +424,17 @@ void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const { int DefIdx = -1; for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) { const MachineOperand &MO = SrcI->getOperand(OpNum); - if (MO.isReg() && MO.isDef() && MO.getReg() == DepR) - DefIdx = OpNum; + bool IsSameOrSubReg = false; + if (MO.isReg()) { + unsigned MOReg = MO.getReg(); + if (Register::isVirtualRegister(DepR)) { + IsSameOrSubReg = (MOReg == DepR); + } else { + IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg); + } + if (MO.isDef() && IsSameOrSubReg) + DefIdx = OpNum; + } } assert(DefIdx >= 0 && "Def Reg not found in Src MI"); MachineInstr *DstI = Dst->getInstr(); |