diff options
Diffstat (limited to 'llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 859 |
1 files changed, 399 insertions, 460 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index ae1f4545c6a4..01e4d17f6236 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -9,9 +9,9 @@ #include "MCTargetDesc/MipsABIFlagsSection.h" #include "MCTargetDesc/MipsABIInfo.h" #include "MCTargetDesc/MipsBaseInfo.h" -#include "MCTargetDesc/MipsMCExpr.h" +#include "MCTargetDesc/MipsMCAsmInfo.h" #include "MCTargetDesc/MipsMCTargetDesc.h" -#include "MipsTargetStreamer.h" +#include "MCTargetDesc/MipsTargetStreamer.h" #include "TargetInfo/MipsTargetInfo.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/SmallVector.h" @@ -25,7 +25,7 @@ #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectFileInfo.h" -#include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCParser/AsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCAsmParserExtension.h" #include "llvm/MC/MCParser/MCAsmParserUtils.h" @@ -205,6 +205,7 @@ class MipsAsmParser : public MCTargetAsmParser { ParseStatus parseJumpTarget(OperandVector &Operands); ParseStatus parseInvNum(OperandVector &Operands); ParseStatus parseRegisterList(OperandVector &Operands); + const MCExpr *parseRelocExpr(); bool searchSymbolAlias(OperandVector &Operands); @@ -224,12 +225,12 @@ class MipsAsmParser : public MCTargetAsmParser { bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); - bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg, + bool loadImmediate(int64_t ImmValue, MCRegister DstReg, MCRegister SrcReg, bool Is32BitImm, bool IsAddress, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); - bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, - unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc, + bool loadAndAddSymbolAddress(const MCExpr *SymExpr, MCRegister DstReg, + MCRegister SrcReg, bool Is32BitSym, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym); @@ -246,7 +247,7 @@ class MipsAsmParser : public MCTargetAsmParser { bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); - bool expandLoadAddress(unsigned DstReg, unsigned BaseReg, + bool expandLoadAddress(MCRegister DstReg, MCRegister BaseReg, const MCOperand &Offset, bool Is32BitAddress, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); @@ -353,8 +354,6 @@ class MipsAsmParser : public MCTargetAsmParser { bool reportParseError(const Twine &ErrorMsg); bool reportParseError(SMLoc Loc, const Twine &ErrorMsg); - bool parseMemOffset(const MCExpr *&Res, bool isParenExpr); - bool parseSetMips0Directive(); bool parseSetArchDirective(); bool parseSetFeature(uint64_t Feature); @@ -428,12 +427,12 @@ class MipsAsmParser : public MCTargetAsmParser { int matchMSA128CtrlRegisterName(StringRef Name); - unsigned getReg(int RC, int RegNo); + MCRegister getReg(int RC, int RegNo); /// Returns the internal register number for the current AT. Also checks if /// the current AT is unavailable (set to $0) and gives an error if it is. /// This should be used in pseudo-instruction expansions which need AT. - unsigned getATReg(SMLoc Loc); + MCRegister getATReg(SMLoc Loc); bool canUseATReg(); @@ -524,9 +523,9 @@ public: MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, const MCTargetOptions &Options) - : MCTargetAsmParser(Options, sti, MII), - ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()), - sti.getCPU(), Options)) { + : MCTargetAsmParser(Options, sti, MII), + ABI(MipsABIInfo::computeTargetABI(sti.getTargetTriple(), sti.getCPU(), + Options)) { MCAsmParserExtension::Initialize(parser); parser.addAliasForDirective(".asciiz", ".asciz"); @@ -584,9 +583,9 @@ public: if (!EmitJalrReloc) return false; MCValue Res; - if (!JalExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) + if (!JalExpr->evaluateAsRelocatable(Res, nullptr)) return false; - if (Res.getSymB() != nullptr) + if (Res.getSubSym()) return false; if (Res.getConstant() != 0) return ABI.IsN32() || ABI.IsN64(); @@ -735,70 +734,12 @@ public: void onEndOfFile() override; /// Warn if RegIndex is the same as the current AT. - void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc); + void warnIfRegIndexIsAT(MCRegister RegIndex, SMLoc Loc); void warnIfNoMacro(SMLoc Loc); bool isLittle() const { return IsLittleEndian; } - const MCExpr *createTargetUnaryExpr(const MCExpr *E, - AsmToken::TokenKind OperatorToken, - MCContext &Ctx) override { - switch(OperatorToken) { - default: - llvm_unreachable("Unknown token"); - return nullptr; - case AsmToken::PercentCall16: - return MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, E, Ctx); - case AsmToken::PercentCall_Hi: - return MipsMCExpr::create(MipsMCExpr::MEK_CALL_HI16, E, Ctx); - case AsmToken::PercentCall_Lo: - return MipsMCExpr::create(MipsMCExpr::MEK_CALL_LO16, E, Ctx); - case AsmToken::PercentDtprel_Hi: - return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_HI, E, Ctx); - case AsmToken::PercentDtprel_Lo: - return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_LO, E, Ctx); - case AsmToken::PercentGot: - return MipsMCExpr::create(MipsMCExpr::MEK_GOT, E, Ctx); - case AsmToken::PercentGot_Disp: - return MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, E, Ctx); - case AsmToken::PercentGot_Hi: - return MipsMCExpr::create(MipsMCExpr::MEK_GOT_HI16, E, Ctx); - case AsmToken::PercentGot_Lo: - return MipsMCExpr::create(MipsMCExpr::MEK_GOT_LO16, E, Ctx); - case AsmToken::PercentGot_Ofst: - return MipsMCExpr::create(MipsMCExpr::MEK_GOT_OFST, E, Ctx); - case AsmToken::PercentGot_Page: - return MipsMCExpr::create(MipsMCExpr::MEK_GOT_PAGE, E, Ctx); - case AsmToken::PercentGottprel: - return MipsMCExpr::create(MipsMCExpr::MEK_GOTTPREL, E, Ctx); - case AsmToken::PercentGp_Rel: - return MipsMCExpr::create(MipsMCExpr::MEK_GPREL, E, Ctx); - case AsmToken::PercentHi: - return MipsMCExpr::create(MipsMCExpr::MEK_HI, E, Ctx); - case AsmToken::PercentHigher: - return MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, E, Ctx); - case AsmToken::PercentHighest: - return MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, E, Ctx); - case AsmToken::PercentLo: - return MipsMCExpr::create(MipsMCExpr::MEK_LO, E, Ctx); - case AsmToken::PercentNeg: - return MipsMCExpr::create(MipsMCExpr::MEK_NEG, E, Ctx); - case AsmToken::PercentPcrel_Hi: - return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_HI16, E, Ctx); - case AsmToken::PercentPcrel_Lo: - return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_LO16, E, Ctx); - case AsmToken::PercentTlsgd: - return MipsMCExpr::create(MipsMCExpr::MEK_TLSGD, E, Ctx); - case AsmToken::PercentTlsldm: - return MipsMCExpr::create(MipsMCExpr::MEK_TLSLDM, E, Ctx); - case AsmToken::PercentTprel_Hi: - return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_HI, E, Ctx); - case AsmToken::PercentTprel_Lo: - return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_LO, E, Ctx); - } - } - bool areEqualRegs(const MCParsedAsmOperand &Op1, const MCParsedAsmOperand &Op2) const override; }; @@ -915,7 +856,7 @@ private: public: /// Coerce the register to GPR32 and return the real register for the current /// target. - unsigned getGPR32Reg() const { + MCRegister getGPR32Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); unsigned ClassID = Mips::GPR32RegClassID; @@ -924,7 +865,7 @@ public: /// Coerce the register to GPR32 and return the real register for the current /// target. - unsigned getGPRMM16Reg() const { + MCRegister getGPRMM16Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); unsigned ClassID = Mips::GPR32RegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -932,7 +873,7 @@ public: /// Coerce the register to GPR64 and return the real register for the current /// target. - unsigned getGPR64Reg() const { + MCRegister getGPR64Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); unsigned ClassID = Mips::GPR64RegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -941,7 +882,7 @@ public: private: /// Coerce the register to AFGR64 and return the real register for the current /// target. - unsigned getAFGR64Reg() const { + MCRegister getAFGR64Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!"); if (RegIdx.Index % 2 != 0) AsmParser.Warning(StartLoc, "Float register should be even."); @@ -951,7 +892,7 @@ private: /// Coerce the register to FGR64 and return the real register for the current /// target. - unsigned getFGR64Reg() const { + MCRegister getFGR64Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!"); return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID) .getRegister(RegIdx.Index); @@ -959,7 +900,7 @@ private: /// Coerce the register to FGR32 and return the real register for the current /// target. - unsigned getFGR32Reg() const { + MCRegister getFGR32Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!"); return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID) .getRegister(RegIdx.Index); @@ -967,7 +908,7 @@ private: /// Coerce the register to FCC and return the real register for the current /// target. - unsigned getFCCReg() const { + MCRegister getFCCReg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!"); return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID) .getRegister(RegIdx.Index); @@ -975,7 +916,7 @@ private: /// Coerce the register to MSA128 and return the real register for the current /// target. - unsigned getMSA128Reg() const { + MCRegister getMSA128Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!"); // It doesn't matter which of the MSA128[BHWD] classes we use. They are all // identical @@ -985,7 +926,7 @@ private: /// Coerce the register to MSACtrl and return the real register for the /// current target. - unsigned getMSACtrlReg() const { + MCRegister getMSACtrlReg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!"); unsigned ClassID = Mips::MSACtrlRegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -993,7 +934,7 @@ private: /// Coerce the register to COP0 and return the real register for the /// current target. - unsigned getCOP0Reg() const { + MCRegister getCOP0Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!"); unsigned ClassID = Mips::COP0RegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -1001,7 +942,7 @@ private: /// Coerce the register to COP2 and return the real register for the /// current target. - unsigned getCOP2Reg() const { + MCRegister getCOP2Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!"); unsigned ClassID = Mips::COP2RegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -1009,7 +950,7 @@ private: /// Coerce the register to COP3 and return the real register for the /// current target. - unsigned getCOP3Reg() const { + MCRegister getCOP3Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!"); unsigned ClassID = Mips::COP3RegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -1017,7 +958,7 @@ private: /// Coerce the register to ACC64DSP and return the real register for the /// current target. - unsigned getACC64DSPReg() const { + MCRegister getACC64DSPReg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!"); unsigned ClassID = Mips::ACC64DSPRegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -1025,7 +966,7 @@ private: /// Coerce the register to HI32DSP and return the real register for the /// current target. - unsigned getHI32DSPReg() const { + MCRegister getHI32DSPReg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!"); unsigned ClassID = Mips::HI32DSPRegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -1033,7 +974,7 @@ private: /// Coerce the register to LO32DSP and return the real register for the /// current target. - unsigned getLO32DSPReg() const { + MCRegister getLO32DSPReg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!"); unsigned ClassID = Mips::LO32DSPRegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -1041,7 +982,7 @@ private: /// Coerce the register to CCR and return the real register for the /// current target. - unsigned getCCRReg() const { + MCRegister getCCRReg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!"); unsigned ClassID = Mips::CCRRegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -1049,7 +990,7 @@ private: /// Coerce the register to HWRegs and return the real register for the /// current target. - unsigned getHWRegsReg() const { + MCRegister getHWRegsReg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!"); unsigned ClassID = Mips::HWRegsRegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); @@ -1311,11 +1252,23 @@ public: } template <unsigned Bits> bool isSImm() const { - return isConstantImm() ? isInt<Bits>(getConstantImm()) : isImm(); + if (!isImm()) + return false; + int64_t Res; + if (getImm()->evaluateAsAbsolute(Res)) + return isInt<Bits>(Res); + // Allow conservatively if not a parse-time constant. + return true; } template <unsigned Bits> bool isUImm() const { - return isConstantImm() ? isUInt<Bits>(getConstantImm()) : isImm(); + if (!isImm()) + return false; + int64_t Res; + if (getImm()->evaluateAsAbsolute(Res)) + return isUInt<Bits>(Res); + // Allow conservatively if not a parse-time constant. + return true; } template <unsigned Bits> bool isAnyImm() const { @@ -1352,12 +1305,12 @@ public: return false; if (!getMemBase()->isGPRAsmReg()) return false; - if (isa<MCTargetExpr>(getMemOff()) || + if (isa<MCSpecifierExpr>(getMemOff()) || (isConstantMemOff() && isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) return true; MCValue Res; - bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr); + bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr); return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); } @@ -1367,11 +1320,11 @@ public: if (!getMemBase()->isGPRAsmReg()) return false; const unsigned PtrBits = AsmParser.getABI().ArePtrs64bit() ? 64 : 32; - if (isa<MCTargetExpr>(getMemOff()) || + if (isa<MCSpecifierExpr>(getMemOff()) || (isConstantMemOff() && isIntN(PtrBits, getConstantMemOff()))) return true; MCValue Res; - bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr); + bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr); return IsReloc && isIntN(PtrBits, Res.getConstant()); } @@ -1412,7 +1365,7 @@ public: if (Kind != k_Immediate) return false; MCValue Res; - bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr); + bool Success = getImm()->evaluateAsRelocatable(Res, nullptr); return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant()); } @@ -1707,18 +1660,18 @@ public: /// getEndLoc - Get the location of the last token of this operand. SMLoc getEndLoc() const override { return EndLoc; } - void print(raw_ostream &OS) const override { + void print(raw_ostream &OS, const MCAsmInfo &MAI) const override { switch (Kind) { case k_Immediate: OS << "Imm<"; - OS << *Imm.Val; + MAI.printExpr(OS, *Imm.Val); OS << ">"; break; case k_Memory: OS << "Mem<"; - Mem.Base->print(OS); + Mem.Base->print(OS, MAI); OS << ", "; - OS << *Mem.Off; + MAI.printExpr(OS, *Mem.Off); OS << ">"; break; case k_RegisterIndex: @@ -1821,7 +1774,7 @@ static bool isEvaluated(const MCExpr *Expr) { case MCExpr::Constant: return true; case MCExpr::SymbolRef: - return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None); + return (cast<MCSymbolRefExpr>(Expr)->getSpecifier()); case MCExpr::Binary: { const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr); if (!isEvaluated(BE->getLHS())) @@ -1830,8 +1783,10 @@ static bool isEvaluated(const MCExpr *Expr) { } case MCExpr::Unary: return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr()); - case MCExpr::Target: + case MCExpr::Specifier: return true; + case MCExpr::Target: + llvm_unreachable("unused by this backend"); } return false; } @@ -1862,7 +1817,7 @@ static bool needsExpandMemInst(MCInst &Inst, const MCInstrDesc &MCID) { // Expand symbol. const MCSymbolRefExpr *SR = static_cast<const MCSymbolRefExpr *>(Expr); - return SR->getKind() == MCSymbolRefExpr::VK_None; + return SR->getSpecifier() == 0; } return false; @@ -2123,7 +2078,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, // of the assembler. We ought to leave it to those later stages. const MCSymbol *JalSym = getSingleMCSymbol(JalExpr); - if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0), + if (expandLoadAddress(Mips::T9, MCRegister(), Inst.getOperand(0), !isGP64bit(), IDLoc, Out, STI)) return true; @@ -2142,8 +2097,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, MCSymbol *TmpLabel = getContext().createTempSymbol(); const MCExpr *TmpExpr = MCSymbolRefExpr::create(TmpLabel, getContext()); const MCExpr *RelocJalrExpr = - MCSymbolRefExpr::create(JalSym, MCSymbolRefExpr::VK_None, - getContext(), IDLoc); + MCSymbolRefExpr::create(JalSym, getContext(), IDLoc); TOut.getStreamer().emitRelocDirective( *TmpExpr, inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR", @@ -2303,8 +2257,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, break; case Mips::MOVEP_MM: case Mips::MOVEP_MMR6: { - unsigned R0 = Inst.getOperand(0).getReg(); - unsigned R1 = Inst.getOperand(1).getReg(); + MCRegister R0 = Inst.getOperand(0).getReg(); + MCRegister R1 = Inst.getOperand(1).getReg(); bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) || (R0 == Mips::A1 && R1 == Mips::A3) || (R0 == Mips::A2 && R1 == Mips::A3) || @@ -2451,10 +2405,9 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) && "expected immediate operand kind"); - return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, - Inst.getOperand(1), - Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, - Out, STI) + return expandLoadAddress( + Inst.getOperand(0).getReg(), MCRegister(), Inst.getOperand(1), + Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::LoadAddrReg32: @@ -2753,14 +2706,14 @@ template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) { /// /// @param ImmValue The immediate to load. /// @param DstReg The register that will hold the immediate. -/// @param SrcReg A register to add to the immediate or Mips::NoRegister +/// @param SrcReg A register to add to the immediate or MCRegister() /// for a simple initialization. /// @param Is32BitImm Is ImmValue 32-bit or 64-bit? /// @param IsAddress True if the immediate represents an address. False if it /// is an integer. /// @param IDLoc Location of the immediate in the source file. -bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, - unsigned SrcReg, bool Is32BitImm, +bool MipsAsmParser::loadImmediate(int64_t ImmValue, MCRegister DstReg, + MCRegister SrcReg, bool Is32BitImm, bool IsAddress, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); @@ -2782,19 +2735,19 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, } } - unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); + MCRegister ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu; bool UseSrcReg = false; - if (SrcReg != Mips::NoRegister) + if (SrcReg) UseSrcReg = true; - unsigned TmpReg = DstReg; + MCRegister TmpReg = DstReg; if (UseSrcReg && getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { // At this point we need AT to perform the expansions and we exit if it is // not available. - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; TmpReg = ATReg; @@ -2817,7 +2770,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, } if (isUInt<16>(ImmValue)) { - unsigned TmpReg = DstReg; + MCRegister TmpReg = DstReg; if (SrcReg == DstReg) { TmpReg = getATReg(IDLoc); if (!TmpReg) @@ -2896,8 +2849,8 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, // The highest 32-bit's are equivalent to a 32-bit immediate load. // Load bits 32-63 of ImmValue into bits 0-31 of the temporary register. - if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false, - IDLoc, Out, STI)) + if (loadImmediate(ImmValue >> 32, TmpReg, MCRegister(), true, false, IDLoc, + Out, STI)) return false; // Shift and accumulate into the register. If a 16-bit chunk is zero, then @@ -2933,14 +2886,14 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, const MCOperand &DstRegOp = Inst.getOperand(0); assert(DstRegOp.isReg() && "expected register operand kind"); - if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, - Is32BitImm, false, IDLoc, Out, STI)) + if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), MCRegister(), Is32BitImm, + false, IDLoc, Out, STI)) return true; return false; } -bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg, +bool MipsAsmParser::expandLoadAddress(MCRegister DstReg, MCRegister BaseReg, const MCOperand &Offset, bool Is32BitAddress, SMLoc IDLoc, MCStreamer &Out, @@ -2972,37 +2925,35 @@ bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg, } bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, - unsigned DstReg, unsigned SrcReg, - bool Is32BitSym, SMLoc IDLoc, - MCStreamer &Out, + MCRegister DstReg, + MCRegister SrcReg, bool Is32BitSym, + SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO && - SrcReg != Mips::ZERO_64; + bool UseSrcReg = + SrcReg.isValid() && SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64; warnIfNoMacro(IDLoc); if (inPicMode()) { MCValue Res; - if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) { + if (!SymExpr->evaluateAsRelocatable(Res, nullptr)) { Error(IDLoc, "expected relocatable expression"); return true; } - if (Res.getSymB() != nullptr) { + if (Res.getSubSym()) { Error(IDLoc, "expected relocatable expression with only one symbol"); return true; } bool IsPtr64 = ABI.ArePtrs64bit(); bool IsLocalSym = - Res.getSymA()->getSymbol().isInSection() || - Res.getSymA()->getSymbol().isTemporary() || - (Res.getSymA()->getSymbol().isELF() && - cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() == - ELF::STB_LOCAL); + Res.getAddSym()->isInSection() || Res.getAddSym()->isTemporary() || + (Res.getAddSym()->isELF() && + cast<MCSymbolELF>(Res.getAddSym())->getBinding() == ELF::STB_LOCAL); // For O32, "$"-prefixed symbols are recognized as temporary while // .L-prefixed symbols are not (PrivateGlobalPrefix is "$"). Recognize ".L" // manually. - if (ABI.IsO32() && Res.getSymA()->getSymbol().getName().starts_with(".L")) + if (ABI.IsO32() && Res.getAddSym()->getName().starts_with(".L")) IsLocalSym = true; bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym; @@ -3013,10 +2964,10 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg && Res.getConstant() == 0 && !IsLocalSym) { if (UseXGOT) { - const MCExpr *CallHiExpr = MipsMCExpr::create(MipsMCExpr::MEK_CALL_HI16, - SymExpr, getContext()); - const MCExpr *CallLoExpr = MipsMCExpr::create(MipsMCExpr::MEK_CALL_LO16, - SymExpr, getContext()); + const MCExpr *CallHiExpr = + MCSpecifierExpr::create(SymExpr, Mips::S_CALL_HI16, getContext()); + const MCExpr *CallLoExpr = + MCSpecifierExpr::create(SymExpr, Mips::S_CALL_LO16, getContext()); TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc, STI); TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg, @@ -3025,20 +2976,20 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, MCOperand::createExpr(CallLoExpr), IDLoc, STI); } else { const MCExpr *CallExpr = - MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, SymExpr, getContext()); + MCSpecifierExpr::create(SymExpr, Mips::S_GOT_CALL, getContext()); TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg, MCOperand::createExpr(CallExpr), IDLoc, STI); } return false; } - unsigned TmpReg = DstReg; + MCRegister TmpReg = DstReg; if (UseSrcReg && getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { // If $rs is the same as $rd, we need to use AT. // If it is not available we exit. - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; TmpReg = ATReg; @@ -3058,9 +3009,9 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, // this happens then the last instruction must use $rd as the result // register. const MCExpr *CallHiExpr = - MipsMCExpr::create(MipsMCExpr::MEK_GOT_HI16, SymExpr, getContext()); - const MCExpr *CallLoExpr = MipsMCExpr::create( - MipsMCExpr::MEK_GOT_LO16, Res.getSymA(), getContext()); + MCSpecifierExpr::create(SymExpr, Mips::S_GOT_HI16, getContext()); + const MCExpr *CallLoExpr = MCSpecifierExpr::create( + Res.getAddSym(), Mips::S_GOT_LO16, getContext()); TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc, STI); @@ -3081,7 +3032,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, return false; } - const MipsMCExpr *GotExpr = nullptr; + const MCSpecifierExpr *GotExpr = nullptr; const MCExpr *LoExpr = nullptr; if (ABI.IsN32() || ABI.IsN64()) { // The remaining cases are: @@ -3091,8 +3042,8 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, // The daddiu's marked with a '>' may be omitted if they are redundant. If // this happens then the last instruction must use $rd as the result // register. - GotExpr = MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, Res.getSymA(), - getContext()); + GotExpr = MCSpecifierExpr::create(Res.getAddSym(), Mips::S_GOT_DISP, + getContext()); if (Res.getConstant() != 0) { // Symbols fully resolve with just the %got_disp(symbol) but we // must still account for any offset to the symbol for @@ -3119,15 +3070,14 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, // this happens then the last instruction must use $rd as the result // register. if (IsLocalSym) { - GotExpr = - MipsMCExpr::create(MipsMCExpr::MEK_GOT, SymExpr, getContext()); - LoExpr = MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext()); + GotExpr = MCSpecifierExpr::create(SymExpr, Mips::S_GOT, getContext()); + LoExpr = MCSpecifierExpr::create(SymExpr, Mips::S_LO, getContext()); } else { // External symbols fully resolve the symbol with just the %got(symbol) // but we must still account for any offset to the symbol for // expressions like symbol+8. - GotExpr = MipsMCExpr::create(MipsMCExpr::MEK_GOT, Res.getSymA(), - getContext()); + GotExpr = + MCSpecifierExpr::create(Res.getAddSym(), Mips::S_GOT, getContext()); if (Res.getConstant() != 0) LoExpr = MCConstantExpr::create(Res.getConstant(), getContext()); } @@ -3147,10 +3097,10 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, return false; } - const MipsMCExpr *HiExpr = - MipsMCExpr::create(MipsMCExpr::MEK_HI, SymExpr, getContext()); - const MipsMCExpr *LoExpr = - MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext()); + const auto *HiExpr = + MCSpecifierExpr::create(SymExpr, Mips::S_HI, getContext()); + const auto *LoExpr = + MCSpecifierExpr::create(SymExpr, Mips::S_LO, getContext()); // This is the 64-bit symbol address expansion. if (ABI.ArePtrs64bit() && isGP64bit()) { @@ -3161,17 +3111,17 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, // If it is not available we exit if the destination is the same as the // source register. - const MipsMCExpr *HighestExpr = - MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, SymExpr, getContext()); - const MipsMCExpr *HigherExpr = - MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, SymExpr, getContext()); + const auto *HighestExpr = + MCSpecifierExpr::create(SymExpr, Mips::S_HIGHEST, getContext()); + const auto *HigherExpr = + MCSpecifierExpr::create(SymExpr, Mips::S_HIGHER, getContext()); bool RdRegIsRsReg = UseSrcReg && getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg); if (canUseATReg() && UseSrcReg && RdRegIsRsReg) { - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); // If $rs is the same as $rd: // (d)la $rd, sym($rd) => lui $at, %highest(sym) @@ -3195,7 +3145,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, return false; } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) { - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); // If the $rs is different from $rd or if $rs isn't specified and we // have $at available: @@ -3265,12 +3215,12 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, // (d)la $rd, sym/sym($rs) => lui $rd, %hi(sym) // ori $rd, $rd, %lo(sym) // (addu $rd, $rd, $rs) - unsigned TmpReg = DstReg; + MCRegister TmpReg = DstReg; if (UseSrcReg && getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { // If $rs is the same as $rd, we need to use AT. // If it is not available we exit. - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; TmpReg = ATReg; @@ -3292,10 +3242,10 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr, // Each double-precision register DO-D15 overlaps with two of the single // precision registers F0-F31. As an example, all of the following hold true: // D0 + 1 == F1, F1 + 1 == D1, F1 + 1 == F2, depending on the context. -static unsigned nextReg(unsigned Reg) { +static MCRegister nextReg(MCRegister Reg) { if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg)) return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1; - switch (Reg) { + switch (Reg.id()) { default: llvm_unreachable("Unknown register in assembly macro expansion!"); case Mips::ZERO: return Mips::AT; case Mips::AT: return Mips::V0; @@ -3356,15 +3306,14 @@ static unsigned nextReg(unsigned Reg) { // address to load a 64 bit value. bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym) { - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; if(IsPicEnabled) { - const MCExpr *GotSym = - MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); - const MipsMCExpr *GotExpr = - MipsMCExpr::create(MipsMCExpr::MEK_GOT, GotSym, getContext()); + const MCExpr *GotSym = MCSymbolRefExpr::create(Sym, getContext()); + const auto *GotExpr = + MCSpecifierExpr::create(GotSym, Mips::S_GOT, getContext()); if(isABI_O32() || isABI_N32()) { TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr), @@ -3374,10 +3323,9 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, IDLoc, STI); } } else { //!IsPicEnabled - const MCExpr *HiSym = - MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); - const MipsMCExpr *HiExpr = - MipsMCExpr::create(MipsMCExpr::MEK_HI, HiSym, getContext()); + const MCExpr *HiSym = MCSymbolRefExpr::create(Sym, getContext()); + const auto *HiExpr = + MCSpecifierExpr::create(HiSym, Mips::S_HI, getContext()); // FIXME: This is technically correct but gives a different result to gas, // but gas is incomplete there (it has a fixme noting it doesn't work with @@ -3388,14 +3336,12 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, if(isABI_O32() || isABI_N32()) { TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); } else { //isABI_N64() - const MCExpr *HighestSym = - MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); - const MipsMCExpr *HighestExpr = - MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, HighestSym, getContext()); - const MCExpr *HigherSym = - MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); - const MipsMCExpr *HigherExpr = - MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, HigherSym, getContext()); + const MCExpr *HighestSym = MCSymbolRefExpr::create(Sym, getContext()); + const auto *HighestExpr = + MCSpecifierExpr::create(HighestSym, Mips::S_HIGHEST, getContext()); + const MCExpr *HigherSym = MCSymbolRefExpr::create(Sym, getContext()); + const auto *HigherExpr = + MCSpecifierExpr::create(HigherSym, Mips::S_HIGHER, getContext()); TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, STI); @@ -3435,13 +3381,13 @@ bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && "Invalid instruction operand."); - unsigned FirstReg = Inst.getOperand(0).getReg(); + MCRegister FirstReg = Inst.getOperand(0).getReg(); uint64_t ImmOp64 = Inst.getOperand(1).getImm(); uint32_t ImmOp32 = covertDoubleImmToSingleImm(convertIntToDoubleImm(ImmOp64)); - return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, - Out, STI); + return loadImmediate(ImmOp32, FirstReg, MCRegister(), true, false, IDLoc, Out, + STI); } bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, @@ -3452,14 +3398,14 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && "Invalid instruction operand."); - unsigned FirstReg = Inst.getOperand(0).getReg(); + MCRegister FirstReg = Inst.getOperand(0).getReg(); uint64_t ImmOp64 = Inst.getOperand(1).getImm(); ImmOp64 = convertIntToDoubleImm(ImmOp64); uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64); - unsigned TmpReg = Mips::ZERO; + MCRegister TmpReg = Mips::ZERO; if (ImmOp32 != 0) { TmpReg = getATReg(IDLoc); if (!TmpReg) @@ -3467,7 +3413,7 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, } if (Lo_32(ImmOp64) == 0) { - if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister, + if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, MCRegister(), true, false, IDLoc, Out, STI)) return true; TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); @@ -3481,10 +3427,8 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); MCSymbol *Sym = getContext().createTempSymbol(); - const MCExpr *LoSym = - MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); - const MipsMCExpr *LoExpr = - MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); + const MCExpr *LoSym = MCSymbolRefExpr::create(Sym, getContext()); + const auto *LoExpr = MCSpecifierExpr::create(LoSym, Mips::S_LO, getContext()); getStreamer().switchSection(ReadOnlySection); getStreamer().emitLabel(Sym, IDLoc); @@ -3506,23 +3450,23 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && "Invalid instruction operand."); - unsigned FirstReg = Inst.getOperand(0).getReg(); + MCRegister FirstReg = Inst.getOperand(0).getReg(); uint64_t ImmOp64 = Inst.getOperand(1).getImm(); ImmOp64 = convertIntToDoubleImm(ImmOp64); if (Lo_32(ImmOp64) == 0) { if (isGP64bit()) { - if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, - IDLoc, Out, STI)) + if (loadImmediate(ImmOp64, FirstReg, MCRegister(), false, false, IDLoc, + Out, STI)) return true; } else { - if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, + if (loadImmediate(Hi_32(ImmOp64), FirstReg, MCRegister(), true, false, IDLoc, Out, STI)) return true; - if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, - IDLoc, Out, STI)) + if (loadImmediate(0, nextReg(FirstReg), MCRegister(), true, false, IDLoc, + Out, STI)) return true; } return false; @@ -3533,10 +3477,8 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); MCSymbol *Sym = getContext().createTempSymbol(); - const MCExpr *LoSym = - MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); - const MipsMCExpr *LoExpr = - MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); + const MCExpr *LoSym = MCSymbolRefExpr::create(Sym, getContext()); + const auto *LoExpr = MCSpecifierExpr::create(LoSym, Mips::S_LO, getContext()); getStreamer().switchSection(ReadOnlySection); getStreamer().emitLabel(Sym, IDLoc); @@ -3544,7 +3486,7 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, getStreamer().emitIntValue(ImmOp64, 8); getStreamer().switchSection(CS); - unsigned TmpReg = getATReg(IDLoc); + MCRegister TmpReg = getATReg(IDLoc); if (!TmpReg) return true; @@ -3571,12 +3513,12 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && "Invalid instruction operand."); - unsigned FirstReg = Inst.getOperand(0).getReg(); + MCRegister FirstReg = Inst.getOperand(0).getReg(); uint64_t ImmOp64 = Inst.getOperand(1).getImm(); ImmOp64 = convertIntToDoubleImm(ImmOp64); - unsigned TmpReg = Mips::ZERO; + MCRegister TmpReg = Mips::ZERO; if (ImmOp64 != 0) { TmpReg = getATReg(IDLoc); if (!TmpReg) @@ -3586,17 +3528,16 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, if ((Lo_32(ImmOp64) == 0) && !((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) { if (isGP64bit()) { - if (TmpReg != Mips::ZERO && - loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc, - Out, STI)) + if (TmpReg != Mips::ZERO && loadImmediate(ImmOp64, TmpReg, MCRegister(), + false, false, IDLoc, Out, STI)) return true; TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI); return false; } if (TmpReg != Mips::ZERO && - loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false, - IDLoc, Out, STI)) + loadImmediate(Hi_32(ImmOp64), TmpReg, MCRegister(), true, false, IDLoc, + Out, STI)) return true; if (hasMips32r2()) { @@ -3616,10 +3557,8 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC); MCSymbol *Sym = getContext().createTempSymbol(); - const MCExpr *LoSym = - MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); - const MipsMCExpr *LoExpr = - MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); + const MCExpr *LoSym = MCSymbolRefExpr::create(Sym, getContext()); + const auto *LoExpr = MCSpecifierExpr::create(LoSym, Mips::S_LO, getContext()); getStreamer().switchSection(ReadOnlySection); getStreamer().emitLabel(Sym, IDLoc); @@ -3729,12 +3668,12 @@ bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, } else { warnIfNoMacro(IDLoc); - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; - if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true, - IDLoc, Out, STI)) + if (loadImmediate(ImmValue, ATReg, MCRegister(), !isGP64bit(), true, IDLoc, + Out, STI)) return true; if (IsLikely) { @@ -3761,9 +3700,9 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, MipsTargetStreamer &TOut = getTargetStreamer(); unsigned OpCode = Inst.getOpcode(); - unsigned DstReg = DstRegOp.getReg(); - unsigned BaseReg = BaseRegOp.getReg(); - unsigned TmpReg = DstReg; + MCRegister DstReg = DstRegOp.getReg(); + MCRegister BaseReg = BaseRegOp.getReg(); + MCRegister TmpReg = DstReg; const MCInstrDesc &Desc = MII.get(OpCode); int16_t DstRegClass = Desc.operands()[StartOp].RegClass; @@ -3800,8 +3739,8 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, if (IsLargeOffset) { bool Is32BitImm = isInt<32>(OffsetOp.getImm()); - if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true, - IDLoc, Out, STI)) + if (loadImmediate(HiOffset, TmpReg, MCRegister(), Is32BitImm, true, IDLoc, + Out, STI)) return; } @@ -3821,17 +3760,18 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, // of R_MIPS_GOT_DISP in appropriate cases to reduce number // of GOT entries. MCValue Res; - if (!OffsetOp.getExpr()->evaluateAsRelocatable(Res, nullptr, nullptr)) { + if (!OffsetOp.getExpr()->evaluateAsRelocatable(Res, nullptr)) { Error(IDLoc, "expected relocatable expression"); return; } - if (Res.getSymB() != nullptr) { + if (Res.getSubSym()) { Error(IDLoc, "expected relocatable expression with only one symbol"); return; } - loadAndAddSymbolAddress(Res.getSymA(), TmpReg, BaseReg, - !ABI.ArePtrs64bit(), IDLoc, Out, STI); + loadAndAddSymbolAddress( + MCSymbolRefExpr::create(Res.getAddSym(), getContext()), TmpReg, + BaseReg, !ABI.ArePtrs64bit(), IDLoc, Out, STI); emitInstWithOffset(MCOperand::createImm(int16_t(Res.getConstant()))); } else { // FIXME: Implement 64-bit case. @@ -3841,15 +3781,15 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, // sw $8, %lo(sym)($at) const MCExpr *OffExpr = OffsetOp.getExpr(); MCOperand LoOperand = MCOperand::createExpr( - MipsMCExpr::create(MipsMCExpr::MEK_LO, OffExpr, getContext())); + MCSpecifierExpr::create(OffExpr, Mips::S_LO, getContext())); MCOperand HiOperand = MCOperand::createExpr( - MipsMCExpr::create(MipsMCExpr::MEK_HI, OffExpr, getContext())); + MCSpecifierExpr::create(OffExpr, Mips::S_HI, getContext())); if (ABI.IsN64()) { MCOperand HighestOperand = MCOperand::createExpr( - MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, OffExpr, getContext())); + MCSpecifierExpr::create(OffExpr, Mips::S_HIGHEST, getContext())); MCOperand HigherOperand = MCOperand::createExpr( - MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, OffExpr, getContext())); + MCSpecifierExpr::create(OffExpr, Mips::S_HIGHER, getContext())); TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI); TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI); @@ -3888,9 +3828,9 @@ void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, MipsTargetStreamer &TOut = getTargetStreamer(); unsigned OpCode = Inst.getOpcode(); - unsigned DstReg = DstRegOp.getReg(); - unsigned BaseReg = BaseRegOp.getReg(); - unsigned TmpReg = DstReg; + MCRegister DstReg = DstRegOp.getReg(); + MCRegister BaseReg = BaseRegOp.getReg(); + MCRegister TmpReg = DstReg; const MCInstrDesc &Desc = MII.get(OpCode); int16_t DstRegClass = Desc.operands()[StartOp].RegClass; @@ -3967,14 +3907,14 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, MipsTargetStreamer &TOut = getTargetStreamer(); bool EmittedNoMacroWarning = false; unsigned PseudoOpcode = Inst.getOpcode(); - unsigned SrcReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(0).getReg(); const MCOperand &TrgOp = Inst.getOperand(1); const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr(); unsigned ZeroSrcOpcode, ZeroTrgOpcode; bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality; - unsigned TrgReg; + MCRegister TrgReg; if (TrgOp.isReg()) TrgReg = TrgOp.getReg(); else if (TrgOp.isImm()) { @@ -4038,8 +3978,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, break; } - if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(), - false, IDLoc, Out, STI)) + if (loadImmediate(TrgOp.getImm(), TrgReg, MCRegister(), !isGP64bit(), false, + IDLoc, Out, STI)) return true; } @@ -4191,7 +4131,7 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, // If neither the SrcReg nor the TrgReg are $0, we need AT to perform the // expansions. If it is not available, we return. - unsigned ATRegNum = getATReg(IDLoc); + MCRegister ATRegNum = getATReg(IDLoc); if (!ATRegNum) return true; @@ -4241,13 +4181,13 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCOperand &RdRegOp = Inst.getOperand(0); assert(RdRegOp.isReg() && "expected register operand kind"); - unsigned RdReg = RdRegOp.getReg(); + MCRegister RdReg = RdRegOp.getReg(); const MCOperand &RsRegOp = Inst.getOperand(1); assert(RsRegOp.isReg() && "expected register operand kind"); - unsigned RsReg = RsRegOp.getReg(); + MCRegister RsReg = RsRegOp.getReg(); - unsigned RtReg; + MCRegister RtReg; int64_t ImmValue; const MCOperand &RtOp = Inst.getOperand(2); @@ -4286,7 +4226,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro; if (RtOp.isImm()) { - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; @@ -4308,7 +4248,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); return false; } else { - if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), + if (loadImmediate(ImmValue, ATReg, MCRegister(), isInt<32>(ImmValue), false, Inst.getLoc(), Out, STI)) return true; TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI); @@ -4339,7 +4279,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, } // Temporary label for first branch traget - MCContext &Context = TOut.getStreamer().getContext(); + MCContext &Context = TOut.getContext(); MCSymbol *BrTarget; MCOperand LabelOp; @@ -4365,7 +4305,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return false; } - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; @@ -4412,12 +4352,12 @@ bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && "Invalid instruction operand."); - unsigned FirstReg = Inst.getOperand(0).getReg(); - unsigned SecondReg = Inst.getOperand(1).getReg(); - unsigned ThirdReg = Inst.getOperand(2).getReg(); + MCRegister FirstReg = Inst.getOperand(0).getReg(); + MCRegister SecondReg = Inst.getOperand(1).getReg(); + MCRegister ThirdReg = Inst.getOperand(2).getReg(); if (hasMips1() && !hasMips2()) { - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); @@ -4456,14 +4396,14 @@ bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, assert(OffsetImmOp.isImm() && "expected immediate operand kind"); MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned DstReg = DstRegOp.getReg(); - unsigned SrcReg = SrcRegOp.getReg(); + MCRegister DstReg = DstRegOp.getReg(); + MCRegister SrcReg = SrcRegOp.getReg(); int64_t OffsetValue = OffsetImmOp.getImm(); // NOTE: We always need AT for ULHU, as it is always used as the source // register for one of the LBu's. warnIfNoMacro(IDLoc); - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; @@ -4479,11 +4419,11 @@ bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, if (isLittle()) std::swap(FirstOffset, SecondOffset); - unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg; - unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg; + MCRegister FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg; + MCRegister SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg; - unsigned LbuSrcReg = IsLargeOffset ? ATReg : SrcReg; - unsigned SllReg = IsLargeOffset ? DstReg : ATReg; + MCRegister LbuSrcReg = IsLargeOffset ? ATReg : SrcReg; + MCRegister SllReg = IsLargeOffset ? DstReg : ATReg; TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg, FirstOffset, IDLoc, STI); @@ -4508,12 +4448,12 @@ bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, assert(OffsetImmOp.isImm() && "expected immediate operand kind"); MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned DstReg = DstRegOp.getReg(); - unsigned SrcReg = SrcRegOp.getReg(); + MCRegister DstReg = DstRegOp.getReg(); + MCRegister SrcReg = SrcRegOp.getReg(); int64_t OffsetValue = OffsetImmOp.getImm(); warnIfNoMacro(IDLoc); - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; @@ -4559,8 +4499,8 @@ bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, assert(OffsetImmOp.isImm() && "expected immediate operand kind"); MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned DstReg = DstRegOp.getReg(); - unsigned SrcReg = SrcRegOp.getReg(); + MCRegister DstReg = DstRegOp.getReg(); + MCRegister SrcReg = SrcRegOp.getReg(); int64_t OffsetValue = OffsetImmOp.getImm(); // Compute left/right load/store offsets. @@ -4572,7 +4512,7 @@ bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw); bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset; - unsigned TmpReg = SrcReg; + MCRegister TmpReg = SrcReg; if (IsLargeOffset || DoMove) { warnIfNoMacro(IDLoc); TmpReg = getATReg(IDLoc); @@ -4609,9 +4549,9 @@ bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); - unsigned OpReg = Inst.getOperand(2).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); + MCRegister OpReg = Inst.getOperand(2).getReg(); unsigned OpCode; warnIfNoMacro(IDLoc); @@ -4643,8 +4583,8 @@ bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); int64_t ImmValue = Inst.getOperand(2).getImm(); unsigned OpRegCode, OpImmCode; @@ -4671,15 +4611,15 @@ bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI); TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); } else { - unsigned ImmReg = DstReg; + MCRegister ImmReg = DstReg; if (DstReg == SrcReg) { - unsigned ATReg = getATReg(Inst.getLoc()); + MCRegister ATReg = getATReg(Inst.getLoc()); if (!ATReg) return true; ImmReg = ATReg; } - if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), + if (loadImmediate(ImmValue, ImmReg, MCRegister(), isInt<32>(ImmValue), false, IDLoc, Out, STI)) return true; @@ -4699,9 +4639,9 @@ bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); - unsigned ImmReg = DstReg; + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); + MCRegister ImmReg = DstReg; int64_t ImmValue = Inst.getOperand(2).getImm(); unsigned OpCode; @@ -4721,14 +4661,14 @@ bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, } if (DstReg == SrcReg) { - unsigned ATReg = getATReg(Inst.getLoc()); + MCRegister ATReg = getATReg(Inst.getLoc()); if (!ATReg) return true; ImmReg = ATReg; } - if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), - false, IDLoc, Out, STI)) + if (loadImmediate(ImmValue, ImmReg, MCRegister(), isInt<32>(ImmValue), false, + IDLoc, Out, STI)) return true; // $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg @@ -4746,9 +4686,9 @@ bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); - unsigned OpReg = Inst.getOperand(2).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); + MCRegister OpReg = Inst.getOperand(2).getReg(); unsigned OpCode; warnIfNoMacro(IDLoc); @@ -4780,8 +4720,8 @@ bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); int64_t ImmValue = Inst.getOperand(2).getImm(); unsigned OpRegCode; @@ -4801,16 +4741,16 @@ bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, } // $SrcReg <= Imm is equal to (not (Imm < $SrcReg)) - unsigned ImmReg = DstReg; + MCRegister ImmReg = DstReg; if (DstReg == SrcReg) { - unsigned ATReg = getATReg(Inst.getLoc()); + MCRegister ATReg = getATReg(Inst.getLoc()); if (!ATReg) return true; ImmReg = ATReg; } - if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), - false, IDLoc, Out, STI)) + if (loadImmediate(ImmValue, ImmReg, MCRegister(), isInt<32>(ImmValue), false, + IDLoc, Out, STI)) return true; TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI); @@ -4829,10 +4769,10 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && "Invalid instruction operand."); - unsigned ATReg = Mips::NoRegister; - unsigned FinalDstReg = Mips::NoRegister; - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); + MCRegister ATReg; + MCRegister FinalDstReg; + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); int64_t ImmValue = Inst.getOperand(2).getImm(); bool Is32Bit = isInt<32>(ImmValue) || (!isGP64bit() && isUInt<32>(ImmValue)); @@ -4847,7 +4787,7 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, DstReg = ATReg; } - if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, + if (!loadImmediate(ImmValue, DstReg, MCRegister(), Is32Bit, false, Inst.getLoc(), Out, STI)) { switch (FinalOpcode) { default: @@ -4917,7 +4857,7 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, break; } - if (FinalDstReg == Mips::NoRegister) + if (!FinalDstReg) TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI); else TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI); @@ -4929,11 +4869,11 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned ATReg = Mips::NoRegister; - unsigned DReg = Inst.getOperand(0).getReg(); - unsigned SReg = Inst.getOperand(1).getReg(); - unsigned TReg = Inst.getOperand(2).getReg(); - unsigned TmpReg = DReg; + MCRegister ATReg; + MCRegister DReg = Inst.getOperand(0).getReg(); + MCRegister SReg = Inst.getOperand(1).getReg(); + MCRegister TReg = Inst.getOperand(2).getReg(); + MCRegister TmpReg = DReg; unsigned FirstShift = Mips::NOP; unsigned SecondShift = Mips::NOP; @@ -4992,9 +4932,9 @@ bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned ATReg = Mips::NoRegister; - unsigned DReg = Inst.getOperand(0).getReg(); - unsigned SReg = Inst.getOperand(1).getReg(); + MCRegister ATReg; + MCRegister DReg = Inst.getOperand(0).getReg(); + MCRegister SReg = Inst.getOperand(1).getReg(); int64_t ImmValue = Inst.getOperand(2).getImm(); unsigned FirstShift = Mips::NOP; @@ -5054,11 +4994,11 @@ bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc, bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned ATReg = Mips::NoRegister; - unsigned DReg = Inst.getOperand(0).getReg(); - unsigned SReg = Inst.getOperand(1).getReg(); - unsigned TReg = Inst.getOperand(2).getReg(); - unsigned TmpReg = DReg; + MCRegister ATReg; + MCRegister DReg = Inst.getOperand(0).getReg(); + MCRegister SReg = Inst.getOperand(1).getReg(); + MCRegister TReg = Inst.getOperand(2).getReg(); + MCRegister TmpReg = DReg; unsigned FirstShift = Mips::NOP; unsigned SecondShift = Mips::NOP; @@ -5117,9 +5057,9 @@ bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned ATReg = Mips::NoRegister; - unsigned DReg = Inst.getOperand(0).getReg(); - unsigned SReg = Inst.getOperand(1).getReg(); + MCRegister ATReg; + MCRegister DReg = Inst.getOperand(0).getReg(); + MCRegister SReg = Inst.getOperand(1).getReg(); int64_t ImmValue = Inst.getOperand(2).getImm() % 64; unsigned FirstShift = Mips::NOP; @@ -5211,8 +5151,8 @@ bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc, bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned FirstRegOp = Inst.getOperand(0).getReg(); - unsigned SecondRegOp = Inst.getOperand(1).getReg(); + MCRegister FirstRegOp = Inst.getOperand(0).getReg(); + MCRegister SecondRegOp = Inst.getOperand(1).getReg(); TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI); if (FirstRegOp != SecondRegOp) @@ -5227,17 +5167,16 @@ bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned ATReg = Mips::NoRegister; - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); + MCRegister ATReg; + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); int32_t ImmValue = Inst.getOperand(2).getImm(); ATReg = getATReg(IDLoc); if (!ATReg) return true; - loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, - STI); + loadImmediate(ImmValue, ATReg, MCRegister(), true, false, IDLoc, Out, STI); TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, SrcReg, ATReg, IDLoc, STI); @@ -5250,10 +5189,10 @@ bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned ATReg = Mips::NoRegister; - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); - unsigned TmpReg = Inst.getOperand(2).getReg(); + MCRegister ATReg; + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); + MCRegister TmpReg = Inst.getOperand(2).getReg(); ATReg = getATReg(Inst.getLoc()); if (!ATReg) @@ -5272,7 +5211,7 @@ bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, if (useTraps()) { TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); } else { - MCContext & Context = TOut.getStreamer().getContext(); + MCContext &Context = TOut.getContext(); MCSymbol * BrTarget = Context.createTempSymbol(); MCOperand LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context)); @@ -5292,10 +5231,10 @@ bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned ATReg = Mips::NoRegister; - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); - unsigned TmpReg = Inst.getOperand(2).getReg(); + MCRegister ATReg; + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); + MCRegister TmpReg = Inst.getOperand(2).getReg(); ATReg = getATReg(IDLoc); if (!ATReg) @@ -5309,7 +5248,7 @@ bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, if (useTraps()) { TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI); } else { - MCContext & Context = TOut.getStreamer().getContext(); + MCContext &Context = TOut.getContext(); MCSymbol * BrTarget = Context.createTempSymbol(); MCOperand LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context)); @@ -5328,9 +5267,9 @@ bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); - unsigned TmpReg = Inst.getOperand(2).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); + MCRegister TmpReg = Inst.getOperand(2).getReg(); TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI); TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); @@ -5354,9 +5293,9 @@ bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MipsTargetStreamer &TOut = getTargetStreamer(); unsigned Opcode = IsLoad ? Mips::LW : Mips::SW; - unsigned FirstReg = Inst.getOperand(0).getReg(); - unsigned SecondReg = nextReg(FirstReg); - unsigned BaseReg = Inst.getOperand(1).getReg(); + MCRegister FirstReg = Inst.getOperand(0).getReg(); + MCRegister SecondReg = nextReg(FirstReg); + MCRegister BaseReg = Inst.getOperand(1).getReg(); if (!SecondReg) return true; @@ -5401,9 +5340,9 @@ bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MipsTargetStreamer &TOut = getTargetStreamer(); unsigned Opcode = Mips::SWC1; - unsigned FirstReg = Inst.getOperand(0).getReg(); - unsigned SecondReg = nextReg(FirstReg); - unsigned BaseReg = Inst.getOperand(1).getReg(); + MCRegister FirstReg = Inst.getOperand(0).getReg(); + MCRegister SecondReg = nextReg(FirstReg); + MCRegister BaseReg = Inst.getOperand(1).getReg(); if (!SecondReg) return true; @@ -5437,9 +5376,9 @@ bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); - unsigned OpReg = Inst.getOperand(2).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); + MCRegister OpReg = Inst.getOperand(2).getReg(); warnIfNoMacro(IDLoc); @@ -5449,7 +5388,7 @@ bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return false; } - unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; + MCRegister Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI); return false; } @@ -5463,8 +5402,8 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); int64_t Imm = Inst.getOperand(2).getImm(); warnIfNoMacro(IDLoc); @@ -5490,12 +5429,12 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, } if (!isUInt<16>(Imm)) { - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; - if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc, - Out, STI)) + if (loadImmediate(Imm, ATReg, MCRegister(), true, isGP64bit(), IDLoc, Out, + STI)) return true; TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); @@ -5518,9 +5457,9 @@ bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); - unsigned OpReg = Inst.getOperand(2).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); + MCRegister OpReg = Inst.getOperand(2).getReg(); warnIfNoMacro(IDLoc); @@ -5530,7 +5469,7 @@ bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return false; } - unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; + MCRegister Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); return false; } @@ -5544,8 +5483,8 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && "Invalid instruction operand."); - unsigned DstReg = Inst.getOperand(0).getReg(); - unsigned SrcReg = Inst.getOperand(1).getReg(); + MCRegister DstReg = Inst.getOperand(0).getReg(); + MCRegister SrcReg = Inst.getOperand(1).getReg(); int64_t ImmValue = Inst.getOperand(2).getImm(); warnIfNoMacro(IDLoc); @@ -5557,8 +5496,7 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, if (SrcReg == Mips::ZERO) { Warning(IDLoc, "comparison is always true"); - if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out, - STI)) + if (loadImmediate(1, DstReg, MCRegister(), true, false, IDLoc, Out, STI)) return true; return false; } @@ -5577,12 +5515,12 @@ bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return false; } - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; - if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), - false, IDLoc, Out, STI)) + if (loadImmediate(ImmValue, ATReg, MCRegister(), isInt<32>(ImmValue), false, + IDLoc, Out, STI)) return true; TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); @@ -5597,7 +5535,7 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) { switch (Inst.getOpcode()) { case Mips::MFTLO: case Mips::MTTLO: - switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { + switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) { case Mips::AC0: return Mips::ZERO; case Mips::AC1: @@ -5611,7 +5549,7 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) { } case Mips::MFTHI: case Mips::MTTHI: - switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { + switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) { case Mips::AC0: return Mips::AT; case Mips::AC1: @@ -5625,7 +5563,7 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) { } case Mips::MFTACX: case Mips::MTTACX: - switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) { + switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg().id()) { case Mips::AC0: return Mips::V0; case Mips::AC1: @@ -5648,7 +5586,7 @@ static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) { // Map the floating point register operand to the corresponding register // operand. static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) { - switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) { + switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg().id()) { case Mips::F0: return Mips::ZERO; case Mips::F1: return Mips::AT; case Mips::F2: return Mips::V0; @@ -5687,7 +5625,7 @@ static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) { // Map the coprocessor operand the corresponding gpr register operand. static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) { - switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) { + switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg().id()) { case Mips::COP00: return Mips::ZERO; case Mips::COP01: return Mips::AT; case Mips::COP02: return Mips::V0; @@ -5729,7 +5667,7 @@ static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) { bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - unsigned rd = 0; + MCRegister rd; unsigned u = 1; unsigned sel = 0; unsigned h = 0; @@ -5806,8 +5744,8 @@ bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, MipsTargetStreamer &TOut = getTargetStreamer(); unsigned Opcode = Inst.getOpcode() == Mips::SaaAddr ? Mips::SAA : Mips::SAAD; - unsigned RtReg = Inst.getOperand(0).getReg(); - unsigned BaseReg = Inst.getOperand(1).getReg(); + MCRegister RtReg = Inst.getOperand(0).getReg(); + MCRegister BaseReg = Inst.getOperand(1).getReg(); const MCOperand &BaseOp = Inst.getOperand(2); if (BaseOp.isImm()) { @@ -5818,7 +5756,7 @@ bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, } } - unsigned ATReg = getATReg(IDLoc); + MCRegister ATReg = getATReg(IDLoc); if (!ATReg) return true; @@ -6197,9 +6135,9 @@ bool MipsAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, llvm_unreachable("Implement any new match types added!"); } -void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { - if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex) - Warning(Loc, "used $at (currently $" + Twine(RegIndex) + +void MipsAsmParser::warnIfRegIndexIsAT(MCRegister RegIndex, SMLoc Loc) { + if (RegIndex && AssemblerOptions.back()->getATRegIndex() == RegIndex) + Warning(Loc, "used $at (currently $" + Twine(RegIndex.id()) + ") without \".set noat\""); } @@ -6214,7 +6152,7 @@ void MipsAsmParser::ConvertXWPOperands(MCInst &Inst, (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) && "Unexpected instruction!"); ((MipsOperand &)*Operands[1]).addGPR32ZeroAsmRegOperands(Inst, 1); - int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); + MCRegister NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); Inst.addOperand(MCOperand::createReg(NextReg)); ((MipsOperand &)*Operands[2]).addMemOperands(Inst, 2); } @@ -6391,20 +6329,78 @@ bool MipsAsmParser::canUseATReg() { return AssemblerOptions.back()->getATRegIndex() != 0; } -unsigned MipsAsmParser::getATReg(SMLoc Loc) { +MCRegister MipsAsmParser::getATReg(SMLoc Loc) { unsigned ATIndex = AssemblerOptions.back()->getATRegIndex(); if (ATIndex == 0) { reportParseError(Loc, "pseudo-instruction requires $at, which is not available"); return 0; } - unsigned AT = getReg( + MCRegister AT = getReg( (isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, ATIndex); return AT; } -unsigned MipsAsmParser::getReg(int RC, int RegNo) { - return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo); +MCRegister MipsAsmParser::getReg(int RC, int RegNo) { + return getContext().getRegisterInfo()->getRegClass(RC).getRegister(RegNo); +} + +// Parse an expression with optional relocation operator prefixes (e.g. %lo). +// Some weird expressions allowed by gas are not supported for simplicity, +// e.g. "%lo foo", "(%lo(foo))", "%lo(foo)+1". +const MCExpr *MipsAsmParser::parseRelocExpr() { + auto getOp = [](StringRef Op) { + return StringSwitch<Mips::Specifier>(Op) + .Case("call16", Mips::S_GOT_CALL) + .Case("call_hi", Mips::S_CALL_HI16) + .Case("call_lo", Mips::S_CALL_LO16) + .Case("dtprel_hi", Mips::S_DTPREL_HI) + .Case("dtprel_lo", Mips::S_DTPREL_LO) + .Case("got", Mips::S_GOT) + .Case("got_disp", Mips::S_GOT_DISP) + .Case("got_hi", Mips::S_GOT_HI16) + .Case("got_lo", Mips::S_GOT_LO16) + .Case("got_ofst", Mips::S_GOT_OFST) + .Case("got_page", Mips::S_GOT_PAGE) + .Case("gottprel", Mips::S_GOTTPREL) + .Case("gp_rel", Mips::S_GPREL) + .Case("hi", Mips::S_HI) + .Case("higher", Mips::S_HIGHER) + .Case("highest", Mips::S_HIGHEST) + .Case("lo", Mips::S_LO) + .Case("neg", Mips::S_NEG) + .Case("pcrel_hi", Mips::S_PCREL_HI16) + .Case("pcrel_lo", Mips::S_PCREL_LO16) + .Case("tlsgd", Mips::S_TLSGD) + .Case("tlsldm", Mips::S_TLSLDM) + .Case("tprel_hi", Mips::S_TPREL_HI) + .Case("tprel_lo", Mips::S_TPREL_LO) + .Default(Mips::S_None); + }; + + MCAsmParser &Parser = getParser(); + StringRef Name; + const MCExpr *Res = nullptr; + SmallVector<Mips::Specifier, 0> Ops; + while (parseOptionalToken(AsmToken::Percent)) { + if (Parser.parseIdentifier(Name) || + Parser.parseToken(AsmToken::LParen, "expected '('")) + return nullptr; + auto Op = getOp(Name); + if (Op == Mips::S_None) { + Error(Parser.getTok().getLoc(), "invalid relocation operator"); + return nullptr; + } + Ops.push_back(Op); + } + if (Parser.parseExpression(Res)) + return nullptr; + while (Ops.size()) { + if (Parser.parseToken(AsmToken::RParen, "expected ')'")) + return nullptr; + Res = MCSpecifierExpr::create(Res, Ops.pop_back_val(), getContext()); + } + return Res; } bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { @@ -6450,22 +6446,17 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); // Otherwise create a symbol reference. - const MCExpr *SymRef = - MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + const MCExpr *SymRef = MCSymbolRefExpr::create(Sym, getContext()); Operands.push_back(MipsOperand::CreateImm(SymRef, S, E, *this)); return false; } default: { - LLVM_DEBUG(dbgs() << ".. generic integer expression\n"); - - const MCExpr *Expr; SMLoc S = Parser.getTok().getLoc(); // Start location of the operand. - if (getParser().parseExpression(Expr)) + const MCExpr *Expr = parseRelocExpr(); + if (!Expr) return true; - SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Operands.push_back(MipsOperand::CreateImm(Expr, S, E, *this)); return false; } @@ -6504,14 +6495,6 @@ ParseStatus MipsAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, return (Reg == (unsigned)-1) ? ParseStatus::NoMatch : ParseStatus::Success; } -bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { - SMLoc S; - - if (isParenExpr) - return getParser().parseParenExprOfDepth(0, Res, S); - return getParser().parseExpression(Res); -} - ParseStatus MipsAsmParser::parseMemOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); LLVM_DEBUG(dbgs() << "parseMemOperand\n"); @@ -6528,7 +6511,10 @@ ParseStatus MipsAsmParser::parseMemOperand(OperandVector &Operands) { } if (getLexer().getKind() != AsmToken::Dollar) { - if (parseMemOffset(IdVal, isParenExpr)) + IdVal = parseRelocExpr(); + if (!IdVal) + return ParseStatus::Failure; + if (isParenExpr && Parser.parseRParen()) return ParseStatus::Failure; const AsmToken &Tok = Parser.getTok(); // Get the next token. @@ -7519,7 +7505,7 @@ bool MipsAsmParser::parseSetAssignment() { if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true, Parser, Sym, Value)) return true; - Sym->setVariableValue(Value); + getStreamer().emitAssignment(Sym, Value); return false; } @@ -8074,109 +8060,61 @@ bool MipsAsmParser::parseDirectiveSet() { /// parseDirectiveGpWord /// ::= .gpword local_sym bool MipsAsmParser::parseDirectiveGpWord() { - MCAsmParser &Parser = getParser(); const MCExpr *Value; - // EmitGPRel32Value requires an expression, so we are using base class - // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().emitGPRel32Value(Value); - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), - "unexpected token, expected end of statement"); - Parser.Lex(); // Eat EndOfStatement token. - return false; + getTargetStreamer().emitGPRel32Value(Value); + return parseEOL(); } /// parseDirectiveGpDWord /// ::= .gpdword local_sym bool MipsAsmParser::parseDirectiveGpDWord() { - MCAsmParser &Parser = getParser(); const MCExpr *Value; - // EmitGPRel64Value requires an expression, so we are using base class - // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().emitGPRel64Value(Value); - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), - "unexpected token, expected end of statement"); - Parser.Lex(); // Eat EndOfStatement token. - return false; + getTargetStreamer().emitGPRel64Value(Value); + return parseEOL(); } /// parseDirectiveDtpRelWord /// ::= .dtprelword tls_sym bool MipsAsmParser::parseDirectiveDtpRelWord() { - MCAsmParser &Parser = getParser(); const MCExpr *Value; - // EmitDTPRel32Value requires an expression, so we are using base class - // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().emitDTPRel32Value(Value); - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), - "unexpected token, expected end of statement"); - Parser.Lex(); // Eat EndOfStatement token. - return false; + getTargetStreamer().emitDTPRel32Value(Value); + return parseEOL(); } /// parseDirectiveDtpRelDWord /// ::= .dtpreldword tls_sym bool MipsAsmParser::parseDirectiveDtpRelDWord() { - MCAsmParser &Parser = getParser(); const MCExpr *Value; - // EmitDTPRel64Value requires an expression, so we are using base class - // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().emitDTPRel64Value(Value); - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), - "unexpected token, expected end of statement"); - Parser.Lex(); // Eat EndOfStatement token. - return false; + getTargetStreamer().emitDTPRel64Value(Value); + return parseEOL(); } /// parseDirectiveTpRelWord /// ::= .tprelword tls_sym bool MipsAsmParser::parseDirectiveTpRelWord() { - MCAsmParser &Parser = getParser(); const MCExpr *Value; - // EmitTPRel32Value requires an expression, so we are using base class - // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().emitTPRel32Value(Value); - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), - "unexpected token, expected end of statement"); - Parser.Lex(); // Eat EndOfStatement token. - return false; + getTargetStreamer().emitTPRel32Value(Value); + return parseEOL(); } /// parseDirectiveTpRelDWord /// ::= .tpreldword tls_sym bool MipsAsmParser::parseDirectiveTpRelDWord() { - MCAsmParser &Parser = getParser(); const MCExpr *Value; - // EmitTPRel64Value requires an expression, so we are using base class - // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().emitTPRel64Value(Value); - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), - "unexpected token, expected end of statement"); - Parser.Lex(); // Eat EndOfStatement token. - return false; + getTargetStreamer().emitTPRel64Value(Value); + return parseEOL(); } bool MipsAsmParser::parseDirectiveOption() { @@ -8291,7 +8229,7 @@ bool MipsAsmParser::parseSSectionDirective(StringRef Section, unsigned Type) { /// ::= .module noginv bool MipsAsmParser::parseDirectiveModule() { MCAsmParser &Parser = getParser(); - MCAsmLexer &Lexer = getLexer(); + AsmLexer &Lexer = getLexer(); SMLoc L = Lexer.getLoc(); if (!getTargetStreamer().isModuleDirectiveAllowed()) { @@ -8532,7 +8470,7 @@ bool MipsAsmParser::parseDirectiveModule() { /// ::= =64 bool MipsAsmParser::parseDirectiveModuleFP() { MCAsmParser &Parser = getParser(); - MCAsmLexer &Lexer = getLexer(); + AsmLexer &Lexer = getLexer(); if (Lexer.isNot(AsmToken::Equal)) { reportParseError("unexpected token, expected equals sign '='"); @@ -8565,7 +8503,7 @@ bool MipsAsmParser::parseDirectiveModuleFP() { bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI, StringRef Directive) { MCAsmParser &Parser = getParser(); - MCAsmLexer &Lexer = getLexer(); + AsmLexer &Lexer = getLexer(); bool ModuleLevelOptions = Directive == ".module"; if (Lexer.is(AsmToken::Identifier)) { @@ -8968,7 +8906,8 @@ bool MipsAsmParser::parseInternalDirectiveReallowModule() { return false; } -extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmParser() { +extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void +LLVMInitializeMipsAsmParser() { RegisterMCAsmParser<MipsAsmParser> X(getTheMipsTarget()); RegisterMCAsmParser<MipsAsmParser> Y(getTheMipselTarget()); RegisterMCAsmParser<MipsAsmParser> A(getTheMips64Target()); |