diff options
Diffstat (limited to 'llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 597b8af176a2..36814d9f5742 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -15,6 +15,7 @@ #include "NVPTXAllocaHoisting.h" #include "NVPTXAtomicLower.h" #include "NVPTXLowerAggrCopies.h" +#include "NVPTXMachineFunctionInfo.h" #include "NVPTXTargetObjectFile.h" #include "NVPTXTargetTransformInfo.h" #include "TargetInfo/NVPTXTargetInfo.h" @@ -31,11 +32,11 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Vectorize.h" #include <cassert> +#include <optional> #include <string> using namespace llvm; @@ -63,16 +64,16 @@ static cl::opt<bool> UseShortPointersOpt( namespace llvm { -void initializeNVVMIntrRangePass(PassRegistry&); -void initializeNVVMReflectPass(PassRegistry&); void initializeGenericToNVVMPass(PassRegistry&); void initializeNVPTXAllocaHoistingPass(PassRegistry &); -void initializeNVPTXAtomicLowerPass(PassRegistry &); void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&); +void initializeNVPTXAtomicLowerPass(PassRegistry &); void initializeNVPTXLowerAggrCopiesPass(PassRegistry &); -void initializeNVPTXLowerArgsPass(PassRegistry &); void initializeNVPTXLowerAllocaPass(PassRegistry &); +void initializeNVPTXLowerArgsPass(PassRegistry &); void initializeNVPTXProxyRegErasurePass(PassRegistry &); +void initializeNVVMIntrRangePass(PassRegistry &); +void initializeNVVMReflectPass(PassRegistry &); } // end namespace llvm @@ -81,9 +82,9 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() { RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32()); RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64()); + PassRegistry &PR = *PassRegistry::getPassRegistry(); // FIXME: This pass is really intended to be invoked during IR optimization, // but it's very NVPTX-specific. - PassRegistry &PR = *PassRegistry::getPassRegistry(); initializeNVVMReflectPass(PR); initializeNVVMIntrRangePass(PR); initializeGenericToNVVMPass(PR); @@ -94,6 +95,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() { initializeNVPTXLowerAllocaPass(PR); initializeNVPTXLowerAggrCopiesPass(PR); initializeNVPTXProxyRegErasurePass(PR); + initializeNVPTXDAGToDAGISelPass(PR); } static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) { @@ -112,8 +114,8 @@ static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) { NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, - Optional<CodeModel::Model> CM, + std::optional<Reloc::Model> RM, + std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool is64bit) // The pic relocation model is used regardless of what the client has // specified, as it is the only relocation model currently supported. @@ -122,7 +124,8 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT, getEffectiveCodeModel(CM, CodeModel::Small), OL), is64bit(is64bit), UseShortPointers(UseShortPointersOpt), TLOF(std::make_unique<NVPTXTargetObjectFile>()), - Subtarget(TT, std::string(CPU), std::string(FS), *this) { + Subtarget(TT, std::string(CPU), std::string(FS), *this), + StrPool(StrAlloc) { if (TT.getOS() == Triple::NVCL) drvInterface = NVPTX::NVCL; else @@ -139,8 +142,8 @@ void NVPTXTargetMachine32::anchor() {} NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, - Optional<CodeModel::Model> CM, + std::optional<Reloc::Model> RM, + std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} @@ -149,8 +152,8 @@ void NVPTXTargetMachine64::anchor() {} NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, - Optional<CodeModel::Model> CM, + std::optional<Reloc::Model> RM, + std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} @@ -201,13 +204,11 @@ TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) { return new NVPTXPassConfig(*this, PM); } -void NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) { - Builder.addExtension( - PassManagerBuilder::EP_EarlyAsPossible, - [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { - PM.add(createNVVMReflectPass(Subtarget.getSmVersion())); - PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion())); - }); +MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator, + F, STI); } void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { @@ -300,6 +301,7 @@ void NVPTXPassConfig::addIRPasses() { // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp). disablePass(&PrologEpilogCodeInserterID); + disablePass(&MachineLateInstrsCleanupID); disablePass(&MachineCopyPropagationID); disablePass(&TailDuplicateID); disablePass(&StackMapLivenessID); |