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Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCFrameLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCFrameLowering.cpp68
1 files changed, 33 insertions, 35 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index ba775c4a679d..c0860fcdaa3b 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -267,7 +267,7 @@ static bool hasNonRISpills(const MachineFunction &MF) {
/// MustSaveLR - Return true if this function requires that we save the LR
/// register onto the stack in the prolog and restore it in the epilog of the
/// function.
-static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
+static bool MustSaveLR(const MachineFunction &MF, MCRegister LR) {
const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
// We need a save/restore of LR if there is any def of LR (which is
@@ -311,7 +311,7 @@ PPCFrameLowering::determineFrameLayout(const MachineFunction &MF,
const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
- unsigned LR = RegInfo->getRARegister();
+ MCRegister LR = RegInfo->getRARegister();
bool DisableRedZone = MF.getFunction().hasFnAttribute(Attribute::NoRedZone);
bool CanUseRedZone = !MFI.hasVarSizedObjects() && // No dynamic alloca.
!MFI.adjustsStack() && // No calls.
@@ -1186,7 +1186,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
// CFA.
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
for (const CalleeSavedInfo &I : CSI) {
- Register Reg = I.getReg();
+ MCRegister Reg = I.getReg();
if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
// This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
@@ -1987,7 +1987,7 @@ void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
// Save and clear the LR state.
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
- unsigned LR = RegInfo->getRARegister();
+ MCRegister LR = RegInfo->getRARegister();
FI->setMustSaveLR(MustSaveLR(MF, LR));
SavedRegs.reset(LR);
@@ -2108,7 +2108,7 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
SmallVector<CalleeSavedInfo, 18> VRegs;
for (const CalleeSavedInfo &I : CSI) {
- Register Reg = I.getReg();
+ MCRegister Reg = I.getReg();
assert((!MF.getInfo<PPCFunctionInfo>()->mustSaveTOC() ||
(Reg != PPC::X2 && Reg != PPC::R2)) &&
"Not expecting to try to spill R2 in a function that must save TOC");
@@ -2170,8 +2170,8 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
// The Floating-point register save area is right below the back chain word
// of the previous stack frame.
if (HasFPSaveArea) {
- for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
- int FI = FPRegs[i].getFrameIdx();
+ for (const CalleeSavedInfo &FPReg : FPRegs) {
+ int FI = FPReg.getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
}
@@ -2219,18 +2219,18 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
if (HasGPSaveArea || HasG8SaveArea) {
// Move general register save area spill slots down, taking into account
// the size of the Floating-point register save area.
- for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
- if (!GPRegs[i].isSpilledToReg()) {
- int FI = GPRegs[i].getFrameIdx();
+ for (const CalleeSavedInfo &GPReg : GPRegs) {
+ if (!GPReg.isSpilledToReg()) {
+ int FI = GPReg.getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
}
}
// Move general register save area spill slots down, taking into account
// the size of the Floating-point register save area.
- for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
- if (!G8Regs[i].isSpilledToReg()) {
- int FI = G8Regs[i].getFrameIdx();
+ for (const CalleeSavedInfo &G8Reg : G8Regs) {
+ if (!G8Reg.isSpilledToReg()) {
+ int FI = G8Reg.getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
}
}
@@ -2272,8 +2272,8 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
assert(LowerBound <= 0 && "Expect LowerBound have a non-positive value!");
LowerBound &= ~(15);
- for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
- int FI = VRegs[i].getFrameIdx();
+ for (const CalleeSavedInfo &VReg : VRegs) {
+ int FI = VReg.getFrameIdx();
MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
}
@@ -2343,9 +2343,9 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
// in our CalleSaveInfo vector.
for (auto &CalleeSaveReg : CSI) {
- MCPhysReg Reg = CalleeSaveReg.getReg();
- MCPhysReg Lower = RegInfo->getSubReg(Reg, 1);
- MCPhysReg Higher = RegInfo->getSubReg(Reg, 2);
+ MCRegister Reg = CalleeSaveReg.getReg();
+ MCRegister Lower = RegInfo->getSubReg(Reg, PPC::sub_32);
+ MCRegister Higher = RegInfo->getSubReg(Reg, PPC::sub_32_hi_phony);
if ( // Check only for SuperRegs.
Lower &&
@@ -2380,7 +2380,7 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
if (BVAllocatable.none())
return false;
- Register Reg = CS.getReg();
+ MCRegister Reg = CS.getReg();
if (!PPC::G8RCRegClass.contains(Reg)) {
AllSpilledToReg = false;
@@ -2437,7 +2437,7 @@ bool PPCFrameLowering::spillCalleeSavedRegisters(
}
for (const CalleeSavedInfo &I : CSI) {
- Register Reg = I.getReg();
+ MCRegister Reg = I.getReg();
// CR2 through CR4 are the nonvolatile CR fields.
bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
@@ -2489,22 +2489,23 @@ bool PPCFrameLowering::spillCalleeSavedRegisters(
if (Spilled[Dst])
continue;
- if (VSRContainingGPRs[Dst].second != 0) {
+ const auto &VSR = VSRContainingGPRs[Dst];
+ if (VSR.second != 0) {
assert(Subtarget.hasP9Vector() &&
"mtvsrdd is unavailable on pre-P9 targets.");
NumPESpillVSR += 2;
BuildMI(MBB, MI, DL, TII.get(PPC::MTVSRDD), Dst)
- .addReg(VSRContainingGPRs[Dst].first, getKillRegState(true))
- .addReg(VSRContainingGPRs[Dst].second, getKillRegState(true));
- } else if (VSRContainingGPRs[Dst].second == 0) {
+ .addReg(VSR.first, getKillRegState(true))
+ .addReg(VSR.second, getKillRegState(true));
+ } else if (VSR.second == 0) {
assert(Subtarget.hasP8Vector() &&
"Can't move GPR to VSR on pre-P8 targets.");
++NumPESpillVSR;
BuildMI(MBB, MI, DL, TII.get(PPC::MTVSRD),
TRI->getSubReg(Dst, PPC::sub_64))
- .addReg(VSRContainingGPRs[Dst].first, getKillRegState(true));
+ .addReg(VSR.first, getKillRegState(true));
} else {
llvm_unreachable("More than two GPRs spilled to a VSR!");
}
@@ -2623,7 +2624,7 @@ bool PPCFrameLowering::restoreCalleeSavedRegisters(
--BeforeI;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
- Register Reg = CSI[i].getReg();
+ MCRegister Reg = CSI[i].getReg();
if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
continue;
@@ -2662,20 +2663,17 @@ bool PPCFrameLowering::restoreCalleeSavedRegisters(
if (Restored[Dst])
continue;
- if (VSRContainingGPRs[Dst].second != 0) {
+ const auto &VSR = VSRContainingGPRs[Dst];
+ if (VSR.second != 0) {
assert(Subtarget.hasP9Vector());
NumPEReloadVSR += 2;
- BuildMI(MBB, I, DL, TII.get(PPC::MFVSRLD),
- VSRContainingGPRs[Dst].second)
- .addReg(Dst);
- BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD),
- VSRContainingGPRs[Dst].first)
+ BuildMI(MBB, I, DL, TII.get(PPC::MFVSRLD), VSR.second).addReg(Dst);
+ BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD), VSR.first)
.addReg(TRI->getSubReg(Dst, PPC::sub_64), getKillRegState(true));
- } else if (VSRContainingGPRs[Dst].second == 0) {
+ } else if (VSR.second == 0) {
assert(Subtarget.hasP8Vector());
++NumPEReloadVSR;
- BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD),
- VSRContainingGPRs[Dst].first)
+ BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD), VSR.first)
.addReg(TRI->getSubReg(Dst, PPC::sub_64), getKillRegState(true));
} else {
llvm_unreachable("More than two GPRs spilled to a VSR!");
generated by cgit v1.3 (git 2.53.0) at 2026-07-30 02:38:29 +0000