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path: root/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
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Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp')
-rw-r--r--llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index 2ee228d72825..a26a3f2411f8 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -175,8 +175,9 @@ static bool isSignExtendedW(Register SrcReg, const MachineRegisterInfo &MRI,
const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
unsigned BitWidth = IntTy->getBitWidth();
- return (BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||
- (BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt));
+ if ((BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||
+ (BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt)))
+ continue;
}
if (!AddRegDefToWorkList(CopySrcReg))