1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index f726f42c9bcb..5555adc19010 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -61,15 +61,15 @@ using EndianWriter = support::endian::Writer;
 // output register in operand 0. If so, we need to swap operands 0 and 1 so the
 // type comes first in the output, despide coming second in the MCInst.
 static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
-  MCInstrDesc MCDesc = MII.get(MI.getOpcode());
+  const MCInstrDesc &MCDesc = MII.get(MI.getOpcode());
   // If we define an output, and have at least one other argument.
   if (MCDesc.getNumDefs() == 1 && MCDesc.getNumOperands() >= 2) {
     // Check if we define an ID, and take a type as operand 1.
-    auto DefOpInfo = MCDesc.opInfo_begin();
-    auto FirstArgOpInfo = MCDesc.opInfo_begin() + 1;
-    return (DefOpInfo->RegClass == SPIRV::IDRegClassID ||
-            DefOpInfo->RegClass == SPIRV::ANYIDRegClassID) &&
-           FirstArgOpInfo->RegClass == SPIRV::TYPERegClassID;
+    auto &DefOpInfo = MCDesc.operands()[0];
+    auto &FirstArgOpInfo = MCDesc.operands()[1];
+    return (DefOpInfo.RegClass == SPIRV::IDRegClassID ||
+            DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) &&
+           FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
   }
   return false;
 }