diff options
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelLowering.cpp | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 2007303d9903..ed1faf6b1fe8 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1614,11 +1614,14 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, if (!Subtarget->is64Bit()) { // These libcalls are not available in 32-bit. + setLibcallName(RTLIB::MULO_I64, nullptr); setLibcallName(RTLIB::SHL_I128, nullptr); setLibcallName(RTLIB::SRL_I128, nullptr); setLibcallName(RTLIB::SRA_I128, nullptr); } + setLibcallName(RTLIB::MULO_I128, nullptr); + if (!Subtarget->isV9()) { // SparcV8 does not have FNEGD and FABSD. setOperationAction(ISD::FNEG, MVT::f64, Custom); @@ -2957,8 +2960,15 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, SDValue ShiftAmt = DAG.getConstant(63, dl, VT); SDValue RHS = Op.getOperand(1); - SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); - SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); + SDValue HiLHS, HiRHS; + if (isSigned) { + HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); + HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); + } else { + HiLHS = DAG.getConstant(0, dl, VT); + HiRHS = DAG.getConstant(0, dl, MVT::i64); + } + SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; TargetLowering::MakeLibCallOptions CallOptions; |