diff options
Diffstat (limited to 'llvm/lib/Target/VE/VEISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/VE/VEISelLowering.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index 0267aefd1e91..0e41a2d7aa03 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -1101,10 +1101,10 @@ Instruction *VETargetLowering::emitTrailingFence(IRBuilderBase &Builder, SDValue VETargetLowering::lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); - AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( - cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); - SyncScope::ID FenceSSID = static_cast<SyncScope::ID>( - cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); + AtomicOrdering FenceOrdering = + static_cast<AtomicOrdering>(Op.getConstantOperandVal(1)); + SyncScope::ID FenceSSID = + static_cast<SyncScope::ID>(Op.getConstantOperandVal(2)); // VE uses Release consistency, so need a fence instruction if it is a // cross-thread fence. @@ -1766,7 +1766,7 @@ static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, SDValue VETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); - unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); + unsigned IntNo = Op.getConstantOperandVal(0); switch (IntNo) { default: // Don't custom lower most intrinsics. return SDValue(); @@ -2937,8 +2937,8 @@ static bool isI32Insn(const SDNode *User, const SDNode *N) { if (User->getOperand(1).getNode() != N && User->getOperand(2).getNode() != N && isa<ConstantSDNode>(User->getOperand(3))) { - VECC::CondCode VECCVal = static_cast<VECC::CondCode>( - cast<ConstantSDNode>(User->getOperand(3))->getZExtValue()); + VECC::CondCode VECCVal = + static_cast<VECC::CondCode>(User->getConstantOperandVal(3)); return isIntVECondCode(VECCVal); } [[fallthrough]]; |