diff options
Diffstat (limited to 'llvm/lib/Target/VE/VEInstrFormats.td')
| -rw-r--r-- | llvm/lib/Target/VE/VEInstrFormats.td | 176 |
1 files changed, 147 insertions, 29 deletions
diff --git a/llvm/lib/Target/VE/VEInstrFormats.td b/llvm/lib/Target/VE/VEInstrFormats.td index a8d3e786ba89..0c02411ff916 100644 --- a/llvm/lib/Target/VE/VEInstrFormats.td +++ b/llvm/lib/Target/VE/VEInstrFormats.td @@ -6,6 +6,20 @@ // //===----------------------------------------------------------------------===// +// SX-Aurora uses little endian, but instructions are encoded little bit +// different manner. Therefore, we need to tranlate the address of each +// bitfield described in ISA documentation like below. +// +// ISA | InstrFormats.td +// --------------------------- +// 0-7 => 63-56 +// 8 => 55 +// 32-63 => 31-0 + +//===----------------------------------------------------------------------===// +// Instruction Format +//===----------------------------------------------------------------------===// + class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<64> Inst; @@ -14,7 +28,7 @@ class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern> let Size = 8; bits<8> op; - let Inst{0-7} = op; + let Inst{63-56} = op; dag OutOperandList = outs; dag InOperandList = ins; @@ -25,50 +39,154 @@ class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern> field bits<64> SoftFail = 0; } -class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]> +//----------------------------------------------------------------------------- +// Section 5.1 RM Type +// +// RM type has sx, sy, sz, and imm32. +// The effective address is generated by sz + sy + imm32. +//----------------------------------------------------------------------------- + +class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []> : InstVE<outs, ins, asmstr, pattern> { bits<1> cx = 0; bits<7> sx; - bits<1> cy = 0; + bits<1> cy = 1; + bits<7> sz; // defines sz prior to sy to assign from sz + bits<7> sy; + bits<1> cz = 1; + bits<32> imm32; + let op = opVal; + let Inst{55} = cx; + let Inst{54-48} = sx; + let Inst{47} = cy; + let Inst{46-40} = sy; + let Inst{39} = cz; + let Inst{38-32} = sz; + let Inst{31-0} = imm32; +} + +//----------------------------------------------------------------------------- +// Section 5.2 RRM Type +// +// RRM type is identical to RM, but the effective address is generated +// by sz + imm32. The sy field is used by other purposes. +//----------------------------------------------------------------------------- + +class RRM<bits<8>opVal, dag outs, dag ins, string asmstr, + list<dag> pattern = []> + : RM<opVal, outs, ins, asmstr, pattern>; + +// RRMHM type is to load/store host memory +// It is similar to RRM and not use sy. +class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr, + list<dag> pattern = []> + : RRM<opVal, outs, ins, asmstr, pattern> { + bits<2> ry = 0; + let cy = 0; + let sy{6-2} = 0; + let sy{1-0} = ry; +} + +//----------------------------------------------------------------------------- +// Section 5.3 CF Type +// +// CF type is used for control flow. +//----------------------------------------------------------------------------- + +class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []> + : InstVE<outs, ins, asmstr, pattern> { + bits<1> cx = 0; + bits<1> cx2 = 0; + bits<2> bpf = 0; + bits<4> cf; + bits<1> cy = 1; bits<7> sy; - bits<1> cz = 0; + bits<1> cz = 1; bits<7> sz; - bits<32> imm32 = 0; + bits<32> imm32; let op = opVal; - let Inst{15} = cx; - let Inst{14-8} = sx; - let Inst{23} = cy; - let Inst{22-16} = sy; - let Inst{31} = cz; - let Inst{30-24} = sz; - let Inst{63-32} = imm32; + let Inst{55} = cx; + let Inst{54} = cx2; + let Inst{53-52} = bpf; + let Inst{51-48} = cf; + let Inst{47} = cy; + let Inst{46-40} = sy; + let Inst{39} = cz; + let Inst{38-32} = sz; + let Inst{31-0} = imm32; } -class RR<bits<8>opVal, dag outs, dag ins, string asmstr> - : RM<opVal, outs, ins, asmstr> { +//----------------------------------------------------------------------------- +// Section 5.4 RR Type +// +// RR type is for generic arithmetic instructions. +//----------------------------------------------------------------------------- + +class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []> + : InstVE<outs, ins, asmstr, pattern> { + bits<1> cx = 0; + bits<7> sx; + bits<1> cy = 1; + bits<7> sy; + bits<1> cz = 1; + bits<7> sz; // m field places at the top sz field + bits<8> vx = 0; + bits<8> vz = 0; bits<1> cw = 0; bits<1> cw2 = 0; bits<4> cfw = 0; - let imm32{0-23} = 0; - let imm32{24} = cw; - let imm32{25} = cw2; - let imm32{26-27} = 0; - let imm32{28-31} = cfw; + let op = opVal; + let Inst{55} = cx; + let Inst{54-48} = sx; + let Inst{47} = cy; + let Inst{46-40} = sy; + let Inst{39} = cz; + let Inst{38-32} = sz; + let Inst{31-24} = vx; + let Inst{23-16} = 0; + let Inst{15-8} = vz; + let Inst{7} = cw; + let Inst{6} = cw2; + let Inst{5-4} = 0; + let Inst{3-0} = cfw; } -class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]> - : RM<opVal, outs, ins, asmstr, pattern> { - bits<1> cx2; - bits<2> bpf; - bits<4> cf; - let cx = 0; - let sx{6} = cx2; - let sx{5-4} = bpf; - let sx{3-0} = cf; +// RRFENCE type is special RR type for a FENCE instruction. +class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr, + list<dag> pattern = []> + : InstVE<outs, ins, asmstr, pattern> { + bits<1> avo = 0; + bits<1> lf = 0; + bits<1> sf = 0; + bits<1> c2 = 0; + bits<1> c1 = 0; + bits<1> c0 = 0; + let op = opVal; + let Inst{55} = avo; + let Inst{54-50} = 0; + let Inst{49} = lf; + let Inst{48} = sf; + let Inst{47-43} = 0; + let Inst{42} = c2; + let Inst{41} = c1; + let Inst{40} = c0; + let Inst{39-0} = 0; } +//----------------------------------------------------------------------------- +// Section 5.5 RW Type +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Section 5.6 RVM Type +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Section 5.7 RV Type +//----------------------------------------------------------------------------- + // Pseudo instructions. -class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern=[]> +class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []> : InstVE<outs, ins, asmstr, pattern> { let isCodeGenOnly = 1; let isPseudo = 1; |