diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86.td | 73 |
1 files changed, 61 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index a2b11d55f650..dc1ff72add49 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -52,13 +52,16 @@ def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", "Support xsave instructions">; def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", - "Support xsaveopt instructions">; + "Support xsaveopt instructions", + [FeatureXSAVE]>; def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", - "Support xsavec instructions">; + "Support xsavec instructions", + [FeatureXSAVE]>; def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", - "Support xsaves instructions">; + "Support xsaves instructions", + [FeatureXSAVE]>; def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", "Enable SSE instructions">; @@ -246,6 +249,14 @@ def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", // target-feature attribute. def FeatureDeprecatedMPX : SubtargetFeature<"mpx", "DeprecatedHasMPX", "false", "Deprecated. Support MPX instructions">; +def FeatureAMXTILE : SubtargetFeature<"amx-tile", "HasAMXTILE", "true", + "Support AMX-TILE instructions">; +def FeatureAMXINT8 : SubtargetFeature<"amx-int8", "HasAMXINT8", "true", + "Support AMX-INT8 instructions", + [FeatureAMXTILE]>; +def FeatureAMXBF16 : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true", + "Support AMX-BF16 instructions", + [FeatureAMXTILE]>; def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", "Use LEA for adjusting the stack pointer">; def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", @@ -273,6 +284,10 @@ def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", "Wait and pause enhancements">; def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true", "Has ENQCMD instructions">; +def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true", + "Has serialize instruction">; +def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true", + "Support TSXLDTRK instructions">; // On some processors, instructions that implicitly take two memory operands are // slow. In practice, this means that CALL, PUSH, and POP with memory operands // should be avoided in favor of a MOV + register CALL/PUSH/POP. @@ -329,6 +344,11 @@ def FeatureFastLZCNT : SubtargetFeature< "fast-lzcnt", "HasFastLZCNT", "true", "LZCNT instructions are as fast as most simple integer ops">; +// If the target can efficiently decode NOPs upto 7-bytes in length. +def FeatureFast7ByteNOP + : SubtargetFeature< + "fast-7bytenop", "HasFast7ByteNOP", "true", + "Target can quickly decode up to 7 byte NOPs">; // If the target can efficiently decode NOPs upto 11-bytes in length. def FeatureFast11ByteNOP : SubtargetFeature< @@ -426,6 +446,31 @@ def FeatureRetpolineExternalThunk "ourselves. Only has effect when combined with some other retpoline " "feature", [FeatureRetpolineIndirectCalls]>; +// Mitigate LVI attacks against indirect calls/branches and call returns +def FeatureLVIControlFlowIntegrity + : SubtargetFeature< + "lvi-cfi", "UseLVIControlFlowIntegrity", "true", + "Prevent indirect calls/branches from using a memory operand, and " + "precede all indirect calls/branches from a register with an " + "LFENCE instruction to serialize control flow. Also decompose RET " + "instructions into a POP+LFENCE+JMP sequence.">; + +// Enable SESES to mitigate speculative execution attacks +def FeatureSpeculativeExecutionSideEffectSuppression + : SubtargetFeature< + "seses", "UseSpeculativeExecutionSideEffectSuppression", "true", + "Prevent speculative execution side channel timing attacks by " + "inserting a speculation barrier before memory reads, memory writes, " + "and conditional branches. Implies LVI Control Flow integrity.", + [FeatureLVIControlFlowIntegrity]>; + +// Mitigate LVI attacks against data loads +def FeatureLVILoadHardening + : SubtargetFeature< + "lvi-load-hardening", "UseLVILoadHardening", "true", + "Insert LFENCE instructions to prevent data speculatively injected " + "into loads from being used maliciously.">; + // Direct Move instructions. def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", "Support movdiri instruction">; @@ -546,7 +591,8 @@ def ProcessorFeatures { FeatureSlow3OpsLEA, FeatureFastScalarFSQRT, FeatureFastSHLDRotate, - FeatureMergeToThreeWayBranch]; + FeatureMergeToThreeWayBranch, + FeatureFast15ByteNOP]; list<SubtargetFeature> SNBSpecificFeatures = [FeatureSlowUAMem32, FeaturePOPCNTFalseDeps]; list<SubtargetFeature> SNBInheritableFeatures = @@ -728,6 +774,7 @@ def ProcessorFeatures { list<SubtargetFeature> SLMSpecificFeatures = [ProcIntelSLM, FeatureSlowDivide64, FeatureSlowPMULLD, + FeatureFast7ByteNOP, FeaturePOPCNTFalseDeps]; list<SubtargetFeature> SLMInheritableFeatures = !listconcat(AtomInheritableFeatures, SLMAdditionalFeatures); @@ -762,15 +809,13 @@ def ProcessorFeatures { !listconcat(GLPInheritableFeatures, GLPSpecificFeatures); // Tremont - list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLDEMOTE, - FeatureGFNI, - FeatureMOVDIRI, - FeatureMOVDIR64B, - FeatureWAITPKG]; + list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB, + FeatureGFNI]; list<SubtargetFeature> TRMSpecificFeatures = [FeatureUseGLMDivSqrtCosts]; + list<SubtargetFeature> TRMInheritableFeatures = + !listconcat(GLPInheritableFeatures, TRMAdditionalFeatures); list<SubtargetFeature> TRMFeatures = - !listconcat(GLPInheritableFeatures, TRMAdditionalFeatures, - TRMSpecificFeatures); + !listconcat(TRMInheritableFeatures, TRMSpecificFeatures); // Knights Landing list<SubtargetFeature> KNLFeatures = [FeatureX87, @@ -822,6 +867,7 @@ def ProcessorFeatures { FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, + FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD, @@ -917,6 +963,8 @@ def ProcessorFeatures { // Excavator list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2, FeatureBMI2, + FeatureMOVBE, + FeatureRDRAND, FeatureMWAITX]; list<SubtargetFeature> BdVer4InheritableFeatures = !listconcat(BdVer3InheritableFeatures, BdVer4AdditionalFeatures); @@ -977,7 +1025,7 @@ def ProcessorFeatures { class Proc<string Name, list<SubtargetFeature> Features> : ProcessorModel<Name, GenericModel, Features>; -// NOTE: CMPXCHG8B is here for legacy compatbility so that it is only disabled +// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled // if i386/i486 is specifically requested. def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureInsertVZEROUPPER]>; @@ -1240,6 +1288,7 @@ def : ProcessorModel<"x86-64", SandyBridgeModel, [ FeatureNOPL, Feature64Bit, FeatureSlow3OpsLEA, + FeatureSlowDivide64, FeatureSlowIncDec, FeatureMacroFusion, FeatureInsertVZEROUPPER |