diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.cpp | 33 |
1 files changed, 29 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index d90b4e7bdc7e..c4748423baea 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -62,7 +62,7 @@ X86RegisterInfo::X86RegisterInfo(const Triple &TT) // This matches the simplified 32-bit pointer code in the data layout // computation. // FIXME: Should use the data layout? - bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32; + bool Use64BitReg = !TT.isX32(); StackPtr = Use64BitReg ? X86::RSP : X86::ESP; FramePtr = Use64BitReg ? X86::RBP : X86::EBP; BasePtr = Use64BitReg ? X86::RBX : X86::EBX; @@ -290,6 +290,11 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { if (MF->getFunction().hasFnAttribute("no_caller_saved_registers")) CC = CallingConv::X86_INTR; + // If atribute specified, override the CSRs normally specified by the + // calling convention and use the empty set instead. + if (MF->getFunction().hasFnAttribute("no_callee_saved_registers")) + return CSR_NoRegs_SaveList; + switch (CC) { case CallingConv::GHC: case CallingConv::HiPE: @@ -349,6 +354,10 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { if (!HasSSE) return CSR_Win64_NoSSE_SaveList; return CSR_Win64_SaveList; + case CallingConv::SwiftTail: + if (!Is64Bit) + return CSR_32_SaveList; + return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList; case CallingConv::X86_64_SysV: if (CallsEHReturn) return CSR_64EHRet_SaveList; @@ -465,6 +474,10 @@ X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF, break; case CallingConv::Win64: return CSR_Win64_RegMask; + case CallingConv::SwiftTail: + if (!Is64Bit) + return CSR_32_RegMask; + return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask; case CallingConv::X86_64_SysV: return CSR_64_RegMask; case CallingConv::X86_INTR: @@ -497,6 +510,7 @@ X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF, F.getAttributes().hasAttrSomewhere(Attribute::SwiftError); if (IsSwiftCC) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask; + return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask; } @@ -643,7 +657,7 @@ bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const { // can't address variables from the stack pointer. MS inline asm can // reference locals while also adjusting the stack pointer. When we can't // use both the SP and the FP, we need a separate base pointer register. - bool CantUseFP = needsStackRealignment(MF); + bool CantUseFP = hasStackRealignment(MF); return CantUseFP && CantUseSP(MFI); } @@ -723,8 +737,8 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int FIOffset; Register BasePtr; if (MI.isReturn()) { - assert((!needsStackRealignment(MF) || - MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) && + assert((!hasStackRealignment(MF) || + MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) && "Return instruction can only reference SP relative frame objects"); FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed(); @@ -870,10 +884,21 @@ static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, default: llvm_unreachable("Unexpected machine instruction on tile register!"); break; + case X86::COPY: { + Register SrcReg = MI->getOperand(1).getReg(); + ShapeT Shape = getTileShape(SrcReg, VRM, MRI); + VRM->assignVirt2Shape(VirtReg, Shape); + return Shape; + } // We only collect the tile shape that is defined. case X86::PTILELOADDV: + case X86::PTILELOADDT1V: case X86::PTDPBSSDV: + case X86::PTDPBSUDV: + case X86::PTDPBUSDV: + case X86::PTDPBUUDV: case X86::PTILEZEROV: + case X86::PTDPBF16PSV: MachineOperand &MO1 = MI->getOperand(1); MachineOperand &MO2 = MI->getOperand(2); ShapeT Shape(&MO1, &MO2, MRI); |
