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Diffstat (limited to 'llvm/utils/TableGen/CodeGenRegisters.cpp')
-rw-r--r--llvm/utils/TableGen/CodeGenRegisters.cpp124
1 files changed, 58 insertions, 66 deletions
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index f9a7ba6bba80..930b7742103e 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -154,14 +154,11 @@ void CodeGenSubRegIndex::computeConcatTransitiveClosure() {
//===----------------------------------------------------------------------===//
CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
- : TheDef(R),
- EnumValue(Enum),
- CostPerUse(R->getValueAsInt("CostPerUse")),
- CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
- HasDisjunctSubRegs(false),
- SubRegsComplete(false),
- SuperRegsComplete(false),
- TopoSig(~0u) {
+ : TheDef(R), EnumValue(Enum),
+ CostPerUse(R->getValueAsListOfInts("CostPerUse")),
+ CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
+ HasDisjunctSubRegs(false), SubRegsComplete(false),
+ SuperRegsComplete(false), TopoSig(~0u) {
Artificial = R->getValueAsBit("isArtificial");
}
@@ -314,18 +311,17 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
// Look at the possible compositions of Idx.
// They may not all be supported by SR.
- for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
- E = Comps.end(); I != E; ++I) {
- SubRegMap::const_iterator SRI = Map.find(I->first);
+ for (auto Comp : Comps) {
+ SubRegMap::const_iterator SRI = Map.find(Comp.first);
if (SRI == Map.end())
continue; // Idx + I->first doesn't exist in SR.
// Add I->second as a name for the subreg SRI->second, assuming it is
// orphaned, and the name isn't already used for something else.
- if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
+ if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second))
continue;
// We found a new name for the orphaned sub-register.
- SubRegs.insert(std::make_pair(I->second, SRI->second));
- Indices.push_back(I->second);
+ SubRegs.insert(std::make_pair(Comp.second, SRI->second));
+ Indices.push_back(Comp.second);
}
}
@@ -531,13 +527,13 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
CodeGenRegister *NewSubReg = NewSubRegs[i].second;
- for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
- SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
- CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
+ for (auto SubReg : NewSubReg->SubRegs) {
+ CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg.second);
if (!SubIdx)
PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
- SI->second->getName() + " in " + getName());
- NewIdx->addComposite(SI->first, SubIdx);
+ SubReg.second->getName() +
+ " in " + getName());
+ NewIdx->addComposite(SubReg.first, SubIdx);
}
}
}
@@ -550,24 +546,23 @@ void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
// Make sure all sub-registers have been visited first, so the super-reg
// lists will be topologically ordered.
- for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
- I != E; ++I)
- I->second->computeSuperRegs(RegBank);
+ for (auto SubReg : SubRegs)
+ SubReg.second->computeSuperRegs(RegBank);
// Now add this as a super-register on all sub-registers.
// Also compute the TopoSigId in post-order.
TopoSigId Id;
- for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
- I != E; ++I) {
+ for (auto SubReg : SubRegs) {
// Topological signature computed from SubIdx, TopoId(SubReg).
// Loops and idempotent indices have TopoSig = ~0u.
- Id.push_back(I->first->EnumValue);
- Id.push_back(I->second->TopoSig);
+ Id.push_back(SubReg.first->EnumValue);
+ Id.push_back(SubReg.second->TopoSig);
// Don't add duplicate entries.
- if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
+ if (!SubReg.second->SuperRegs.empty() &&
+ SubReg.second->SuperRegs.back() == this)
continue;
- I->second->SuperRegs.push_back(this);
+ SubReg.second->SuperRegs.push_back(this);
}
TopoSig = RegBank.getTopoSig(Id);
}
@@ -582,17 +577,15 @@ CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
SR->addSubRegsPreOrder(OSet, RegBank);
}
// Add any secondary sub-registers that weren't part of the explicit tree.
- for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
- I != E; ++I)
- OSet.insert(I->second);
+ for (auto SubReg : SubRegs)
+ OSet.insert(SubReg.second);
}
// Get the sum of this register's unit weights.
unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
unsigned Weight = 0;
- for (RegUnitList::iterator I = RegUnits.begin(), E = RegUnits.end();
- I != E; ++I) {
- Weight += RegBank.getRegUnit(*I).Weight;
+ for (unsigned RegUnit : RegUnits) {
+ Weight += RegBank.getRegUnit(RegUnit).Weight;
}
return Weight;
}
@@ -646,16 +639,18 @@ struct TupleExpander : SetTheory::Expander {
std::string Name;
Record *Proto = Lists[0][n];
std::vector<Init*> Tuple;
- unsigned CostPerUse = 0;
for (unsigned i = 0; i != Dim; ++i) {
Record *Reg = Lists[i][n];
if (i) Name += '_';
Name += Reg->getName();
Tuple.push_back(DefInit::get(Reg));
- CostPerUse = std::max(CostPerUse,
- unsigned(Reg->getValueAsInt("CostPerUse")));
}
+ // Take the cost list of the first register in the tuple.
+ ListInit *CostList = Proto->getValueAsListInit("CostPerUse");
+ SmallVector<Init *, 2> CostPerUse;
+ CostPerUse.insert(CostPerUse.end(), CostList->begin(), CostList->end());
+
StringInit *AsmName = StringInit::get("");
if (!RegNames.empty()) {
if (RegNames.size() <= n)
@@ -697,7 +692,7 @@ struct TupleExpander : SetTheory::Expander {
// CostPerUse is aggregated from all Tuple members.
if (Field == "CostPerUse")
- RV.setValue(IntInit::get(CostPerUse));
+ RV.setValue(ListInit::get(CostPerUse, CostList->getElementType()));
// Composite registers are always covered by sub-registers.
if (Field == "CoveredBySubRegs")
@@ -797,7 +792,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
RI.RegSize = RI.SpillSize = Size ? Size
: VTs[0].getSimple().getSizeInBits();
RI.SpillAlignment = R->getValueAsInt("Alignment");
- RSI.Map.insert({DefaultMode, RI});
+ RSI.insertRegSizeForMode(DefaultMode, RI);
}
CopyCost = R->getValueAsInt("CopyCost");
@@ -838,7 +833,10 @@ void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
Namespace = Super.Namespace;
VTs = Super.VTs;
CopyCost = Super.CopyCost;
- Allocatable = Super.Allocatable;
+ // Check for allocatable superclasses.
+ Allocatable = any_of(SuperClasses, [&](const CodeGenRegisterClass *S) {
+ return S->Allocatable;
+ });
AltOrderSelect = Super.AltOrderSelect;
AllocationPriority = Super.AllocationPriority;
GeneratePressureSet |= Super.GeneratePressureSet;
@@ -1396,19 +1394,17 @@ void CodeGenRegBank::computeComposites() {
TopoSigs.set(Reg1.getTopoSig());
const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
- for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
- e1 = SRM1.end(); i1 != e1; ++i1) {
- CodeGenSubRegIndex *Idx1 = i1->first;
- CodeGenRegister *Reg2 = i1->second;
+ for (auto I1 : SRM1) {
+ CodeGenSubRegIndex *Idx1 = I1.first;
+ CodeGenRegister *Reg2 = I1.second;
// Ignore identity compositions.
if (&Reg1 == Reg2)
continue;
const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
// Try composing Idx1 with another SubRegIndex.
- for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
- e2 = SRM2.end(); i2 != e2; ++i2) {
- CodeGenSubRegIndex *Idx2 = i2->first;
- CodeGenRegister *Reg3 = i2->second;
+ for (auto I2 : SRM2) {
+ CodeGenSubRegIndex *Idx2 = I2.first;
+ CodeGenRegister *Reg3 = I2.second;
// Ignore identity compositions.
if (Reg2 == Reg3)
continue;
@@ -1425,7 +1421,7 @@ void CodeGenRegBank::computeComposites() {
" and " + Idx2->getQualifiedName() +
" compose ambiguously as " + Prev->getQualifiedName() +
" or " + Idx3->getQualifiedName());
- }
+ }
}
}
}
@@ -1728,13 +1724,12 @@ static bool normalizeWeight(CodeGenRegister *Reg,
bool Changed = false;
const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
- for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
- SRE = SRM.end(); SRI != SRE; ++SRI) {
- if (SRI->second == Reg)
+ for (auto SRI : SRM) {
+ if (SRI.second == Reg)
continue; // self-cycles happen
- Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
- NormalRegs, NormalUnits, RegBank);
+ Changed |= normalizeWeight(SRI.second, UberSets, RegSets, NormalRegs,
+ NormalUnits, RegBank);
}
// Postorder register normalization.
@@ -2064,15 +2059,14 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
// Iterate through SubRegisters.
typedef CodeGenRegister::SubRegMap SubRegMap;
const SubRegMap &SubRegs = Register.getSubRegs();
- for (SubRegMap::const_iterator S = SubRegs.begin(),
- SE = SubRegs.end(); S != SE; ++S) {
- CodeGenRegister *SubReg = S->second;
+ for (auto S : SubRegs) {
+ CodeGenRegister *SubReg = S.second;
// Ignore non-leaf subregisters, their lane masks are fully covered by
// the leaf subregisters anyway.
if (!SubReg->getSubRegs().empty())
continue;
- CodeGenSubRegIndex *SubRegIndex = S->first;
- const CodeGenRegister *SubRegister = S->second;
+ CodeGenSubRegIndex *SubRegIndex = S.first;
+ const CodeGenRegister *SubRegister = S.second;
LaneBitmask LaneMask = SubRegIndex->LaneMask;
// Distribute LaneMask to Register Units touched.
for (unsigned SUI : SubRegister->getRegUnits()) {
@@ -2194,10 +2188,9 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
if (R->Artificial)
continue;
const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
- for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
- E = SRM.end(); I != E; ++I) {
- if (!I->first->Artificial)
- SRSets[I->first].push_back(R);
+ for (auto I : SRM) {
+ if (!I.first->Artificial)
+ SRSets[I.first].push_back(R);
}
}
@@ -2422,9 +2415,8 @@ BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
// This new super-register is covered by its sub-registers.
bool AllSubsInSet = true;
const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
- for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
- E = SRM.end(); I != E; ++I)
- if (!Set.count(I->second)) {
+ for (auto I : SRM)
+ if (!Set.count(I.second)) {
AllSubsInSet = false;
break;
}
generated by cgit v1.3 (git 2.53.0) at 2026-09-04 03:26:43 +0000