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Diffstat (limited to 'llvm/utils/TableGen/FastISelEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/FastISelEmitter.cpp75
1 files changed, 32 insertions, 43 deletions
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index 0729ab70d696..d64262124308 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -290,9 +290,11 @@ struct OperandsSignature {
}
void PrintParameters(raw_ostream &OS) const {
+ ListSeparator LS;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ OS << LS;
if (Operands[i].isReg()) {
- OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
+ OS << "unsigned Op" << i;
} else if (Operands[i].isImm()) {
OS << "uint64_t imm" << i;
} else if (Operands[i].isFP()) {
@@ -300,31 +302,25 @@ struct OperandsSignature {
} else {
llvm_unreachable("Unknown operand kind!");
}
- if (i + 1 != e)
- OS << ", ";
}
}
void PrintArguments(raw_ostream &OS,
const std::vector<std::string> &PR) const {
assert(PR.size() == Operands.size());
- bool PrintedArg = false;
+ ListSeparator LS;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (PR[i] != "")
// Implicit physical register operand.
continue;
- if (PrintedArg)
- OS << ", ";
+ OS << LS;
if (Operands[i].isReg()) {
- OS << "Op" << i << ", Op" << i << "IsKill";
- PrintedArg = true;
+ OS << "Op" << i;
} else if (Operands[i].isImm()) {
OS << "imm" << i;
- PrintedArg = true;
} else if (Operands[i].isFP()) {
OS << "f" << i;
- PrintedArg = true;
} else {
llvm_unreachable("Unknown operand kind!");
}
@@ -332,9 +328,11 @@ struct OperandsSignature {
}
void PrintArguments(raw_ostream &OS) const {
+ ListSeparator LS;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ OS << LS;
if (Operands[i].isReg()) {
- OS << "Op" << i << ", Op" << i << "IsKill";
+ OS << "Op" << i;
} else if (Operands[i].isImm()) {
OS << "imm" << i;
} else if (Operands[i].isFP()) {
@@ -342,8 +340,6 @@ struct OperandsSignature {
} else {
llvm_unreachable("Unknown operand kind!");
}
- if (i + 1 != e)
- OS << ", ";
}
}
@@ -620,10 +616,10 @@ void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
return;
OS << "\n// FastEmit Immediate Predicate functions.\n";
- for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
- E = ImmediatePredicates.end(); I != E; ++I) {
- OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
- OS << I->getImmediatePredicateCode() << "\n}\n";
+ for (auto ImmediatePredicate : ImmediatePredicates) {
+ OS << "static bool " << ImmediatePredicate.getFnName()
+ << "(int64_t Imm) {\n";
+ OS << ImmediatePredicate.getImmediatePredicateCode() << "\n}\n";
}
OS << "\n\n";
@@ -677,7 +673,7 @@ void FastISelMap::emitInstructionCode(raw_ostream &OS,
OS << ");\n";
} else {
OS << "extractsubreg(" << RetVTName
- << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
+ << ", Op0, " << Memo.SubRegNo << ");\n";
}
if (!PredicateCheck.empty()) {
@@ -695,29 +691,25 @@ void FastISelMap::emitInstructionCode(raw_ostream &OS,
void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
// Now emit code for all the patterns that we collected.
- for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
- OE = SimplePatterns.end(); OI != OE; ++OI) {
- const OperandsSignature &Operands = OI->first;
- const OpcodeTypeRetPredMap &OTM = OI->second;
+ for (const auto &SimplePattern : SimplePatterns) {
+ const OperandsSignature &Operands = SimplePattern.first;
+ const OpcodeTypeRetPredMap &OTM = SimplePattern.second;
- for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
- I != E; ++I) {
- const std::string &Opcode = I->first;
- const TypeRetPredMap &TM = I->second;
+ for (const auto &I : OTM) {
+ const std::string &Opcode = I.first;
+ const TypeRetPredMap &TM = I.second;
OS << "// FastEmit functions for " << Opcode << ".\n";
OS << "\n";
// Emit one function for each opcode,type pair.
- for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
- TI != TE; ++TI) {
- MVT::SimpleValueType VT = TI->first;
- const RetPredMap &RM = TI->second;
+ for (const auto &TI : TM) {
+ MVT::SimpleValueType VT = TI.first;
+ const RetPredMap &RM = TI.second;
if (RM.size() != 1) {
- for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
- RI != RE; ++RI) {
- MVT::SimpleValueType RetVT = RI->first;
- const PredMap &PM = RI->second;
+ for (const auto &RI : RM) {
+ MVT::SimpleValueType RetVT = RI.first;
+ const PredMap &PM = RI.second;
OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_"
<< getLegalCName(std::string(getName(VT))) << "_"
@@ -739,9 +731,8 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\nswitch (RetVT.SimpleTy) {\n";
- for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
- RI != RE; ++RI) {
- MVT::SimpleValueType RetVT = RI->first;
+ for (const auto &RI : RM) {
+ MVT::SimpleValueType RetVT = RI.first;
OS << " case " << getName(RetVT) << ": return fastEmit_"
<< getLegalCName(Opcode) << "_"
<< getLegalCName(std::string(getName(VT))) << "_"
@@ -783,9 +774,8 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
Operands.PrintParameters(OS);
OS << ") {\n";
OS << " switch (VT.SimpleTy) {\n";
- for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
- TI != TE; ++TI) {
- MVT::SimpleValueType VT = TI->first;
+ for (const auto &TI : TM) {
+ MVT::SimpleValueType VT = TI.first;
std::string TypeName = std::string(getName(VT));
OS << " case " << TypeName << ": return fastEmit_"
<< getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
@@ -850,9 +840,8 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
}
OS << " switch (Opcode) {\n";
- for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
- I != E; ++I) {
- const std::string &Opcode = I->first;
+ for (const auto &I : OTM) {
+ const std::string &Opcode = I.first;
OS << " case " << Opcode << ": return fastEmit_"
<< getLegalCName(Opcode) << "_";
generated by cgit v1.3 (git 2.53.0) at 2026-09-03 09:36:12 +0000