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Diffstat (limited to 'pl/math/v_sinh_3u.c')
-rw-r--r--pl/math/v_sinh_3u.c120
1 files changed, 72 insertions, 48 deletions
diff --git a/pl/math/v_sinh_3u.c b/pl/math/v_sinh_3u.c
index 57ec66ecc282..a644f54b4a0f 100644
--- a/pl/math/v_sinh_3u.c
+++ b/pl/math/v_sinh_3u.c
@@ -6,47 +6,73 @@
*/
#include "v_math.h"
-#include "estrin.h"
+#include "poly_advsimd_f64.h"
#include "pl_sig.h"
#include "pl_test.h"
-#define AbsMask 0x7fffffffffffffff
-#define Half 0x3fe0000000000000
-#define BigBound \
- 0x4080000000000000 /* 2^9. expm1 helper overflows for large input. */
-#define TinyBound \
- 0x3e50000000000000 /* 2^-26, below which sinh(x) rounds to x. */
-#define InvLn2 v_f64 (0x1.71547652b82fep0)
-#define MLn2hi v_f64 (-0x1.62e42fefa39efp-1)
-#define MLn2lo v_f64 (-0x1.abc9e3b39803fp-56)
-#define Shift v_f64 (0x1.8p52)
-#define One 0x3ff0000000000000
-#define C(i) v_f64 (__expm1_poly[i])
+static const struct data
+{
+ float64x2_t poly[11];
+ float64x2_t inv_ln2, m_ln2, shift;
+ uint64x2_t halff;
+ int64x2_t onef;
+#if WANT_SIMD_EXCEPT
+ uint64x2_t tiny_bound, thresh;
+#else
+ uint64x2_t large_bound;
+#endif
+} data = {
+ /* Generated using Remez, deg=12 in [-log(2)/2, log(2)/2]. */
+ .poly = { V2 (0x1p-1), V2 (0x1.5555555555559p-3), V2 (0x1.555555555554bp-5),
+ V2 (0x1.111111110f663p-7), V2 (0x1.6c16c16c1b5f3p-10),
+ V2 (0x1.a01a01affa35dp-13), V2 (0x1.a01a018b4ecbbp-16),
+ V2 (0x1.71ddf82db5bb4p-19), V2 (0x1.27e517fc0d54bp-22),
+ V2 (0x1.af5eedae67435p-26), V2 (0x1.1f143d060a28ap-29), },
-#if V_SUPPORTED
+ .inv_ln2 = V2 (0x1.71547652b82fep0),
+ .m_ln2 = (float64x2_t) {-0x1.62e42fefa39efp-1, -0x1.abc9e3b39803fp-56},
+ .shift = V2 (0x1.8p52),
-static inline v_f64_t
-expm1_inline (v_f64_t x)
+ .halff = V2 (0x3fe0000000000000),
+ .onef = V2 (0x3ff0000000000000),
+#if WANT_SIMD_EXCEPT
+ /* 2^-26, below which sinh(x) rounds to x. */
+ .tiny_bound = V2 (0x3e50000000000000),
+ /* asuint(large_bound) - asuint(tiny_bound). */
+ .thresh = V2 (0x0230000000000000),
+#else
+/* 2^9. expm1 helper overflows for large input. */
+ .large_bound = V2 (0x4080000000000000),
+#endif
+};
+
+static inline float64x2_t
+expm1_inline (float64x2_t x)
{
+ const struct data *d = ptr_barrier (&data);
+
/* Reduce argument:
exp(x) - 1 = 2^i * (expm1(f) + 1) - 1
where i = round(x / ln2)
and f = x - i * ln2 (f in [-ln2/2, ln2/2]). */
- v_f64_t j = v_fma_f64 (InvLn2, x, Shift) - Shift;
- v_s64_t i = v_to_s64_f64 (j);
- v_f64_t f = v_fma_f64 (j, MLn2hi, x);
- f = v_fma_f64 (j, MLn2lo, f);
+ float64x2_t j = vsubq_f64 (vfmaq_f64 (d->shift, d->inv_ln2, x), d->shift);
+ int64x2_t i = vcvtq_s64_f64 (j);
+ float64x2_t f = vfmaq_laneq_f64 (x, j, d->m_ln2, 0);
+ f = vfmaq_laneq_f64 (f, j, d->m_ln2, 1);
/* Approximate expm1(f) using polynomial. */
- v_f64_t f2 = f * f, f4 = f2 * f2, f8 = f4 * f4;
- v_f64_t p = v_fma_f64 (f2, ESTRIN_10 (f, f2, f4, f8, C), f);
+ float64x2_t f2 = vmulq_f64 (f, f);
+ float64x2_t f4 = vmulq_f64 (f2, f2);
+ float64x2_t f8 = vmulq_f64 (f4, f4);
+ float64x2_t p = vfmaq_f64 (f, f2, v_estrin_10_f64 (f, f2, f4, f8, d->poly));
/* t = 2^i. */
- v_f64_t t = v_as_f64_u64 (v_as_u64_s64 (i << 52) + One);
+ float64x2_t t = vreinterpretq_f64_u64 (
+ vreinterpretq_u64_s64 (vaddq_s64 (vshlq_n_s64 (i, 52), d->onef)));
/* expm1(x) ~= p * t + (t - 1). */
- return v_fma_f64 (p, t, t - 1);
+ return vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t);
}
-static NOINLINE VPCS_ATTR v_f64_t
-special_case (v_f64_t x)
+static float64x2_t NOINLINE VPCS_ATTR
+special_case (float64x2_t x)
{
return v_call_f64 (sinh, x, x, v_u64 (-1));
}
@@ -54,20 +80,22 @@ special_case (v_f64_t x)
/* Approximation for vector double-precision sinh(x) using expm1.
sinh(x) = (exp(x) - exp(-x)) / 2.
The greatest observed error is 2.57 ULP:
- sinh(0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2
- want 0x1.ab34e59d678d9p-2. */
-VPCS_ATTR v_f64_t V_NAME (sinh) (v_f64_t x)
+ _ZGVnN2v_sinh (0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2
+ want 0x1.ab34e59d678d9p-2. */
+float64x2_t VPCS_ATTR V_NAME_D1 (sinh) (float64x2_t x)
{
- v_u64_t ix = v_as_u64_f64 (x);
- v_u64_t iax = ix & AbsMask;
- v_f64_t ax = v_as_f64_u64 (iax);
- v_u64_t sign = ix & ~AbsMask;
- v_f64_t halfsign = v_as_f64_u64 (sign | Half);
+ const struct data *d = ptr_barrier (&data);
+
+ float64x2_t ax = vabsq_f64 (x);
+ uint64x2_t sign
+ = veorq_u64 (vreinterpretq_u64_f64 (x), vreinterpretq_u64_f64 (ax));
+ float64x2_t halfsign = vreinterpretq_f64_u64 (vorrq_u64 (sign, d->halff));
#if WANT_SIMD_EXCEPT
- v_u64_t special = v_cond_u64 ((iax - TinyBound) >= (BigBound - TinyBound));
+ uint64x2_t special = vcgeq_u64 (
+ vsubq_u64 (vreinterpretq_u64_f64 (ax), d->tiny_bound), d->thresh);
#else
- v_u64_t special = v_cond_u64 (iax >= BigBound);
+ uint64x2_t special = vcgeq_u64 (vreinterpretq_u64_f64 (ax), d->large_bound);
#endif
/* Fall back to scalar variant for all lanes if any of them are special. */
@@ -77,18 +105,14 @@ VPCS_ATTR v_f64_t V_NAME (sinh) (v_f64_t x)
/* Up to the point that expm1 overflows, we can use it to calculate sinh
using a slight rearrangement of the definition of sinh. This allows us to
retain acceptable accuracy for very small inputs. */
- v_f64_t t = expm1_inline (ax);
- return (t + t / (t + 1)) * halfsign;
+ float64x2_t t = expm1_inline (ax);
+ t = vaddq_f64 (t, vdivq_f64 (t, vaddq_f64 (t, v_f64 (1.0))));
+ return vmulq_f64 (t, halfsign);
}
-VPCS_ALIAS
PL_SIG (V, D, 1, sinh, -10.0, 10.0)
-PL_TEST_ULP (V_NAME (sinh), 2.08)
-PL_TEST_EXPECT_FENV (V_NAME (sinh), WANT_SIMD_EXCEPT)
-PL_TEST_INTERVAL (V_NAME (sinh), 0, TinyBound, 1000)
-PL_TEST_INTERVAL (V_NAME (sinh), -0, -TinyBound, 1000)
-PL_TEST_INTERVAL (V_NAME (sinh), TinyBound, BigBound, 500000)
-PL_TEST_INTERVAL (V_NAME (sinh), -TinyBound, -BigBound, 500000)
-PL_TEST_INTERVAL (V_NAME (sinh), BigBound, inf, 1000)
-PL_TEST_INTERVAL (V_NAME (sinh), -BigBound, -inf, 1000)
-#endif
+PL_TEST_ULP (V_NAME_D1 (sinh), 2.08)
+PL_TEST_EXPECT_FENV (V_NAME_D1 (sinh), WANT_SIMD_EXCEPT)
+PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0, 0x1p-26, 1000)
+PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0x1p-26, 0x1p9, 500000)
+PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0x1p9, inf, 1000)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 17:29:35 +0000