diff options
Diffstat (limited to 'src/arm64/qcom/sa8540p-ride.dts')
| -rw-r--r-- | src/arm64/qcom/sa8540p-ride.dts | 192 |
1 files changed, 163 insertions, 29 deletions
diff --git a/src/arm64/qcom/sa8540p-ride.dts b/src/arm64/qcom/sa8540p-ride.dts index 6c547f1b13dc..24fa449d48a6 100644 --- a/src/arm64/qcom/sa8540p-ride.dts +++ b/src/arm64/qcom/sa8540p-ride.dts @@ -10,14 +10,19 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sa8540p.dtsi" -#include "pm8450a.dtsi" +#include "sa8540p-pmics.dtsi" / { model = "Qualcomm SA8540P Ride"; compatible = "qcom,sa8540p-ride", "qcom,sa8540p"; aliases { - serial0 = &qup2_uart17; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c12 = &i2c12; + i2c15 = &i2c15; + i2c18 = &i2c18; + serial0 = &uart17; }; chosen { @@ -146,6 +151,62 @@ }; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; + + status = "okay"; +}; + +&i2c12 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_default>; + + status = "okay"; +}; + +&i2c15 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c15_default>; + + status = "okay"; +}; + +&i2c18 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c18_default>; + + status = "okay"; +}; + +&pcie2a { + ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, + <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; + + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + &pcie3a { ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, @@ -167,17 +228,20 @@ status = "okay"; }; -&qup2 { +&qup0 { status = "okay"; }; -&qup2_uart17 { - compatible = "qcom,geni-debug-uart"; +&qup1 { + status = "okay"; +}; + +&qup2 { status = "okay"; }; &remoteproc_nsp0 { - firmware-name = "qcom/sa8540p/cdsp.mbn"; + firmware-name = "qcom/sa8540p/cdsp0.mbn"; status = "okay"; }; @@ -186,29 +250,9 @@ status = "okay"; }; -&tlmm { - pcie3a_default: pcie3a-default-state { - perst-pins { - pins = "gpio151"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio150"; - function = "pcie3a_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio56"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; +&uart17 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; }; &ufs_mem_hc { @@ -268,3 +312,93 @@ &xo_board_clk { clock-frequency = <38400000>; }; + +/* PINCTRL */ + +&tlmm { + i2c0_default: i2c0-default-state { + /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ + pins = "gpio135", "gpio136"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c1_default: i2c1-default-state { + /* To PM40028B-F3EI PCIe switch */ + pins = "gpio158", "gpio159"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c12_default: i2c12-default-state { + /* To Maxim max20411 */ + pins = "gpio0", "gpio1"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c15_default: i2c15-default-state { + /* To display connector (SIP1 only) */ + pins = "gpio36", "gpio37"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c18_default: i2c18-default-state { + /* To ASM330LHH IMU (SIP1 only) */ + pins = "gpio66", "gpio67"; + function = "qup18"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie2a_default: pcie2a-default-state { + perst-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3a_default: pcie3a-default-state { + perst-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; |