aboutsummaryrefslogtreecommitdiff
path: root/src/arm64/qcom/sm8450.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'src/arm64/qcom/sm8450.dtsi')
-rw-r--r--src/arm64/qcom/sm8450.dtsi489
1 files changed, 416 insertions, 73 deletions
diff --git a/src/arm64/qcom/sm8450.dtsi b/src/arm64/qcom/sm8450.dtsi
index 570475040d95..b285b1530c10 100644
--- a/src/arm64/qcom/sm8450.dtsi
+++ b/src/arm64/qcom/sm8450.dtsi
@@ -57,9 +57,11 @@
clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
};
@@ -77,6 +79,7 @@
clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -94,6 +97,7 @@
clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -111,6 +115,7 @@
clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -128,6 +133,7 @@
clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -145,6 +151,7 @@
clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -163,6 +170,7 @@
clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -180,6 +188,7 @@
clocks = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@@ -270,6 +279,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sm8450", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x13000>;
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
#reset-cells = <1>;
};
@@ -302,55 +312,55 @@
compatible = "arm,psci-1.0";
method = "smc";
- CPU_PD0: cpu0 {
+ CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
- CPU_PD1: cpu1 {
+ CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
- CPU_PD2: cpu2 {
+ CPU_PD2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
- CPU_PD3: cpu3 {
+ CPU_PD3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
- CPU_PD4: cpu4 {
+ CPU_PD4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
- CPU_PD5: cpu5 {
+ CPU_PD5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
- CPU_PD6: cpu6 {
+ CPU_PD6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
- CPU_PD7: cpu7 {
+ CPU_PD7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
- CLUSTER_PD: cpu-cluster0 {
+ CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
};
@@ -731,19 +741,29 @@
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
<&pcie0_lane>,
<&pcie1_lane>,
- <&sleep_clk>;
+ <0>,
+ <&ufs_mem_phy_lanes 0>,
+ <&ufs_mem_phy_lanes 1>,
+ <&ufs_mem_phy_lanes 2>,
+ <0>;
clock-names = "bi_tcxo",
+ "sleep_clk",
"pcie_0_pipe_clk",
"pcie_1_pipe_clk",
- "sleep_clk";
+ "pcie_1_phy_aux_clk",
+ "ufs_phy_rx_symbol_0_clk",
+ "ufs_phy_rx_symbol_1_clk",
+ "ufs_phy_tx_symbol_0_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
};
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
#dma-cells = <3>;
- reg = <0 0x800000 0 0x60000>;
+ reg = <0 0x00800000 0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
@@ -997,8 +1017,6 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart20_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
@@ -1064,7 +1082,7 @@
gpi_dma0: dma-controller@900000 {
compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
#dma-cells = <3>;
- reg = <0 0x900000 0 0x60000>;
+ reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
@@ -1345,7 +1363,7 @@
i2c6: i2c@998000 {
compatible = "qcom,geni-i2c";
- reg = <0x0 0x998000 0x0 0x4000>;
+ reg = <0x0 0x00998000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
@@ -1365,7 +1383,7 @@
spi6: spi@998000 {
compatible = "qcom,geni-spi";
- reg = <0x0 0x998000 0x0 0x4000>;
+ reg = <0x0 0x00998000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
@@ -1391,8 +1409,6 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
};
@@ -1400,7 +1416,7 @@
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
#dma-cells = <3>;
- reg = <0 0xa00000 0 0x60000>;
+ reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
@@ -1733,6 +1749,13 @@
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+ /*
+ * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
+ * Hence, the IDs are swapped.
+ */
+ msi-map = <0x0 &gic_its 0x5981 0x1>,
+ <0x100 &gic_its 0x5980 0x1>;
+ msi-map-mask = <0xff00>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
@@ -1810,10 +1833,10 @@
status = "disabled";
pcie0_lane: phy@1c06200 {
- reg = <0 0x1c06e00 0 0x200>, /* tx */
- <0 0x1c07000 0 0x200>, /* rx */
- <0 0x1c06200 0 0x200>, /* pcs */
- <0 0x1c06600 0 0x200>; /* pcs_pcie */
+ reg = <0 0x01c06e00 0 0x200>, /* tx */
+ <0 0x01c07000 0 0x200>, /* rx */
+ <0 0x01c06200 0 0x200>, /* pcs */
+ <0 0x01c06600 0 0x200>; /* pcs_pcie */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
@@ -1842,6 +1865,13 @@
ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
+ /*
+ * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
+ * Hence, the IDs are swapped.
+ */
+ msi-map = <0x0 &gic_its 0x5a01 0x1>,
+ <0x100 &gic_its 0x5a00 0x1>;
+ msi-map-mask = <0xff00>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
@@ -1917,12 +1947,12 @@
status = "disabled";
pcie1_lane: phy@1c0e000 {
- reg = <0 0x1c0e000 0 0x200>, /* tx */
- <0 0x1c0e200 0 0x300>, /* rx */
- <0 0x1c0f200 0 0x200>, /* pcs */
- <0 0x1c0e800 0 0x200>, /* tx */
- <0 0x1c0ea00 0 0x300>, /* rx */
- <0 0x1c0f400 0 0xc00>; /* pcs_pcie */
+ reg = <0 0x01c0e000 0 0x200>, /* tx */
+ <0 0x01c0e200 0 0x300>, /* rx */
+ <0 0x01c0f200 0 0x200>, /* pcs */
+ <0 0x01c0e800 0 0x200>, /* tx */
+ <0 0x01c0ea00 0 0x300>, /* rx */
+ <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe0";
@@ -1986,6 +2016,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sm8450-tcsr", "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x30000>;
+ };
+
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8450-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
@@ -2108,8 +2143,8 @@
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
assigned-clock-rates = <19200000>, <19200000>;
#clock-cells = <0>;
@@ -2143,11 +2178,12 @@
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
+ status = "disabled";
};
rxmacro: codec@3200000 {
compatible = "qcom,sm8450-lpass-rx-macro";
- reg = <0 0x3200000 0 0x1000>;
+ reg = <0 0x03200000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
@@ -2168,7 +2204,7 @@
swr1: soundwire-controller@3210000 {
compatible = "qcom,soundwire-v1.7.0";
- reg = <0 0x3210000 0 0x2000>;
+ reg = <0 0x03210000 0 0x2000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rxmacro>;
clock-names = "iface";
@@ -2189,11 +2225,12 @@
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
+ status = "disabled";
};
txmacro: codec@3220000 {
compatible = "qcom,sm8450-lpass-tx-macro";
- reg = <0 0x3220000 0 0x1000>;
+ reg = <0 0x03220000 0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
@@ -2256,14 +2293,15 @@
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
+ status = "disabled";
};
swr2: soundwire-controller@33b0000 {
compatible = "qcom,soundwire-v1.7.0";
- reg = <0 0x33b0000 0 0x2000>;
+ reg = <0 0x033b0000 0 0x2000>;
interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "core", "wake";
+ interrupt-names = "core", "wakeup";
clocks = <&vamacro>;
clock-names = "iface";
@@ -2284,6 +2322,7 @@
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
+ status = "disabled";
};
vamacro: codec@33f0000 {
@@ -2300,6 +2339,7 @@
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
+ status = "disabled";
};
remoteproc_adsp: remoteproc@30000000 {
@@ -2554,8 +2594,8 @@
};
cci0: cci@ac15000 {
- compatible = "qcom,sm8450-cci";
- reg = <0 0xac15000 0 0x1000>;
+ compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac15000 0 0x1000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc TITAN_TOP_GDSC>;
@@ -2593,8 +2633,8 @@
};
cci1: cci@ac16000 {
- compatible = "qcom,sm8450-cci";
- reg = <0 0xac16000 0 0x1000>;
+ compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac16000 0 0x1000>;
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc TITAN_TOP_GDSC>;
@@ -2646,6 +2686,281 @@
status = "disabled";
};
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,sm8450-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
+ <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x2800 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8450-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8450_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-172000000 {
+ opp-hz = /bits/ 64 <172000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+ power-domains = <&rpmhpd SM8450_MMCX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sm8450-dsi-phy-5nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss_dsi1: dsi@ae96000 {
+ compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+ power-domains = <&rpmhpd SM8450_MMCX>;
+
+ phys = <&mdss_dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,sm8450-dsi-phy-5nm";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sm8450-dispcc";
reg = <0 0x0af00000 0 0x20000>;
@@ -2653,10 +2968,10 @@
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
- <0>, /* dsi0 */
- <0>,
- <0>, /* dsi1 */
- <0>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
<0>, /* dp0 */
<0>,
<0>, /* dp1 */
@@ -2705,7 +3020,7 @@
#thermal-sensor-cells = <1>;
};
- aoss_qmp: power-controller@c300000 {
+ aoss_qmp: power-management@c300000 {
compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
@@ -2715,6 +3030,28 @@
#clock-cells = <0>;
};
+ spmi_bus: spmi@c400000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c400000 0 0x00003000>,
+ <0 0x0c500000 0 0x00400000>,
+ <0 0x0c440000 0 0x00080000>,
+ <0 0x0c4c0000 0 0x00010000>,
+ <0 0x0c42d000 0 0x00010000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "intr",
+ "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
ipcc: mailbox@ed18000 {
compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
reg = <0 0x0ed18000 0 0x1000>;
@@ -3235,10 +3572,10 @@
};
- lpass_tlmm: pinctrl@3440000{
+ lpass_tlmm: pinctrl@3440000 {
compatible = "qcom,sm8450-lpass-lpi-pinctrl";
- reg = <0 0x3440000 0x0 0x20000>,
- <0 0x34d0000 0x0 0x10000>;
+ reg = <0 0x03440000 0x0 0x20000>,
+ <0 0x034d0000 0x0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
@@ -3580,35 +3917,39 @@
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
- rpmhpd_opp_low_svs: opp3 {
+ rpmhpd_opp_low_svs_d1: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
- rpmhpd_opp_svs: opp4 {
+ rpmhpd_opp_svs: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
- rpmhpd_opp_svs_l1: opp5 {
+ rpmhpd_opp_svs_l1: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
- rpmhpd_opp_nom: opp6 {
+ rpmhpd_opp_nom: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
- rpmhpd_opp_nom_l1: opp7 {
+ rpmhpd_opp_nom_l1: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
- rpmhpd_opp_nom_l2: opp8 {
+ rpmhpd_opp_nom_l2: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
- rpmhpd_opp_turbo: opp9 {
+ rpmhpd_opp_turbo: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
- rpmhpd_opp_turbo_l1: opp10 {
+ rpmhpd_opp_turbo_l1: opp11 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
@@ -3662,6 +4003,7 @@
power-domains = <&gcc UFS_PHY_GDSC>;
iommus = <&apps_smmu 0xe0 0x0>;
+ dma-coherent;
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
@@ -3720,6 +4062,7 @@
<0 0x01d87c00 0 0x200>,
<0 0x01d87800 0 0x188>,
<0 0x01d87a00 0 0x200>;
+ #clock-cells = <1>;
#phy-cells = <0>;
};
};
@@ -3825,7 +4168,7 @@
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,sm8450-lpass-ag-noc";
- reg = <0 0x3c40000 0 0x17200>;
+ reg = <0 0x03c40000 0 0x17200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
@@ -3953,7 +4296,7 @@
type = "passive";
};
- cpu4_top_crit: cpu_crit {
+ cpu4_top_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -3979,7 +4322,7 @@
type = "passive";
};
- cpu4_bottom_crit: cpu_crit {
+ cpu4_bottom_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4005,7 +4348,7 @@
type = "passive";
};
- cpu5_top_crit: cpu_crit {
+ cpu5_top_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4031,7 +4374,7 @@
type = "passive";
};
- cpu5_bottom_crit: cpu_crit {
+ cpu5_bottom_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4057,7 +4400,7 @@
type = "passive";
};
- cpu6_top_crit: cpu_crit {
+ cpu6_top_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4083,7 +4426,7 @@
type = "passive";
};
- cpu6_bottom_crit: cpu_crit {
+ cpu6_bottom_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4109,7 +4452,7 @@
type = "passive";
};
- cpu7_top_crit: cpu_crit {
+ cpu7_top_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4135,7 +4478,7 @@
type = "passive";
};
- cpu7_middle_crit: cpu_crit {
+ cpu7_middle_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4161,7 +4504,7 @@
type = "passive";
};
- cpu7_bottom_crit: cpu_crit {
+ cpu7_bottom_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4193,7 +4536,7 @@
type = "passive";
};
- gpu0_tj_cfg: tj_cfg {
+ gpu0_tj_cfg: tj-cfg {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
@@ -4225,7 +4568,7 @@
type = "passive";
};
- gpu1_tj_cfg: tj_cfg {
+ gpu1_tj_cfg: tj-cfg {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
@@ -4271,7 +4614,7 @@
type = "passive";
};
- cpu0_crit: cpu_crit {
+ cpu0_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4297,7 +4640,7 @@
type = "passive";
};
- cpu1_crit: cpu_crit {
+ cpu1_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4323,7 +4666,7 @@
type = "passive";
};
- cpu2_crit: cpu_crit {
+ cpu2_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4349,7 +4692,7 @@
type = "passive";
};
- cpu3_crit: cpu_crit {
+ cpu3_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 20:16:47 +0000