diff options
Diffstat (limited to 'src/arm64/ti/k3-j721s2-main.dtsi')
| -rw-r--r-- | src/arm64/ti/k3-j721s2-main.dtsi | 405 |
1 files changed, 405 insertions, 0 deletions
diff --git a/src/arm64/ti/k3-j721s2-main.dtsi b/src/arm64/ti/k3-j721s2-main.dtsi index 2dd7865f7654..ed79ab3a3271 100644 --- a/src/arm64/ti/k3-j721s2-main.dtsi +++ b/src/arm64/ti/k3-j721s2-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/phy/phy-cadence.h> +#include <dt-bindings/phy/phy-ti.h> + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +37,29 @@ }; }; + scm_conf: syscon@104000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00104000 0x00 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible = "mmio-mux"; + reg = <0x0 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + + serdes_ln_ctrl: mux-controller@80 { + compatible = "mmio-mux"; + reg = <0x80 0x10>; + #mux-control-cells = <1>; + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -72,6 +106,24 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x00 0x04e00000 0x00 0x1200>; @@ -91,6 +143,246 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>; + assigned-clock-parents = <&k3_clks 64 2>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>; + assigned-clock-parents = <&k3_clks 66 2>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>; + assigned-clock-parents = <&k3_clks 68 2>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>; + assigned-clock-parents = <&k3_clks 70 2>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>; + assigned-clock-parents = <&k3_clks 71 2>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>; + assigned-clock-parents = <&k3_clks 73 2>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>; + assigned-clock-parents = <&k3_clks 75 2>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>; + assigned-clock-parents = <&k3_clks 77 2>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>; + assigned-clock-parents = <&k3_clks 79 2>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 80 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 80 1>; + assigned-clock-parents = <&k3_clks 80 2>; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 81 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 81 1>; + assigned-clock-parents = <&k3_clks 81 2>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 82 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 82 1>; + assigned-clock-parents = <&k3_clks 82 2>; + power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; @@ -738,6 +1030,8 @@ reg-names = "cpts"; clocks = <&k3_clks 226 5>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ + assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&main_navss_intr 391>; interrupt-names = "cpts"; ti,cpts-periodic-outputs = <6>; @@ -745,6 +1039,117 @@ }; }; + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x04104000 0x00 0x100>; + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 360 17>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + + status = "disabled"; /* Needs pinmux */ + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721s2-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 365 3>; + assigned-clock-parents = <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x800000>, + <0x00 0x18000000 0x00 0x1000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status = "disabled"; /* Needs gpio and serdes info */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, |