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-rw-r--r--test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll30
-rw-r--r--test/CodeGen/ARM/ifcvt-branch-weight-bug.ll2
2 files changed, 31 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
index 53577dbd76f6..1a0c7fd8e1d6 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+++ b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
@@ -699,3 +699,33 @@ define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32
%res = extractelement <2 x i32> %shuffle, i32 0
ret i32 %res
}
+
+%struct.v2s32 = type { <2 x i32> }
+
+define i32 @test_constantstruct_v2s32() {
+; CHECK-LABEL: name: test_constantstruct_v2s32
+; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
+; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
+; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
+ %vec = extractvalue %struct.v2s32 {<2 x i32><i32 1, i32 2>}, 0
+ %elt = extractelement <2 x i32> %vec, i32 0
+ ret i32 %elt
+}
+
+%struct.v2s32.s32.s32 = type { <2 x i32>, i32, i32 }
+
+define i32 @test_constantstruct_v2s32_s32_s32() {
+; CHECK-LABEL: name: test_constantstruct_v2s32_s32_s32
+; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
+; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
+; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
+; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
+; CHECK: [[CS:%[0-9]+]](s128) = G_SEQUENCE [[VEC]](<2 x s32>), 0, [[C3]](s32), 64, [[C4]](s32), 96
+; CHECK: [[EXT:%[0-9]+]](<2 x s32>) = G_EXTRACT [[CS]](s128), 0
+; CHECK: G_EXTRACT_VECTOR_ELT [[EXT]](<2 x s32>)
+ %vec = extractvalue %struct.v2s32.s32.s32 {<2 x i32><i32 1, i32 2>, i32 3, i32 4}, 0
+ %elt = extractelement <2 x i32> %vec, i32 0
+ ret i32 %elt
+}
diff --git a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
index a44c9721d6c1..1c8142e5ddd5 100644
--- a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
+++ b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
@@ -22,7 +22,7 @@ entry:
; for.body -> for.cond.backedge (100%)
; -> cond.false.i (0%)
; CHECK: BB#1: derived from LLVM BB %for.body
-; CHECK: Successors according to CFG: BB#2(0x7ffffc00 / 0x80000000 = 100.00%) BB#4(0x00000400 / 0x80000000 = 0.00%)
+; CHECK: Successors according to CFG: BB#2(0x80000000 / 0x80000000 = 100.00%) BB#4(0x00000001 / 0x80000000 = 0.00%)
for.body:
br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1