diff options
Diffstat (limited to 'test/CodeGen/ARM')
178 files changed, 7198 insertions, 1948 deletions
diff --git a/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/test/CodeGen/ARM/2007-03-13-InstrSched.ll index 9c0143be06c3..81a6bb64971d 100644 --- a/test/CodeGen/ARM/2007-03-13-InstrSched.ll +++ b/test/CodeGen/ARM/2007-03-13-InstrSched.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \ ; RUN: -mattr=+v6 | grep r9 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \ -; RUN: -mattr=+v6 -arm-reserve-r9 -ifcvt-limit=0 -stats 2>&1 | grep asm-printer +; RUN: -mattr=+v6,+reserve-r9 -ifcvt-limit=0 -stats 2>&1 | grep asm-printer ; | grep 35 define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) { diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll index 3f47488372b8..613694f091d1 100644 --- a/test/CodeGen/ARM/2009-10-16-Scope.ll +++ b/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -24,9 +24,9 @@ declare i32 @foo(i32) ssp !0 = !DILocation(line: 5, column: 2, scope: !1) !1 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !2) -!2 = !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !3) -!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 1.1", isOptimized: true, emissionKind: 0, file: !8, retainedTypes: !9) -!4 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "count_", line: 5, scope: !5, file: !3, type: !6) +!2 = distinct !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !3) +!3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang 1.1", isOptimized: true, emissionKind: 0, file: !8, retainedTypes: !9) +!4 = !DILocalVariable(name: "count_", line: 5, scope: !5, file: !3, type: !6) !5 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !1) !6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !7 = !DILocation(line: 6, column: 1, scope: !2) diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index 638b26c73146..1341830b4a4b 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -14,11 +14,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!15} -!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 93, arg: 0, scope: !1, file: !2, type: !6) -!1 = !DISubprogram(name: "__addvsi3", linkageName: "__addvsi3", line: 94, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: null, type: !4) +!0 = !DILocalVariable(name: "b", line: 93, arg: 2, scope: !1, file: !2, type: !6) +!1 = distinct !DISubprogram(name: "__addvsi3", linkageName: "__addvsi3", line: 94, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: null, type: !4) !2 = !DIFile(filename: "libgcc2.c", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc") !12 = !DIFile(filename: "libgcc2.c", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc") -!3 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", isOptimized: true, emissionKind: 0, file: !12, enums: !13, retainedTypes: !13, subprograms: !14) +!3 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", isOptimized: true, emissionKind: 0, file: !12, enums: !13, retainedTypes: !13, subprograms: !14) !4 = !DISubroutineType(types: !5) !5 = !{!6, !6, !6} !6 = !DIDerivedType(tag: DW_TAG_typedef, name: "SItype", line: 152, file: !12, baseType: !8) diff --git a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll index cfaffd8234ba..171b6d2bcc5c 100644 --- a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll +++ b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -1,36 +1,36 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+neon -O0 -optimize-regalloc -regalloc=basic %s -o /dev/null ; This test would crash the rewriter when trying to handle a spill after one of -; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. +; the @llvm.arm.neon.vld3.v8i8.p0i8 defined three parts of a register. %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } -declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly -declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind define <8 x i8> @t3(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind { - %tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A2, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A2, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2b = extractvalue %struct.__neon_int8x8x3_t %tmp1b, 0 ; <<8 x i8>> [#uses=1] %tmp4b = extractvalue %struct.__neon_int8x8x3_t %tmp1b, 1 ; <<8 x i8>> [#uses=1] - %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1] %tmp4d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 1 ; <<8 x i8>> [#uses=1] - %tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A5, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A5, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] %tmp2e = extractvalue %struct.__neon_int8x8x3_t %tmp1e, 0 ; <<8 x i8>> [#uses=1] - %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] %tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1] - %tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A7, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A7, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2g = extractvalue %struct.__neon_int8x8x3_t %tmp1g, 0 ; <<8 x i8>> [#uses=1] %tmp4g = extractvalue %struct.__neon_int8x8x3_t %tmp1g, 1 ; <<8 x i8>> [#uses=1] - %tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A8, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A8, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2h = extractvalue %struct.__neon_int8x8x3_t %tmp1h, 0 ; <<8 x i8>> [#uses=1] %tmp3h = extractvalue %struct.__neon_int8x8x3_t %tmp1h, 2 ; <<8 x i8>> [#uses=1] %tmp2bd = add <8 x i8> %tmp2b, %tmp2d ; <<8 x i8>> [#uses=1] %tmp4bd = add <8 x i8> %tmp4b, %tmp4d ; <<8 x i8>> [#uses=1] %tmp2abcd = mul <8 x i8> undef, %tmp2bd ; <<8 x i8>> [#uses=1] %tmp4abcd = mul <8 x i8> undef, %tmp4bd ; <<8 x i8>> [#uses=2] - call void @llvm.arm.neon.vst3.v8i8(i8* %A1, <8 x i8> %tmp4abcd, <8 x i8> zeroinitializer, <8 x i8> %tmp2abcd, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A1, <8 x i8> %tmp4abcd, <8 x i8> zeroinitializer, <8 x i8> %tmp2abcd, i32 1) %tmp2ef = sub <8 x i8> %tmp2e, %tmp2f ; <<8 x i8>> [#uses=1] %tmp2gh = sub <8 x i8> %tmp2g, %tmp2h ; <<8 x i8>> [#uses=1] %tmp3gh = sub <8 x i8> zeroinitializer, %tmp3h ; <<8 x i8>> [#uses=1] @@ -38,8 +38,8 @@ define <8 x i8> @t3(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A %tmp2efgh = mul <8 x i8> %tmp2ef, %tmp2gh ; <<8 x i8>> [#uses=1] %tmp3efgh = mul <8 x i8> undef, %tmp3gh ; <<8 x i8>> [#uses=1] %tmp4efgh = mul <8 x i8> %tmp4ef, undef ; <<8 x i8>> [#uses=2] - call void @llvm.arm.neon.vst3.v8i8(i8* %A2, <8 x i8> %tmp4efgh, <8 x i8> %tmp3efgh, <8 x i8> %tmp2efgh, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A2, <8 x i8> %tmp4efgh, <8 x i8> %tmp3efgh, <8 x i8> %tmp2efgh, i32 1) %tmp4 = sub <8 x i8> %tmp4efgh, %tmp4abcd ; <<8 x i8>> [#uses=1] - tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> zeroinitializer, <8 x i8> undef, <8 x i8> undef, i32 1) + tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> zeroinitializer, <8 x i8> undef, <8 x i8> undef, i32 1) ret <8 x i8> %tmp4 } diff --git a/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/test/CodeGen/ARM/2010-05-21-BuildVector.ll index 6a6ccf3d0a01..c6c0e2caee42 100644 --- a/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -36,8 +36,8 @@ entry: %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3 %19 = fmul <4 x float> %tmp5, %2 %20 = bitcast float* %fltp to i8* - tail call void @llvm.arm.neon.vst1.v4f32(i8* %20, <4 x float> %19, i32 1) + tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %20, <4 x float> %19, i32 1) ret void } -declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind diff --git a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll index f86c3ba9ef6e..1deb98631a4f 100644 --- a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll +++ b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll @@ -12,8 +12,8 @@ entry: %tmp9 = trunc i128 %tmp8 to i64 ; <i64> [#uses=1] %tmp16.i = bitcast i64 %tmp6 to <8 x i8> ; <<8 x i8>> [#uses=1] %tmp20.i = bitcast i64 %tmp9 to <8 x i8> ; <<8 x i8>> [#uses=1] - tail call void @llvm.arm.neon.vst2.v8i8(i8* %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i, i32 1) nounwind + tail call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %b, <8 x i8> %tmp16.i, <8 x i8> %tmp20.i, i32 1) nounwind ret void } -declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind diff --git a/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll index bead8d9781e8..47a5ef0bc544 100755 --- a/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll +++ b/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll @@ -20,7 +20,7 @@ @.str51 = external constant [45 x i8] ; <[45 x i8]*> [#uses=1] @__PRETTY_FUNCTION__._ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs = external constant [116 x i8] ; <[116 x i8]*> [#uses=1] -@_ZN4llvm9RecordValC1ERKSsPNS_5RecTyEj = alias void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)* @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj ; <void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)*> [#uses=0] +@_ZN4llvm9RecordValC1ERKSsPNS_5RecTyEj = alias void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32), void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)* @_ZN4llvm9RecordValC2ERKSsPNS_5RecTyEj ; <void (%"class.llvm::RecordVal"*, %"class.std::basic_string"*, %"struct.llvm::Init"*, i32)*> [#uses=0] declare i8* @__dynamic_cast(i8*, i8*, i8*, i32) diff --git a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll index 95bb2769759e..38b352c473b1 100644 --- a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll +++ b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -47,19 +47,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.lv.fn = !{!0, !8, !10, !12} !llvm.dbg.gv = !{!14} -!0 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "buf", line: 4, arg: 0, scope: !1, file: !2, type: !6) -!1 = !DISubprogram(name: "x0", linkageName: "x0", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !26, scope: null, type: !4) +!0 = !DILocalVariable(name: "buf", line: 4, arg: 1, scope: !1, file: !2, type: !6) +!1 = distinct !DISubprogram(name: "x0", linkageName: "x0", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !26, scope: null, type: !4) !2 = !DIFile(filename: "t.c", directory: "/private/tmp") -!3 = !DICompileUnit(language: DW_LANG_C99, producer: "clang 2.0", isOptimized: true, file: !26) +!3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang 2.0", isOptimized: true, file: !26) !4 = !DISubroutineType(types: !5) !5 = !{null} !6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !26, scope: !2, baseType: !7) !7 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) -!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "nbytes", line: 4, arg: 0, scope: !1, file: !2, type: !9) +!8 = !DILocalVariable(name: "nbytes", line: 4, arg: 2, scope: !1, file: !2, type: !9) !9 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned long", size: 32, align: 32, encoding: DW_ATE_unsigned) -!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "nread", line: 6, scope: !11, file: !2, type: !9) +!10 = !DILocalVariable(name: "nread", line: 6, scope: !11, file: !2, type: !9) !11 = distinct !DILexicalBlock(line: 5, column: 1, file: !26, scope: !1) -!12 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "c", line: 7, scope: !11, file: !2, type: !13) +!12 = !DILocalVariable(name: "c", line: 7, scope: !11, file: !2, type: !13) !13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !14 = !DIGlobalVariable(name: "length", linkageName: "length", line: 1, isLocal: false, isDefinition: true, scope: !2, file: !2, type: !13, variable: i32* @length) !15 = !DILocation(line: 4, column: 24, scope: !1) diff --git a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll index 1aee5088eee4..130221d38c23 100644 --- a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll +++ b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll @@ -16,10 +16,10 @@ target triple = "thumbv7-apple-darwin10" define i32 @test(i8* %arg) nounwind { entry: - %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg, i32 1) + %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %arg, i32 1) %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2> store <2 x i64> %1, <2 x i64>* undef, align 16 ret i32 undef } -declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly +declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8*, i32) nounwind readonly diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index 953e2bbf291c..14ddb59b5387 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -3,7 +3,7 @@ %struct.SVal = type { i8*, i32 } -define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp { +define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp !dbg !17 { entry: %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !23, metadata !DIExpression()), !dbg !24 @@ -31,7 +31,7 @@ return: ; preds = %bb2 ret i32 %.0, !dbg !29 } -define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { +define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 !dbg !16 { entry: %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] call void @llvm.dbg.value(metadata %struct.SVal* %this, i64 0, metadata !31, metadata !DIExpression()), !dbg !34 @@ -47,7 +47,7 @@ return: ; preds = %entry declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone -define i32 @main() nounwind ssp { +define i32 @main() nounwind ssp !dbg !20 { entry: %0 = alloca %struct.SVal ; <%struct.SVal*> [#uses=3] %v = alloca %struct.SVal ; <%struct.SVal*> [#uses=4] @@ -80,7 +80,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !0 = !DISubprogram(name: "SVal", line: 11, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14) !1 = !DICompositeType(tag: DW_TAG_structure_type, name: "SVal", line: 1, size: 128, align: 64, file: !48, elements: !4) !2 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330") -!3 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 1, file: !48, enums: !47, retainedTypes: !47, subprograms: !46, globals: !47, imports: !47) +!3 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 1, file: !48, enums: !47, retainedTypes: !47, subprograms: !46, globals: !47, imports: !47) !4 = !{!5, !7, !0, !9} !5 = !DIDerivedType(tag: DW_TAG_member, name: "Data", line: 7, size: 64, align: 64, file: !48, scope: !1, baseType: !6) !6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !48, baseType: null) @@ -93,35 +93,35 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !14 = !DISubroutineType(types: !15) !15 = !{null, !12} -!16 = !DISubprogram(name: "SVal", linkageName: "_ZN4SValC1Ev", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14, function: void (%struct.SVal*)* @_ZN4SValC1Ev) -!17 = !DISubprogram(name: "foo", linkageName: "_Z3fooi4SVal", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !18, function: i32 (i32, %struct.SVal*)* @_Z3fooi4SVal) +!16 = distinct !DISubprogram(name: "SVal", linkageName: "_ZN4SValC1Ev", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14) +!17 = distinct !DISubprogram(name: "foo", linkageName: "_Z3fooi4SVal", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !18) !18 = !DISubroutineType(types: !19) !19 = !{!13, !13, !1} -!20 = !DISubprogram(name: "main", linkageName: "main", line: 23, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !21, function: i32 ()* @main) +!20 = distinct !DISubprogram(name: "main", linkageName: "main", line: 23, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !21) !21 = !DISubroutineType(types: !22) !22 = !{!13} -!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "i", line: 16, arg: 0, scope: !17, file: !2, type: !13) +!23 = !DILocalVariable(name: "i", line: 16, arg: 1, scope: !17, file: !2, type: !13) !24 = !DILocation(line: 16, scope: !17) -!25 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "location", line: 16, arg: 0, scope: !17, file: !2, type: !26) +!25 = !DILocalVariable(name: "location", line: 16, arg: 2, scope: !17, file: !2, type: !26) !26 = !DIDerivedType(tag: DW_TAG_reference_type, name: "SVal", size: 64, align: 64, file: !48, scope: !2, baseType: !1) !27 = !DILocation(line: 17, scope: !28) !28 = distinct !DILexicalBlock(line: 16, column: 0, file: !2, scope: !17) !29 = !DILocation(line: 18, scope: !28) !30 = !DILocation(line: 20, scope: !28) -!31 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 11, arg: 0, scope: !16, file: !2, type: !32) +!31 = !DILocalVariable(name: "this", line: 11, arg: 1, scope: !16, file: !2, type: !32) !32 = !DIDerivedType(tag: DW_TAG_const_type, size: 64, align: 64, flags: DIFlagArtificial, file: !48, scope: !2, baseType: !33) !33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !48, scope: !2, baseType: !1) !34 = !DILocation(line: 11, scope: !16) !35 = !DILocation(line: 11, scope: !36) !36 = distinct !DILexicalBlock(line: 11, column: 0, file: !48, scope: !37) !37 = distinct !DILexicalBlock(line: 11, column: 0, file: !48, scope: !16) -!38 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "v", line: 24, scope: !39, file: !2, type: !1) +!38 = !DILocalVariable(name: "v", line: 24, scope: !39, file: !2, type: !1) !39 = distinct !DILexicalBlock(line: 23, column: 0, file: !48, scope: !40) !40 = distinct !DILexicalBlock(line: 23, column: 0, file: !48, scope: !20) !41 = !DILocation(line: 24, scope: !39) !42 = !DILocation(line: 25, scope: !39) !43 = !DILocation(line: 26, scope: !39) -!44 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 26, scope: !39, file: !2, type: !13) +!44 = !DILocalVariable(name: "k", line: 26, scope: !39, file: !2, type: !13) !45 = !DILocation(line: 27, scope: !39) !46 = !{!16, !17, !20} !47 = !{} diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 9a5baf21b8fb..d5eed8b6a2c4 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -28,7 +28,7 @@ target triple = "thumbv7-apple-darwin10" ; CHECK-NOT: {{DW_TAG|NULL}} ; CHECK: DW_AT_location [DW_FORM_exprloc] (<0x8> 03 [[ADDR]] 10 01 22 ) -define zeroext i8 @get1(i8 zeroext %a) nounwind optsize { +define zeroext i8 @get1(i8 zeroext %a) nounwind optsize !dbg !0 { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !10, metadata !DIExpression()), !dbg !30 %0 = load i8, i8* @x1, align 4, !dbg !30 @@ -39,7 +39,7 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone -define zeroext i8 @get2(i8 zeroext %a) nounwind optsize { +define zeroext i8 @get2(i8 zeroext %a) nounwind optsize !dbg !6 { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !18, metadata !DIExpression()), !dbg !32 %0 = load i8, i8* @x2, align 4, !dbg !32 @@ -48,7 +48,7 @@ entry: ret i8 %0, !dbg !33 } -define zeroext i8 @get3(i8 zeroext %a) nounwind optsize { +define zeroext i8 @get3(i8 zeroext %a) nounwind optsize !dbg !7 { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !21, metadata !DIExpression()), !dbg !34 %0 = load i8, i8* @x3, align 4, !dbg !34 @@ -57,7 +57,7 @@ entry: ret i8 %0, !dbg !35 } -define zeroext i8 @get4(i8 zeroext %a) nounwind optsize { +define zeroext i8 @get4(i8 zeroext %a) nounwind optsize !dbg !8 { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !24, metadata !DIExpression()), !dbg !36 %0 = load i8, i8* @x4, align 4, !dbg !36 @@ -66,7 +66,7 @@ entry: ret i8 %0, !dbg !37 } -define zeroext i8 @get5(i8 zeroext %a) nounwind optsize { +define zeroext i8 @get5(i8 zeroext %a) nounwind optsize !dbg !9 { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !27, metadata !DIExpression()), !dbg !38 %0 = load i8, i8* @x5, align 4, !dbg !38 @@ -78,35 +78,35 @@ entry: !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!49} -!0 = !DISubprogram(name: "get1", linkageName: "get1", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !47, scope: !1, type: !3, function: i8 (i8)* @get1, variables: !42) +!0 = distinct !DISubprogram(name: "get1", linkageName: "get1", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !47, scope: !1, type: !3, variables: !42) !1 = !DIFile(filename: "foo.c", directory: "/tmp/") -!2 = !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", isOptimized: true, emissionKind: 0, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports: !48) +!2 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", isOptimized: true, emissionKind: 0, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports: !48) !3 = !DISubroutineType(types: !4) !4 = !{!5, !5} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "_Bool", size: 8, align: 8, encoding: DW_ATE_boolean) -!6 = !DISubprogram(name: "get2", linkageName: "get2", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !47, scope: !1, type: !3, function: i8 (i8)* @get2, variables: !43) -!7 = !DISubprogram(name: "get3", linkageName: "get3", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !47, scope: !1, type: !3, function: i8 (i8)* @get3, variables: !44) -!8 = !DISubprogram(name: "get4", linkageName: "get4", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !47, scope: !1, type: !3, function: i8 (i8)* @get4, variables: !45) -!9 = !DISubprogram(name: "get5", linkageName: "get5", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 16, file: !47, scope: !1, type: !3, function: i8 (i8)* @get5, variables: !46) -!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 0, scope: !0, file: !1, type: !5) -!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 4, scope: !12, file: !1, type: !5) +!6 = distinct !DISubprogram(name: "get2", linkageName: "get2", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !47, scope: !1, type: !3, variables: !43) +!7 = distinct !DISubprogram(name: "get3", linkageName: "get3", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !47, scope: !1, type: !3, variables: !44) +!8 = distinct !DISubprogram(name: "get4", linkageName: "get4", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !47, scope: !1, type: !3, variables: !45) +!9 = distinct !DISubprogram(name: "get5", linkageName: "get5", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 16, file: !47, scope: !1, type: !3, variables: !46) +!10 = !DILocalVariable(name: "a", line: 4, arg: 1, scope: !0, file: !1, type: !5) +!11 = !DILocalVariable(name: "b", line: 4, scope: !12, file: !1, type: !5) !12 = distinct !DILexicalBlock(line: 4, column: 0, file: !47, scope: !0) !13 = !DIGlobalVariable(name: "x1", line: 3, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x1) !14 = !DIGlobalVariable(name: "x2", line: 6, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x2) !15 = !DIGlobalVariable(name: "x3", line: 9, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x3) !16 = !DIGlobalVariable(name: "x4", line: 12, isLocal: true, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x4) !17 = !DIGlobalVariable(name: "x5", line: 15, isLocal: false, isDefinition: true, scope: !1, file: !1, type: !5, variable: i8* @x5) -!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 7, arg: 0, scope: !6, file: !1, type: !5) -!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 7, scope: !20, file: !1, type: !5) +!18 = !DILocalVariable(name: "a", line: 7, arg: 1, scope: !6, file: !1, type: !5) +!19 = !DILocalVariable(name: "b", line: 7, scope: !20, file: !1, type: !5) !20 = distinct !DILexicalBlock(line: 7, column: 0, file: !47, scope: !6) -!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 10, arg: 0, scope: !7, file: !1, type: !5) -!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 10, scope: !23, file: !1, type: !5) +!21 = !DILocalVariable(name: "a", line: 10, arg: 1, scope: !7, file: !1, type: !5) +!22 = !DILocalVariable(name: "b", line: 10, scope: !23, file: !1, type: !5) !23 = distinct !DILexicalBlock(line: 10, column: 0, file: !47, scope: !7) -!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 13, arg: 0, scope: !8, file: !1, type: !5) -!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 13, scope: !26, file: !1, type: !5) +!24 = !DILocalVariable(name: "a", line: 13, arg: 1, scope: !8, file: !1, type: !5) +!25 = !DILocalVariable(name: "b", line: 13, scope: !26, file: !1, type: !5) !26 = distinct !DILexicalBlock(line: 13, column: 0, file: !47, scope: !8) -!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 16, arg: 0, scope: !9, file: !1, type: !5) -!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 16, scope: !29, file: !1, type: !5) +!27 = !DILocalVariable(name: "a", line: 16, arg: 1, scope: !9, file: !1, type: !5) +!28 = !DILocalVariable(name: "b", line: 16, scope: !29, file: !1, type: !5) !29 = distinct !DILexicalBlock(line: 16, column: 0, file: !47, scope: !9) !30 = !DILocation(line: 4, scope: !0) !31 = !DILocation(line: 4, scope: !12) diff --git a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll index aac8f7b3a026..1097050df54b 100644 --- a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll +++ b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -arm-global-merge -global-merge-group-by-use=false | FileCheck %s -; CHECK: .zerofill __DATA,__bss,__MergedGlobals,16,2 +; CHECK: .zerofill __DATA,__bss,l__MergedGlobals,16,2 @prev = external global [0 x i16] @max_lazy_match = internal unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index 067c719f491c..3d82e706862c 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -28,7 +28,7 @@ target triple = "thumbv7-apple-macosx10.7.0" @x4 = internal unnamed_addr global i32 4, align 4 @x5 = global i32 0, align 4 -define i32 @get1(i32 %a) nounwind optsize ssp { +define i32 @get1(i32 %a) nounwind optsize ssp !dbg !1 { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !10, metadata !DIExpression()), !dbg !30 %1 = load i32, i32* @x1, align 4, !dbg !31 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !11, metadata !DIExpression()), !dbg !31 @@ -36,7 +36,7 @@ define i32 @get1(i32 %a) nounwind optsize ssp { ret i32 %1, !dbg !31 } -define i32 @get2(i32 %a) nounwind optsize ssp { +define i32 @get2(i32 %a) nounwind optsize ssp !dbg !6 { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !13, metadata !DIExpression()), !dbg !32 %1 = load i32, i32* @x2, align 4, !dbg !33 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !14, metadata !DIExpression()), !dbg !33 @@ -44,7 +44,7 @@ define i32 @get2(i32 %a) nounwind optsize ssp { ret i32 %1, !dbg !33 } -define i32 @get3(i32 %a) nounwind optsize ssp { +define i32 @get3(i32 %a) nounwind optsize ssp !dbg !7 { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !16, metadata !DIExpression()), !dbg !34 %1 = load i32, i32* @x3, align 4, !dbg !35 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !17, metadata !DIExpression()), !dbg !35 @@ -52,7 +52,7 @@ define i32 @get3(i32 %a) nounwind optsize ssp { ret i32 %1, !dbg !35 } -define i32 @get4(i32 %a) nounwind optsize ssp { +define i32 @get4(i32 %a) nounwind optsize ssp !dbg !8 { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !19, metadata !DIExpression()), !dbg !36 %1 = load i32, i32* @x4, align 4, !dbg !37 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !20, metadata !DIExpression()), !dbg !37 @@ -60,7 +60,7 @@ define i32 @get4(i32 %a) nounwind optsize ssp { ret i32 %1, !dbg !37 } -define i32 @get5(i32 %a) nounwind optsize ssp { +define i32 @get5(i32 %a) nounwind optsize ssp !dbg !9 { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !27, metadata !DIExpression()), !dbg !38 %1 = load i32, i32* @x5, align 4, !dbg !39 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !28, metadata !DIExpression()), !dbg !39 @@ -73,32 +73,32 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!49} -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: 1, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports: !48) -!1 = !DISubprogram(name: "get1", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !47, scope: !2, type: !3, function: i32 (i32)* @get1, variables: !42) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: 1, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports: !48) +!1 = distinct !DISubprogram(name: "get1", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !47, scope: !2, type: !3, variables: !42) !2 = !DIFile(filename: "ss3.c", directory: "/private/tmp") !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!6 = !DISubprogram(name: "get2", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 8, file: !47, scope: !2, type: !3, function: i32 (i32)* @get2, variables: !43) -!7 = !DISubprogram(name: "get3", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !47, scope: !2, type: !3, function: i32 (i32)* @get3, variables: !44) -!8 = !DISubprogram(name: "get4", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 14, file: !47, scope: !2, type: !3, function: i32 (i32)* @get4, variables: !45) -!9 = !DISubprogram(name: "get5", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 17, file: !47, scope: !2, type: !3, function: i32 (i32)* @get5, variables: !46) -!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 5, arg: 1, scope: !1, file: !2, type: !5) -!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 5, scope: !12, file: !2, type: !5) +!6 = distinct !DISubprogram(name: "get2", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 8, file: !47, scope: !2, type: !3, variables: !43) +!7 = distinct !DISubprogram(name: "get3", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !47, scope: !2, type: !3, variables: !44) +!8 = distinct !DISubprogram(name: "get4", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 14, file: !47, scope: !2, type: !3, variables: !45) +!9 = distinct !DISubprogram(name: "get5", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 17, file: !47, scope: !2, type: !3, variables: !46) +!10 = !DILocalVariable(name: "a", line: 5, arg: 1, scope: !1, file: !2, type: !5) +!11 = !DILocalVariable(name: "b", line: 5, scope: !12, file: !2, type: !5) !12 = distinct !DILexicalBlock(line: 5, column: 19, file: !47, scope: !1) -!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 8, arg: 1, scope: !6, file: !2, type: !5) -!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 8, scope: !15, file: !2, type: !5) +!13 = !DILocalVariable(name: "a", line: 8, arg: 1, scope: !6, file: !2, type: !5) +!14 = !DILocalVariable(name: "b", line: 8, scope: !15, file: !2, type: !5) !15 = distinct !DILexicalBlock(line: 8, column: 17, file: !47, scope: !6) -!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 11, arg: 1, scope: !7, file: !2, type: !5) -!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 11, scope: !18, file: !2, type: !5) +!16 = !DILocalVariable(name: "a", line: 11, arg: 1, scope: !7, file: !2, type: !5) +!17 = !DILocalVariable(name: "b", line: 11, scope: !18, file: !2, type: !5) !18 = distinct !DILexicalBlock(line: 11, column: 19, file: !47, scope: !7) -!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 14, arg: 1, scope: !8, file: !2, type: !5) -!20 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 14, scope: !21, file: !2, type: !5) +!19 = !DILocalVariable(name: "a", line: 14, arg: 1, scope: !8, file: !2, type: !5) +!20 = !DILocalVariable(name: "b", line: 14, scope: !21, file: !2, type: !5) !21 = distinct !DILexicalBlock(line: 14, column: 19, file: !47, scope: !8) !25 = !DIGlobalVariable(name: "x1", line: 4, isLocal: true, isDefinition: true, scope: !0, file: !2, type: !5, variable: i32* @x1) !26 = !DIGlobalVariable(name: "x2", line: 7, isLocal: true, isDefinition: true, scope: !0, file: !2, type: !5, variable: i32* @x2) -!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 17, arg: 1, scope: !9, file: !2, type: !5) -!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "b", line: 17, scope: !29, file: !2, type: !5) +!27 = !DILocalVariable(name: "a", line: 17, arg: 1, scope: !9, file: !2, type: !5) +!28 = !DILocalVariable(name: "b", line: 17, scope: !29, file: !2, type: !5) !29 = distinct !DILexicalBlock(line: 17, column: 19, file: !47, scope: !9) !30 = !DILocation(line: 5, column: 16, scope: !1) !31 = !DILocation(line: 5, column: 32, scope: !12) diff --git a/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll b/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll index 3cbc4cdcd707..d702af7c0c70 100644 --- a/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll +++ b/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll @@ -4,9 +4,9 @@ define void @test_vmovqqqq_pseudo() nounwind ssp { entry: - %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2) + %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2) store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef ret void } -declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly +declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly diff --git a/test/CodeGen/ARM/2011-10-26-memset-inline.ll b/test/CodeGen/ARM/2011-10-26-memset-inline.ll index 17bd291a6b55..5df439389cdb 100644 --- a/test/CodeGen/ARM/2011-10-26-memset-inline.ll +++ b/test/CodeGen/ARM/2011-10-26-memset-inline.ll @@ -1,5 +1,5 @@ ; Make sure short memsets on ARM lower to stores, even when optimizing for size. -; RUN: llc -march=arm < %s | FileCheck %s -check-prefix=CHECK-GENERIC +; RUN: llc -march=arm -mattr=+strict-align < %s | FileCheck %s -check-prefix=CHECK-GENERIC ; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s -check-prefix=CHECK-UNALIGNED target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" diff --git a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll index b70b7f6f3b2e..f622ceb584e6 100644 --- a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll +++ b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -52,8 +52,8 @@ cond.end295: ; preds = %entry %shuffle.i35.i.i = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer %shuffle.i34.i.i = shufflevector <1 x i64> %shuffle.i36.i.i, <1 x i64> %shuffle.i35.i.i, <2 x i32> <i32 0, i32 1> %2 = bitcast <2 x i64> %shuffle.i34.i.i to <4 x float> - tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind - tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind + tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind + tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind unreachable for.end: ; preds = %entry @@ -63,10 +63,10 @@ for.end: ; preds = %entry ; Check that pseudo-expansion preserves <undef> flags. define void @foo3(i8* %p) nounwind ssp { entry: - tail call void @llvm.arm.neon.vst2.v4f32(i8* %p, <4 x float> undef, <4 x float> undef, i32 4) + tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %p, <4 x float> undef, <4 x float> undef, i32 4) ret void } declare arm_aapcs_vfpcc void @bar(i8*, float, float, float) -declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind -declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind diff --git a/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll b/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll index 7f30ae10e436..606af47a3d8e 100644 --- a/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll +++ b/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll @@ -7,8 +7,8 @@ entry: %vecinit.i = insertelement <2 x i32> undef, i32 %x, i32 0 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %x, i32 1 %0 = bitcast i32* %p to i8* - tail call void @llvm.arm.neon.vst1.v2i32(i8* %0, <2 x i32> %vecinit1.i, i32 4) + tail call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %0, <2 x i32> %vecinit1.i, i32 4) ret void } -declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v2i32(i8*, <2 x i32>, i32) nounwind diff --git a/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll b/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll index 545bfc73c590..6cff67614c64 100644 --- a/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll +++ b/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll @@ -5,9 +5,9 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios5.1.0" -declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8*, i32) nounwind readonly +declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind readonly -declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32) nounwind define void @findEdges(i8*) nounwind ssp { %2 = icmp sgt i32 undef, 0 @@ -19,16 +19,16 @@ define void @findEdges(i8*) nounwind ssp { ; <label>:5 ; preds = %5, %1 %6 = phi i8* [ %19, %5 ], [ %0, %1 ] - %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* null, i32 1) + %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* null, i32 1) %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 0 %9 = getelementptr inbounds i8, i8* null, i32 3 - %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %9, i32 1) + %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %9, i32 1) %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 2 - %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %6, i32 1) + %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %6, i32 1) %13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 0 %14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 1 %15 = getelementptr inbounds i8, i8* %6, i32 3 - %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %15, i32 1) + %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %15, i32 1) %17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 1 %18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 2 %19 = getelementptr inbounds i8, i8* %6, i32 48 @@ -111,7 +111,7 @@ define void @findEdges(i8*) nounwind ssp { %96 = bitcast <8 x i8> %94 to <1 x i64> %97 = shufflevector <1 x i64> %95, <1 x i64> %96, <2 x i32> <i32 0, i32 1> %98 = bitcast <2 x i64> %97 to <16 x i8> - tail call void @llvm.arm.neon.vst1.v16i8(i8* null, <16 x i8> %98, i32 1) + tail call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* null, <16 x i8> %98, i32 1) %99 = icmp slt i32 undef, undef br i1 %99, label %5, label %3 } diff --git a/test/CodeGen/ARM/2012-11-14-subs_carry.ll b/test/CodeGen/ARM/2012-11-14-subs_carry.ll index 33083303a3d4..f7abac06919d 100644 --- a/test/CodeGen/ARM/2012-11-14-subs_carry.ll +++ b/test/CodeGen/ARM/2012-11-14-subs_carry.ll @@ -1,10 +1,14 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s ;CHECK-LABEL: foo: -;CHECK: adds -;CHECK-NEXT: adc -;CHECK-NEXT: bx +;CHECK: movs r0, #0 +;CHECK-NEXT: bx lr +; Note: This test case originally checked, per r167963, for: +; adds +; adc +; bx +; But SDAG now, like InstCombine, can fold everything away. ;rdar://12028498 define i32 @foo() nounwind ssp { diff --git a/test/CodeGen/ARM/2013-10-11-select-stalls.ll b/test/CodeGen/ARM/2013-10-11-select-stalls.ll index d6045c7b8c8c..2c15c1a943ba 100644 --- a/test/CodeGen/ARM/2013-10-11-select-stalls.ll +++ b/test/CodeGen/ARM/2013-10-11-select-stalls.ll @@ -1,16 +1,21 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=thumbv7-apple-ios -stats 2>&1 | not grep "Number of pipeline stalls" +; RUN: llc < %s -mtriple=thumbv7-apple-ios -disable-ifcvt-diamond -stats 2>&1 | FileCheck %s ; Evaluate the two vld1.8 instructions in separate MBB's, ; instead of stalling on one and conditionally overwriting its result. +; +; Update: After if-conversion the two vld1.8 instructions are in the same MBB +; again. So we disable this if-conversion to eliminate its influence to this +; test. +; CHECK-NOT: Number of pipeline stalls define <16 x i8> @multiselect(i32 %avail, i8* %foo, i8* %bar) { entry: - %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %foo, i32 1) - %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1) + %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %foo, i32 1) + %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %bar, i32 1) %and = and i32 %avail, 3 %tobool = icmp eq i32 %and, 0 %retv = select i1 %tobool, <16 x i8> %vld1, <16 x i8> %vld2 ret <16 x i8> %retv } -declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* , i32 ) +declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* , i32 ) diff --git a/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll index ef575f4c41ec..be87a2fb1c89 100644 --- a/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll +++ b/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll @@ -27,7 +27,7 @@ entry: %n0 = insertelement <2 x i64> undef, i64 %tmp0, i32 0 %n1 = insertelement <2 x i64> %n0, i64 %tmp1, i32 1 - call void @llvm.arm.neon.vst4.v1i64(i8* %m, <1 x i64> %s0, <1 x i64> %s1, <1 x i64> %s2, <1 x i64> %s3, i32 8) + call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %m, <1 x i64> %s0, <1 x i64> %s1, <1 x i64> %s2, <1 x i64> %s3, i32 8) call void @bar(<2 x i64> %n1) @@ -50,7 +50,7 @@ define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C ret <8 x i8> %tmp8 } -declare void @llvm.arm.neon.vst4.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) +declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone declare void @bar2(%struct.__neon_int8x8x4_t, <8 x i8>) declare void @bar(<2 x i64> %arg) diff --git a/test/CodeGen/ARM/MachO-subtypes.ll b/test/CodeGen/ARM/MachO-subtypes.ll new file mode 100644 index 000000000000..8176d6640847 --- /dev/null +++ b/test/CodeGen/ARM/MachO-subtypes.ll @@ -0,0 +1,68 @@ +; Check that MachO ARM CPU Subtypes are respected + +; RUN: llc -mtriple=armv4t-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V4T + +; RUN: llc -mtriple=armv5-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5 +; RUN: llc -mtriple=armv5e-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5 +; RUN: llc -mtriple=armv5t-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5 +; RUN: llc -mtriple=armv5te-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5 +; RUN: llc -mtriple=armv5tej-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V5 + +; RUN: llc -mtriple=armv6-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6 +; RUN: llc -mtriple=armv6k-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6 +; RUN: llc -mtriple=thumbv6-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6 +; RUN: llc -mtriple=thumbv6k-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6 + +; RUN: llc -mtriple=armv6m-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6M +; RUN: llc -mtriple=thumbv6m-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V6M + +; RUN: llc -mtriple=armv7-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7 +; RUN: llc -mtriple=thumbv7-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7 + +; RUN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m4 -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7EM +; RUN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m7 -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7EM + +; RUN: llc -mtriple=armv7k-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7K +; RUN: llc -mtriple=thumbv7k-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7K + +; RUN: llc -mtriple=thumbv7m-apple-darwin -mcpu=sc300 -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7M +; RUN: llc -mtriple=thumbv7m-apple-darwin -mcpu=cortex-m3 -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7M + +; RUN: llc -mtriple=armv7s-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7S +; RUN: llc -mtriple=thumbv7s-apple-darwin -filetype=obj -o - < %s \ +; RUN: | llvm-readobj -file-headers | FileCheck %s --check-prefix=CHECK-V7S + +define void @_test() { + ret void +} + +; CHECK-V4T: CpuSubType: CPU_SUBTYPE_ARM_V4T (0x5) +; CHECK-V5: CpuSubType: CPU_SUBTYPE_ARM_V5 (0x7) +; CHECK-V6: CpuSubType: CPU_SUBTYPE_ARM_V6 (0x6) +; CHECK-V6M: CpuSubType: CPU_SUBTYPE_ARM_V6M (0xE) +; CHECK-V7: CpuSubType: CPU_SUBTYPE_ARM_V7 (0x9) +; CHECK-V7EM: CpuSubType: CPU_SUBTYPE_ARM_V7EM (0x10) +; CHECK-V7K: CpuSubType: CPU_SUBTYPE_ARM_V7K (0xC) +; CHECK-V7M: CpuSubType: CPU_SUBTYPE_ARM_V7M (0xF) +; CHECK-V7S: CpuSubType: CPU_SUBTYPE_ARM_V7S (0xB) diff --git a/test/CodeGen/ARM/Windows/division.ll b/test/CodeGen/ARM/Windows/division.ll new file mode 100644 index 000000000000..b3ef9c6d278b --- /dev/null +++ b/test/CodeGen/ARM/Windows/division.ll @@ -0,0 +1,38 @@ +; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s +; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s + +define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) { +entry: + %div = sdiv i32 %divident, %divisor + ret i32 %div +} + +; CHECK-LABEL: sdiv32 +; CHECK: b __rt_sdiv + +define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) { +entry: + %div = udiv i32 %divident, %divisor + ret i32 %div +} + +; CHECK-LABEL: udiv32: +; CHECK: b __rt_udiv + +define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) { +entry: + %div = sdiv i64 %divident, %divisor + ret i64 %div +} + +; CHECK-LABEL: sdiv64 +; CHECK: bl __rt_sdiv64 + +define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) { +entry: + %div = udiv i64 %divident, %divisor + ret i64 %div +} + +; CHECK-LABEL: udiv64: +; CHECK: bl __rt_udiv64 diff --git a/test/CodeGen/ARM/Windows/integer-floating-point-conversion.ll b/test/CodeGen/ARM/Windows/libcalls.ll index acf21a1caad3..d8b498a40d97 100644 --- a/test/CodeGen/ARM/Windows/integer-floating-point-conversion.ll +++ b/test/CodeGen/ARM/Windows/libcalls.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple thumbv7-windows -filetype asm -o - %s | FileCheck %s +; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s +; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s define arm_aapcs_vfpcc i64 @stoi64(float %f) { entry: diff --git a/test/CodeGen/ARM/Windows/no-eabi.ll b/test/CodeGen/ARM/Windows/no-eabi.ll new file mode 100644 index 000000000000..033ca0267ee0 --- /dev/null +++ b/test/CodeGen/ARM/Windows/no-eabi.ll @@ -0,0 +1,10 @@ +; RUN: llc -O3 -mtriple thumbv7-windows %s -filetype asm -o - | FileCheck -check-prefix CHECK-NONEABI %s +; RUN: llc -O3 -mtriple armv7--linux-gnueabi %s -filetype asm -o - | FileCheck -check-prefix CHECK-EABI %s + +define arm_aapcs_vfpcc void @function() { + ret void +} + +; CHECK-EABI: .eabi_attribute +; CHECK-NONEABI-NOT: .eabi_attribute + diff --git a/test/CodeGen/ARM/Windows/no-frame-register.ll b/test/CodeGen/ARM/Windows/no-frame-register.ll new file mode 100644 index 000000000000..80187af7ef22 --- /dev/null +++ b/test/CodeGen/ARM/Windows/no-frame-register.ll @@ -0,0 +1,22 @@ +; RUN: llc -mtriple thumbv7-windows -filetype asm -o - %s | FileCheck %s + +declare void @callee(i32) + +define i32 @calleer(i32 %i) { +entry: + %i.addr = alloca i32, align 4 + %j = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 + %add = add nsw i32 %0, 1 + store i32 %add, i32* %j, align 4 + %1 = load i32, i32* %j, align 4 + call void @callee(i32 %1) + %2 = load i32, i32* %j, align 4 + %add1 = add nsw i32 %2, 1 + ret i32 %add1 +} + +; CHECK-NOT: push.w {r7, lr} +; CHECK: push.w {r11, lr} + diff --git a/test/CodeGen/ARM/Windows/overflow.ll b/test/CodeGen/ARM/Windows/overflow.ll new file mode 100644 index 000000000000..5f74f25ac224 --- /dev/null +++ b/test/CodeGen/ARM/Windows/overflow.ll @@ -0,0 +1,77 @@ +; RUN: llc -mtriple thumbv7-windows-gnu -filetype asm -o - %s + +define i32 @divsoverflow32(i32 %a, i32 %b) { + %1 = alloca i32, align 4 + %2 = alloca i32, align 4 + %3 = load i32, i32* %1, align 4 + %4 = load i32, i32* %2, align 4 + %5 = sub nsw i32 0, %4 + %6 = sdiv i32 -2147483647, %3 + %7 = icmp sgt i32 %5, %6 + br i1 %7, label %8, label %9 + call void (...) @abort_simpl32() + unreachable + %10 = load i32, i32* %1, align 4 + %11 = load i32, i32* %2, align 4 + %12 = mul nsw i32 %10, %11 + ret i32 %12 +} + +declare void @abort_simpl32(...) + +define i64 @divsoverflow64(i64 %a, i64 %b) { + %1 = alloca i64, align 8 + %2 = alloca i64, align 8 + %3 = load i64, i64* %1, align 8 + %4 = load i64, i64* %2, align 8 + %5 = sub nsw i64 0, %4 + %6 = sdiv i64 -9223372036854775808, %3 + %7 = icmp sgt i64 %5, %6 + br i1 %7, label %8, label %9 + call void (...) @abort_simpl64() + unreachable + %10 = load i64, i64* %1, align 8 + %11 = load i64, i64* %2, align 8 + %12 = mul nsw i64 %10, %11 + ret i64 %12 +} + +declare void @abort_simpl64(...) + +define i32 @divuoverflow32(i32 %a, i32 %b) { + %1 = alloca i32, align 4 + %2 = alloca i32, align 4 + %3 = load i32, i32* %1, align 4 + %4 = load i32, i32* %2, align 4 + %5 = sub nsw i32 0, %4 + %6 = udiv i32 4294967296, %3 + %7 = icmp sgt i32 %5, %6 + br i1 %7, label %8, label %9 + call void (...) @abort_uimpl32() + unreachable + %10 = load i32, i32* %1, align 4 + %11 = load i32, i32* %2, align 4 + %12 = mul nsw i32 %10, %11 + ret i32 %12 +} + +declare void @abort_uimpl32(...) + +define i64 @divuoverflow64(i64 %a, i64 %b) { + %1 = alloca i64, align 8 + %2 = alloca i64, align 8 + %3 = load i64, i64* %1, align 8 + %4 = load i64, i64* %2, align 8 + %5 = sub nsw i64 0, %4 + %6 = udiv i64 18446744073709551616, %3 + %7 = icmp sgt i64 %5, %6 + br i1 %7, label %8, label %9 + call void (...) @abort_uimpl64() + unreachable + %10 = load i64, i64* %1, align 8 + %11 = load i64, i64* %2, align 8 + %12 = mul nsw i64 %10, %11 + ret i64 %12 +} + +declare void @abort_uimpl64(...) diff --git a/test/CodeGen/ARM/adv-copy-opt.ll b/test/CodeGen/ARM/adv-copy-opt.ll index f71bf78b62c4..395be3457203 100644 --- a/test/CodeGen/ARM/adv-copy-opt.ll +++ b/test/CodeGen/ARM/adv-copy-opt.ll @@ -11,25 +11,25 @@ ; r0 = r0 / r2 ; r1 = r1 / r3 ; -; NOOPT: vmov [[B:d[0-9]+]], r2, r3 -; NOOPT-NEXT: vmov [[A:d[0-9]+]], r0, r1 +; NOOPT: vmov [[A:d[0-9]+]], r0, r1 +; NOOPT-NEXT: vmov [[B:d[0-9]+]], r2, r3 ; Move the low part of B into a register. ; Unfortunately, we cannot express that the 's' register is the low ; part of B, i.e., sIdx == BIdx x 2. E.g., B = d1, B_low = s2. ; NOOPT-NEXT: vmov [[B_LOW:r[0-9]+]], s{{[0-9]+}} -; NOOPT-NEXT: vmov [[A_LOW:r[0-9]+]], s{{[0-9]+}} -; NOOPT-NEXT: udiv [[RES_LOW:r[0-9]+]], [[A_LOW]], [[B_LOW]] ; NOOPT-NEXT: vmov [[B_HIGH:r[0-9]+]], s{{[0-9]+}} +; NOOPT-NEXT: vmov [[A_LOW:r[0-9]+]], s{{[0-9]+}} ; NOOPT-NEXT: vmov [[A_HIGH:r[0-9]+]], s{{[0-9]+}} -; NOOPT-NEXT: udiv [[RES_HIGH:r[0-9]+]], [[A_HIGH]], [[B_HIGH]] +; NOOPT-NEXT: udiv [[RES_LOW:r[0-9]+]], [[A_LOW]], [[B_LOW]] ; NOOPT-NEXT: vmov.32 [[RES:d[0-9]+]][0], [[RES_LOW]] +; NOOPT-NEXT: udiv [[RES_HIGH:r[0-9]+]], [[A_HIGH]], [[B_HIGH]] ; NOOPT-NEXT: vmov.32 [[RES]][1], [[RES_HIGH]] ; NOOPT-NEXT: vmov r0, r1, [[RES]] ; NOOPT-NEXT: bx lr ; ; OPT-NOT: vmov -; OPT: udiv r0, r0, r2 -; OPT-NEXT: udiv r1, r1, r3 +; OPT: udiv r1, r1, r3 +; OPT-NEXT: udiv r0, r0, r2 ; OPT-NEXT: bx lr define <2 x i32> @simpleVectorDiv(<2 x i32> %A, <2 x i32> %B) nounwind { entry: diff --git a/test/CodeGen/ARM/aliases.ll b/test/CodeGen/ARM/aliases.ll index 04ca3e875487..665ffe902c81 100644 --- a/test/CodeGen/ARM/aliases.ll +++ b/test/CodeGen/ARM/aliases.ll @@ -2,34 +2,54 @@ ; CHECK: .globl test +; CHECK: .Lstructvar: +; CHECK: .size .Lstructvar, 8 + ; CHECK: .globl foo1 ; CHECK: foo1 = bar +; CHECK-NOT: .size foo1 ; CHECK: .globl foo2 ; CHECK: foo2 = bar +; CHECK-NOT: .size foo2 ; CHECK: .weak bar_f ; CHECK: bar_f = foo_f +; CHECK-NOT: .size bar_f ; CHECK: bar_i = bar +; CHECK-NOT: .size bar_i ; CHECK: .globl A ; CHECK: A = bar +; CHECK-NOT: .size A + +; CHECK: .globl elem0 +; CHECK: elem0 = .Lstructvar +; CHECK: .size elem0, 4 + +; CHECK: .globl elem1 +; CHECK: elem1 = .Lstructvar+4 +; CHECK: .size elem1, 4 @bar = global i32 42 -@foo1 = alias i32* @bar -@foo2 = alias i32* @bar +@foo1 = alias i32, i32* @bar +@foo2 = alias i32, i32* @bar %FunTy = type i32() define i32 @foo_f() { ret i32 0 } -@bar_f = weak alias %FunTy* @foo_f +@bar_f = weak alias %FunTy, %FunTy* @foo_f + +@bar_i = internal alias i32, i32* @bar -@bar_i = internal alias i32* @bar +@A = alias i64, bitcast (i32* @bar to i64*) -@A = alias bitcast (i32* @bar to i64*) +@structvar = private global {i32, i32} {i32 1, i32 2} +@elem0 = alias i32, getelementptr({i32, i32}, {i32, i32}* @structvar, i32 0, i32 0) +@elem1 = alias i32, getelementptr({i32, i32}, {i32, i32}* @structvar, i32 0, i32 1) define i32 @test() { entry: diff --git a/test/CodeGen/ARM/align-sp-adjustment.ll b/test/CodeGen/ARM/align-sp-adjustment.ll new file mode 100644 index 000000000000..cce7b03e2362 --- /dev/null +++ b/test/CodeGen/ARM/align-sp-adjustment.ll @@ -0,0 +1,47 @@ +; RUN: llc -mtriple=thumbv7 -o - %s | FileCheck %s + +; CHECK: [sp, #2120] + +%struct.struct_2 = type { [172 x %struct.struct_1] } +%struct.struct_1 = type { i32, i32, i32 } + +@.str = private unnamed_addr constant [2 x i8] c"a\00", align 1 +@.str.1 = private unnamed_addr constant [2 x i8] c"b\00", align 1 +@.str.2 = private unnamed_addr constant [2 x i8] c"c\00", align 1 +@.str.3 = private unnamed_addr constant [2 x i8] c"d\00", align 1 + +declare i32* @_Z4bar3iiPKcS0_i(i32, i32, i8*, i8*, i32) +declare void @_Z4bar1i8struct_2(i32, %struct.struct_2* byval align 4) +declare i32 @_Z4bar2PiPKc(i32*, i8*) + +define void @_Z3fooiiiii(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) #0 { +entry: + %params = alloca %struct.struct_2, align 4 + %0 = bitcast %struct.struct_2* %params to i8* + br label %for.body + +for.body: + %i.015 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %call = tail call i32* @_Z4bar3iiPKcS0_i(i32 %p1, i32 %p5, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.1, i32 0, i32 0), i32 %i.015) #4 + %cmp1 = icmp eq i32* %call, null + br i1 %cmp1, label %cleanup.8, label %for.inc + +for.inc: + %call2 = tail call i32 @_Z4bar2PiPKc(i32* %call, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.2, i32 0, i32 0)) #4 + %f1 = getelementptr inbounds %struct.struct_2, %struct.struct_2* %params, i32 0, i32 0, i32 %i.015, i32 0 + store i32 %call2, i32* %f1, align 4 + %call3 = tail call i32 @_Z4bar2PiPKc(i32* %call, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.3, i32 0, i32 0)) #4 + %f2 = getelementptr inbounds %struct.struct_2, %struct.struct_2* %params, i32 0, i32 0, i32 %i.015, i32 1 + store i32 %call3, i32* %f2, align 4 + %inc = add nuw nsw i32 %i.015, 1 + %cmp = icmp slt i32 %inc, 4 + br i1 %cmp, label %for.body, label %for.end + +for.end: + call void @_Z4bar1i8struct_2(i32 %p4, %struct.struct_2* byval nonnull align 4 %params) #4 + br label %cleanup.8 + +cleanup.8: + ret void +} + diff --git a/test/CodeGen/ARM/apcs-vfp.ll b/test/CodeGen/ARM/apcs-vfp.ll new file mode 100644 index 000000000000..9157521bfbc4 --- /dev/null +++ b/test/CodeGen/ARM/apcs-vfp.ll @@ -0,0 +1,153 @@ +; RUN: llc -mtriple=armv7k-apple-watchos2.0 < %s | FileCheck %s + +define arm_aapcs_vfpcc float @t1(float %a, float %b) { +entry: +; CHECK: t1 +; CHECK-NOT: vmov +; CHECK: vadd.f32 + %a.addr = alloca float, align 4 + %b.addr = alloca float, align 4 + store float %a, float* %a.addr, align 4 + store float %b, float* %b.addr, align 4 + %0 = load float, float* %a.addr, align 4 + %1 = load float, float* %b.addr, align 4 + %add = fadd float %0, %1 + ret float %add +} + +define arm_aapcs_vfpcc double @t2(double %a, double %b) { +entry: +; CHECK: t2 +; CHECK-NOT: vmov +; CHECK: vadd.f64 + %a.addr = alloca double, align 8 + %b.addr = alloca double, align 8 + store double %a, double* %a.addr, align 8 + store double %b, double* %b.addr, align 8 + %0 = load double, double* %a.addr, align 8 + %1 = load double, double* %b.addr, align 8 + %add = fadd double %0, %1 + ret double %add +} + +define arm_aapcs_vfpcc i64 @t3(double %ti) { +entry: +; CHECK-LABEL: t3: +; CHECK-NOT: vmov +; CHECK: bl ___fixunsdfdi + %conv = fptoui double %ti to i64 + ret i64 %conv +} + +define arm_aapcs_vfpcc i64 @t4(double %ti) { +entry: +; CHECK-LABEL: t4: +; CHECK-NOT: vmov +; CHECK: bl ___fixdfdi + %conv = fptosi double %ti to i64 + ret i64 %conv +} + +define arm_aapcs_vfpcc double @t5(i64 %ti) { +entry: +; CHECK-LABEL: t5: +; CHECK: bl ___floatundidf +; CHECK-NOT: vmov +; CHECK: pop + %conv = uitofp i64 %ti to double + ret double %conv +} + +define arm_aapcs_vfpcc double @t6(i64 %ti) { +entry: +; CHECK-LABEL: t6: +; CHECK: bl ___floatdidf +; CHECK-NOT: vmov +; CHECK: pop + %conv = sitofp i64 %ti to double + ret double %conv +} + +define arm_aapcs_vfpcc float @t7(i64 %ti) { +entry: +; CHECK-LABEL: t7: +; CHECK: bl ___floatundisf +; CHECK-NOT: vmov +; CHECK: pop + %conv = uitofp i64 %ti to float + ret float %conv +} + +define arm_aapcs_vfpcc float @t8(i64 %ti) { +entry: +; CHECK-LABEL: t8: +; CHECK: bl ___floatdisf +; CHECK-NOT: vmov +; CHECK: pop + %conv = sitofp i64 %ti to float + ret float %conv +} + +define arm_aapcs_vfpcc double @t9(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %a, float %b) { +entry: +; CHECK-LABEL: t9: +; CHECK-NOT: vmov +; CHECK: vldr + %add = fadd float %a, %b + %conv = fpext float %add to double + ret double %conv +} + +define arm_aapcs_vfpcc double @t10(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %a, float %b, double %c) { +entry: +; CHECK-LABEL: t10: +; CHECK-NOT: vmov +; CHECK: vldr + %add = fadd double %a, %c + ret double %add +} + +define arm_aapcs_vfpcc float @t11(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, float %a, double %b, float %c) { +entry: +; CHECK-LABEL: t11: +; CHECK: vldr + %add = fadd float %a, %c + ret float %add +} + +define arm_aapcs_vfpcc double @t12(double %a, double %b) { +entry: +; CHECK-LABEL: t12: +; CHECK: vstr + %add = fadd double %a, %b + %sub = fsub double %a, %b + %call = tail call arm_aapcs_vfpcc double @x(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double %add, float 0.000000e+00, double %sub) + ret double %call +} + +define arm_aapcs_vfpcc double @t13(double %x) { +entry: +; CHECK-LABEL: t13: +; CHECK-NOT: vmov +; CHECK: bl ___sincos_stret + %call = tail call arm_aapcs_vfpcc double @cos(double %x) + %call1 = tail call arm_aapcs_vfpcc double @sin(double %x) + %mul = fmul double %call, %call1 + ret double %mul +} + +define arm_aapcs_vfpcc double @t14(double %x) { +; CHECK-LABEL: t14: +; CHECK-NOT: vmov +; CHECK: b ___exp10 + %__exp10 = tail call double @__exp10(double %x) #1 + ret double %__exp10 +} + +declare arm_aapcs_vfpcc double @x(double, double, double, double, double, double, double, float, double) +declare arm_aapcs_vfpcc double @cos(double) #0 +declare arm_aapcs_vfpcc double @sin(double) #0 +declare double @__exp10(double) + +attributes #0 = { readnone } +attributes #1 = { readonly } diff --git a/test/CodeGen/ARM/arm-eabi.ll b/test/CodeGen/ARM/arm-eabi.ll new file mode 100644 index 000000000000..d1e7a947553f --- /dev/null +++ b/test/CodeGen/ARM/arm-eabi.ll @@ -0,0 +1,63 @@ +; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-eabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-eabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-eabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI + +%struct.my_s = type { [18 x i32] } + +define void @foo(i32* %t) { + ; CHECK-LABEL: foo + + %1 = alloca i32*, align 4 + store i32* %t, i32** %1, align 4 + %2 = load i32*, i32** %1, align 4 + %3 = bitcast i32* %2 to %struct.my_s* + %4 = bitcast %struct.my_s* %3 to i8* + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %4, i8* inttoptr (i32 1 to i8*), i32 72, i32 4, i1 false) + ret void +} + +define void @f1(i8* %dest, i8* %src) { +entry: + ; CHECK-LABEL: f1 + + ; memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: bl memmove + call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 0, i1 false) + + ; memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 0, i1 false) + + ; memset + ; CHECK-EABI: mov r2, #1 + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset + call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 0, i1 false) + ret void +} + +declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind diff --git a/test/CodeGen/ARM/arm-interleaved-accesses.ll b/test/CodeGen/ARM/arm-interleaved-accesses.ll index 9a9885ccdd0c..002e71f6d9b8 100644 --- a/test/CodeGen/ARM/arm-interleaved-accesses.ll +++ b/test/CodeGen/ARM/arm-interleaved-accesses.ll @@ -1,7 +1,10 @@ -; RUN: llc -mtriple=arm-eabi -mattr=+neon -lower-interleaved-accesses=true < %s | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NEON +; RUN: llc -mtriple=arm-eabi -mattr=-neon -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NONEON -; CHECK-LABEL: load_factor2: -; CHECK: vld2.8 {d16, d17}, [r0] +; NEON-LABEL: load_factor2: +; NEON: vld2.8 {d16, d17}, [r0] +; NONEON-LABEL: load_factor2: +; NONEON-NOT: vld2 define <8 x i8> @load_factor2(<16 x i8>* %ptr) { %wide.vec = load <16 x i8>, <16 x i8>* %ptr, align 4 %strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -10,8 +13,10 @@ define <8 x i8> @load_factor2(<16 x i8>* %ptr) { ret <8 x i8> %add } -; CHECK-LABEL: load_factor3: -; CHECK: vld3.32 {d16, d17, d18}, [r0] +; NEON-LABEL: load_factor3: +; NEON: vld3.32 {d16, d17, d18}, [r0] +; NONEON-LABEL: load_factor3: +; NONEON-NOT: vld3 define <2 x i32> @load_factor3(i32* %ptr) { %base = bitcast i32* %ptr to <6 x i32>* %wide.vec = load <6 x i32>, <6 x i32>* %base, align 4 @@ -21,9 +26,11 @@ define <2 x i32> @load_factor3(i32* %ptr) { ret <2 x i32> %add } -; CHECK-LABEL: load_factor4: -; CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! -; CHECK: vld4.32 {d17, d19, d21, d23}, [r0] +; NEON-LABEL: load_factor4: +; NEON: vld4.32 {d16, d18, d20, d22}, [r0]! +; NEON: vld4.32 {d17, d19, d21, d23}, [r0] +; NONEON-LABEL: load_factor4: +; NONEON-NOT: vld4 define <4 x i32> @load_factor4(i32* %ptr) { %base = bitcast i32* %ptr to <16 x i32>* %wide.vec = load <16 x i32>, <16 x i32>* %base, align 4 @@ -33,17 +40,21 @@ define <4 x i32> @load_factor4(i32* %ptr) { ret <4 x i32> %add } -; CHECK-LABEL: store_factor2: -; CHECK: vst2.8 {d16, d17}, [r0] +; NEON-LABEL: store_factor2: +; NEON: vst2.8 {d16, d17}, [r0] +; NONEON-LABEL: store_factor2: +; NONEON-NOT: vst2 define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) { %interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4 ret void } -; CHECK-LABEL: store_factor3: -; CHECK: vst3.32 {d16, d18, d20}, [r0]! -; CHECK: vst3.32 {d17, d19, d21}, [r0] +; NEON-LABEL: store_factor3: +; NEON: vst3.32 {d16, d18, d20}, [r0]! +; NEON: vst3.32 {d17, d19, d21}, [r0] +; NONEON-LABEL: store_factor3: +; NONEON-NOT: vst3.32 define void @store_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) { %base = bitcast i32* %ptr to <12 x i32>* %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -53,9 +64,11 @@ define void @store_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v ret void } -; CHECK-LABEL: store_factor4: -; CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! -; CHECK: vst4.32 {d17, d19, d21, d23}, [r0] +; NEON-LABEL: store_factor4: +; NEON: vst4.32 {d16, d18, d20, d22}, [r0]! +; NEON: vst4.32 {d17, d19, d21, d23}, [r0] +; NONEON-LABEL: store_factor4: +; NONEON-NOT: vst4 define void @store_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { %base = bitcast i32* %ptr to <16 x i32>* %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -68,8 +81,10 @@ define void @store_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v ; The following cases test that interleaved access of pointer vectors can be ; matched to ldN/stN instruction. -; CHECK-LABEL: load_ptrvec_factor2: -; CHECK: vld2.32 {d16, d17}, [r0] +; NEON-LABEL: load_ptrvec_factor2: +; NEON: vld2.32 {d16, d17}, [r0] +; NONEON-LABEL: load_ptrvec_factor2: +; NONEON-NOT: vld2 define <2 x i32*> @load_ptrvec_factor2(i32** %ptr) { %base = bitcast i32** %ptr to <4 x i32*>* %wide.vec = load <4 x i32*>, <4 x i32*>* %base, align 4 @@ -77,8 +92,10 @@ define <2 x i32*> @load_ptrvec_factor2(i32** %ptr) { ret <2 x i32*> %strided.v0 } -; CHECK-LABEL: load_ptrvec_factor3: -; CHECK: vld3.32 {d16, d17, d18}, [r0] +; NEON-LABEL: load_ptrvec_factor3: +; NEON: vld3.32 {d16, d17, d18}, [r0] +; NONEON-LABEL: load_ptrvec_factor3: +; NONEON-NOT: vld3 define void @load_ptrvec_factor3(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) { %base = bitcast i32** %ptr to <6 x i32*>* %wide.vec = load <6 x i32*>, <6 x i32*>* %base, align 4 @@ -89,8 +106,10 @@ define void @load_ptrvec_factor3(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr ret void } -; CHECK-LABEL: load_ptrvec_factor4: -; CHECK: vld4.32 {d16, d17, d18, d19}, [r0] +; NEON-LABEL: load_ptrvec_factor4: +; NEON: vld4.32 {d16, d17, d18, d19}, [r0] +; NONEON-LABEL: load_ptrvec_factor4: +; NONEON-NOT: vld4 define void @load_ptrvec_factor4(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) { %base = bitcast i32** %ptr to <8 x i32*>* %wide.vec = load <8 x i32*>, <8 x i32*>* %base, align 4 @@ -101,8 +120,10 @@ define void @load_ptrvec_factor4(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr ret void } -; CHECK-LABEL: store_ptrvec_factor2: -; CHECK: vst2.32 {d16, d17}, [r0] +; NEON-LABEL: store_ptrvec_factor2: +; NEON: vst2.32 {d16, d17}, [r0] +; NONEON-LABEL: store_ptrvec_factor2: +; NONEON-NOT: vst2 define void @store_ptrvec_factor2(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1) { %base = bitcast i32** %ptr to <4 x i32*>* %interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3> @@ -110,8 +131,10 @@ define void @store_ptrvec_factor2(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1) { ret void } -; CHECK-LABEL: store_ptrvec_factor3: -; CHECK: vst3.32 {d16, d17, d18}, [r0] +; NEON-LABEL: store_ptrvec_factor3: +; NEON: vst3.32 {d16, d17, d18}, [r0] +; NONEON-LABEL: store_ptrvec_factor3: +; NONEON-NOT: vst3 define void @store_ptrvec_factor3(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) { %base = bitcast i32** %ptr to <6 x i32*>* %v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -121,8 +144,10 @@ define void @store_ptrvec_factor3(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 ret void } -; CHECK-LABEL: store_ptrvec_factor4: -; CHECK: vst4.32 {d16, d17, d18, d19}, [r0] +; NEON-LABEL: store_ptrvec_factor4: +; NEON: vst4.32 {d16, d17, d18, d19}, [r0] +; NONEON-LABEL: store_ptrvec_factor4: +; NONEON-NOT: vst4 define void @store_ptrvec_factor4(i32* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) { %base = bitcast i32* %ptr to <8 x i32*>* %v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -135,8 +160,10 @@ define void @store_ptrvec_factor4(i32* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 ; Following cases check that shuffle maskes with undef indices can be matched ; into ldN/stN instruction. -; CHECK-LABEL: load_undef_mask_factor2: -; CHECK: vld2.32 {d16, d17, d18, d19}, [r0] +; NEON-LABEL: load_undef_mask_factor2: +; NEON: vld2.32 {d16, d17, d18, d19}, [r0] +; NONEON-LABEL: load_undef_mask_factor2: +; NONEON-NOT: vld2 define <4 x i32> @load_undef_mask_factor2(i32* %ptr) { %base = bitcast i32* %ptr to <8 x i32>* %wide.vec = load <8 x i32>, <8 x i32>* %base, align 4 @@ -146,9 +173,11 @@ define <4 x i32> @load_undef_mask_factor2(i32* %ptr) { ret <4 x i32> %add } -; CHECK-LABEL: load_undef_mask_factor3: -; CHECK: vld3.32 {d16, d18, d20}, [r0]! -; CHECK: vld3.32 {d17, d19, d21}, [r0] +; NEON-LABEL: load_undef_mask_factor3: +; NEON: vld3.32 {d16, d18, d20}, [r0]! +; NEON: vld3.32 {d17, d19, d21}, [r0] +; NONEON-LABEL: load_undef_mask_factor3: +; NONEON-NOT: vld3 define <4 x i32> @load_undef_mask_factor3(i32* %ptr) { %base = bitcast i32* %ptr to <12 x i32>* %wide.vec = load <12 x i32>, <12 x i32>* %base, align 4 @@ -158,9 +187,11 @@ define <4 x i32> @load_undef_mask_factor3(i32* %ptr) { ret <4 x i32> %add } -; CHECK-LABEL: load_undef_mask_factor4: -; CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! -; CHECK: vld4.32 {d17, d19, d21, d23}, [r0] +; NEON-LABEL: load_undef_mask_factor4: +; NEON: vld4.32 {d16, d18, d20, d22}, [r0]! +; NEON: vld4.32 {d17, d19, d21, d23}, [r0] +; NONEON-LABEL: load_undef_mask_factor4: +; NONEON-NOT: vld4 define <4 x i32> @load_undef_mask_factor4(i32* %ptr) { %base = bitcast i32* %ptr to <16 x i32>* %wide.vec = load <16 x i32>, <16 x i32>* %base, align 4 @@ -170,8 +201,10 @@ define <4 x i32> @load_undef_mask_factor4(i32* %ptr) { ret <4 x i32> %add } -; CHECK-LABEL: store_undef_mask_factor2: -; CHECK: vst2.32 {d16, d17, d18, d19}, [r0] +; NEON-LABEL: store_undef_mask_factor2: +; NEON: vst2.32 {d16, d17, d18, d19}, [r0] +; NONEON-LABEL: store_undef_mask_factor2: +; NONEON-NOT: vst2 define void @store_undef_mask_factor2(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1) { %base = bitcast i32* %ptr to <8 x i32>* %interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7> @@ -179,9 +212,11 @@ define void @store_undef_mask_factor2(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1) { ret void } -; CHECK-LABEL: store_undef_mask_factor3: -; CHECK: vst3.32 {d16, d18, d20}, [r0]! -; CHECK: vst3.32 {d17, d19, d21}, [r0] +; NEON-LABEL: store_undef_mask_factor3: +; NEON: vst3.32 {d16, d18, d20}, [r0]! +; NEON: vst3.32 {d17, d19, d21}, [r0] +; NONEON-LABEL: store_undef_mask_factor3: +; NONEON-NOT: vst3 define void @store_undef_mask_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) { %base = bitcast i32* %ptr to <12 x i32>* %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -191,9 +226,11 @@ define void @store_undef_mask_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, < ret void } -; CHECK-LABEL: store_undef_mask_factor4: -; CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! -; CHECK: vst4.32 {d17, d19, d21, d23}, [r0] +; NEON-LABEL: store_undef_mask_factor4: +; NEON: vst4.32 {d16, d18, d20, d22}, [r0]! +; NEON: vst4.32 {d17, d19, d21, d23}, [r0] +; NONEON-LABEL: store_undef_mask_factor4: +; NONEON-NOT: vst4 define void @store_undef_mask_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { %base = bitcast i32* %ptr to <16 x i32>* %v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -202,3 +239,68 @@ define void @store_undef_mask_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, < store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4 ret void } + +; The following test cases check that address spaces are properly handled + +; NEON-LABEL: load_address_space +; NEON: vld3.32 +; NONEON-LABEL: load_address_space +; NONEON-NOT: vld3 +define void @load_address_space(<4 x i32> addrspace(1)* %A, <2 x i32>* %B) { + %tmp = load <4 x i32>, <4 x i32> addrspace(1)* %A + %interleaved = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 3> + store <2 x i32> %interleaved, <2 x i32>* %B + ret void +} + +; NEON-LABEL: store_address_space +; NEON: vst2.32 +; NONEON-LABEL: store_address_space +; NONEON-NOT: vst2 +define void @store_address_space(<2 x i32>* %A, <2 x i32>* %B, <4 x i32> addrspace(1)* %C) { + %tmp0 = load <2 x i32>, <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %B + %interleaved = shufflevector <2 x i32> %tmp0, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 3> + store <4 x i32> %interleaved, <4 x i32> addrspace(1)* %C + ret void +} + +; Check that we do something sane with illegal types. + +; NEON-LABEL: load_illegal_factor2: +; NEON: BB#0: +; NEON-NEXT: vld1.64 {d16, d17}, [r0:128] +; NEON-NEXT: vuzp.32 q8, {{.*}} +; NEON-NEXT: vmov r0, r1, d16 +; NEON-NEXT: vmov r2, r3, {{.*}} +; NEON-NEXT: mov pc, lr +; NONEON-LABEL: load_illegal_factor2: +; NONEON: BB#0: +; NONEON-NEXT: ldr [[ELT0:r[0-9]+]], [r0] +; NONEON-NEXT: ldr r1, [r0, #8] +; NONEON-NEXT: mov r0, [[ELT0]] +; NONEON-NEXT: mov pc, lr +define <3 x float> @load_illegal_factor2(<3 x float>* %p) nounwind { + %tmp1 = load <3 x float>, <3 x float>* %p, align 16 + %tmp2 = shufflevector <3 x float> %tmp1, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef> + ret <3 x float> %tmp2 +} + +; This lowering isn't great, but it's at least correct. + +; NEON-LABEL: store_illegal_factor2: +; NEON: BB#0: +; NEON-NEXT: vldr d17, [sp] +; NEON-NEXT: vmov d16, r2, r3 +; NEON-NEXT: vuzp.32 q8, {{.*}} +; NEON-NEXT: vstr d16, [r0] +; NEON-NEXT: mov pc, lr +; NONEON-LABEL: store_illegal_factor2: +; NONEON: BB#0: +; NONEON-NEXT: stm r0, {r1, r3} +; NONEON-NEXT: mov pc, lr +define void @store_illegal_factor2(<3 x float>* %p, <3 x float> %v) nounwind { + %tmp1 = shufflevector <3 x float> %v, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef> + store <3 x float> %tmp1, <3 x float>* %p, align 16 + ret void +} diff --git a/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll b/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll new file mode 100644 index 000000000000..1434f40137b5 --- /dev/null +++ b/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll @@ -0,0 +1,142 @@ +; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE +; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE +; We cannot merge this test with the main test for shrink-wrapping, because +; the code path we want to exerce is not taken with ios lowering. +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64" +target triple = "armv7--linux-gnueabi" + +@skip = internal unnamed_addr constant [2 x i8] c"\01\01", align 1 + +; Check that we do not restore the before having used the saved CSRs. +; This happened because of a bad use of the post-dominance property. +; The exit block of the loop happens to also lead to defs/uses of CSRs. +; It also post-dominates the loop body and we use to generate invalid +; restore sequence. I.e., we restored too early. +; +; CHECK-LABEL: wrongUseOfPostDominate: +; +; The prologue is the first thing happening in the function +; without shrink-wrapping. +; DISABLE: push +; +; CHECK: cmp r1, #0 +; +; With shrink-wrapping, we branch to a pre-header, where the prologue +; is located. +; ENABLE-NEXT: blt [[LOOP_PREHEADER:[.a-zA-Z0-9_]+]] +; Without shrink-wrapping, we go straight into the loop. +; DISABLE-NEXT: blt [[LOOP_HEADER:[.a-zA-Z0-9_]+]] +; +; CHECK: @ %if.end29 +; DISABLE-NEXT: pop +; ENABLE-NEXT: bx lr +; +; ENABLE: [[LOOP_PREHEADER]] +; ENABLE: push +; We must not find a pop here, otherwise that means we are in the loop +; and are restoring before using the saved CSRs. +; ENABLE-NOT: pop +; ENALBE-NEXT: [[LOOP_HEADER:[.a-zA-Z0-9_]+]]: @ %while.cond2.outer +; +; DISABLE: [[LOOP_HEADER]]: @ %while.cond2.outer +; +; ENABLE-NOT: pop +; +; CHECK: @ %while.cond2 +; CHECK: add +; CHECK-NEXT: cmp r{{[0-1]+}}, #1 +; Set the return value. +; CHECK-NEXT: moveq r0, +; CHECK-NEXT: popeq +; +; Use the back edge to check we get the label of the loop right. +; This is to make sure we check the right loop pattern. +; CHECK: @ %while.body24.land.rhs14_crit_edge +; CHECK: cmp r{{[0-9]+}}, #192 +; CHECK-NEXT bhs [[LOOP_HEADER]] +define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnone %lim) { +entry: + %cmp = icmp sgt i32 %off, -1 + br i1 %cmp, label %while.cond.preheader, label %while.cond2.outer + +while.cond.preheader: ; preds = %entry + %tobool4 = icmp ne i32 %off, 0 + %cmp15 = icmp ult i8* %s, %lim + %sel66 = and i1 %tobool4, %cmp15 + br i1 %sel66, label %while.body, label %if.end29 + +while.body: ; preds = %while.body, %while.cond.preheader + %s.addr.08 = phi i8* [ %add.ptr, %while.body ], [ %s, %while.cond.preheader ] + %off.addr.07 = phi i32 [ %dec, %while.body ], [ %off, %while.cond.preheader ] + %dec = add nsw i32 %off.addr.07, -1 + %tmp = load i8, i8* %s.addr.08, align 1, !tbaa !2 + %idxprom = zext i8 %tmp to i32 + %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* @skip, i32 0, i32 %idxprom + %tmp1 = load i8, i8* %arrayidx, align 1, !tbaa !2 + %conv = zext i8 %tmp1 to i32 + %add.ptr = getelementptr inbounds i8, i8* %s.addr.08, i32 %conv + %tobool = icmp ne i32 %off.addr.07, 1 + %cmp1 = icmp ult i8* %add.ptr, %lim + %sel6 = and i1 %tobool, %cmp1 + br i1 %sel6, label %while.body, label %if.end29 + +while.cond2.outer: ; preds = %while.body24.land.rhs14_crit_edge, %while.body24, %land.rhs14.preheader, %if.then7, %entry + %off.addr.1.ph = phi i32 [ %off, %entry ], [ %inc, %land.rhs14.preheader ], [ %inc, %if.then7 ], [ %inc, %while.body24.land.rhs14_crit_edge ], [ %inc, %while.body24 ] + %s.addr.1.ph = phi i8* [ %s, %entry ], [ %incdec.ptr, %land.rhs14.preheader ], [ %incdec.ptr, %if.then7 ], [ %lsr.iv, %while.body24.land.rhs14_crit_edge ], [ %lsr.iv, %while.body24 ] + br label %while.cond2 + +while.cond2: ; preds = %while.body4, %while.cond2.outer + %off.addr.1 = phi i32 [ %inc, %while.body4 ], [ %off.addr.1.ph, %while.cond2.outer ] + %inc = add nsw i32 %off.addr.1, 1 + %tobool3 = icmp eq i32 %off.addr.1, 0 + br i1 %tobool3, label %if.end29, label %while.body4 + +while.body4: ; preds = %while.cond2 + %tmp2 = icmp ugt i8* %s.addr.1.ph, %lim + br i1 %tmp2, label %if.then7, label %while.cond2 + +if.then7: ; preds = %while.body4 + %incdec.ptr = getelementptr inbounds i8, i8* %s.addr.1.ph, i32 -1 + %tmp3 = load i8, i8* %incdec.ptr, align 1, !tbaa !2 + %conv1525 = zext i8 %tmp3 to i32 + %tobool9 = icmp slt i8 %tmp3, 0 + %cmp129 = icmp ugt i8* %incdec.ptr, %lim + %or.cond13 = and i1 %tobool9, %cmp129 + br i1 %or.cond13, label %land.rhs14.preheader, label %while.cond2.outer + +land.rhs14.preheader: ; preds = %if.then7 + %cmp1624 = icmp slt i8 %tmp3, 0 + %cmp2026 = icmp ult i32 %conv1525, 192 + %or.cond27 = and i1 %cmp1624, %cmp2026 + br i1 %or.cond27, label %while.body24.preheader, label %while.cond2.outer + +while.body24.preheader: ; preds = %land.rhs14.preheader + %scevgep = getelementptr i8, i8* %s.addr.1.ph, i32 -2 + br label %while.body24 + +while.body24: ; preds = %while.body24.land.rhs14_crit_edge, %while.body24.preheader + %lsr.iv = phi i8* [ %scevgep, %while.body24.preheader ], [ %scevgep34, %while.body24.land.rhs14_crit_edge ] + %cmp12 = icmp ugt i8* %lsr.iv, %lim + br i1 %cmp12, label %while.body24.land.rhs14_crit_edge, label %while.cond2.outer + +while.body24.land.rhs14_crit_edge: ; preds = %while.body24 + %.pre = load i8, i8* %lsr.iv, align 1, !tbaa !2 + %cmp16 = icmp slt i8 %.pre, 0 + %conv15 = zext i8 %.pre to i32 + %cmp20 = icmp ult i32 %conv15, 192 + %or.cond = and i1 %cmp16, %cmp20 + %scevgep34 = getelementptr i8, i8* %lsr.iv, i32 -1 + br i1 %or.cond, label %while.body24, label %while.cond2.outer + +if.end29: ; preds = %while.cond2, %while.body, %while.cond.preheader + %s.addr.3 = phi i8* [ %s, %while.cond.preheader ], [ %add.ptr, %while.body ], [ %s.addr.1.ph, %while.cond2 ] + ret i8* %s.addr.3 +} + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"min_enum_size", i32 4} +!2 = !{!3, !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/ARM/arm-shrink-wrapping.ll b/test/CodeGen/ARM/arm-shrink-wrapping.ll new file mode 100644 index 000000000000..9375df4b15cb --- /dev/null +++ b/test/CodeGen/ARM/arm-shrink-wrapping.ll @@ -0,0 +1,683 @@ +; RUN: llc %s -o - -enable-shrink-wrap=true -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=armv7-apple-ios \ +; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=ARM --check-prefix=ENABLE --check-prefix=ARM-ENABLE +; RUN: llc %s -o - -enable-shrink-wrap=false -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=armv7-apple-ios \ +; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=ARM --check-prefix=DISABLE --check-prefix=ARM-DISABLE +; RUN: llc %s -o - -enable-shrink-wrap=true -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=thumbv7-apple-ios \ +; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB --check-prefix=ENABLE --check-prefix=THUMB-ENABLE +; RUN: llc %s -o - -enable-shrink-wrap=false -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=thumbv7-apple-ios \ +; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB --check-prefix=DISABLE --check-prefix=THUMB-DISABLE + +; +; Note: Lots of tests use inline asm instead of regular calls. +; This allows to have a better control on what the allocation will do. +; Otherwise, we may have spill right in the entry block, defeating +; shrink-wrapping. Moreover, some of the inline asm statements (nop) +; are here to ensure that the related paths do not end up as critical +; edges. +; Also disable the late if-converter as it makes harder to reason on +; the diffs. + +; Initial motivating example: Simple diamond with a call just on one side. +; CHECK-LABEL: foo: +; +; Compare the arguments and jump to exit. +; No prologue needed. +; ENABLE: cmp r0, r1 +; ENABLE-NEXT: bge [[EXIT_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; CHECK: push {r7, lr} +; CHECK-NEXT: mov r7, sp +;; +; Compare the arguments and jump to exit. +; After the prologue is set. +; DISABLE: sub sp +; DISABLE: cmp r0, r1 +; DISABLE-NEXT: bge [[EXIT_LABEL:LBB[0-9_]+]] +; +; Store %a in the alloca. +; ARM-ENABLE: push {r0} +; THUMB-ENABLE: str r0, [sp, #-4] +; DISABLE: str r0, [sp] +; Set the alloca address in the second argument. +; CHECK-NEXT: mov r1, sp +; Set the first argument to zero. +; CHECK-NEXT: mov{{s?}} r0, #0 +; CHECK-NEXT: bl{{x?}} _doSomething +; +; With shrink-wrapping, epilogue is just after the call. +; ARM-ENABLE-NEXT: mov sp, r7 +; THUMB-ENABLE-NEXT: add sp, #4 +; ENABLE-NEXT: pop{{(\.w)?}} {r7, lr} +; +; CHECK: [[EXIT_LABEL]]: +; +; Without shrink-wrapping, epilogue is in the exit block. +; Epilogue code. (What we pop does not matter.) +; ARM-DISABLE: mov sp, r7 +; THUMB-DISABLE: add sp, +; DISABLE-NEXT: pop {r7, pc} +; +; ENABLE-NEXT: bx lr +define i32 @foo(i32 %a, i32 %b) { + %tmp = alloca i32, align 4 + %tmp2 = icmp slt i32 %a, %b + br i1 %tmp2, label %true, label %false + +true: + store i32 %a, i32* %tmp, align 4 + %tmp4 = call i32 @doSomething(i32 0, i32* %tmp) + br label %false + +false: + %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ] + ret i32 %tmp.0 +} + +; Function Attrs: optsize +declare i32 @doSomething(i32, i32*) + + +; Check that we do not perform the restore inside the loop whereas the save +; is outside. +; CHECK-LABEL: freqSaveAndRestoreOutsideLoop: +; +; Shrink-wrapping allows to skip the prologue in the else case. +; ARM-ENABLE: cmp r0, #0 +; ARM-ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; Make sure we save the CSR used in the inline asm: r4. +; CHECK: push {r4, r7, lr} +; CHECK-NEXT: add r7, sp, #4 +; +; ARM-DISABLE: cmp r0, #0 +; ARM-DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-DISABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; SUM is in r0 because it is coalesced with the second +; argument on the else path. +; CHECK: mov{{s?}} [[SUM:r0]], #0 +; CHECK-NEXT: mov{{s?}} [[IV:r[0-9]+]], #10 +; +; Next BB. +; CHECK: [[LOOP:LBB[0-9_]+]]: @ %for.body +; CHECK: mov{{(\.w)?}} [[TMP:r[0-9]+]], #1 +; ARM: subs [[IV]], [[IV]], #1 +; THUMB: subs [[IV]], #1 +; ARM-NEXT: add [[SUM]], [[TMP]], [[SUM]] +; THUMB-NEXT: add [[SUM]], [[TMP]] +; CHECK-NEXT: bne [[LOOP]] +; +; Next BB. +; SUM << 3. +; CHECK: lsl{{s?}} [[SUM]], [[SUM]], #3 +; ENABLE-NEXT: pop {r4, r7, pc} +; +; Duplicated epilogue. +; DISABLE: pop {r4, r7, pc} +; +; CHECK: [[ELSE_LABEL]]: @ %if.else +; Shift second argument by one and store into returned register. +; CHECK: lsl{{s?}} r0, r1, #1 +; DISABLE-NEXT: pop {r4, r7, pc} +; +; ENABLE-NEXT: bx lr +define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %for.preheader + +for.preheader: + tail call void asm "nop", ""() + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ] + %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ] + %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"() + %add = add nsw i32 %call, %sum.04 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + %shl = shl i32 %add, 3 + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %if.else, %for.end + %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ] + ret i32 %sum.1 +} + +declare i32 @something(...) + +; Check that we do not perform the shrink-wrapping inside the loop even +; though that would be legal. The cost model must prevent that. +; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2: +; Prologue code. +; Make sure we save the CSR used in the inline asm: r4. +; CHECK: push {r4 +; CHECK: mov{{s?}} [[SUM:r0]], #0 +; CHECK-NEXT: mov{{s?}} [[IV:r[0-9]+]], #10 +; CHECK: nop +; Next BB. +; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: @ %for.body +; CHECK: mov{{(\.w)?}} [[TMP:r[0-9]+]], #1 +; ARM: subs [[IV]], [[IV]], #1 +; THUMB: subs [[IV]], #1 +; ARM: add [[SUM]], [[TMP]], [[SUM]] +; THUMB: add [[SUM]], [[TMP]] +; CHECK-NEXT: bne [[LOOP_LABEL]] +; Next BB. +; CHECK: @ %for.exit +; CHECK: nop +; CHECK: pop {r4 +define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) { +entry: + br label %for.preheader + +for.preheader: + tail call void asm "nop", ""() + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ] + %sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ] + %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"() + %add = add nsw i32 %call, %sum.03 + %inc = add nuw nsw i32 %i.04, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.exit, label %for.body + +for.exit: + tail call void asm "nop", ""() + br label %for.end + +for.end: ; preds = %for.body + ret i32 %add +} + +; Check with a more complex case that we do not have save within the loop and +; restore outside. +; CHECK-LABEL: loopInfoSaveOutsideLoop: +; +; ARM-ENABLE: cmp r0, #0 +; ARM-ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; Make sure we save the CSR used in the inline asm: r4. +; CHECK: push {r4, r7, lr} +; CHECK-NEXT: add r7, sp, #4 +; +; ARM-DISABLE: cmp r0, #0 +; ARM-DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-DISABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; SUM is in r0 because it is coalesced with the second +; argument on the else path. +; CHECK: mov{{s?}} [[SUM:r0]], #0 +; CHECK-NEXT: mov{{s?}} [[IV:r[0-9]+]], #10 +; +; Next BB. +; CHECK: [[LOOP:LBB[0-9_]+]]: @ %for.body +; CHECK: mov{{(\.w)?}} [[TMP:r[0-9]+]], #1 +; ARM: subs [[IV]], [[IV]], #1 +; THUMB: subs [[IV]], #1 +; ARM-NEXT: add [[SUM]], [[TMP]], [[SUM]] +; THUMB-NEXT: add [[SUM]], [[TMP]] +; CHECK-NEXT: bne [[LOOP]] +; +; Next BB. +; SUM << 3. +; CHECK: lsl{{s?}} [[SUM]], [[SUM]], #3 +; ENABLE: pop {r4, r7, pc} +; +; Duplicated epilogue. +; DISABLE: pop {r4, r7, pc} +; +; CHECK: [[ELSE_LABEL]]: @ %if.else +; Shift second argument by one and store into returned register. +; CHECK: lsl{{s?}} r0, r1, #1 +; DISABLE-NEXT: pop {r4, r7, pc} +; +; ENABLE-NEXT: bx lr +define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %for.preheader + +for.preheader: + tail call void asm "nop", ""() + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ] + %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ] + %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"() + %add = add nsw i32 %call, %sum.04 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + tail call void asm "nop", "~{r4}"() + %shl = shl i32 %add, 3 + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %if.else, %for.end + %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ] + ret i32 %sum.1 +} + +declare void @somethingElse(...) + +; Check with a more complex case that we do not have restore within the loop and +; save outside. +; CHECK-LABEL: loopInfoRestoreOutsideLoop: +; +; ARM-ENABLE: cmp r0, #0 +; ARM-ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; Make sure we save the CSR used in the inline asm: r4. +; CHECK: push {r4, r7, lr} +; CHECK-NEXT: add r7, sp, #4 +; +; ARM-DISABLE: cmp r0, #0 +; ARM-DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-DISABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; SUM is in r0 because it is coalesced with the second +; argument on the else path. +; CHECK: mov{{s?}} [[SUM:r0]], #0 +; CHECK-NEXT: mov{{s?}} [[IV:r[0-9]+]], #10 +; +; Next BB. +; CHECK: [[LOOP:LBB[0-9_]+]]: @ %for.body +; CHECK: mov{{(\.w)?}} [[TMP:r[0-9]+]], #1 +; ARM: subs [[IV]], [[IV]], #1 +; THUMB: subs [[IV]], #1 +; ARM-NEXT: add [[SUM]], [[TMP]], [[SUM]] +; THUMB-NEXT: add [[SUM]], [[TMP]] +; CHECK-NEXT: bne [[LOOP]] +; +; Next BB. +; SUM << 3. +; CHECK: lsl{{s?}} [[SUM]], [[SUM]], #3 +; ENABLE-NEXT: pop {r4, r7, pc} +; +; Duplicated epilogue. +; DISABLE: pop {r4, r7, pc} +; +; CHECK: [[ELSE_LABEL]]: @ %if.else +; Shift second argument by one and store into returned register. +; CHECK: lsl{{s?}} r0, r1, #1 +; DISABLE-NEXT: pop {r4, r7, pc} +; +; ENABLE-NEXT: bx lr +define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + tail call void asm "nop", "~{r4}"() + br label %for.body + +for.body: ; preds = %for.body, %if.then + %i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ] + %sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ] + %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"() + %add = add nsw i32 %call, %sum.04 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + %shl = shl i32 %add, 3 + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %if.else, %for.end + %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ] + ret i32 %sum.1 +} + +; Check that we handle function with no frame information correctly. +; CHECK-LABEL: emptyFrame: +; CHECK: @ %entry +; CHECK-NEXT: mov{{s?}} r0, #0 +; CHECK-NEXT: bx lr +define i32 @emptyFrame() { +entry: + ret i32 0 +} + +; Check that we handle inline asm correctly. +; CHECK-LABEL: inlineAsm: +; +; ARM-ENABLE: cmp r0, #0 +; ARM-ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; Make sure we save the CSR used in the inline asm: r4. +; CHECK: push {r4, r7, lr} +; CHECK-NEXT: add r7, sp, #4 +; +; ARM-DISABLE: cmp r0, #0 +; ARM-DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-DISABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; CHECK: mov{{s?}} [[IV:r[0-9]+]], #10 +; +; Next BB. +; CHECK: [[LOOP:LBB[0-9_]+]]: @ %for.body +; ARM: subs [[IV]], [[IV]], #1 +; THUMB: subs [[IV]], #1 +; CHECK: add{{(\.w)?}} r4, r4, #1 +; CHECK: bne [[LOOP]] +; +; Next BB. +; CHECK: mov{{s?}} r0, #0 +; +; Duplicated epilogue. +; DISABLE: pop {r4, r7, pc} +; +; CHECK: [[ELSE_LABEL]]: @ %if.else +; Shift second argument by one and store into returned register. +; CHECK: lsl{{s?}} r0, r1, #1 +; DISABLE-NEXT: pop {r4, r7, pc} +; +; ENABLE-NEXT: bx lr +define i32 @inlineAsm(i32 %cond, i32 %N) { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %for.preheader + +for.preheader: + tail call void asm "nop", ""() + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ] + tail call void asm sideeffect "add r4, #1", "~{r4}"() + %inc = add nuw nsw i32 %i.03, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.exit, label %for.body + +for.exit: + tail call void asm "nop", ""() + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %for.body, %if.else + %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ] + ret i32 %sum.0 +} + +; Check that we handle calls to variadic functions correctly. +; CHECK-LABEL: callVariadicFunc: +; +; ARM-ENABLE: cmp r0, #0 +; ARM-ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; CHECK: push {r7, lr} +; CHECK-NEXT: mov r7, sp +; CHECK-NEXT: sub sp, {{(sp, )?}}#12 +; +; ARM-DISABLE: cmp r0, #0 +; ARM-DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]] +; THUMB-DISABLE-NEXT: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]] +; +; Setup of the varags. +; CHECK: mov r0, r1 +; CHECK-NEXT: mov r2, r1 +; CHECK-NEXT: mov r3, r1 +; ARM-NEXT: str r1, [sp] +; ARM-NEXT: str r1, [sp, #4] +; THUMB-NEXT: strd r1, r1, [sp] +; CHECK-NEXT: str r1, [sp, #8] +; CHECK-NEXT: bl{{x?}} _someVariadicFunc +; CHECK-NEXT: lsl{{s?}} r0, r0, #3 +; ARM-NEXT: mov sp, r7 +; THUMB-NEXT: add sp, #12 +; CHECK-NEXT: pop {r7, pc} +; +; CHECK: [[ELSE_LABEL]]: @ %if.else +; Shift second argument by one and store into returned register. +; CHECK: lsl{{s?}} r0, r1, #1 +; +; Epilogue code. +; ENABLE-NEXT: bx lr +; +; ARM-DISABLE-NEXT: mov sp, r7 +; THUMB-DISABLE-NEXT: add sp, #12 +; DISABLE-NEXT: pop {r7, pc} +define i32 @callVariadicFunc(i32 %cond, i32 %N) { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N) + %shl = shl i32 %call, 3 + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %if.else, %if.then + %sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ] + ret i32 %sum.0 +} + +declare i32 @someVariadicFunc(i32, ...) + +; Make sure we do not insert unreachable code after noreturn function. +; Although this is not incorrect to insert such code, it is useless +; and it hurts the binary size. +; +; CHECK-LABEL: noreturn: +; DISABLE: push +; +; CHECK: tst{{(\.w)?}} r0, #255 +; CHECK-NEXT: bne [[ABORT:LBB[0-9_]+]] +; +; CHECK: mov{{s?}} r0, #42 +; +; ENABLE-NEXT: bx lr +; +; DISABLE-NEXT: pop +;; +; CHECK: [[ABORT]]: @ %if.abort +; +; ENABLE: push +; +; CHECK: bl{{x?}} _abort +; ENABLE-NOT: pop +define i32 @noreturn(i8 signext %bad_thing) { +entry: + %tobool = icmp eq i8 %bad_thing, 0 + br i1 %tobool, label %if.end, label %if.abort + +if.abort: + %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"() + tail call void @abort() #0 + unreachable + +if.end: + ret i32 42 +} + +declare void @abort() #0 + +attributes #0 = { noreturn nounwind } + +; Make sure that we handle infinite loops properly When checking that the Save +; and Restore blocks are control flow equivalent, the loop searches for the +; immediate (post) dominator for the (restore) save blocks. When either the Save +; or Restore block is located in an infinite loop the only immediate (post) +; dominator is itself. In this case, we cannot perform shrink wrapping, but we +; should return gracefully and continue compilation. +; The only condition for this test is the compilation finishes correctly. +; CHECK-LABEL: infiniteloop +; CHECK: pop +define void @infiniteloop() { +entry: + br i1 undef, label %if.then, label %if.end + +if.then: + %ptr = alloca i32, i32 4 + br label %for.body + +for.body: ; preds = %for.body, %entry + %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ] + %call = tail call i32 asm sideeffect "mov $0, #1", "=r,~{r4}"() + %add = add nsw i32 %call, %sum.03 + store i32 %add, i32* %ptr + br label %for.body + +if.end: + ret void +} + +; Another infinite loop test this time with a body bigger than just one block. +; CHECK-LABEL: infiniteloop2 +; CHECK: pop +define void @infiniteloop2() { +entry: + br i1 undef, label %if.then, label %if.end + +if.then: + %ptr = alloca i32, i32 4 + br label %for.body + +for.body: ; preds = %for.body, %entry + %sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2] + %call = tail call i32 asm "mov $0, #0", "=r,~{r4}"() + %add = add nsw i32 %call, %sum.03 + store i32 %add, i32* %ptr + br i1 undef, label %body1, label %body2 + +body1: + tail call void asm sideeffect "nop", "~{r4}"() + br label %for.body + +body2: + tail call void asm sideeffect "nop", "~{r4}"() + br label %for.body + +if.end: + ret void +} + +; Another infinite loop test this time with two nested infinite loop. +; CHECK-LABEL: infiniteloop3 +; CHECK: bx lr +define void @infiniteloop3() { +entry: + br i1 undef, label %loop2a, label %body + +body: ; preds = %entry + br i1 undef, label %loop2a, label %end + +loop1: ; preds = %loop2a, %loop2b + %var.phi = phi i32* [ %next.phi, %loop2b ], [ %var, %loop2a ] + %next.phi = phi i32* [ %next.load, %loop2b ], [ %next.var, %loop2a ] + %0 = icmp eq i32* %var, null + %next.load = load i32*, i32** undef + br i1 %0, label %loop2a, label %loop2b + +loop2a: ; preds = %loop1, %body, %entry + %var = phi i32* [ null, %body ], [ null, %entry ], [ %next.phi, %loop1 ] + %next.var = phi i32* [ undef, %body ], [ null, %entry ], [ %next.load, %loop1 ] + br label %loop1 + +loop2b: ; preds = %loop1 + %gep1 = bitcast i32* %var.phi to i32* + %next.ptr = bitcast i32* %gep1 to i32** + store i32* %next.phi, i32** %next.ptr + br label %loop1 + +end: + ret void +} + +; Function Attrs: nounwind readnone +declare double @llvm.pow.f64(double, double) + +; This function needs to spill floating point registers to +; exerce the path where we were deferencing the end iterator +; to access debug info location while inserting the spill code +; during PEI with shrink-wrapping enable. +; CHECK-LABEL: debug_info: +; +; ENABLE: tst{{(\.w)?}} r2, #1 +; ENABLE-NEXT: beq [[BB13:LBB[0-9_]+]] +; +; CHECK: push +; +; DISABLE: tst{{(\.w)?}} r2, #1 +; DISABLE-NEXT: beq [[BB13:LBB[0-9_]+]] +; +; CHECK: bl{{x?}} _pow +; +; +; ENABLE: pop +; +; CHECK: [[BB13]]: +; CHECK: vldr +; +; DISABLE: pop +; +; CHECK: bl +define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %tmp) { +bb: + br i1 %or.cond, label %bb3, label %bb13 + +bb3: ; preds = %bb + %tmp4 = fcmp ogt float %gamma, 1.000000e+00 + %tmp5 = fadd double 1.000000e+00, %tmp + %tmp6 = select i1 %tmp4, double %tmp5, double %tmp + %tmp10 = tail call double @llvm.pow.f64(double %tmp, double %tmp) + %tmp11 = fcmp une double %tmp6, %tmp + %tmp12 = fadd double %tmp10, %tmp10 + %cutoff.0 = select i1 %tmp11, double %tmp12, double %tmp + %phitmp = fptrunc double %cutoff.0 to float + br label %bb13 + +bb13: ; preds = %bb3, %bb + %cutoff.1 = phi float [ 0.000000e+00, %bb ], [ %phitmp, %bb3 ] + ret float %cutoff.1 +} + + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "LLVM", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2, imports: !2) +!1 = !DIFile(filename: "a.cpp", directory: "b") +!2 = !{} +!3 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index 7510d6ccdc33..573cd45c0825 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -208,10 +208,16 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { define i64 @test8(i64* %ptr) { ; CHECK-LABEL: test8: ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] +; CHECK-NOT: strexd +; CHECK: clrex +; CHECK-NOT: strexd ; CHECK: dmb {{ish$}} ; CHECK-THUMB-LABEL: test8: ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] +; CHECK-THUMB-NOT: strexd +; CHECK-THUMB: clrex +; CHECK-THUMB-NOT: strexd ; CHECK-THUMB: dmb {{ish$}} %r = load atomic i64, i64* %ptr seq_cst, align 8 diff --git a/test/CodeGen/ARM/atomic-cmp.ll b/test/CodeGen/ARM/atomic-cmp.ll index 629b16d86ab5..7f41b7d93d1a 100644 --- a/test/CodeGen/ARM/atomic-cmp.ll +++ b/test/CodeGen/ARM/atomic-cmp.ll @@ -6,10 +6,12 @@ define i8 @t(i8* %a, i8 %b, i8 %c) nounwind { ; ARM-LABEL: t: ; ARM: ldrexb ; ARM: strexb +; ARM: clrex ; T2-LABEL: t: -; T2: ldrexb ; T2: strexb +; T2: ldrexb +; T2: clrex %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic monotonic %tmp1 = extractvalue { i8, i1 } %tmp0, 0 ret i8 %tmp1 diff --git a/test/CodeGen/ARM/atomic-cmpxchg.ll b/test/CodeGen/ARM/atomic-cmpxchg.ll index 84790be6d605..32cdf4174ddc 100644 --- a/test/CodeGen/ARM/atomic-cmpxchg.ll +++ b/test/CodeGen/ARM/atomic-cmpxchg.ll @@ -1,8 +1,11 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARM -; RUN: llc < %s -mtriple=thumb-linux-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMB +; RUN: llc < %s -mtriple=arm-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARM +; RUN: llc < %s -mtriple=thumb-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMB -; RUN: llc < %s -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARMV7 -; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMBV7 +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARMV6 +; RUN: llc < %s -mtriple=thumbv6-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMBV6 + +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-ARMV7 +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -asm-verbose=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-THUMBV7 define zeroext i1 @test_cmpxchg_res_i8(i8* %addr, i8 %desired, i8 zeroext %new) { entry: @@ -26,28 +29,71 @@ entry: ; CHECK-THUMB: movs r0, #1 ; CHECK-THUMB: movs [[R2:r[0-9]+]], #0 ; CHECK-THUMB: cmp [[R1]], {{r[0-9]+}} -; CHECK-THU<B: beq +; CHECK-THUMB: beq ; CHECK-THUMB: push {[[R2]]} ; CHECK-THUMB: pop {r0} -; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8 -; CHECK-ARMV7: ldrexb [[R3:r[0-9]+]], [r0] -; CHECK-ARMV7: mov [[R1:r[0-9]+]], #0 -; CHECK-ARMV7: cmp [[R3]], {{r[0-9]+}} -; CHECK-ARMV7: bne -; CHECK-ARMV7: strexb [[R3]], {{r[0-9]+}}, [{{r[0-9]+}}] -; CHECK-ARMV7: mov [[R1]], #1 -; CHECK-ARMV7: cmp [[R3]], #0 -; CHECK-ARMV7: bne -; CHECK-ARMV7: mov r0, [[R1]] +; CHECK-ARMV6-LABEL: test_cmpxchg_res_i8: +; CHECK-ARMV6-NEXT: .fnstart +; CHECK-ARMV6-NEXT: uxtb [[DESIRED:r[0-9]+]], r1 +; CHECK-ARMV6-NEXT: [[TRY:.LBB[0-9_]+]]: +; CHECK-ARMV6-NEXT: ldrexb [[LD:r[0-9]+]], [r0] +; CHECK-ARMV6-NEXT: mov [[RES:r[0-9]+]], #0 +; CHECK-ARMV6-NEXT: cmp [[LD]], [[DESIRED]] +; CHECK-ARMV6-NEXT: bne [[END:.LBB[0-9_]+]] +; CHECK-ARMV6-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0] +; CHECK-ARMV6-NEXT: mov [[RES]], #1 +; CHECK-ARMV6-NEXT: cmp [[SUCCESS]], #0 +; CHECK-ARMV6-NEXT: bne [[TRY]] +; CHECK-ARMV6-NEXT: [[END]]: +; CHECK-ARMV6-NEXT: mov r0, [[RES]] +; CHECK-ARMV6-NEXT: bx lr + +; CHECK-THUMBV6-LABEL: test_cmpxchg_res_i8: +; CHECK-THUMBV6: mov [[EXPECTED:r[0-9]+]], r1 +; CHECK-THUMBV6-NEXT: bl __sync_val_compare_and_swap_1 +; CHECK-THUMBV6-NEXT: mov [[RES:r[0-9]+]], r0 +; CHECK-THUMBV6-NEXT: movs r0, #1 +; CHECK-THUMBV6-NEXT: movs [[ZERO:r[0-9]+]], #0 +; CHECK-THUMBV6-NEXT: cmp [[RES]], [[EXPECTED]] +; CHECK-THUMBV6-NEXT: beq [[END:.LBB[0-9_]+]] +; CHECK-THUMBV6-NEXT: mov r0, [[ZERO]] +; CHECK-THUMBV6-NEXT: [[END]]: +; CHECK-THUMBV6-NEXT: pop {{.*}}pc} + +; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8: +; CHECK-ARMV7-NEXT: .fnstart +; CHECK-ARMV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1 +; CHECK-ARMV7-NEXT: [[TRY:.LBB[0-9_]+]]: +; CHECK-ARMV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0] +; CHECK-ARMV7-NEXT: cmp [[LD]], [[DESIRED]] +; CHECK-ARMV7-NEXT: bne [[FAIL:.LBB[0-9_]+]] +; CHECK-ARMV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0] +; CHECK-ARMV7-NEXT: mov [[RES:r[0-9]+]], #1 +; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], #0 +; CHECK-ARMV7-NEXT: bne [[TRY]] +; CHECK-ARMV7-NEXT: b [[END:.LBB[0-9_]+]] +; CHECK-ARMV7-NEXT: [[FAIL]]: +; CHECK-ARMV7-NEXT: clrex +; CHECK-ARMV7-NEXT: mov [[RES]], #0 +; CHECK-ARMV7-NEXT: [[END]]: +; CHECK-ARMV7-NEXT: mov r0, [[RES]] +; CHECK-ARMV7-NEXT: bx lr -; CHECK-THUMBV7-LABEL: test_cmpxchg_res_i8 -; CHECK-THUMBV7: ldrexb [[R3:r[0-9]+]], [r0] -; CHECK-THUMBV7: cmp [[R3]], {{r[0-9]+}} -; CHECK-THUMBV7: movne r0, #0 -; CHECK-THUMBV7: bxne lr -; CHECK-THUMBV7: strexb [[R3]], {{r[0-9]+}}, [{{r[0-9]+}}] -; CHECK-THUMBV7: cmp [[R3]], #0 -; CHECK-THUMBV7: itt eq -; CHECK-THUMBV7: moveq r0, #1 -; CHECK-THUMBV7: bxeq lr +; CHECK-THUMBV7-LABEL: test_cmpxchg_res_i8: +; CHECK-THUMBV7-NEXT: .fnstart +; CHECK-THUMBV7-NEXT: uxtb [[DESIRED:r[0-9]+]], r1 +; CHECK-THUMBV7-NEXT: b [[TRYLD:.LBB[0-9_]+]] +; CHECK-THUMBV7-NEXT: [[TRYST:.LBB[0-9_]+]]: +; CHECK-THUMBV7-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0] +; CHECK-THUMBV7-NEXT: cmp [[SUCCESS]], #0 +; CHECK-THUMBV7-NEXT: itt eq +; CHECK-THUMBV7-NEXT: moveq r0, #1 +; CHECK-THUMBV7-NEXT: bxeq lr +; CHECK-THUMBV7-NEXT: [[TRYLD]]: +; CHECK-THUMBV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0] +; CHECK-THUMBV7-NEXT: cmp [[LD]], [[DESIRED]] +; CHECK-THUMBV7-NEXT: beq [[TRYST:.LBB[0-9_]+]] +; CHECK-THUMBV7-NEXT: clrex +; CHECK-THUMBV7-NEXT: movs r0, #0 +; CHECK-THUMBV7-NEXT: bx lr diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll index db32bffdd5d1..791389456619 100644 --- a/test/CodeGen/ARM/atomic-op.ll +++ b/test/CodeGen/ARM/atomic-op.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix CHECK-ARMV7 +; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-T2 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0 ; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL @@ -272,16 +272,31 @@ define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) { %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic %oldval = extractvalue { i32, i1 } %pair, 0 -; CHECK: dmb ish -; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]: -; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]] -; CHECK: cmp [[OLDVAL]], r1 -; CHECK: bxne lr -; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] -; CHECK: cmp [[SUCCESS]], #0 -; CHECK: bne [[LOOP_BB]] -; CHECK: dmb ish -; CHECK: bx lr +; CHECK-ARMV7: dmb ish +; CHECK-ARMV7: [[LOOP_BB:\.?LBB[0-9]+_1]]: +; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]] +; CHECK-ARMV7: cmp [[OLDVAL]], r1 +; CHECK-ARMV7: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]] +; CHECK-ARMV7: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] +; CHECK-ARMV7: cmp [[SUCCESS]], #0 +; CHECK-ARMV7: bne [[LOOP_BB]] +; CHECK-ARMV7: dmb ish +; CHECK-ARMV7: bx lr +; CHECK-ARMV7: [[FAIL_BB]]: +; CHECK-ARMV7: clrex +; CHECK-ARMV7: bx lr + +; CHECK-T2: dmb ish +; CHECK-T2: [[LOOP_BB:\.?LBB[0-9]+_1]]: +; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]] +; CHECK-T2: cmp [[OLDVAL]], r1 +; CHECK-T2: clrexne +; CHECK-T2: bxne lr +; CHECK-T2: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] +; CHECK-T2: cmp [[SUCCESS]], #0 +; CHECK-T2: dmbeq ish +; CHECK-T2: bxeq lr +; CHECK-T2: b [[LOOP_BB]] ret i32 %oldval } @@ -295,11 +310,14 @@ define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) { ; CHECK: [[LOOP_BB:\.?LBB[0-9]+_1]]: ; CHECK: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]] ; CHECK: cmp [[OLDVAL]], r1 -; CHECK: bne [[END_BB:\.?LBB[0-9]+_[0-9]+]] +; CHECK: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]] ; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] ; CHECK: cmp [[SUCCESS]], #0 ; CHECK: bne [[LOOP_BB]] -; CHECK: [[END_BB]]: +; CHECK: b [[END_BB:\.?LBB[0-9]+_[0-9]+]] +; CHECK: [[FAIL_BB]]: +; CHECK-NEXT: clrex +; CHECK-NEXT: [[END_BB]]: ; CHECK: dmb ish ; CHECK: bx lr diff --git a/test/CodeGen/ARM/atomic-ops-v8.ll b/test/CodeGen/ARM/atomic-ops-v8.ll index 86287c1178db..efdb75b63222 100644 --- a/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/test/CodeGen/ARM/atomic-ops-v8.ll @@ -1055,24 +1055,30 @@ define i8 @test_atomic_cmpxchg_i8(i8 zeroext %wanted, i8 zeroext %new) nounwind %old = extractvalue { i8, i1 } %pair, 0 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 -; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK-DAG: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK-DAG: movt r[[ADDR]], :upper16:var8 +; CHECK-THUMB-DAG: mov r[[WANTED:[0-9]+]], r0 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-ARM-NEXT: cmp r[[OLD]], r0 +; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]] ; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r1 is a reasonable guess. -; CHECK: strexb [[STATUS:r[0-9]+]], r1, {{.*}}[[ADDR]] +; CHECK: strexb [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NEXT: b .LBB{{[0-9]+}}_4 +; CHECK-NEXT: .LBB{{[0-9]+}}_3: +; CHECK-NEXT: clrex +; CHECK-NEXT: .LBB{{[0-9]+}}_4: ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD]] +; CHECK-ARM: mov r0, r[[OLD]] ret i8 %old } @@ -1082,24 +1088,30 @@ define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounw %old = extractvalue { i16, i1 } %pair, 0 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 -; CHECK: movt r[[ADDR]], :upper16:var16 +; CHECK-DAG: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK-DAG: movt r[[ADDR]], :upper16:var16 +; CHECK-THUMB-DAG: mov r[[WANTED:[0-9]+]], r0 ; CHECK: .LBB{{[0-9]+}}_1: ; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-ARM-NEXT: cmp r[[OLD]], r0 +; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]] ; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r1 is a reasonable guess. ; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NEXT: b .LBB{{[0-9]+}}_4 +; CHECK-NEXT: .LBB{{[0-9]+}}_3: +; CHECK-NEXT: clrex +; CHECK-NEXT: .LBB{{[0-9]+}}_4: ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD]] +; CHECK-ARM: mov r0, r[[OLD]] ret i16 %old } @@ -1124,6 +1136,10 @@ define void @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; CHECK: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NEXT: b .LBB{{[0-9]+}}_4 +; CHECK-NEXT: .LBB{{[0-9]+}}_3: +; CHECK-NEXT: clrex +; CHECK-NEXT: .LBB{{[0-9]+}}_4: ; CHECK-NOT: dmb ; CHECK-NOT: mcr @@ -1158,6 +1174,10 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; CHECK: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NEXT: b .LBB{{[0-9]+}}_4 +; CHECK-NEXT: .LBB{{[0-9]+}}_3: +; CHECK-NEXT: clrex +; CHECK-NEXT: .LBB{{[0-9]+}}_4: ; CHECK-NOT: dmb ; CHECK-NOT: mcr diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll index c3de07e03b6b..79e8e68e2f57 100644 --- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll +++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false ; dependency) when it isn't dependent on last CPSR defining instruction. ; rdar://8928208 @@ -7,8 +7,10 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { entry: ; CHECK-LABEL: t1: -; CHECK: muls [[REG:(r[0-9]+)]], r3, r2 -; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 +; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2 +; CHECK-CORTEX-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 +; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0 +; CHECK-SWIFT-NEXT: mul [[REG:(r[0-9]+)]], r2, r3 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]] %0 = mul nsw i32 %a, %b %1 = mul nsw i32 %c, %d @@ -21,8 +23,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind { entry: ; CHECK-LABEL: t2: - %tobool7 = icmp eq i32* %ptr2, null - br i1 %tobool7, label %while.end, label %while.body + br label %while.body while.body: ; CHECK: while.body @@ -55,8 +56,7 @@ while.end: define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize { entry: ; CHECK-LABEL: t3: - %tobool7 = icmp eq i32* %ptr2, null - br i1 %tobool7, label %while.end, label %while.body + br label %while.body while.body: ; CHECK: while.body diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll index 0661960d1ae0..893fef3add7e 100644 --- a/test/CodeGen/ARM/bfi.ll +++ b/test/CodeGen/ARM/bfi.ll @@ -74,3 +74,98 @@ entry: %or = or i32 %shl, %and ret i32 %or } + +define i32 @f7(i32 %x, i32 %y) { +; CHECK-LABEL: f7: +; CHECK: bfi r1, r0, #4, #1 + %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 + %and = and i32 %x, 4 + %or = or i32 %y2, 16 + %cmp = icmp ne i32 %and, 0 + %sel = select i1 %cmp, i32 %or, i32 %y2 + ret i32 %sel +} + +define i32 @f8(i32 %x, i32 %y) { +; CHECK-LABEL: f8: +; CHECK: bfi r1, r0, #4, #1 +; CHECK: bfi r1, r0, #5, #1 + %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 + %and = and i32 %x, 4 + %or = or i32 %y2, 48 + %cmp = icmp ne i32 %and, 0 + %sel = select i1 %cmp, i32 %or, i32 %y2 + ret i32 %sel +} + +define i32 @f9(i32 %x, i32 %y) { +; CHECK-LABEL: f9: +; CHECK-NOT: bfi + %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 + %and = and i32 %x, 4 + %or = or i32 %y2, 48 + %cmp = icmp ne i32 %and, 0 + %sel = select i1 %cmp, i32 %y2, i32 %or + ret i32 %sel +} + +define i32 @f10(i32 %x, i32 %y) { +; CHECK-LABEL: f10: +; CHECK: bfi r1, r0, #4, #2 + %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 + %and = and i32 %x, 4 + %or = or i32 %y2, 32 + %cmp = icmp ne i32 %and, 0 + %sel = select i1 %cmp, i32 %or, i32 %y2 + + %aand = and i32 %x, 2 + %aor = or i32 %sel, 16 + %acmp = icmp ne i32 %aand, 0 + %asel = select i1 %acmp, i32 %aor, i32 %sel + + ret i32 %asel +} + +define i32 @f11(i32 %x, i32 %y) { +; CHECK-LABEL: f11: +; CHECK: bfi r1, r0, #4, #3 + %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 + %and = and i32 %x, 4 + %or = or i32 %y2, 32 + %cmp = icmp ne i32 %and, 0 + %sel = select i1 %cmp, i32 %or, i32 %y2 + + %aand = and i32 %x, 2 + %aor = or i32 %sel, 16 + %acmp = icmp ne i32 %aand, 0 + %asel = select i1 %acmp, i32 %aor, i32 %sel + + %band = and i32 %x, 8 + %bor = or i32 %asel, 64 + %bcmp = icmp ne i32 %band, 0 + %bsel = select i1 %bcmp, i32 %bor, i32 %asel + + ret i32 %bsel +} + +define i32 @f12(i32 %x, i32 %y) { +; CHECK-LABEL: f12: +; CHECK: bfi r1, r0, #4, #1 + %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 + %and = and i32 %x, 4 + %or = or i32 %y2, 16 + %cmp = icmp eq i32 %and, 0 + %sel = select i1 %cmp, i32 %y2, i32 %or + ret i32 %sel +} + +define i32 @f13(i32 %x, i32 %y) { +; CHECK-LABEL: f13: +; CHECK-NOT: bfi + %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 + %and = and i32 %x, 4 + %or = or i32 %y2, 16 + %cmp = icmp eq i32 %and, 42 ; Not comparing against zero! + %sel = select i1 %cmp, i32 %y2, i32 %or + ret i32 %sel +} diff --git a/test/CodeGen/ARM/build-attributes-optimization-minsize.ll b/test/CodeGen/ARM/build-attributes-optimization-minsize.ll new file mode 100644 index 000000000000..4cfb6012f439 --- /dev/null +++ b/test/CodeGen/ARM/build-attributes-optimization-minsize.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 | FileCheck %s + +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ + +; CHECK: .eabi_attribute 30, 4 @ Tag_ABI_optimization_goals +; CHECK-OBJ: TagName: ABI_optimization_goals +; CHECK-OBJ-NEXT: Description: Aggressive Size + +define i32 @f(i64 %z) #0 { + ret i32 0 +} + +attributes #0 = { minsize optsize } + diff --git a/test/CodeGen/ARM/build-attributes-optimization-mixed.ll b/test/CodeGen/ARM/build-attributes-optimization-mixed.ll new file mode 100644 index 000000000000..8009fc6e28f8 --- /dev/null +++ b/test/CodeGen/ARM/build-attributes-optimization-mixed.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 | FileCheck %s + +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s + +; CHECK-NOT: .eabi_attribute 30 +; CHECK-NOT: Tag_ABI_optimization_goals + +define i32 @f(i64 %z) #0 { + ret i32 0 +} + +define i32 @g(i64 %z) #1 { + ret i32 1 +} + +attributes #0 = { noinline optnone } + +attributes #1 = { minsize optsize } + diff --git a/test/CodeGen/ARM/build-attributes-optimization-optnone.ll b/test/CodeGen/ARM/build-attributes-optimization-optnone.ll new file mode 100644 index 000000000000..cbdb915045c6 --- /dev/null +++ b/test/CodeGen/ARM/build-attributes-optimization-optnone.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 | FileCheck %s + +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ + +; CHECK: .eabi_attribute 30, 6 @ Tag_ABI_optimization_goals +; CHECK-OBJ: TagName: ABI_optimization_goals +; CHECK-OBJ-NEXT: Description: Best Debugging + +define i32 @f(i64 %z) #0 { + ret i32 0 +} + +attributes #0 = { noinline optnone } + diff --git a/test/CodeGen/ARM/build-attributes-optimization-optsize.ll b/test/CodeGen/ARM/build-attributes-optimization-optsize.ll new file mode 100644 index 000000000000..bab210aa8d01 --- /dev/null +++ b/test/CodeGen/ARM/build-attributes-optimization-optsize.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 | FileCheck %s + +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ + +; CHECK: .eabi_attribute 30, 3 @ Tag_ABI_optimization_goals +; CHECK-OBJ: TagName: ABI_optimization_goals +; CHECK-OBJ-NEXT: Description: Size + +define i32 @f(i64 %z) #0 { + ret i32 0 +} + +attributes #0 = { optsize } + diff --git a/test/CodeGen/ARM/build-attributes-optimization.ll b/test/CodeGen/ARM/build-attributes-optimization.ll new file mode 100644 index 000000000000..21b7b3c3ab0c --- /dev/null +++ b/test/CodeGen/ARM/build-attributes-optimization.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 | FileCheck %s --check-prefix=NONE +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 | FileCheck %s --check-prefix=SPEED +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 | FileCheck %s --check-prefix=MAXSPEED + +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O0 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=NONE-OBJ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O1 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=SPEED-OBJ +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-a7 -O3 -filetype obj -o - | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=MAXSPEED-OBJ + +; NONE: .eabi_attribute 30, 5 @ Tag_ABI_optimization_goals +; SPEED: .eabi_attribute 30, 1 @ Tag_ABI_optimization_goals +; MAXSPEED: .eabi_attribute 30, 2 @ Tag_ABI_optimization_goals + +; NONE-OBJ: TagName: ABI_optimization_goals +; NONE-OBJ-NEXT: Description: Debugging +; SPEED-OBJ: TagName: ABI_optimization_goals +; SPEED-OBJ-NEXT: Description: Speed +; MAXSPEED-OBJ: TagName: ABI_optimization_goals +; MAXSPEED-OBJ-NEXT: Description: Aggressive Speed + +define i32 @f(i64 %z) { + ret i32 0 +} + diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index 29c702304a3f..bf502b3ae077 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -1,17 +1,17 @@ ; This tests that MC/asm header conversion is smooth and that the ; build attributes are correct -; RUN: llc < %s -mtriple=thumbv5-linux-gnueabi -mcpu=xscale | FileCheck %s --check-prefix=XSCALE -; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s --check-prefix=V6 -; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6-FAST -; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi | FileCheck %s --check-prefix=V6M -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST -; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi | FileCheck %s --check-prefix=V6M -; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST -; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s | FileCheck %s --check-prefix=ARM1156T2F-S -; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=ARM1156T2F-S-FAST -; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv5-linux-gnueabi -mcpu=xscale -mattr=+strict-align | FileCheck %s --check-prefix=XSCALE +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6 +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6-FAST +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6M +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST +; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=V6M +; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align | FileCheck %s --check-prefix=ARM1156T2F-S +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=ARM1156T2F-S-FAST +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7M-FAST ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING @@ -59,18 +59,18 @@ ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=+neon,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-NEON-FP16 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus | FileCheck %s --check-prefix=CORTEX-M0PLUS -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0PLUS-FAST -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 | FileCheck %s --check-prefix=CORTEX-M1 -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M1-FAST -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 | FileCheck %s --check-prefix=SC000 -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC000-FAST -; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=CORTEX-M0 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -mattr=+strict-align | FileCheck %s --check-prefix=CORTEX-M0PLUS +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0PLUS-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -mattr=+strict-align | FileCheck %s --check-prefix=CORTEX-M1 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M1-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -mattr=+strict-align | FileCheck %s --check-prefix=SC000 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -mattr=+strict-align -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC000-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -mattr=+strict-align -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M3-FAST ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING @@ -96,6 +96,9 @@ ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 | FileCheck %s --check-prefix=CORTEX-R7 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R7-FAST ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35 | FileCheck %s --check-prefix=CORTEX-A35 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A35-FAST +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING @@ -116,58 +119,50 @@ ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-FPUV4-FAST ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,,+d16,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4 -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=pic | FileCheck %s --check-prefix=RELOC-PIC -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=static | FileCheck %s --check-prefix=RELOC-OTHER -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=default | FileCheck %s --check-prefix=RELOC-OTHER -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=RELOC-OTHER -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=PCS-R9-USE -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -arm-reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=pic | FileCheck %s --check-prefix=RELOC-PIC +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=static | FileCheck %s --check-prefix=RELOC-OTHER +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=default | FileCheck %s --check-prefix=RELOC-OTHER +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=RELOC-OTHER +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=PCS-R9-USE +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+reserve-r9,+strict-align | FileCheck %s --check-prefix=PCS-R9-RESERVE ; ARMv8.1a (AArch32) -; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; ARMv8a (AArch32) -; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a35 | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a35 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; ARMv7a -; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; ARMv7r -; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; ARMv7m -; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; ARMv6 ; RUN: llc < %s -mtriple=armv6-none-netbsd-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=STRICT-ALIGN -; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; ARMv6k ; RUN: llc < %s -mtriple=armv6k-none-netbsd-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=STRICT-ALIGN -; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv6k-none-linux-gnueabi -mcpu=arm1176j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; ARMv6m -; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-no-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN -; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN -; RUN: llc < %s -mtriple=thumbv6m-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN -; RUN: llc < %s -mtriple=thumbv6m-none-linux-gnueabi -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN -; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN -; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mattr=+strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=thumbv6m-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; ARMv5 -; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN -; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN -; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; XSCALE: .eabi_attribute 6, 5 ; XSCALE: .eabi_attribute 8, 1 @@ -748,6 +743,7 @@ ; CORTEX-M0: .eabi_attribute 21, 1 ; CORTEX-M0-NOT: .eabi_attribute 22 ; CORTEX-M0: .eabi_attribute 23, 3 +; CORTEX-M0: .eabi_attribute 34, 0 ; CORTEX-M0: .eabi_attribute 24, 1 ; CORTEX-M0: .eabi_attribute 25, 1 ; CORTEX-M0-NOT: .eabi_attribute 27 @@ -1109,7 +1105,7 @@ ; CORTEX-R7: .eabi_attribute 25, 1 ; CORTEX-R7: .eabi_attribute 27, 1 ; CORTEX-R7-NOT: .eabi_attribute 28 -; CORTEX-R7-NOT: .eabi_attribute 36 +; CORTEX-R7: .eabi_attribute 36, 1 ; CORTEX-R7: .eabi_attribute 38, 1 ; CORTEX-R7: .eabi_attribute 42, 1 ; CORTEX-R7: .eabi_attribute 44, 2 @@ -1122,6 +1118,36 @@ ; CORTEX-R7-FAST-NOT: .eabi_attribute 22 ; CORTEX-R7-FAST: .eabi_attribute 23, 1 +; CORTEX-A35: .cpu cortex-a35 +; CORTEX-A35: .eabi_attribute 6, 14 +; CORTEX-A35: .eabi_attribute 7, 65 +; CORTEX-A35: .eabi_attribute 8, 1 +; CORTEX-A35: .eabi_attribute 9, 2 +; CORTEX-A35: .fpu crypto-neon-fp-armv8 +; CORTEX-A35: .eabi_attribute 12, 3 +; CORTEX-A35-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A35: .eabi_attribute 20, 1 +; CORTEX-A35: .eabi_attribute 21, 1 +; CORTEX-A35-NOT: .eabi_attribute 22 +; CORTEX-A35: .eabi_attribute 23, 3 +; CORTEX-A35: .eabi_attribute 24, 1 +; CORTEX-A35: .eabi_attribute 25, 1 +; CORTEX-A35-NOT: .eabi_attribute 27 +; CORTEX-A35-NOT: .eabi_attribute 28 +; CORTEX-A35: .eabi_attribute 36, 1 +; CORTEX-A35: .eabi_attribute 38, 1 +; CORTEX-A35: .eabi_attribute 42, 1 +; CORTEX-A35-NOT: .eabi_attribute 44 +; CORTEX-A35: .eabi_attribute 68, 3 + +; CORTEX-A35-FAST-NOT: .eabi_attribute 19 +;; The A35 has the ARMv8 FP unit, which always flushes preserving sign. +; CORTEX-A35-FAST: .eabi_attribute 20, 2 +; CORTEX-A35-FAST-NOT: .eabi_attribute 21 +; CORTEX-A35-FAST-NOT: .eabi_attribute 22 +; CORTEX-A35-FAST: .eabi_attribute 23, 1 + ; CORTEX-A53: .cpu cortex-a53 ; CORTEX-A53: .eabi_attribute 6, 14 ; CORTEX-A53: .eabi_attribute 7, 65 diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index b2b6aaec8131..8821029520fe 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -83,9 +83,11 @@ declare void @foo() nounwind define void @t7() nounwind { entry: ; CHECKT2D-LABEL: t7: -; CHECKT2D: blxeq _foo -; CHECKT2D-NEXT: pop.w -; CHECKT2D-NEXT: b.w _foo +; CHECKT2D: it ne +; CHECKT2D-NEXT: bne.w _foo +; CHECKT2D-NEXT: push +; CHECKT2D-NEXT: mov r7, sp +; CHECKT2D-NEXT: blx _foo br i1 undef, label %bb, label %bb1.lr.ph bb1.lr.ph: diff --git a/test/CodeGen/ARM/cfi-alignment.ll b/test/CodeGen/ARM/cfi-alignment.ll new file mode 100644 index 000000000000..11add2242656 --- /dev/null +++ b/test/CodeGen/ARM/cfi-alignment.ll @@ -0,0 +1,48 @@ +; RUN: llc -mtriple=thumbv7k-apple-watchos7.0 -o - %s | FileCheck %s + +; Since d11 doesn't get pushed with the aligned registers, its frameindex +; shouldn't be modified to say it has been. + +define void @foo() { +; CHECK-LABEL: foo: +; CHECK: push {r7, lr} +; CHECK: .cfi_offset r7, -8 +; CHECK: vpush {d11} +; CHECK: vpush {d8, d9} +; CHECK: .cfi_offset d11, -16 +; CHECK: .cfi_offset d9, -24 +; CHECK: .cfi_offset d8, -32 + call void asm sideeffect "", "~{d8},~{d9},~{d11}"() + call void @bar() + ret void +} + +define void @variadic_foo(i8, ...) { +; CHECK-LABEL: variadic_foo: +; CHECK: sub sp, #12 +; CHECK: push {r7, lr} +; CHECK: .cfi_offset r7, -20 +; CHECK: sub sp, #4 +; CHECK: vpush {d11} +; CHECK: vpush {d8, d9} +; CHECK: .cfi_offset d11, -32 +; CHECK: .cfi_offset d9, -40 +; CHECK: .cfi_offset d8, -48 + call void asm sideeffect "", "~{d8},~{d9},~{d11}"() + call void @llvm.va_start(i8* null) + call void @bar() + ret void +} + +define void @test_maintain_stack_align() { +; CHECK-LABEL: test_maintain_stack_align: +; CHECK: push {r7, lr} +; CHECK: vpush {d8, d9} +; CHECK: sub sp, #8 + call void asm sideeffect "", "~{d8},~{d9}"() + call void @bar() + ret void +} + +declare void @bar() +declare void @llvm.va_start(i8*) nounwind diff --git a/test/CodeGen/ARM/cmpxchg-idioms.ll b/test/CodeGen/ARM/cmpxchg-idioms.ll index fb88575cab3b..81e05acfef79 100644 --- a/test/CodeGen/ARM/cmpxchg-idioms.ll +++ b/test/CodeGen/ARM/cmpxchg-idioms.ll @@ -15,14 +15,14 @@ define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) { ; CHECK: bne [[LOOP]] ; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} -; CHECK: movs r0, #1 ; CHECK: dmb ish +; CHECK: movs r0, #1 ; CHECK: bx lr ; CHECK: [[FAILED]]: ; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} -; CHECK: movs r0, #0 ; CHECK: dmb ish +; CHECK: movs r0, #0 ; CHECK: bx lr %pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst @@ -34,8 +34,8 @@ define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) { define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) { ; CHECK-LABEL: test_return_bool: -; CHECK: uxtb [[OLDBYTE:r[0-9]+]], r1 ; CHECK: dmb ishst +; CHECK: uxtb [[OLDBYTE:r[0-9]+]], r1 ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]: ; CHECK: ldrexb [[LOADED:r[0-9]+]], [r0] diff --git a/test/CodeGen/ARM/cmpxchg-weak.ll b/test/CodeGen/ARM/cmpxchg-weak.ll index 126e33062623..1eac9c41cf92 100644 --- a/test/CodeGen/ARM/cmpxchg-weak.ll +++ b/test/CodeGen/ARM/cmpxchg-weak.ll @@ -5,16 +5,24 @@ define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) { %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic %oldval = extractvalue { i32, i1 } %pair, 0 -; CHECK: dmb ish -; CHECK: ldrex [[LOADED:r[0-9]+]], [r0] -; CHECK: cmp [[LOADED]], r1 -; CHECK: strexeq [[SUCCESS:r[0-9]+]], r2, [r0] -; CHECK: cmpeq [[SUCCESS]], #0 -; CHECK: bne [[DONE:LBB[0-9]+_[0-9]+]] -; CHECK: dmb ish -; CHECK: [[DONE]]: -; CHECK: str r3, [r0] -; CHECK: bx lr +; CHECK-NEXT: BB#0: +; CHECK-NEXT: dmb ish +; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0] +; CHECK-NEXT: cmp [[LOADED]], r1 +; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: BB#1: +; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0] +; CHECK-NEXT: cmp [[SUCCESS]], #0 +; CHECK-NEXT: bne [[FAILBB:LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: BB#2: +; CHECK-NEXT: dmb ish +; CHECK-NEXT: str r3, [r0] +; CHECK-NEXT: bx lr +; CHECK-NEXT: [[LDFAILBB]]: +; CHECK-NEXT: clrex +; CHECK-NEXT: [[FAILBB]]: +; CHECK-NEXT: str r3, [r0] +; CHECK-NEXT: bx lr store i32 %oldval, i32* %addr ret void @@ -27,17 +35,23 @@ define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) { %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic %success = extractvalue { i32, i1 } %pair, 1 -; CHECK: dmb ish -; CHECK: mov r0, #0 -; CHECK: ldrex [[LOADED:r[0-9]+]], [r1] -; CHECK: cmp [[LOADED]], r2 -; CHECK: strexeq [[STATUS:r[0-9]+]], r3, [r1] -; CHECK: cmpeq [[STATUS]], #0 -; CHECK: bne [[DONE:LBB[0-9]+_[0-9]+]] -; CHECK: dmb ish -; CHECK: mov r0, #1 -; CHECK: [[DONE]]: -; CHECK: bx lr +; CHECK-NEXT: BB#0: +; CHECK-NEXT: dmb ish +; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1] +; CHECK-NEXT: cmp [[LOADED]], r2 +; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: BB#1: +; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1] +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: cmp [[SUCCESS]], #0 +; CHECK-NEXT: bxne lr +; CHECK-NEXT: dmb ish +; CHECK-NEXT: mov r0, #1 +; CHECK-NEXT: bx lr +; CHECK-NEXT: [[LDFAILBB]]: +; CHECK-NEXT: clrex +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: bx lr ret i1 %success } diff --git a/test/CodeGen/ARM/coalesce-dbgvalue.ll b/test/CodeGen/ARM/coalesce-dbgvalue.ll index cd2ab257207a..4468f1ec9c42 100644 --- a/test/CodeGen/ARM/coalesce-dbgvalue.ll +++ b/test/CodeGen/ARM/coalesce-dbgvalue.ll @@ -15,7 +15,7 @@ target triple = "thumbv7-apple-ios3.0.0" @d = common global i32 0, align 4 ; Function Attrs: nounwind ssp -define i32 @pr16110() #0 { +define i32 @pr16110() #0 !dbg !4 { for.cond1.preheader: store i32 0, i32* @c, align 4, !dbg !21 br label %for.cond1.outer, !dbg !26 @@ -79,18 +79,18 @@ attributes #3 = { nounwind } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 182024) (llvm/trunk 182023)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !15, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 182024) (llvm/trunk 182023)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !15, imports: !2) !1 = !DIFile(filename: "pr16110.c", directory: "/d/b") !2 = !{} !3 = !{!4} -!4 = !DISubprogram(name: "pr16110", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 7, file: !1, scope: !5, type: !6, function: i32 ()* @pr16110, variables: !9) +!4 = distinct !DISubprogram(name: "pr16110", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 7, file: !1, scope: !5, type: !6, variables: !9) !5 = !DIFile(filename: "pr16110.c", directory: "/d/b") !6 = !DISubroutineType(types: !7) !7 = !{!8} !8 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !9 = !{!10, !11} -!10 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "e", line: 8, scope: !4, file: !5, type: !8) -!11 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "f", line: 13, scope: !12, file: !5, type: !14) +!10 = !DILocalVariable(name: "e", line: 8, scope: !4, file: !5, type: !8) +!11 = !DILocalVariable(name: "f", line: 13, scope: !12, file: !5, type: !14) !12 = distinct !DILexicalBlock(line: 12, column: 0, file: !1, scope: !13) !13 = distinct !DILexicalBlock(line: 12, column: 0, file: !1, scope: !4) !14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !8) diff --git a/test/CodeGen/ARM/coalesce-subregs.ll b/test/CodeGen/ARM/coalesce-subregs.ll index 72fefeacfc5b..a11976e27448 100644 --- a/test/CodeGen/ARM/coalesce-subregs.ll +++ b/test/CodeGen/ARM/coalesce-subregs.ll @@ -14,11 +14,11 @@ target triple = "thumbv7-apple-ios0.0.0" define void @f(float* %p, i32 %c) nounwind ssp { entry: %0 = bitcast float* %p to i8* - %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4) + %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %0, i32 4) %vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1 %add.ptr = getelementptr inbounds float, float* %p, i32 8 %1 = bitcast float* %add.ptr to i8* - tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4) + tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4) ret void } @@ -27,13 +27,13 @@ entry: define void @f1(float* %p, i32 %c) nounwind ssp { entry: %0 = bitcast float* %p to i8* - %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4) + %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %0, i32 4) %vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1 %add.ptr = getelementptr inbounds float, float* %p, i32 8 %1 = bitcast float* %add.ptr to i8* - %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4) + %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %1, i32 4) %vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0 - tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4) + tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4) ret void } @@ -42,7 +42,7 @@ entry: define void @f2(float* %p, i32 %c) nounwind ssp { entry: %0 = bitcast float* %p to i8* - %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4) + %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %0, i32 4) %vld224 = extractvalue { <4 x float>, <4 x float> } %vld2, 1 br label %do.body @@ -52,10 +52,10 @@ do.body: ; preds = %do.body, %entry %p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ] %add.ptr = getelementptr inbounds float, float* %p.addr.0, i32 8 %1 = bitcast float* %add.ptr to i8* - %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4) + %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8* %1, i32 4) %vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0 %vld2216 = extractvalue { <4 x float>, <4 x float> } %vld22, 1 - tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4) + tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4) %dec = add nsw i32 %c.addr.0, -1 %tobool = icmp eq i32 %dec, 0 br i1 %tobool, label %do.end, label %do.body @@ -64,8 +64,8 @@ do.end: ; preds = %do.body ret void } -declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly -declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind +declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32.p0i8(i8*, i32) nounwind readonly +declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind ; CHECK: f3 ; This function has lane insertions that span basic blocks. @@ -109,12 +109,12 @@ if.end: ; preds = %if.else, %if.then %x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ] %add.ptr = getelementptr inbounds float, float* %p, i32 4 %4 = bitcast float* %add.ptr to i8* - tail call void @llvm.arm.neon.vst1.v2f32(i8* %4, <2 x float> %x.0, i32 4) + tail call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %4, <2 x float> %x.0, i32 4) ret void } -declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) nounwind -declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly +declare void @llvm.arm.neon.vst1.p0i8.v2f32(i8*, <2 x float>, i32) nounwind +declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0i8(i8*, i32) nounwind readonly ; CHECK: f4 ; This function inserts a lane into a fully defined vector. @@ -124,7 +124,7 @@ declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly define void @f4(float* %p, float* %q) nounwind ssp { entry: %0 = bitcast float* %p to i8* - %vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %0, i32 4) + %vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32.p0i8(i8* %0, i32 4) %tobool = icmp eq float* %q, null br i1 %tobool, label %if.end, label %if.then @@ -138,7 +138,7 @@ if.then: ; preds = %entry if.end: ; preds = %entry, %if.then %x.0 = phi <2 x float> [ %vecins, %if.then ], [ %vld1, %entry ] - tail call void @llvm.arm.neon.vst1.v2f32(i8* %0, <2 x float> %x.0, i32 4) + tail call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %0, <2 x float> %x.0, i32 4) ret void } @@ -154,7 +154,7 @@ if.end: ; preds = %entry, %if.then define void @f5(float* %p, float* %q) nounwind ssp { entry: %0 = bitcast float* %p to i8* - %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %0, i32 4) + %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %0, i32 4) %vecext = extractelement <4 x float> %vld1, i32 0 %vecext1 = extractelement <4 x float> %vld1, i32 1 %vecext2 = extractelement <4 x float> %vld1, i32 2 @@ -182,13 +182,13 @@ if.end: ; preds = %entry, %if.then %vecinit9 = insertelement <4 x float> %vecinit, float %b.0, i32 1 %vecinit10 = insertelement <4 x float> %vecinit9, float %c.0, i32 2 %vecinit11 = insertelement <4 x float> %vecinit10, float %add, i32 3 - tail call void @llvm.arm.neon.vst1.v4f32(i8* %0, <4 x float> %vecinit11, i32 4) + tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %0, <4 x float> %vecinit11, i32 4) ret void } -declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly +declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly -declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind ; CHECK: pr13999 define void @pr13999() nounwind readonly { diff --git a/test/CodeGen/ARM/combine-vmovdrr.ll b/test/CodeGen/ARM/combine-vmovdrr.ll new file mode 100644 index 000000000000..358f7e3a983e --- /dev/null +++ b/test/CodeGen/ARM/combine-vmovdrr.ll @@ -0,0 +1,72 @@ +; RUN: llc %s -o - | FileCheck %s + +target triple = "thumbv7s-apple-ios" + +declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %shuffle.i.i307, <8 x i8> %shuffle.i27.i308, <8 x i8> %vtbl2.i25.i) + +; Check that we get the motivating example: +; The bitcasts force the values to go through the GPRs, whereas +; they are defined on VPRs and used on VPRs. +; +; CHECK-LABEL: motivatingExample: +; CHECK: vldr [[ARG2_VAL:d[0-9]+]], [r1] +; CHECK-NEXT: vld1.32 {[[ARG1_VALlo:d[0-9]+]], [[ARG1_VALhi:d[0-9]+]]}, [r0] +; CHECK-NEXT: vtbl.8 [[RES:d[0-9]+]], {[[ARG1_VALlo]], [[ARG1_VALhi]]}, [[ARG2_VAL]] +; CHECK-NEXT: vstr [[RES]], [r1] +; CHECK-NEXT: bx lr +define void @motivatingExample(<2 x i64>* %addr, <8 x i8>* %addr2) { + %shuffle.i.bc.i309 = load <2 x i64>, <2 x i64>* %addr + %vtbl2.i25.i = load <8 x i8>, <8 x i8>* %addr2 + %shuffle.i.extract.i310 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 0 + %shuffle.i27.extract.i311 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 1 + %tmp45 = bitcast i64 %shuffle.i.extract.i310 to <8 x i8> + %tmp46 = bitcast i64 %shuffle.i27.extract.i311 to <8 x i8> + %vtbl2.i25.i313 = tail call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp45, <8 x i8> %tmp46, <8 x i8> %vtbl2.i25.i) + store <8 x i8> %vtbl2.i25.i313, <8 x i8>* %addr2 + ret void +} + +; Check that we do not perform the transformation for dynamic index. +; CHECK-LABEL: dynamicIndex: +; CHECK-NOT: mul +; CHECK: pop +define void @dynamicIndex(<2 x i64>* %addr, <8 x i8>* %addr2, i32 %index) { + %shuffle.i.bc.i309 = load <2 x i64>, <2 x i64>* %addr + %vtbl2.i25.i = load <8 x i8>, <8 x i8>* %addr2 + %shuffle.i.extract.i310 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 %index + %shuffle.i27.extract.i311 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 1 + %tmp45 = bitcast i64 %shuffle.i.extract.i310 to <8 x i8> + %tmp46 = bitcast i64 %shuffle.i27.extract.i311 to <8 x i8> + %vtbl2.i25.i313 = tail call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp45, <8 x i8> %tmp46, <8 x i8> %vtbl2.i25.i) + store <8 x i8> %vtbl2.i25.i313, <8 x i8>* %addr2 + ret void +} + +; Check that we do not perform the transformation when there are several uses +; of the result of the bitcast. +; CHECK-LABEL: severalUses: +; ARG1_VALlo is hard coded because we need to access the high part of d0, +; i.e., s1, and we can't express that with filecheck. +; CHECK: vld1.32 {[[ARG1_VALlo:d0]], [[ARG1_VALhi:d[0-9]+]]}, [r0] +; CHECK-NEXT: vldr [[ARG2_VAL:d[0-9]+]], [r1] +; s1 is actually 2 * ARG1_VALlo + 1, but we cannot express that with filecheck. +; CHECK-NEXT: vmov [[REThi:r[0-9]+]], s1 +; We build the return value here. s0 is 2 * ARG1_VALlo. +; CHECK-NEXT: vmov r0, s0 +; This copy is correct but actually useless. We should be able to clean it up. +; CHECK-NEXT: vmov [[ARG1_VALloCPY:d[0-9]+]], r0, [[REThi]] +; CHECK-NEXT: vtbl.8 [[RES:d[0-9]+]], {[[ARG1_VALloCPY]], [[ARG1_VALhi]]}, [[ARG2_VAL]] +; CHECK-NEXT: vstr [[RES]], [r1] +; CHECK-NEXT: mov r1, [[REThi]] +; CHECK-NEXT: bx lr +define i64 @severalUses(<2 x i64>* %addr, <8 x i8>* %addr2) { + %shuffle.i.bc.i309 = load <2 x i64>, <2 x i64>* %addr + %vtbl2.i25.i = load <8 x i8>, <8 x i8>* %addr2 + %shuffle.i.extract.i310 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 0 + %shuffle.i27.extract.i311 = extractelement <2 x i64> %shuffle.i.bc.i309, i32 1 + %tmp45 = bitcast i64 %shuffle.i.extract.i310 to <8 x i8> + %tmp46 = bitcast i64 %shuffle.i27.extract.i311 to <8 x i8> + %vtbl2.i25.i313 = tail call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp45, <8 x i8> %tmp46, <8 x i8> %vtbl2.i25.i) + store <8 x i8> %vtbl2.i25.i313, <8 x i8>* %addr2 + ret i64 %shuffle.i.extract.i310 +} diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll index 3baa103e3d5d..75a90bbf0caa 100644 --- a/test/CodeGen/ARM/constants.ll +++ b/test/CodeGen/ARM/constants.ll @@ -63,7 +63,7 @@ define i32 @f8() nounwind { float 3.000000e+00> }, align 16 ; CHECK: const1 ; CHECK: .zero 16 -; CHECK: float 1.0 -; CHECK: float 2.0 -; CHECK: float 3.0 +; CHECK: float 1 +; CHECK: float 2 +; CHECK: float 3 ; CHECK: .zero 4 diff --git a/test/CodeGen/ARM/dagcombine-concatvector.ll b/test/CodeGen/ARM/dagcombine-concatvector.ll index 80ef2ab7b8bf..578d80d1cef4 100644 --- a/test/CodeGen/ARM/dagcombine-concatvector.ll +++ b/test/CodeGen/ARM/dagcombine-concatvector.ll @@ -19,8 +19,8 @@ bb: %tmp5 = bitcast i64 %tmp4 to <8 x i8> %tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> %tmp3, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> - tail call void @llvm.arm.neon.vst1.v16i8(i8* %arg, <16 x i8> %tmp7, i32 2) + tail call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* %arg, <16 x i8> %tmp7, i32 2) ret void } -declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) +declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32) diff --git a/test/CodeGen/ARM/debug-frame-vararg.ll b/test/CodeGen/ARM/debug-frame-vararg.ll index c1eff0a5bd67..13ca20c20359 100644 --- a/test/CodeGen/ARM/debug-frame-vararg.ll +++ b/test/CodeGen/ARM/debug-frame-vararg.ll @@ -25,11 +25,11 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) !1 = !DIFile(filename: "var.c", directory: "/tmp") !2 = !{} !3 = !{!4} -!4 = !DISubprogram(name: "sum", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: i32 (i32, ...)* @sum, variables: !2) +!4 = distinct !DISubprogram(name: "sum", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "var.c", directory: "/tmp") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} @@ -37,9 +37,9 @@ !9 = !{i32 2, !"Dwarf Version", i32 4} !10 = !{i32 1, !"Debug Info Version", i32 3} !11 = !{!"clang version 3.5 "} -!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "count", line: 5, arg: 1, scope: !4, file: !5, type: !8) +!12 = !DILocalVariable(name: "count", line: 5, arg: 1, scope: !4, file: !5, type: !8) !13 = !DILocation(line: 5, scope: !4) -!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vl", line: 6, scope: !4, file: !5, type: !15) +!14 = !DILocalVariable(name: "vl", line: 6, scope: !4, file: !5, type: !15) !15 = !DIDerivedType(tag: DW_TAG_typedef, name: "va_list", line: 30, file: !16, baseType: !17) !16 = !DIFile(filename: "/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", directory: "/tmp") !17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__builtin_va_list", line: 6, file: !1, baseType: !18) @@ -49,9 +49,9 @@ !21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: null) !22 = !DILocation(line: 6, scope: !4) !23 = !DILocation(line: 7, scope: !4) -!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "sum", line: 8, scope: !4, file: !5, type: !8) +!24 = !DILocalVariable(name: "sum", line: 8, scope: !4, file: !5, type: !8) !25 = !DILocation(line: 8, scope: !4) -!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 9, scope: !27, file: !5, type: !8) +!26 = !DILocalVariable(name: "i", line: 9, scope: !27, file: !5, type: !8) !27 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !4) !28 = !DILocation(line: 9, scope: !27) !29 = !DILocation(line: 10, scope: !30) @@ -108,7 +108,7 @@ ; CHECK-THUMB-FP-ELIM: add r7, sp, #8 ; CHECK-THUMB-FP-ELIM: .cfi_def_cfa r7, 20 -define i32 @sum(i32 %count, ...) { +define i32 @sum(i32 %count, ...) !dbg !4 { entry: %vl = alloca i8*, align 4 %vl1 = bitcast i8** %vl to i8* diff --git a/test/CodeGen/ARM/debug-frame.ll b/test/CodeGen/ARM/debug-frame.ll index cc07400c2e1c..4bd401b68496 100644 --- a/test/CodeGen/ARM/debug-frame.ll +++ b/test/CodeGen/ARM/debug-frame.ll @@ -30,11 +30,11 @@ ; RUN: -filetype=asm -o - %s \ ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM -; RUN: llc -mtriple thumb-unknown-linux-gnueabi \ +; RUN: llc -mtriple thumbv5-unknown-linux-gnueabi \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-FP -; RUN: llc -mtriple thumb-unknown-linux-gnueabi \ +; RUN: llc -mtriple thumbv5-unknown-linux-gnueabi \ ; RUN: -filetype=asm -o - %s \ ; RUN: | FileCheck %s --check-prefix=CHECK-THUMB-FP-ELIM @@ -125,11 +125,11 @@ declare void @_ZSt9terminatev() !llvm.module.flags = !{!10, !11} !llvm.ident = !{!12} -!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) !1 = !DIFile(filename: "exp.cpp", directory: "/tmp") !2 = !{} !3 = !{!4} -!4 = !DISubprogram(name: "test", linkageName: "_Z4testiiiiiddddd", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: void (i32, i32, i32, i32, i32, double, double, double, double, double)* @_Z4testiiiiiddddd, variables: !2) +!4 = distinct !DISubprogram(name: "test", linkageName: "_Z4testiiiiiddddd", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "exp.cpp", directory: "/tmp") !6 = !DISubroutineType(types: !7) !7 = !{null, !8, !8, !8, !8, !8, !9, !9, !9, !9, !9} @@ -138,18 +138,18 @@ declare void @_ZSt9terminatev() !10 = !{i32 2, !"Dwarf Version", i32 4} !11 = !{i32 1, !"Debug Info Version", i32 3} !12 = !{!"clang version 3.5 "} -!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 4, arg: 1, scope: !4, file: !5, type: !8) +!13 = !DILocalVariable(name: "a", line: 4, arg: 1, scope: !4, file: !5, type: !8) !14 = !DILocation(line: 4, scope: !4) -!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 4, arg: 2, scope: !4, file: !5, type: !8) -!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !4, file: !5, type: !8) -!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "d", line: 4, arg: 4, scope: !4, file: !5, type: !8) -!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "e", line: 4, arg: 5, scope: !4, file: !5, type: !8) -!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "m", line: 5, arg: 6, scope: !4, file: !5, type: !9) +!15 = !DILocalVariable(name: "b", line: 4, arg: 2, scope: !4, file: !5, type: !8) +!16 = !DILocalVariable(name: "c", line: 4, arg: 3, scope: !4, file: !5, type: !8) +!17 = !DILocalVariable(name: "d", line: 4, arg: 4, scope: !4, file: !5, type: !8) +!18 = !DILocalVariable(name: "e", line: 4, arg: 5, scope: !4, file: !5, type: !8) +!19 = !DILocalVariable(name: "m", line: 5, arg: 6, scope: !4, file: !5, type: !9) !20 = !DILocation(line: 5, scope: !4) -!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "n", line: 5, arg: 7, scope: !4, file: !5, type: !9) -!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "p", line: 5, arg: 8, scope: !4, file: !5, type: !9) -!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "q", line: 5, arg: 9, scope: !4, file: !5, type: !9) -!24 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "r", line: 5, arg: 10, scope: !4, file: !5, type: !9) +!21 = !DILocalVariable(name: "n", line: 5, arg: 7, scope: !4, file: !5, type: !9) +!22 = !DILocalVariable(name: "p", line: 5, arg: 8, scope: !4, file: !5, type: !9) +!23 = !DILocalVariable(name: "q", line: 5, arg: 9, scope: !4, file: !5, type: !9) +!24 = !DILocalVariable(name: "r", line: 5, arg: 10, scope: !4, file: !5, type: !9) !25 = !DILocation(line: 7, scope: !26) !26 = distinct !DILexicalBlock(line: 6, column: 0, file: !1, scope: !4) !27 = !DILocation(line: 8, scope: !26) diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index 84eae77794a4..bf7e7321ae3d 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -6,12 +6,12 @@ target triple = "thumbv7-apple-ios" %struct.tag_s = type { i32, i32, i32 } -define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp { +define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp !dbg !1 { tail call void @llvm.dbg.value(metadata %struct.tag_s* %this, i64 0, metadata !5, metadata !DIExpression()), !dbg !20 tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, i64 0, metadata !13, metadata !DIExpression()), !dbg !21 tail call void @llvm.dbg.value(metadata i64 %x, i64 0, metadata !14, metadata !DIExpression()), !dbg !22 tail call void @llvm.dbg.value(metadata i64 %y, i64 0, metadata !17, metadata !DIExpression()), !dbg !23 -;CHECK: @DEBUG_VALUE: foo:y <- [R7+8] +;CHECK: @DEBUG_VALUE: foo:y <- [%R7+8] tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, i64 0, metadata !18, metadata !DIExpression()), !dbg !24 tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, i64 0, metadata !19, metadata !DIExpression()), !dbg !25 %1 = icmp eq %struct.tag_s* %c, null, !dbg !26 @@ -32,12 +32,12 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 1, file: !32, enums: !{}, retainedTypes: !{}, subprograms: !30, imports: null) -!1 = !DISubprogram(name: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !2, scope: !2, type: !3, function: void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, variables: !31) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 1, file: !32, enums: !{}, retainedTypes: !{}, subprograms: !30, imports: null) +!1 = distinct !DISubprogram(name: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !2, scope: !2, type: !3, variables: !31) !2 = !DIFile(filename: "one.c", directory: "/Volumes/Athwagate/R10048772") !3 = !DISubroutineType(types: !4) !4 = !{null} -!5 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", line: 11, arg: 1, scope: !1, file: !2, type: !6) +!5 = !DILocalVariable(name: "this", line: 11, arg: 1, scope: !1, file: !2, type: !6) !6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !0, baseType: !7) !7 = !DICompositeType(tag: DW_TAG_structure_type, name: "tag_s", line: 5, size: 96, align: 32, file: !32, scope: !0, elements: !8) !8 = !{!9, !11, !12} @@ -45,13 +45,13 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !11 = !DIDerivedType(tag: DW_TAG_member, name: "y", line: 7, size: 32, align: 32, offset: 32, file: !32, scope: !7, baseType: !10) !12 = !DIDerivedType(tag: DW_TAG_member, name: "z", line: 8, size: 32, align: 32, offset: 64, file: !32, scope: !7, baseType: !10) -!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 2, scope: !1, file: !2, type: !6) -!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "x", line: 11, arg: 3, scope: !1, file: !2, type: !15) +!13 = !DILocalVariable(name: "c", line: 11, arg: 2, scope: !1, file: !2, type: !6) +!14 = !DILocalVariable(name: "x", line: 11, arg: 3, scope: !1, file: !2, type: !15) !15 = !DIDerivedType(tag: DW_TAG_typedef, name: "UInt64", line: 1, file: !32, scope: !0, baseType: !16) !16 = !DIBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 32, encoding: DW_ATE_unsigned) -!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "y", line: 11, arg: 4, scope: !1, file: !2, type: !15) -!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr1", line: 11, arg: 5, scope: !1, file: !2, type: !6) -!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr2", line: 11, arg: 6, scope: !1, file: !2, type: !6) +!17 = !DILocalVariable(name: "y", line: 11, arg: 4, scope: !1, file: !2, type: !15) +!18 = !DILocalVariable(name: "ptr1", line: 11, arg: 5, scope: !1, file: !2, type: !6) +!19 = !DILocalVariable(name: "ptr2", line: 11, arg: 6, scope: !1, file: !2, type: !6) !20 = !DILocation(line: 11, column: 24, scope: !1) !21 = !DILocation(line: 11, column: 44, scope: !1) !22 = !DILocation(line: 11, column: 54, scope: !1) diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll index 366102755174..c628c5e9038d 100644 --- a/test/CodeGen/ARM/debug-info-blocks.ll +++ b/test/CodeGen/ARM/debug-info-blocks.ll @@ -1,5 +1,21 @@ -; RUN: llc -O0 < %s | FileCheck %s -; CHECK: @DEBUG_VALUE: foobar_func_block_invoke_0:mydata <- [SP+{{[0-9]+}}] +; RUN: llc -filetype=obj -O0 < %s | llvm-dwarfdump - | FileCheck %s + +; debug_info content +; CHECK: DW_AT_name {{.*}} "foobar_func_block_invoke_0" +; CHECK-NOT: DW_TAG_subprogram +; CHECK: DW_TAG_variable +; CHECK-NOT: DW_TAG +; CHECK-NEXT: DW_AT_location [DW_FORM_sec_offset] ([[MYDATA_LOC:0x[0-9a-f]*]]) +; CHECK-NEXT: DW_AT_name {{.*}} "mydata" + +; debug_loc content +; CHECK: .debug_loc contents: +; CHECK: [[MYDATA_LOC]]: Beginning address offset: {{.*}} +; CHECK-NOT: {{0x[0-9a-f]*}}: Beginning address offset +; CHECK: Location description: {{.*}} 23 04 06 23 18 +; CHECK-NOT: {{0x[0-9a-f]*}}: Beginning address offset +; CHECK: Location description: {{.*}} 23 04 06 23 18 + ; Radar 9331779 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-ios" @@ -27,7 +43,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind -define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %loadedMydata, [4 x i32] %bounds.coerce0, [4 x i32] %data.coerce0) ssp { +define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %loadedMydata, [4 x i32] %bounds.coerce0, [4 x i32] %data.coerce0) ssp !dbg !23 { %1 = alloca %0*, align 4 %bounds = alloca %struct.CR, align 4 %data = alloca %struct.CR, align 4 @@ -95,7 +111,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!162} -!0 = !DICompileUnit(language: DW_LANG_ObjC, producer: "Apple clang version 2.1", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !153, enums: !147, retainedTypes: !{}, subprograms: !148) +!0 = distinct !DICompileUnit(language: DW_LANG_ObjC, producer: "Apple clang version 2.1", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !153, enums: !147, retainedTypes: !{}, subprograms: !148) !1 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 248, size: 32, align: 32, file: !160, scope: !0, elements: !3) !2 = !DIFile(filename: "header.h", directory: "/Volumes/Sandbox/llvm") !3 = !{!4} @@ -118,11 +134,11 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !20 = !DIFile(filename: "header4.h", directory: "/Volumes/Sandbox/llvm") !21 = !{!22} !22 = !DIEnumerator(name: "Eleven", value: 0) ; [ DW_TAG_enumerator ] -!23 = !DISubprogram(name: "foobar_func_block_invoke_0", line: 609, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 609, file: !152, scope: !24, type: !25, function: void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0) +!23 = distinct !DISubprogram(name: "foobar_func_block_invoke_0", line: 609, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 609, file: !152, scope: !24, type: !25) !24 = !DIFile(filename: "MyLibrary.m", directory: "/Volumes/Sandbox/llvm") !25 = !DISubroutineType(types: !26) !26 = !{null} -!27 = !DILocalVariable(tag: DW_TAG_arg_variable, name: ".block_descriptor", line: 609, arg: 1, flags: DIFlagArtificial, scope: !23, file: !24, type: !28) +!27 = !DILocalVariable(name: ".block_descriptor", line: 609, arg: 1, flags: DIFlagArtificial, scope: !23, file: !24, type: !28) !28 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, scope: !0, baseType: !29) !29 = !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_14", line: 609, size: 256, align: 32, file: !152, scope: !24, elements: !30) !30 = !{!31, !33, !35, !36, !37, !48, !89, !124} @@ -225,16 +241,16 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !127 = !DICompositeType(tag: DW_TAG_structure_type, name: "my_struct", line: 49, flags: DIFlagFwdDecl, file: !159, scope: !0) !128 = !DIFile(filename: "header15.h", directory: "/Volumes/Sandbox/llvm") !129 = !DILocation(line: 609, column: 144, scope: !23) -!130 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "loadedMydata", line: 609, arg: 2, scope: !23, file: !24, type: !59) +!130 = !DILocalVariable(name: "loadedMydata", line: 609, arg: 2, scope: !23, file: !24, type: !59) !131 = !DILocation(line: 609, column: 155, scope: !23) -!132 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bounds", line: 609, arg: 3, scope: !23, file: !24, type: !108) +!132 = !DILocalVariable(name: "bounds", line: 609, arg: 3, scope: !23, file: !24, type: !108) !133 = !DILocation(line: 609, column: 175, scope: !23) -!134 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "data", line: 609, arg: 4, scope: !23, file: !24, type: !108) +!134 = !DILocalVariable(name: "data", line: 609, arg: 4, scope: !23, file: !24, type: !108) !135 = !DILocation(line: 609, column: 190, scope: !23) -!136 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "mydata", line: 604, scope: !23, file: !24, type: !50) +!136 = !DILocalVariable(name: "mydata", line: 604, scope: !23, file: !24, type: !50) !137 = !DILocation(line: 604, column: 49, scope: !23) -!138 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "self", line: 604, scope: !23, file: !40, type: !90) -!139 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "semi", line: 607, scope: !23, file: !24, type: !125) +!138 = !DILocalVariable(name: "self", line: 604, scope: !23, file: !40, type: !90) +!139 = !DILocalVariable(name: "semi", line: 607, scope: !23, file: !24, type: !125) !140 = !DILocation(line: 607, column: 30, scope: !23) !141 = !DILocation(line: 610, column: 17, scope: !142) !142 = distinct !DILexicalBlock(line: 609, column: 200, file: !152, scope: !23) diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index 03b4d6b38151..b9d110e42cd4 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -6,15 +6,15 @@ target triple = "thumbv7-apple-macosx10.6.7" ;CHECK-NEXT: Ltmp1 ;CHECK-NEXT: LBB0_1 -;CHECK:@DEBUG_VALUE: x <- Q4{{$}} -;CHECK-NEXT:@DEBUG_VALUE: y <- Q4{{$}} +;CHECK:@DEBUG_VALUE: x <- %Q4{{$}} +;CHECK-NEXT:@DEBUG_VALUE: y <- %Q4{{$}} @.str = external constant [13 x i8] declare <4 x float> @test0001(float) nounwind readnone ssp -define i32 @main(i32 %argc, i8** nocapture %argv, i1 %cond) nounwind ssp { +define i32 @main(i32 %argc, i8** nocapture %argv, i1 %cond) nounwind ssp !dbg !10 { entry: br label %for.body9 @@ -42,9 +42,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.module.flags = !{!56} !llvm.dbg.cu = !{!2} -!0 = !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !3, function: <4 x float> (float)* @test0001, variables: !51) +!0 = distinct !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !3, variables: !51) !1 = !DIFile(filename: "build2.c", directory: "/private/tmp") -!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6) @@ -52,27 +52,27 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) !8 = !{!9} !9 = !DISubrange(count: 4) -!10 = !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !11, function: i32 (i32, i8**, i1)* @main, variables: !52) +!10 = distinct !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !11, variables: !52) !11 = !DISubroutineType(types: !12) !12 = !{!13} !13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!14 = !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !55, scope: null, type: !16, variables: !53) +!14 = distinct !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !55, scope: null, type: !16, variables: !53) !15 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp") !16 = !DISubroutineType(types: !17) !17 = !{null} -!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !0, file: !1, type: !7) -!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 59, arg: 1, scope: !10, file: !1, type: !13) -!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 59, arg: 2, scope: !10, file: !1, type: !21) +!18 = !DILocalVariable(name: "a", line: 3, arg: 1, scope: !0, file: !1, type: !7) +!19 = !DILocalVariable(name: "argc", line: 59, arg: 1, scope: !10, file: !1, type: !13) +!20 = !DILocalVariable(name: "argv", line: 59, arg: 2, scope: !10, file: !1, type: !21) !21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !22) !22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !23) !23 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) -!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 60, scope: !25, file: !1, type: !13) +!24 = !DILocalVariable(name: "i", line: 60, scope: !25, file: !1, type: !13) !25 = distinct !DILexicalBlock(line: 59, column: 33, file: !1, scope: !10) -!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 60, scope: !25, file: !1, type: !13) -!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 61, scope: !25, file: !1, type: !5) -!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 62, scope: !25, file: !1, type: !5) -!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "z", line: 63, scope: !25, file: !1, type: !5) -!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "F", line: 41, arg: 1, scope: !14, file: !15, type: !31) +!26 = !DILocalVariable(name: "j", line: 60, scope: !25, file: !1, type: !13) +!27 = !DILocalVariable(name: "x", line: 61, scope: !25, file: !1, type: !5) +!28 = !DILocalVariable(name: "y", line: 62, scope: !25, file: !1, type: !5) +!29 = !DILocalVariable(name: "z", line: 63, scope: !25, file: !1, type: !5) +!30 = !DILocalVariable(name: "F", line: 41, arg: 1, scope: !14, file: !15, type: !31) !31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !32) !32 = !DIDerivedType(tag: DW_TAG_typedef, name: "FV", line: 25, file: !55, scope: !2, baseType: !33) !33 = !DICompositeType(tag: DW_TAG_union_type, line: 22, size: 128, align: 128, file: !55, scope: !2, elements: !34) diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll index 27bd3b8639c4..0d457d3a7371 100644 --- a/test/CodeGen/ARM/debug-info-d16-reg.ll +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -10,7 +10,7 @@ target triple = "thumbv7-apple-darwin10" @.str = private unnamed_addr constant [11 x i8] c"%p %lf %c\0A\00", align 4 @.str1 = private unnamed_addr constant [6 x i8] c"point\00", align 4 -define i32 @inlineprinter(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize { +define i32 @inlineprinter(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize !dbg !9 { entry: tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !19, metadata !DIExpression()), !dbg !26 tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !20, metadata !DIExpression()), !dbg !26 @@ -20,7 +20,7 @@ entry: ret i32 0, !dbg !29 } -define i32 @printer(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize noinline { +define i32 @printer(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize noinline !dbg !0 { entry: tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !16, metadata !DIExpression()), !dbg !30 tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !17, metadata !DIExpression()), !dbg !30 @@ -34,7 +34,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone -define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize { +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize !dbg !10 { entry: tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !22, metadata !DIExpression()), !dbg !34 tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !23, metadata !DIExpression()), !dbg !34 @@ -59,36 +59,36 @@ declare i32 @puts(i8* nocapture) nounwind !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!48} -!0 = !DISubprogram(name: "printer", linkageName: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !46, scope: !1, type: !3, function: i32 (i8*, double, i8)* @printer, variables: !43) +!0 = distinct !DISubprogram(name: "printer", linkageName: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !46, scope: !1, type: !3, variables: !43) !1 = !DIFile(filename: "a.c", directory: "/tmp/") -!2 = !DICompileUnit(language: DW_LANG_C89, producer: "(LLVM build 00)", isOptimized: true, emissionKind: 1, file: !46, enums: !47, retainedTypes: !47, subprograms: !42, imports: null) +!2 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "(LLVM build 00)", isOptimized: true, emissionKind: 1, file: !46, enums: !47, retainedTypes: !47, subprograms: !42, imports: null) !3 = !DISubroutineType(types: !4) !4 = !{!5, !6, !7, !8} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: null) !7 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 32, encoding: DW_ATE_float) !8 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) -!9 = !DISubprogram(name: "inlineprinter", linkageName: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !46, scope: !1, type: !3, function: i32 (i8*, double, i8)* @inlineprinter, variables: !44) -!10 = !DISubprogram(name: "main", linkageName: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !46, scope: !1, type: !11, function: i32 (i32, i8**)* @main, variables: !45) +!9 = distinct !DISubprogram(name: "inlineprinter", linkageName: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !46, scope: !1, type: !3, variables: !44) +!10 = distinct !DISubprogram(name: "main", linkageName: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !46, scope: !1, type: !11, variables: !45) !11 = !DISubroutineType(types: !12) !12 = !{!5, !5, !13} !13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !14) !14 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !15) !15 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) -!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 1, scope: !0, file: !1, type: !6) -!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 2, scope: !0, file: !1, type: !7) -!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 3, scope: !0, file: !1, type: !8) -!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6) -!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7) -!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !9, file: !1, type: !8) +!16 = !DILocalVariable(name: "ptr", line: 11, arg: 1, scope: !0, file: !1, type: !6) +!17 = !DILocalVariable(name: "val", line: 11, arg: 2, scope: !0, file: !1, type: !7) +!18 = !DILocalVariable(name: "c", line: 11, arg: 3, scope: !0, file: !1, type: !8) +!19 = !DILocalVariable(name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6) +!20 = !DILocalVariable(name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7) +!21 = !DILocalVariable(name: "c", line: 4, arg: 3, scope: !9, file: !1, type: !8) -!49 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6) -!50 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7) -!51 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 2, scope: !9, file: !1, type: !8) +!49 = !DILocalVariable(name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6) +!50 = !DILocalVariable(name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7) +!51 = !DILocalVariable(name: "c", line: 4, arg: 2, scope: !9, file: !1, type: !8) -!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 17, arg: 0, scope: !10, file: !1, type: !5) -!23 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 17, arg: 0, scope: !10, file: !1, type: !13) -!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dval", line: 19, scope: !25, file: !1, type: !7) +!22 = !DILocalVariable(name: "argc", line: 17, arg: 1, scope: !10, file: !1, type: !5) +!23 = !DILocalVariable(name: "argv", line: 17, arg: 2, scope: !10, file: !1, type: !13) +!24 = !DILocalVariable(name: "dval", line: 19, scope: !25, file: !1, type: !7) !25 = distinct !DILexicalBlock(line: 18, column: 0, file: !46, scope: !10) !26 = !DILocation(line: 4, scope: !9) !27 = !DILocation(line: 6, scope: !28) diff --git a/test/CodeGen/ARM/debug-info-no-frame.ll b/test/CodeGen/ARM/debug-info-no-frame.ll index e00563cc47c4..d77a195b9528 100644 --- a/test/CodeGen/ARM/debug-info-no-frame.ll +++ b/test/CodeGen/ARM/debug-info-no-frame.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=armv7-none-linux-gnueabihf < %s -o - | FileCheck %s ; Function Attrs: nounwind -define void @need_cfi_def_cfa_offset() #0 { +define void @need_cfi_def_cfa_offset() #0 !dbg !3 { ; CHECK-LABEL: need_cfi_def_cfa_offset: ; CHECK: sub sp, sp, #4 ; CHECK: .cfi_def_cfa_offset 4 @@ -21,16 +21,16 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!7, !8} -!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !{!3}) !1 = !DIFile(filename: "file.c", directory: "/dir") !2 = !{} -!3 = !DISubprogram(name: "need_cfi_def_cfa_offset", scope: !1, file: !1, line: 1, type: !4, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @need_cfi_def_cfa_offset, variables: !2) +!3 = distinct !DISubprogram(name: "need_cfi_def_cfa_offset", scope: !1, file: !1, line: 1, type: !4, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, variables: !2) !4 = !DISubroutineType(types: !5) !5 = !{null} !6 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !7 = !{i32 2, !"Dwarf Version", i32 4} !8 = !{i32 2, !"Debug Info Version", i32 3} -!9 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Depth", scope: !3, file: !1, line: 3, type: !6) +!9 = !DILocalVariable(name: "Depth", scope: !3, file: !1, line: 3, type: !6) !10 = !DIExpression() !11 = !DILocation(line: 3, column: 9, scope: !3) !12 = !DILocation(line: 7, column: 5, scope: !3) diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll index 665818fc0b2e..1cd90d433640 100644 --- a/test/CodeGen/ARM/debug-info-qreg.ll +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -15,7 +15,7 @@ target triple = "thumbv7-apple-macosx10.6.7" declare <4 x float> @test0001(float) nounwind readnone ssp -define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp !dbg !10 { entry: br label %for.body9 @@ -38,9 +38,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!56} -!0 = !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !54, scope: !1, type: !3, function: <4 x float> (float)* @test0001, variables: !51) +!0 = distinct !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !54, scope: !1, type: !3, variables: !51) !1 = !DIFile(filename: "build2.c", directory: "/private/tmp") -!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6) @@ -48,27 +48,27 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) !8 = !{!9} !9 = !DISubrange(count: 4) -!10 = !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 59, file: !54, scope: !1, type: !11, function: i32 (i32, i8**)* @main, variables: !52) +!10 = distinct !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 59, file: !54, scope: !1, type: !11, variables: !52) !11 = !DISubroutineType(types: !12) !12 = !{!13} !13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!14 = !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 41, file: !55, scope: !15, type: !16, variables: !53) +!14 = distinct !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 41, file: !55, scope: !15, type: !16, variables: !53) !15 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp") !16 = !DISubroutineType(types: !17) !17 = !{null} -!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 3, arg: 1, scope: !0, file: !1, type: !7) -!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 59, arg: 1, scope: !10, file: !1, type: !13) -!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 59, arg: 2, scope: !10, file: !1, type: !21) +!18 = !DILocalVariable(name: "a", line: 3, arg: 1, scope: !0, file: !1, type: !7) +!19 = !DILocalVariable(name: "argc", line: 59, arg: 1, scope: !10, file: !1, type: !13) +!20 = !DILocalVariable(name: "argv", line: 59, arg: 2, scope: !10, file: !1, type: !21) !21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !22) !22 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !23) !23 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) -!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 60, scope: !25, file: !1, type: !13) +!24 = !DILocalVariable(name: "i", line: 60, scope: !25, file: !1, type: !13) !25 = distinct !DILexicalBlock(line: 59, column: 33, file: !54, scope: !10) -!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 60, scope: !25, file: !1, type: !13) -!27 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "x", line: 61, scope: !25, file: !1, type: !5) -!28 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 62, scope: !25, file: !1, type: !5) -!29 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "z", line: 63, scope: !25, file: !1, type: !5) -!30 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "F", line: 41, arg: 1, scope: !14, file: !15, type: !31) +!26 = !DILocalVariable(name: "j", line: 60, scope: !25, file: !1, type: !13) +!27 = !DILocalVariable(name: "x", line: 61, scope: !25, file: !1, type: !5) +!28 = !DILocalVariable(name: "y", line: 62, scope: !25, file: !1, type: !5) +!29 = !DILocalVariable(name: "z", line: 63, scope: !25, file: !1, type: !5) +!30 = !DILocalVariable(name: "F", line: 41, arg: 1, scope: !14, file: !15, type: !31) !31 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !32) !32 = !DIDerivedType(tag: DW_TAG_typedef, name: "FV", line: 25, file: !55, scope: !2, baseType: !33) !33 = !DICompositeType(tag: DW_TAG_union_type, line: 22, size: 128, align: 128, file: !55, scope: !2, elements: !34) diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll index ec080f20db9c..654aa4545ca4 100644 --- a/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -12,7 +12,7 @@ target triple = "thumbv7-apple-macosx10.6.7" @.str = private unnamed_addr constant [11 x i8] c"%p %lf %c\0A\00" @.str1 = private unnamed_addr constant [6 x i8] c"point\00" -define i32 @inlineprinter(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize ssp { +define i32 @inlineprinter(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize ssp !dbg !0 { entry: tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !8, metadata !DIExpression()), !dbg !24 tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !10, metadata !DIExpression()), !dbg !25 @@ -25,7 +25,7 @@ entry: declare i32 @printf(i8* nocapture, ...) nounwind optsize -define i32 @printer(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize noinline ssp { +define i32 @printer(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize noinline ssp !dbg !6 { entry: tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !14, metadata !DIExpression()), !dbg !30 tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !15, metadata !DIExpression()), !dbg !31 @@ -36,7 +36,7 @@ entry: ret i32 0, !dbg !35 } -define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize ssp { +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize ssp !dbg !7 { entry: tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !17, metadata !DIExpression()), !dbg !36 tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !18, metadata !DIExpression()), !dbg !37 @@ -65,34 +65,34 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!53} -!0 = !DISubprogram(name: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !51, scope: !1, type: !3, function: i32 (i8*, float, i8)* @inlineprinter, variables: !48) +!0 = distinct !DISubprogram(name: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !51, scope: !1, type: !3, variables: !48) !1 = !DIFile(filename: "a.c", directory: "/private/tmp") -!2 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !51, enums: !52, retainedTypes: !52, subprograms: !47, imports: null) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !51, enums: !52, retainedTypes: !52, subprograms: !47, imports: null) !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!6 = !DISubprogram(name: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !51, scope: !1, type: !3, function: i32 (i8*, float, i8)* @printer, variables: !49) -!7 = !DISubprogram(name: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !51, scope: !1, type: !3, function: i32 (i32, i8**)* @main, variables: !50) -!8 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9) +!6 = distinct !DISubprogram(name: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !51, scope: !1, type: !3, variables: !49) +!7 = distinct !DISubprogram(name: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !51, scope: !1, type: !3, variables: !50) +!8 = !DILocalVariable(name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9) !9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: null) -!10 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11) +!10 = !DILocalVariable(name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11) !11 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) -!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13) +!12 = !DILocalVariable(name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13) !13 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) -!58 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9) -!60 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11) -!62 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13) +!58 = !DILocalVariable(name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9) +!60 = !DILocalVariable(name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11) +!62 = !DILocalVariable(name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13) -!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 1, scope: !6, file: !1, type: !9) -!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 2, scope: !6, file: !1, type: !11) -!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 3, scope: !6, file: !1, type: !13) -!17 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 17, arg: 1, scope: !7, file: !1, type: !5) -!18 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 17, arg: 2, scope: !7, file: !1, type: !19) +!14 = !DILocalVariable(name: "ptr", line: 11, arg: 1, scope: !6, file: !1, type: !9) +!15 = !DILocalVariable(name: "val", line: 11, arg: 2, scope: !6, file: !1, type: !11) +!16 = !DILocalVariable(name: "c", line: 11, arg: 3, scope: !6, file: !1, type: !13) +!17 = !DILocalVariable(name: "argc", line: 17, arg: 1, scope: !7, file: !1, type: !5) +!18 = !DILocalVariable(name: "argv", line: 17, arg: 2, scope: !7, file: !1, type: !19) !19 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !20) !20 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: !21) !21 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) -!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dval", line: 19, scope: !23, file: !1, type: !11) +!22 = !DILocalVariable(name: "dval", line: 19, scope: !23, file: !1, type: !11) !23 = distinct !DILexicalBlock(line: 18, column: 1, file: !51, scope: !7) !24 = !DILocation(line: 4, column: 22, scope: !0) !25 = !DILocation(line: 4, column: 33, scope: !0) diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll index f22559efad4d..eadf1b48156b 100644 --- a/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -12,7 +12,7 @@ target triple = "thumbv7-apple-macosx10.6.7" ; CHECK-NEXT: Ending address offset: ; CHECK-NEXT: Location description: 90 {{.. .. .. .. $}} -define void @_Z3foov() optsize ssp { +define void @_Z3foov() optsize ssp !dbg !1 { entry: %call = tail call float @_Z3barv() optsize, !dbg !11 tail call void @llvm.dbg.value(metadata float %call, i64 0, metadata !5, metadata !DIExpression()), !dbg !11 @@ -43,15 +43,15 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!20} -!0 = !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 130845)", isOptimized: true, emissionKind: 1, file: !18, enums: !19, retainedTypes: !19, subprograms: !16, imports: null) -!1 = !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !18, scope: !2, type: !3, function: void ()* @_Z3foov, variables: !17) +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 130845)", isOptimized: true, emissionKind: 1, file: !18, enums: !19, retainedTypes: !19, subprograms: !16, imports: null) +!1 = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !18, scope: !2, type: !3, variables: !17) !2 = !DIFile(filename: "k.cc", directory: "/private/tmp") !3 = !DISubroutineType(types: !4) !4 = !{null} -!5 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 6, scope: !6, file: !2, type: !7) +!5 = !DILocalVariable(name: "k", line: 6, scope: !6, file: !2, type: !7) !6 = distinct !DILexicalBlock(line: 5, column: 12, file: !18, scope: !1) !7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) -!8 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "y", line: 8, scope: !9, file: !2, type: !7) +!8 = !DILocalVariable(name: "y", line: 8, scope: !9, file: !2, type: !7) !9 = distinct !DILexicalBlock(line: 7, column: 25, file: !18, scope: !10) !10 = distinct !DILexicalBlock(line: 7, column: 3, file: !18, scope: !6) !11 = !DILocation(line: 6, column: 18, scope: !6) diff --git a/test/CodeGen/ARM/debug-segmented-stacks.ll b/test/CodeGen/ARM/debug-segmented-stacks.ll index 47d366e49ded..bd0abedc4133 100644 --- a/test/CodeGen/ARM/debug-segmented-stacks.ll +++ b/test/CodeGen/ARM/debug-segmented-stacks.ll @@ -5,7 +5,7 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} -define void @test_basic() #0 { +define void @test_basic() #0 !dbg !4 { %mem = alloca i32, i32 10 call void @dummy_use (i32* %mem, i32 10) ret void @@ -39,11 +39,11 @@ define void @test_basic() #0 { ; ARM-linux .cfi_same_value r5 } -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) !1 = !DIFile(filename: "var.c", directory: "/tmp") !2 = !{} !3 = !{!4} -!4 = !DISubprogram(name: "test_basic", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, function: void ()* @test_basic, variables: !2) +!4 = distinct !DISubprogram(name: "test_basic", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "var.c", directory: "/tmp") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} @@ -51,9 +51,9 @@ define void @test_basic() #0 { !9 = !{i32 2, !"Dwarf Version", i32 4} !10 = !{i32 1, !"Debug Info Version", i32 3} !11 = !{!"clang version 3.5 "} -!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "count", line: 5, arg: 1, scope: !4, file: !5, type: !8) +!12 = !DILocalVariable(name: "count", line: 5, arg: 1, scope: !4, file: !5, type: !8) !13 = !DILocation(line: 5, scope: !4) -!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vl", line: 6, scope: !4, file: !5, type: !15) +!14 = !DILocalVariable(name: "vl", line: 6, scope: !4, file: !5, type: !15) !15 = !DIDerivedType(tag: DW_TAG_typedef, name: "va_list", line: 30, file: !16, baseType: !17) !16 = !DIFile(filename: "/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", directory: "/tmp") !17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__builtin_va_list", line: 6, file: !1, baseType: !18) @@ -63,9 +63,9 @@ define void @test_basic() #0 { !21 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: null) !22 = !DILocation(line: 6, scope: !4) !23 = !DILocation(line: 7, scope: !4) -!24 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "test_basic", line: 8, scope: !4, file: !5, type: !8) +!24 = !DILocalVariable(name: "test_basic", line: 8, scope: !4, file: !5, type: !8) !25 = !DILocation(line: 8, scope: !4) -!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 9, scope: !27, file: !5, type: !8) +!26 = !DILocalVariable(name: "i", line: 9, scope: !27, file: !5, type: !8) !27 = distinct !DILexicalBlock(line: 9, column: 0, file: !1, scope: !4) !28 = !DILocation(line: 9, scope: !27) !29 = !DILocation(line: 10, scope: !30) diff --git a/test/CodeGen/ARM/debugtrap.ll b/test/CodeGen/ARM/debugtrap.ll new file mode 100644 index 000000000000..9ce73939ce56 --- /dev/null +++ b/test/CodeGen/ARM/debugtrap.ll @@ -0,0 +1,17 @@ +; This test ensures the @llvm.debugtrap() call is not removed when generating
+; the 'pop' instruction to restore the callee saved registers on ARM.
+
+; RUN: llc < %s -mtriple=armv7 -O0 -filetype=asm | FileCheck %s
+
+declare void @llvm.debugtrap() nounwind
+declare void @foo() nounwind
+
+define void @test() nounwind {
+entry:
+ ; CHECK: bl foo
+ ; CHECK-NEXT: pop
+ ; CHECK-NEXT: trap
+ call void @foo()
+ call void @llvm.debugtrap()
+ ret void
+}
diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll index 7b298fee42a5..997f50760f3a 100644 --- a/test/CodeGen/ARM/div.ll +++ b/test/CodeGen/ARM/div.ll @@ -1,52 +1,97 @@ -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-SWDIV -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | FileCheck %s -check-prefix=CHECK-SWDIV -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | FileCheck %s -check-prefix=CHECK-SWDIV -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI define i32 @f1(i32 %a, i32 %b) { entry: -; CHECK-SWDIV: f1 +; CHECK-LABEL: f1 ; CHECK-SWDIV: __divsi3 -; CHECK-HWDIV: f1 ; CHECK-HWDIV: sdiv + +; CHECK-EABI: __aeabi_idiv %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f2(i32 %a, i32 %b) { entry: -; CHECK-SWDIV: f2 +; CHECK-LABEL: f2 ; CHECK-SWDIV: __udivsi3 -; CHECK-HWDIV: f2 ; CHECK-HWDIV: udiv + +; CHECK-EABI: __aeabi_uidiv %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f3(i32 %a, i32 %b) { entry: -; CHECK-SWDIV: f3 +; CHECK-LABEL: f3 ; CHECK-SWDIV: __modsi3 -; CHECK-HWDIV: f3 ; CHECK-HWDIV: sdiv ; CHECK-HWDIV: mls + +; EABI MODE = Remainder in R1, quotient in R0 +; CHECK-EABI: __aeabi_idivmod +; CHECK-EABI-NEXT: mov r0, r1 %tmp1 = srem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } define i32 @f4(i32 %a, i32 %b) { entry: -; CHECK-SWDIV: f4 +; CHECK-LABEL: f4 ; CHECK-SWDIV: __umodsi3 -; CHECK-HWDIV: f4 ; CHECK-HWDIV: udiv ; CHECK-HWDIV: mls + +; EABI MODE = Remainder in R1, quotient in R0 +; CHECK-EABI: __aeabi_uidivmod +; CHECK-EABI-NEXT: mov r0, r1 %tmp1 = urem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } + +define i64 @f5(i64 %a, i64 %b) { +entry: +; CHECK-LABEL: f5 +; CHECK-SWDIV: __moddi3 + +; CHECK-HWDIV: __moddi3 + +; EABI MODE = Remainder in R2-R3, quotient in R0-R1 +; CHECK-EABI: __aeabi_ldivmod +; CHECK-EABI-NEXT: mov r0, r2 +; CHECK-EABI-NEXT: mov r1, r3 + %tmp1 = srem i64 %a, %b ; <i64> [#uses=1] + ret i64 %tmp1 +} + +define i64 @f6(i64 %a, i64 %b) { +entry: +; CHECK-LABEL: f6 +; CHECK-SWDIV: __umoddi3 + +; CHECK-HWDIV: __umoddi3 + +; EABI MODE = Remainder in R2-R3, quotient in R0-R1 +; CHECK-EABI: __aeabi_uldivmod +; CHECK-EABI-NEXT: mov r0, r2 +; CHECK-EABI-NEXT: mov r1, r3 + %tmp1 = urem i64 %a, %b ; <i64> [#uses=1] + ret i64 %tmp1 +} diff --git a/test/CodeGen/ARM/divmod-eabi.ll b/test/CodeGen/ARM/divmod-eabi.ll index 7f72048d391e..4178af397e66 100644 --- a/test/CodeGen/ARM/divmod-eabi.ll +++ b/test/CodeGen/ARM/divmod-eabi.ll @@ -1,5 +1,7 @@ ; RUN: llc -mtriple armv7-none-eabi %s -o - | FileCheck %s --check-prefix=EABI ; RUN: llc -mtriple armv7-none-eabihf %s -o - | FileCheck %s --check-prefix=EABI +; Both "none-eabi" and "androideabi" must lower SREM/UREM to __aeabi_{u,i}divmod +; RUN: llc -mtriple armv7-linux-androideabi %s -o - | FileCheck %s --check-prefix=EABI ; RUN: llc -mtriple armv7-linux-gnueabi %s -o - | FileCheck %s --check-prefix=GNU ; RUN: llc -mtriple armv7-apple-darwin %s -o - | FileCheck %s --check-prefix=DARWIN ; FIXME: long-term, we will use "-apple-macho" and won't need this exception: @@ -187,7 +189,7 @@ define i32 @g4(i32 %a, i32 %b) { ; DARWIN-LABEL: g4: entry: %div = sdiv i32 %a, %b -; EABI: __aeabi_idivmod +; EABI: __aeabi_idiv{{$}} ; EABI: mov [[div:r[0-9]+]], r0 ; GNU: __aeabi_idiv ; GNU: mov [[sum:r[0-9]+]], r0 diff --git a/test/CodeGen/ARM/eh-resume-darwin.ll b/test/CodeGen/ARM/eh-resume-darwin.ll index 0cd49775cfb4..d3a8481275f3 100644 --- a/test/CodeGen/ARM/eh-resume-darwin.ll +++ b/test/CodeGen/ARM/eh-resume-darwin.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=arm | FileCheck %s -target triple = "armv6-apple-macosx10.6" +; RUN: llc < %s -mtriple=armv7-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=IOS +; RUN: llc < %s -mtriple=armv7k-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=IOS +; RUN: llc < %s -mtriple=armv7k-apple-watchos -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=WATCHOS declare void @func() @@ -19,4 +20,5 @@ lpad: resume { i8*, i32 } %exn } -; CHECK: __Unwind_SjLj_Resume +; IOS: __Unwind_SjLj_Resume +; WATCHOS: __Unwind_Resume diff --git a/test/CodeGen/ARM/emutls.ll b/test/CodeGen/ARM/emutls.ll new file mode 100644 index 000000000000..7ba50dd249bb --- /dev/null +++ b/test/CodeGen/ARM/emutls.ll @@ -0,0 +1,258 @@ +; RUN: llc -emulated-tls -mtriple=arm-linux-android \ +; RUN: -relocation-model=pic < %s | FileCheck -check-prefix=ARM32 %s + +; Copied from X86/emutls.ll + +; Use my_emutls_get_address like __emutls_get_address. +@my_emutls_v_xyz = external global i8*, align 4 +declare i8* @my_emutls_get_address(i8*) + +define i32 @my_get_xyz() { +; ARM32-LABEL: my_get_xyz: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl my_emutls_get_address(PLT) +; ARM32-NEXT: ldr r0, [r0] + +entry: + %call = call i8* @my_emutls_get_address(i8* bitcast (i8** @my_emutls_v_xyz to i8*)) + %0 = bitcast i8* %call to i32* + %1 = load i32, i32* %0, align 4 + ret i32 %1 +} + +@i1 = thread_local global i32 15 +@i2 = external thread_local global i32 +@i3 = internal thread_local global i32 15 +@i4 = hidden thread_local global i32 15 +@i5 = external hidden thread_local global i32 +@s1 = thread_local global i16 15 +@b1 = thread_local global i8 0 + +define i32 @f1() { +; ARM32-LABEL: f1: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldr r0, [r0] + +entry: + %tmp1 = load i32, i32* @i1 + ret i32 %tmp1 +} + +define i32* @f2() { +; ARM32-LABEL: f2: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: pop + +entry: + ret i32* @i1 +} + +define i32 @f3() nounwind { +; ARM32-LABEL: f3: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldr r0, [r0] + +entry: + %tmp1 = load i32, i32* @i2 + ret i32 %tmp1 +} + +define i32* @f4() { +; ARM32-LABEL: f4: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: pop + +entry: + ret i32* @i2 +} + +define i32 @f5() nounwind { +; ARM32-LABEL: f5: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldr r0, [r0] + +entry: + %tmp1 = load i32, i32* @i3 + ret i32 %tmp1 +} + +define i32* @f6() { +; ARM32-LABEL: f6: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: pop + +entry: + ret i32* @i3 +} + +define i32 @f7() { +; ARM32-LABEL: f7: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldr r0, [r0] + +entry: + %tmp1 = load i32, i32* @i4 + ret i32 %tmp1 +} + +define i32* @f8() { +; ARM32-LABEL: f8: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: pop + +entry: + ret i32* @i4 +} + +define i32 @f9() { +; ARM32-LABEL: f9: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldr r0, [r0] + +entry: + %tmp1 = load i32, i32* @i5 + ret i32 %tmp1 +} + +define i32* @f10() { +; ARM32-LABEL: f10: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: pop + +entry: + ret i32* @i5 +} + +define i16 @f11() { +; ARM32-LABEL: f11: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldrh r0, [r0] + +entry: + %tmp1 = load i16, i16* @s1 + ret i16 %tmp1 +} + +define i32 @f12() { +; ARM32-LABEL: f12: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldrsh r0, [r0] + +entry: + %tmp1 = load i16, i16* @s1 + %tmp2 = sext i16 %tmp1 to i32 + ret i32 %tmp2 +} + +define i8 @f13() { +; ARM32-LABEL: f13: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldrb r0, [r0] +; ARM32-NEXT: pop + +entry: + %tmp1 = load i8, i8* @b1 + ret i8 %tmp1 +} + +define i32 @f14() { +; ARM32-LABEL: f14: +; ARM32: ldr r0, +; ARM32: ldr r0, [pc, r0] +; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: ldrsb r0, [r0] +; ARM32-NEXT: pop + +entry: + %tmp1 = load i8, i8* @b1 + %tmp2 = sext i8 %tmp1 to i32 + ret i32 %tmp2 +} + +;;;;;;;;;;;;;; 32-bit __emutls_v. and __emutls_t. + +; ARM32 .section .data.rel.local, +; ARM32-LABEL: __emutls_v.i1: +; ARM32-NEXT: .long 4 +; ARM32-NEXT: .long 4 +; ARM32-NEXT: .long 0 +; ARM32-NEXT: .long __emutls_t.i1 + +; ARM32 .section .rodata, +; ARM32-LABEL: __emutls_t.i1: +; ARM32-NEXT: .long 15 + +; ARM32-NOT: __emutls_v.i2 + +; ARM32 .section .data.rel.local, +; ARM32-LABEL: __emutls_v.i3: +; ARM32-NEXT: .long 4 +; ARM32-NEXT: .long 4 +; ARM32-NEXT: .long 0 +; ARM32-NEXT: .long __emutls_t.i3 + +; ARM32 .section .rodata, +; ARM32-LABEL: __emutls_t.i3: +; ARM32-NEXT: .long 15 + +; ARM32 .section .data.rel.local, +; ARM32-LABEL: __emutls_v.i4: +; ARM32-NEXT: .long 4 +; ARM32-NEXT: .long 4 +; ARM32-NEXT: .long 0 +; ARM32-NEXT: .long __emutls_t.i4 + +; ARM32 .section .rodata, +; ARM32-LABEL: __emutls_t.i4: +; ARM32-NEXT: .long 15 + +; ARM32-NOT: __emutls_v.i5: +; ARM32 .hidden __emutls_v.i5 +; ARM32-NOT: __emutls_v.i5: + +; ARM32 .section .data.rel.local, +; ARM32-LABEL: __emutls_v.s1: +; ARM32-NEXT: .long 2 +; ARM32-NEXT: .long 2 +; ARM32-NEXT: .long 0 +; ARM32-NEXT: .long __emutls_t.s1 + +; ARM32 .section .rodata, +; ARM32-LABEL: __emutls_t.s1: +; ARM32-NEXT: .short 15 + +; ARM32 .section .data.rel.local, +; ARM32-LABEL: __emutls_v.b1: +; ARM32-NEXT: .long 1 +; ARM32-NEXT: .long 1 +; ARM32-NEXT: .long 0 +; ARM32-NEXT: .long 0 + +; ARM32-NOT: __emutls_t.b1 diff --git a/test/CodeGen/ARM/emutls1.ll b/test/CodeGen/ARM/emutls1.ll new file mode 100644 index 000000000000..d4ba7eced66c --- /dev/null +++ b/test/CodeGen/ARM/emutls1.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -emulated-tls -march=arm -mtriple=arm-linux-androideabi \ +; RUN: | FileCheck %s +; RUN: llc < %s -emulated-tls -march=arm -mtriple=arm-linux-androideabi \ +; RUN: -relocation-model=pic | FileCheck %s --check-prefix=PIC + +; Compared with tls1.ll, emulated mode should not use __aeabi_read_tp or __tls_get_addr. + +; CHECK-NOT: _aeabi_read_tp +; CHECK-NOT: _tls_get_addr +; CHECK: __emutls_get_addr +; CHECK-NOT: __aeabi_read_tp +; CHECK-NOT: _tls_get_addr + +; PIC-NOT: _aeabi_read_tp +; PIC-NOT: _tls_get_addr +; PIC: __emutls_get_addr +; PIC-NOT: _aeabi_read_tp +; PIC-NOT: _tls_get_addr + +@i = thread_local global i32 15 ; <i32*> [#uses=2] + +define i32 @f() { +entry: + %tmp1 = load i32, i32* @i ; <i32> [#uses=1] + ret i32 %tmp1 +} + +define i32* @g() { +entry: + ret i32* @i +} diff --git a/test/CodeGen/ARM/emutls_generic.ll b/test/CodeGen/ARM/emutls_generic.ll new file mode 100644 index 000000000000..0fada88fb5d9 --- /dev/null +++ b/test/CodeGen/ARM/emutls_generic.ll @@ -0,0 +1,61 @@ +; RUN: llc < %s -emulated-tls -mtriple=arm-linux-android -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=ARM_32 %s +; RUN: llc < %s -emulated-tls -mtriple=arm-linux-androidabi -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=ARM_32 %s +; RUN: llc < %s -emulated-tls -mtriple=arm-linux-androidabi -relocation-model=pic -O3 \ +; RUN: | FileCheck -check-prefix=ARM_32 %s +; RUN: llc < %s -emulated-tls -mtriple=arm-linux-androidabi -O3 \ +; RUN: | FileCheck -check-prefix=ARM_32 %s + +; Make sure that TLS symbols are emitted in expected order. + +@external_x = external thread_local global i32, align 8 +@external_y = thread_local global i8 7, align 2 +@internal_y = internal thread_local global i64 9, align 16 + +define i32* @get_external_x() { +entry: + ret i32* @external_x +} + +define i8* @get_external_y() { +entry: + ret i8* @external_y +} + +define i64* @get_internal_y() { +entry: + ret i64* @internal_y +} + +; ARM_32-LABEL: get_external_x: +; ARM_32: bl __emutls_get_address +; ARM_32: .long __emutls_v.external_x +; ARM_32-LABEL: get_external_y: +; ARM_32: bl __emutls_get_address +; ARM_32: .long __emutls_v.external_y +; ARM_32-LABEL: get_internal_y: +; ARM_32: bl __emutls_get_address +; ARM_32: .long __emutls_v.internal_y +; ARM_32-NOT: __emutls_t.external_x +; ARM_32-NOT: __emutls_v.external_x: +; ARM_32: .data +; ARM_32: .align 2 +; ARM_32-LABEL: __emutls_v.external_y: +; ARM_32-NEXT: .long 1 +; ARM_32-NEXT: .long 2 +; ARM_32-NEXT: .long 0 +; ARM_32-NEXT: .long __emutls_t.external_y +; ARM_32: .section .rodata, +; ARM_32-LABEL: __emutls_t.external_y: +; ARM_32-NEXT: .byte 7 +; ARM_32: .data +; ARM_32: .align 2 +; ARM_32-LABEL: __emutls_v.internal_y: +; ARM_32-NEXT: .long 8 +; ARM_32-NEXT: .long 16 +; ARM_32-NEXT: .long 0 +; ARM_32-NEXT: .long __emutls_t.internal_y +; ARM_32-LABEL: __emutls_t.internal_y: +; ARM_32-NEXT: .long 9 +; ARM_32-NEXT: .long 0 diff --git a/test/CodeGen/ARM/fast-isel-align.ll b/test/CodeGen/ARM/fast-isel-align.ll index 39085db95316..701884e926a8 100644 --- a/test/CodeGen/ARM/fast-isel-align.ll +++ b/test/CodeGen/ARM/fast-isel-align.ll @@ -1,22 +1,22 @@ ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN +; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN +; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN -; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN +; RUN: llc < %s -O0 -mattr=+strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; Check unaligned stores %struct.anon = type <{ float }> diff --git a/test/CodeGen/ARM/fast-isel-ext.ll b/test/CodeGen/ARM/fast-isel-ext.ll index b792f7a90738..440aa426067c 100644 --- a/test/CodeGen/ARM/fast-isel-ext.ll +++ b/test/CodeGen/ARM/fast-isel-ext.ll @@ -1,9 +1,5 @@ ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7 -; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 ; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports @@ -19,8 +15,6 @@ define i8 @zext_1_8(i1 %a) nounwind ssp { ; v7-LABEL: zext_1_8: ; v7: and r0, r0, #1 -; prev6-LABEL: zext_1_8: -; prev6: and r0, r0, #1 %r = zext i1 %a to i8 ret i8 %r } @@ -28,8 +22,6 @@ define i8 @zext_1_8(i1 %a) nounwind ssp { define i16 @zext_1_16(i1 %a) nounwind ssp { ; v7-LABEL: zext_1_16: ; v7: and r0, r0, #1 -; prev6-LABEL: zext_1_16: -; prev6: and r0, r0, #1 %r = zext i1 %a to i16 ret i16 %r } @@ -37,8 +29,6 @@ define i16 @zext_1_16(i1 %a) nounwind ssp { define i32 @zext_1_32(i1 %a) nounwind ssp { ; v7-LABEL: zext_1_32: ; v7: and r0, r0, #1 -; prev6-LABEL: zext_1_32: -; prev6: and r0, r0, #1 %r = zext i1 %a to i32 ret i32 %r } @@ -46,8 +36,6 @@ define i32 @zext_1_32(i1 %a) nounwind ssp { define i16 @zext_8_16(i8 %a) nounwind ssp { ; v7-LABEL: zext_8_16: ; v7: and r0, r0, #255 -; prev6-LABEL: zext_8_16: -; prev6: and r0, r0, #255 %r = zext i8 %a to i16 ret i16 %r } @@ -55,8 +43,6 @@ define i16 @zext_8_16(i8 %a) nounwind ssp { define i32 @zext_8_32(i8 %a) nounwind ssp { ; v7-LABEL: zext_8_32: ; v7: and r0, r0, #255 -; prev6-LABEL: zext_8_32: -; prev6: and r0, r0, #255 %r = zext i8 %a to i32 ret i32 %r } @@ -64,9 +50,6 @@ define i32 @zext_8_32(i8 %a) nounwind ssp { define i32 @zext_16_32(i16 %a) nounwind ssp { ; v7-LABEL: zext_16_32: ; v7: uxth r0, r0 -; prev6-LABEL: zext_16_32: -; prev6: lsl{{s?}} r0, r0, #16 -; prev6: lsr{{s?}} r0, r0, #16 %r = zext i16 %a to i32 ret i32 %r } @@ -77,9 +60,6 @@ define i8 @sext_1_8(i1 %a) nounwind ssp { ; v7-LABEL: sext_1_8: ; v7: lsl{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31 -; prev6-LABEL: sext_1_8: -; prev6: lsl{{s?}} r0, r0, #31 -; prev6: asr{{s?}} r0, r0, #31 %r = sext i1 %a to i8 ret i8 %r } @@ -88,9 +68,6 @@ define i16 @sext_1_16(i1 %a) nounwind ssp { ; v7-LABEL: sext_1_16: ; v7: lsl{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31 -; prev6-LABEL: sext_1_16: -; prev6: lsl{{s?}} r0, r0, #31 -; prev6: asr{{s?}} r0, r0, #31 %r = sext i1 %a to i16 ret i16 %r } @@ -99,9 +76,6 @@ define i32 @sext_1_32(i1 %a) nounwind ssp { ; v7-LABEL: sext_1_32: ; v7: lsl{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31 -; prev6-LABEL: sext_1_32: -; prev6: lsl{{s?}} r0, r0, #31 -; prev6: asr{{s?}} r0, r0, #31 %r = sext i1 %a to i32 ret i32 %r } @@ -109,9 +83,6 @@ define i32 @sext_1_32(i1 %a) nounwind ssp { define i16 @sext_8_16(i8 %a) nounwind ssp { ; v7-LABEL: sext_8_16: ; v7: sxtb r0, r0 -; prev6-LABEL: sext_8_16: -; prev6: lsl{{s?}} r0, r0, #24 -; prev6: asr{{s?}} r0, r0, #24 %r = sext i8 %a to i16 ret i16 %r } @@ -119,9 +90,6 @@ define i16 @sext_8_16(i8 %a) nounwind ssp { define i32 @sext_8_32(i8 %a) nounwind ssp { ; v7-LABEL: sext_8_32: ; v7: sxtb r0, r0 -; prev6-LABEL: sext_8_32: -; prev6: lsl{{s?}} r0, r0, #24 -; prev6: asr{{s?}} r0, r0, #24 %r = sext i8 %a to i32 ret i32 %r } @@ -129,9 +97,6 @@ define i32 @sext_8_32(i8 %a) nounwind ssp { define i32 @sext_16_32(i16 %a) nounwind ssp { ; v7-LABEL: sext_16_32: ; v7: sxth r0, r0 -; prev6-LABEL: sext_16_32: -; prev6: lsl{{s?}} r0, r0, #16 -; prev6: asr{{s?}} r0, r0, #16 %r = sext i16 %a to i32 ret i32 %r } diff --git a/test/CodeGen/ARM/fast-isel-mvn.ll b/test/CodeGen/ARM/fast-isel-mvn.ll index 89b7c05158cd..34bb7225854a 100644 --- a/test/CodeGen/ARM/fast-isel-mvn.ll +++ b/test/CodeGen/ARM/fast-isel-mvn.ll @@ -1,8 +1,8 @@ -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB -; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=MOVT +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mattr=+no-movt -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mattr=+no-movt -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mattr=+no-movt -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios < %s | FileCheck %s --check-prefix=MOVT ; rdar://10412592 define void @t1() nounwind { diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll index 70e15daaca62..4cee5a7eba90 100644 --- a/test/CodeGen/ARM/fast-isel-pic.ll +++ b/test/CodeGen/ARM/fast-isel-pic.ll @@ -1,8 +1,7 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7 -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -arm-force-fast-isel -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -arm-force-fast-isel -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF @g = global i32 0, align 4 @@ -14,8 +13,8 @@ entry: ; THUMB: add [[reg0]], pc ; THUMB-ELF: LoadGV ; THUMB-ELF: ldr r[[reg0:[0-9]+]], -; THUMB-ELF: ldr r[[reg1:[0-9]+]], -; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]] +; THUMB-ELF: add r[[reg0]], pc +; THUMB-ELF: ldr r[[reg0]], [r[[reg0]]] ; ARM: LoadGV ; ARM: ldr [[reg1:r[0-9]+]], ; ARM: add [[reg1]], pc, [[reg1]] @@ -26,9 +25,8 @@ entry: ; ARMv7-ELF: LoadGV ; ARMv7-ELF: ldr r[[reg2:[0-9]+]], ; ARMv7-ELF: .LPC -; ARMv7-ELF-NEXT: add r[[reg2]], pc -; ARMv7-ELF: ldr r[[reg3:[0-9]+]], -; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]] +; ARMv7-ELF-NEXT: ldr r[[reg2]], [pc, r[[reg2]]] +; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]]] %tmp = load i32, i32* @g ret i32 %tmp } @@ -44,8 +42,8 @@ entry: ; THUMB: ldr r[[reg3]], [r[[reg3]]] ; THUMB-ELF: LoadIndirectSymbol ; THUMB-ELF: ldr r[[reg3:[0-9]+]], -; THUMB-ELF: ldr r[[reg4:[0-9]+]], -; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]] +; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]] +; THUMB-ELF: ldr r0, [r[[reg4]]] ; ARM: LoadIndirectSymbol ; ARM: ldr [[reg4:r[0-9]+]], ; ARM: ldr [[reg4]], [pc, [[reg4]]] @@ -57,9 +55,8 @@ entry: ; ARMv7-ELF: LoadIndirectSymbol ; ARMv7-ELF: ldr r[[reg5:[0-9]+]], ; ARMv7-ELF: .LPC -; ARMv7-ELF-NEXT: add r[[reg5]], pc -; ARMv7-ELF: ldr r[[reg6:[0-9]+]], -; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]] +; ARMv7-ELF: ldr r[[reg6:[0-9]+]], [pc, r[[reg5]]] +; ARMv7-ELF: ldr r0, [r[[reg5]]] %tmp = load i32, i32* @i ret i32 %tmp } diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll index 1fd9bd9e47a3..8944a40f311f 100644 --- a/test/CodeGen/ARM/fold-stack-adjust.ll +++ b/test/CodeGen/ARM/fold-stack-adjust.ll @@ -1,4 +1,6 @@ -; RUN: llc -mtriple=thumbv7-apple-none-macho < %s | FileCheck %s +; Disable shrink-wrapping on the first test otherwise we wouldn't +; exerce the path for PR18136. +; RUN: llc -mtriple=thumbv7-apple-none-macho < %s -enable-shrink-wrap=false | FileCheck %s ; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1 ; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS ; RUN: llc -mtriple=thumbv7--linux-gnueabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX @@ -60,20 +62,19 @@ define void @check_vfp_fold() minsize { ; CHECK: vpush {d6, d7, d8, d9} ; CHECK-NOT: sub sp, ; ... -; CHECK: vldmia r[[GLOBREG]], {d8, d9} -; ... ; CHECK-NOT: add sp, ; CHECK: vpop {d6, d7, d8, d9} -; CHECKL pop {r[[GLOBREG]], pc} +; CHECK: pop {r[[GLOBREG]], pc} ; iOS uses aligned NEON stores here, which is convenient since we ; want to make sure that works too. ; CHECK-IOS-LABEL: check_vfp_fold: -; CHECK-IOS: push {r0, r1, r2, r3, r4, r7, lr} +; CHECK-IOS: push {r4, r7, lr} ; CHECK-IOS: sub.w r4, sp, #16 ; CHECK-IOS: bfc r4, #0, #4 ; CHECK-IOS: mov sp, r4 ; CHECK-IOS: vst1.64 {d8, d9}, [r4:128] +; CHECK-IOS: sub sp, #16 ; ... ; CHECK-IOS: add r4, sp, #16 ; CHECK-IOS: vld1.64 {d8, d9}, [r4:128] @@ -82,9 +83,8 @@ define void @check_vfp_fold() minsize { %var = alloca i8, i32 16 - %tmp = load %bigVec, %bigVec* @var + call void asm "", "r,~{d8},~{d9}"(i8* %var) call void @bar(i8* %var) - store %bigVec %tmp, %bigVec* @var ret void } @@ -170,9 +170,9 @@ define void @test_varsize(...) minsize { ; CHECK-T1: push {r5, r6, r7, lr} ; ... ; CHECK-T1: pop {r2, r3, r7} -; CHECK-T1: pop {r3} +; CHECK-T1: pop {[[POP_REG:r[0-3]]]} ; CHECK-T1: add sp, #16 -; CHECK-T1: bx r3 +; CHECK-T1: bx [[POP_REG]] ; CHECK-LABEL: test_varsize: ; CHECK: sub sp, #16 diff --git a/test/CodeGen/ARM/fp16-args.ll b/test/CodeGen/ARM/fp16-args.ll new file mode 100644 index 000000000000..31a20f85483b --- /dev/null +++ b/test/CodeGen/ARM/fp16-args.ll @@ -0,0 +1,40 @@ +; RUN: llc -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT +; RUN: llc -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv7a--none-eabi" + +define float @foo(float %a.coerce, float %b.coerce) { +entry: + %0 = bitcast float %a.coerce to i32 + %tmp.0.extract.trunc = trunc i32 %0 to i16 + %1 = bitcast i16 %tmp.0.extract.trunc to half + %2 = bitcast float %b.coerce to i32 + %tmp1.0.extract.trunc = trunc i32 %2 to i16 + %3 = bitcast i16 %tmp1.0.extract.trunc to half + %4 = fadd half %1, %3 + %5 = bitcast half %4 to i16 + %tmp5.0.insert.ext = zext i16 %5 to i32 + %6 = bitcast i32 %tmp5.0.insert.ext to float + ret float %6 +; CHECK: foo: + +; SOFT: vmov {{s[0-9]+}}, r1 +; SOFT: vmov {{s[0-9]+}}, r0 +; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}} +; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}} +; SOFT: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; SOFT: vcvtb.f16.f32 {{s[0-9]+}}, {{s[0-9]+}} +; SOFT: vmov r0, {{s[0-9]+}} + +; HARD-NOT: vmov +; HARD-NOT: uxth +; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s1 +; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s0 +; HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; HARD: vcvtb.f16.f32 s0, {{s[0-9]+}} +; HARD-NOT: vmov +; HARD-NOT: uxth + +; CHECK: bx lr +} diff --git a/test/CodeGen/ARM/fp16-promote.ll b/test/CodeGen/ARM/fp16-promote.ll index e691c2bb8a97..2a2eb8d2b6ba 100644 --- a/test/CodeGen/ARM/fp16-promote.ll +++ b/test/CodeGen/ARM/fp16-promote.ll @@ -1,19 +1,19 @@ -; RUN: llc -asm-verbose=false < %s -mattr=+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 -check-prefix=CHECK-ALL -; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=CHECK-LIBCALL -check-prefix=CHECK-ALL +; RUN: llc -asm-verbose=false < %s -mattr=+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 --check-prefix=CHECK-VFP -check-prefix=CHECK-ALL +; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=CHECK-LIBCALL --check-prefix=CHECK-VFP -check-prefix=CHECK-ALL --check-prefix=CHECK-LIBCALL-VFP +; RUN: llc -asm-verbose=false < %s -mattr=-vfp2 | FileCheck %s --check-prefix=CHECK-LIBCALL -check-prefix=CHECK-NOVFP -check-prefix=CHECK-ALL target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -target triple = "armv7-eabihf" +target triple = "armv7---eabihf" -; CHECK-FP16-LABEL: test_fadd: +; CHECK-ALL-LABEL: test_fadd: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vadd.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vadd.f32 +; CHECK-NOVFP: bl __aeabi_fadd ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_fadd: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vadd.f32 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fadd(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -22,16 +22,15 @@ define void @test_fadd(half* %p, half* %q) #0 { ret void } -; CHECK-FP16-LABEL: test_fsub: +; CHECK-ALL-LABEL: test_fsub: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vsub.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vsub.f32 +; CHECK-NOVFP: bl __aeabi_fsub ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_fsub: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vsub.f32 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fsub(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -40,16 +39,15 @@ define void @test_fsub(half* %p, half* %q) #0 { ret void } -; CHECK-FP16-LABEL: test_fmul: +; CHECK-ALL-LABEL: test_fmul: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vmul.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vmul.f32 +; CHECK-NOVFP: bl __aeabi_fmul ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_fmul -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vmul.f32 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fmul(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -58,16 +56,15 @@ define void @test_fmul(half* %p, half* %q) #0 { ret void } -; CHECK-FP16-LABEL: test_fdiv: +; CHECK-ALL-LABEL: test_fdiv: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vdiv.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vdiv.f32 +; CHECK-NOVFP: bl __aeabi_fdiv ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_fdiv -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vdiv.f32 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fdiv(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -76,16 +73,14 @@ define void @test_fdiv(half* %p, half* %q) #0 { ret void } -; CHECK-FP16-LABEL: test_frem: +; CHECK-ALL-LABEL: test_frem: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: bl fmodf -; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_frem -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl fmodf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_frem(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -96,9 +91,8 @@ define void @test_frem(half* %p, half* %q) #0 { ; CHECK-ALL-LABEL: test_load_store: ; CHECK-ALL-NEXT: .fnstart -; CHECK-ALL-NEXT: ldrh r0, [r0] -; CHECK-ALL-NEXT: strh r0, [r1] -; CHECK-ALL-NEXT: bx lr +; CHECK-ALL: ldrh {{r[0-9]+}}, [{{r[0-9]+}}] +; CHECK-ALL: strh {{r[0-9]+}}, [{{r[0-9]+}}] define void @test_load_store(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 store half %a, half* %q @@ -112,6 +106,7 @@ declare half @test_callee(half %a, half %b) #0 ; CHECK-ALL-LABEL: test_call: ; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: .save {r11, lr} ; CHECK-ALL-NEXT: push {r11, lr} ; CHECK-ALL-NEXT: bl test_callee ; CHECK-ALL-NEXT: pop {r11, pc} @@ -122,10 +117,14 @@ define half @test_call(half %a, half %b) #0 { ; CHECK-ALL-LABEL: test_call_flipped: ; CHECK-ALL-NEXT: .fnstart +; CHECK-ALL-NEXT: .save {r11, lr} ; CHECK-ALL-NEXT: push {r11, lr} -; CHECK-ALL-NEXT: mov r2, r0 -; CHECK-ALL-NEXT: mov r0, r1 -; CHECK-ALL-NEXT: mov r1, r2 +; CHECK-VFP-NEXT: vmov.f32 s2, s0 +; CHECK-VFP-NEXT: vmov.f32 s0, s1 +; CHECK-VFP-NEXT: vmov.f32 s1, s2 +; CHECK-NOVFP-NEXT: mov r2, r0 +; CHECK-NOVFP-NEXT: mov r0, r1 +; CHECK-NOVFP-NEXT: mov r1, r2 ; CHECK-ALL-NEXT: bl test_callee ; CHECK-ALL-NEXT: pop {r11, pc} define half @test_call_flipped(half %a, half %b) #0 { @@ -135,9 +134,12 @@ define half @test_call_flipped(half %a, half %b) #0 { ; CHECK-ALL-LABEL: test_tailcall_flipped: ; CHECK-ALL-NEXT: .fnstart -; CHECK-ALL-NEXT: mov r2, r0 -; CHECK-ALL-NEXT: mov r0, r1 -; CHECK-ALL-NEXT: mov r1, r2 +; CHECK-VFP-NEXT: vmov.f32 s2, s0 +; CHECK-VFP-NEXT: vmov.f32 s0, s1 +; CHECK-VFP-NEXT: vmov.f32 s1, s2 +; CHECK-NOVFP-NEXT: mov r2, r0 +; CHECK-NOVFP-NEXT: mov r0, r1 +; CHECK-NOVFP-NEXT: mov r1, r2 ; CHECK-ALL-NEXT: b test_callee define half @test_tailcall_flipped(half %a, half %b) #0 { %r = tail call half @test_callee(half %b, half %a) @@ -147,12 +149,10 @@ define half @test_tailcall_flipped(half %a, half %b) #0 { ; Optimizer picks %p or %q based on %c and only loads that value ; No conversion is needed ; CHECK-ALL-LABEL: test_select: -; CHECK-ALL-NEXT: .fnstart -; CHECK-ALL-NEXT: cmp r2, #0 -; CHECK-ALL-NEXT: movne r1, r0 -; CHECK-ALL-NEXT: ldrh r1, [r1] -; CHECK-ALL-NEXT: strh r1, [r0] -; CHECK-ALL-NEXT: bx lr +; CHECK-ALL: cmp {{r[0-9]+}}, #0 +; CHECK-ALL: movne {{r[0-9]+}}, {{r[0-9]+}} +; CHECK-ALL: ldrh {{r[0-9]+}}, [{{r[0-9]+}}] +; CHECK-ALL: strh {{r[0-9]+}}, [{{r[0-9]+}}] define void @test_select(half* %p, half* %q, i1 zeroext %c) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -163,17 +163,15 @@ define void @test_select(half* %p, half* %q, i1 zeroext %c) #0 { ; Test only two variants of fcmp. These get translated to f32 vcmpe ; instructions anyway. -; CHECK-FP16-LABEL: test_fcmp_une: +; CHECK-ALL-LABEL: test_fcmp_une: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vcmpe.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vcmpe.f32 +; CHECK-NOVFP: bl __aeabi_fcmpeq ; CHECK-FP16: vmrs APSR_nzcv, fpscr -; CHECK-FP16: movwne -; CHECK-LIBCALL-LABEL: test_fcmp_une: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vcmpe.f32 -; CHECK-LIBCALL: movwne +; CHECK-ALL: movw{{ne|eq}} define i1 @test_fcmp_une(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -181,18 +179,15 @@ define i1 @test_fcmp_une(half* %p, half* %q) #0 { ret i1 %r } -; CHECK-FP16-LABEL: test_fcmp_ueq: +; CHECK-ALL-LABEL: test_fcmp_ueq: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vcmpe.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vcmpe.f32 +; CHECK-NOVFP: bl __aeabi_fcmpeq ; CHECK-FP16: vmrs APSR_nzcv, fpscr -; CHECK-FP16: movweq -; CHECK-FP16: movwvs -; CHECK-LIBCALL-LABEL: test_fcmp_ueq: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vcmpe.f32 -; CHECK-LIBCALL: movweq +; CHECK-LIBCALL: movw{{ne|eq}} define i1 @test_fcmp_ueq(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -200,19 +195,18 @@ define i1 @test_fcmp_ueq(half* %p, half* %q) #0 { ret i1 %r } -; CHECK-FP16-LABEL: test_br_cc: +; CHECK-ALL-LABEL: test_br_cc: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vcmpe.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vcmpe.f32 +; CHECK-NOVFP: bl __aeabi_fcmplt ; CHECK-FP16: vmrs APSR_nzcv, fpscr -; CHECK-FP16: strmi -; CHECK-FP16: strpl -; CHECK-LIBCALL-LABEL: test_br_cc: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vcmpe.f32 -; CHECK-LIBCALL: strmi -; CHECK-LIBCALL: strpl +; CHECK-VFP: strmi +; CHECK-VFP: strpl +; CHECK-NOVFP: strne +; CHECK-NOVFP: streq define void @test_br_cc(half* %p, half* %q, i32* %p1, i32* %p2) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -227,20 +221,19 @@ else: } declare i1 @test_dummy(half* %p) #0 -; CHECK-FP16-LABEL: test_phi: +; CHECK-ALL-LABEL: test_phi: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: [[LOOP:.LBB[1-9_]+]]: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: bl test_dummy ; CHECK-FP16: bne [[LOOP]] ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_phi: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL-VFP: bl __aeabi_h2f ; CHECK-LIBCALL: [[LOOP:.LBB[1-9_]+]]: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL-VFP: bl __aeabi_h2f ; CHECK-LIBCALL: bl test_dummy ; CHECK-LIBCALL: bne [[LOOP]] -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL-VFP: bl __aeabi_f2h define void @test_phi(half* %p) #0 { entry: %a = load half, half* %p @@ -255,96 +248,84 @@ return: ret void } -; CHECK-FP16-LABEL: test_fptosi_i32: +; CHECK-ALL-LABEL: test_fptosi_i32: ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vcvt.s32.f32 -; CHECK-LIBCALL-LABEL: test_fptosi_i32: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vcvt.s32.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vcvt.s32.f32 +; CHECK-NOVFP: bl __aeabi_f2iz define i32 @test_fptosi_i32(half* %p) #0 { %a = load half, half* %p, align 2 %r = fptosi half %a to i32 ret i32 %r } -; CHECK-FP16-LABEL: test_fptosi_i64: +; CHECK-ALL-LABEL: test_fptosi_i64: ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: bl __aeabi_f2lz -; CHECK-LIBCALL-LABEL: test_fptosi_i64: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __aeabi_f2lz +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-ALL: bl __aeabi_f2lz define i64 @test_fptosi_i64(half* %p) #0 { %a = load half, half* %p, align 2 %r = fptosi half %a to i64 ret i64 %r } -; CHECK-FP16-LABEL: test_fptoui_i32: +; CHECK-ALL-LABEL: test_fptoui_i32: ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vcvt.u32.f32 -; CHECK-LIBCALL-LABEL: test_fptoui_i32: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vcvt.u32.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vcvt.u32.f32 +; CHECK-NOVFP: bl __aeabi_f2uiz define i32 @test_fptoui_i32(half* %p) #0 { %a = load half, half* %p, align 2 %r = fptoui half %a to i32 ret i32 %r } -; CHECK-FP16-LABEL: test_fptoui_i64: +; CHECK-ALL-LABEL: test_fptoui_i64: ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: bl __aeabi_f2ulz -; CHECK-LIBCALL-LABEL: test_fptoui_i64: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __aeabi_f2ulz +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-ALL: bl __aeabi_f2ulz define i64 @test_fptoui_i64(half* %p) #0 { %a = load half, half* %p, align 2 %r = fptoui half %a to i64 ret i64 %r } -; CHECK-FP16-LABEL: test_sitofp_i32: -; CHECK-FP16: vcvt.f32.s32 +; CHECK-ALL-LABEL: test_sitofp_i32: +; CHECK-VFP: vcvt.f32.s32 +; CHECK-NOVFP: bl __aeabi_i2f ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_sitofp_i32: -; CHECK-LIBCALL: vcvt.f32.s32 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_sitofp_i32(i32 %a, half* %p) #0 { %r = sitofp i32 %a to half store half %r, half* %p ret void } -; CHECK-FP16-LABEL: test_uitofp_i32: -; CHECK-FP16: vcvt.f32.u32 +; CHECK-ALL-LABEL: test_uitofp_i32: +; CHECK-VFP: vcvt.f32.u32 +; CHECK-NOVFP: bl __aeabi_ui2f ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_uitofp_i32: -; CHECK-LIBCALL: vcvt.f32.u32 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_uitofp_i32(i32 %a, half* %p) #0 { %r = uitofp i32 %a to half store half %r, half* %p ret void } -; CHECK-FP16-LABEL: test_sitofp_i64: -; CHECK-FP16: bl __aeabi_l2f +; CHECK-ALL-LABEL: test_sitofp_i64: +; CHECK-ALL: bl __aeabi_l2f ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_sitofp_i64: -; CHECK-LIBCALL: bl __aeabi_l2f -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_sitofp_i64(i64 %a, half* %p) #0 { %r = sitofp i64 %a to half store half %r, half* %p ret void } -; CHECK-FP16-LABEL: test_uitofp_i64: -; CHECK-FP16: bl __aeabi_ul2f +; CHECK-ALL-LABEL: test_uitofp_i64: +; CHECK-ALL: bl __aeabi_ul2f ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_uitofp_i64: -; CHECK-LIBCALL: bl __aeabi_ul2f -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_uitofp_i64(i64 %a, half* %p) #0 { %r = uitofp i64 %a to half store half %r, half* %p @@ -354,7 +335,7 @@ define void @test_uitofp_i64(i64 %a, half* %p) #0 { ; CHECK-FP16-LABEL: test_fptrunc_float: ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_fptrunc_float: -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fptrunc_float(float %f, half* %p) #0 { %a = fptrunc float %f to half store half %a, half* %p @@ -374,7 +355,7 @@ define void @test_fptrunc_double(double %d, half* %p) #0 { ; CHECK-FP16-LABEL: test_fpextend_float: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-LIBCALL-LABEL: test_fpextend_float: -; CHECK-LIBCALL: b __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f define float @test_fpextend_float(half* %p) { %a = load half, half* %p, align 2 %r = fpext half %a to float @@ -383,10 +364,10 @@ define float @test_fpextend_float(half* %p) { ; CHECK-FP16-LABEL: test_fpextend_double: ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-FP16: vcvt.f64.f32 ; CHECK-LIBCALL-LABEL: test_fpextend_double: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vcvt.f64.f32 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vcvt.f64.f32 +; CHECK-NOVFP: bl __aeabi_f2d define double @test_fpextend_double(half* %p) { %a = load half, half* %p, align 2 %r = fpext half %a to double @@ -436,14 +417,14 @@ declare half @llvm.nearbyint.f16(half %a) #0 declare half @llvm.round.f16(half %a) #0 declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0 -; CHECK-FP16-LABEL: test_sqrt: +; CHECK-ALL-LABEL: test_sqrt: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vsqrt.f32 ; CHECK-FP16: vcvtb.f16.f32 -; CHECK-LIBCALL-LABEL: test_sqrt: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vsqrt.f32 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP-LIBCALL: vsqrt.f32 +; CHECK-NOVFP: bl sqrtf +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_sqrt(half* %p) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.sqrt.f16(half %a) @@ -456,9 +437,9 @@ define void @test_sqrt(half* %p) #0 { ; CHECK-FP16: bl __powisf2 ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_fpowi: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl __powisf2 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fpowi(half* %p, i32 %b) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.powi.f16(half %a, i32 %b) @@ -471,9 +452,9 @@ define void @test_fpowi(half* %p, i32 %b) #0 { ; CHECK-FP16: bl sinf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_sin: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl sinf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_sin(half* %p) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.sin.f16(half %a) @@ -486,9 +467,9 @@ define void @test_sin(half* %p) #0 { ; CHECK-FP16: bl cosf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_cos: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl cosf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_cos(half* %p) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.cos.f16(half %a) @@ -502,10 +483,10 @@ define void @test_cos(half* %p) #0 { ; CHECK-FP16: bl powf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_pow: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl powf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_pow(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -519,9 +500,9 @@ define void @test_pow(half* %p, half* %q) #0 { ; CHECK-FP16: bl expf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_exp: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl expf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_exp(half* %p) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.exp.f16(half %a) @@ -534,9 +515,9 @@ define void @test_exp(half* %p) #0 { ; CHECK-FP16: bl exp2f ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_exp2: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl exp2f -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_exp2(half* %p) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.exp2.f16(half %a) @@ -549,9 +530,9 @@ define void @test_exp2(half* %p) #0 { ; CHECK-FP16: bl logf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_log: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl logf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_log(half* %p) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.log.f16(half %a) @@ -564,9 +545,9 @@ define void @test_log(half* %p) #0 { ; CHECK-FP16: bl log10f ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_log10: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl log10f -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_log10(half* %p) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.log10.f16(half %a) @@ -579,9 +560,9 @@ define void @test_log10(half* %p) #0 { ; CHECK-FP16: bl log2f ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_log2: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl log2f -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_log2(half* %p) #0 { %a = load half, half* %p, align 2 %r = call half @llvm.log2.f16(half %a) @@ -596,11 +577,11 @@ define void @test_log2(half* %p) #0 { ; CHECK-FP16: bl fmaf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_fma: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl fmaf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fma(half* %p, half* %q, half* %r) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -615,9 +596,9 @@ define void @test_fma(half* %p, half* %q, half* %r) #0 { ; CHECK-FP16: vabs.f32 ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_fabs: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bfc -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fabs(half* %p) { %a = load half, half* %p, align 2 %r = call half @llvm.fabs.f16(half %a) @@ -631,10 +612,10 @@ define void @test_fabs(half* %p) { ; CHECK-FP16: bl fminf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_minnum: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl fminf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_minnum(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -649,10 +630,10 @@ define void @test_minnum(half* %p, half* %q) #0 { ; CHECK-FP16: bl fmaxf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_maxnum: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl fmaxf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_maxnum(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -667,10 +648,13 @@ define void @test_maxnum(half* %p, half* %q) #0 { ; CHECK-FP16: vbsl ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_copysign: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vbsl -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP-LIBCALL: vbsl +; CHECK-NOVFP: bfc +; CHECK-NOVFP: and +; CHECK-NOVFP: orr +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_copysign(half* %p, half* %q) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -684,9 +668,9 @@ define void @test_copysign(half* %p, half* %q) #0 { ; CHECK-FP16: bl floorf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_floor: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl floorf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_floor(half* %p) { %a = load half, half* %p, align 2 %r = call half @llvm.floor.f16(half %a) @@ -699,9 +683,9 @@ define void @test_floor(half* %p) { ; CHECK-FP16: bl ceilf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_ceil: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl ceilf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_ceil(half* %p) { %a = load half, half* %p, align 2 %r = call half @llvm.ceil.f16(half %a) @@ -714,9 +698,9 @@ define void @test_ceil(half* %p) { ; CHECK-FP16: bl truncf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_trunc: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl truncf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_trunc(half* %p) { %a = load half, half* %p, align 2 %r = call half @llvm.trunc.f16(half %a) @@ -729,9 +713,9 @@ define void @test_trunc(half* %p) { ; CHECK-FP16: bl rintf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_rint: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl rintf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_rint(half* %p) { %a = load half, half* %p, align 2 %r = call half @llvm.rint.f16(half %a) @@ -744,9 +728,9 @@ define void @test_rint(half* %p) { ; CHECK-FP16: bl nearbyintf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_nearbyint: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl nearbyintf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_nearbyint(half* %p) { %a = load half, half* %p, align 2 %r = call half @llvm.nearbyint.f16(half %a) @@ -759,9 +743,9 @@ define void @test_nearbyint(half* %p) { ; CHECK-FP16: bl roundf ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_round: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl roundf -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_round(half* %p) { %a = load half, half* %p, align 2 %r = call half @llvm.round.f16(half %a) @@ -776,11 +760,12 @@ define void @test_round(half* %p) { ; CHECK-FP16: vmla.f32 ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL-LABEL: test_fmuladd: -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: bl __gnu_h2f_ieee -; CHECK-LIBCALL: vmla.f32 -; CHECK-LIBCALL: bl __gnu_f2h_ieee +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP-LIBCALL: vmla.f32 +; CHECK-NOVFP: bl __aeabi_fmul +; CHECK-LIBCALL: bl __aeabi_f2h define void @test_fmuladd(half* %p, half* %q, half* %r) #0 { %a = load half, half* %p, align 2 %b = load half, half* %q, align 2 @@ -795,30 +780,28 @@ define void @test_fmuladd(half* %p, half* %q, half* %r) #0 { ; and extractelement have these extra loads and stores. ; CHECK-ALL-LABEL: test_insertelement: -; CHECK-ALL-NEXT: .fnstart -; CHECK-ALL-NEXT: sub sp, sp, #8 -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: mov -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: add -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: add sp, sp, #8 -; CHECK-ALL-NEXT: bx lr +; CHECK-ALL: sub sp, sp, #8 +; CHECK-ALL: ldrh +; CHECK-ALL: strh +; CHECK-ALL: ldrh +; CHECK-ALL: strh +; CHECK-ALL: ldrh +; CHECK-ALL: strh +; CHECK-ALL: ldrh +; CHECK-ALL: strh +; CHECK-ALL: mov +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: add +; CHECK-ALL: strh +; CHECK-ALL: ldrh +; CHECK-ALL: strh +; CHECK-ALL: ldrh +; CHECK-ALL: strh +; CHECK-ALL: ldrh +; CHECK-ALL: strh +; CHECK-ALL: ldrh +; CHECK-ALL: strh +; CHECK-ALL: add sp, sp, #8 define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 { %a = load half, half* %p, align 2 %b = load <4 x half>, <4 x half>* %q, align 8 @@ -828,22 +811,30 @@ define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 { } ; CHECK-ALL-LABEL: test_extractelement: -; CHECK-ALL-NEXT: .fnstart -; CHECK-ALL-NEXT: sub sp, sp, #8 -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: orr -; CHECK-ALL-NEXT: str -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: orr -; CHECK-ALL-NEXT: str -; CHECK-ALL-NEXT: mov -; CHECK-ALL-NEXT: add -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: add sp, sp, #8 -; CHECK-ALL-NEXT: bx lr +; CHECK-VFP: sub sp, sp, #8 +; CHECK-VFP: ldrh +; CHECK-VFP: ldrh +; CHECK-VFP: orr +; CHECK-VFP: str +; CHECK-VFP: ldrh +; CHECK-VFP: ldrh +; CHECK-VFP: orr +; CHECK-VFP: str +; CHECK-VFP: mov +; CHECK-VFP: add +; CHECK-VFP: ldrh +; CHECK-VFP: strh +; CHECK-VFP: add sp, sp, #8 +; CHECK-VFP: bx lr +; CHECK-NOVFP: ldrh +; CHECK-NOVFP: strh +; CHECK-NOVFP: ldrh +; CHECK-NOVFP: strh +; CHECK-NOVFP: ldrh +; CHECK-NOVFP: strh +; CHECK-NOVFP: ldrh +; CHECK-NOVFP: strh +; CHECK-NOVFP: ldrh define void @test_extractelement(half* %p, <4 x half>* %q, i32 %i) #0 { %a = load <4 x half>, <4 x half>* %q, align 8 %b = extractelement <4 x half> %a, i32 %i @@ -856,12 +847,10 @@ define void @test_extractelement(half* %p, <4 x half>* %q, i32 %i) #0 { %struct.dummy = type { i32, half } ; CHECK-ALL-LABEL: test_insertvalue: -; CHECK-ALL-NEXT: .fnstart -; CHECK-ALL-NEXT: ldr -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: str -; CHECK-ALL-NEXT: bx lr +; CHECK-ALL-DAG: ldr +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: str define void @test_insertvalue(%struct.dummy* %p, half* %q) { %a = load %struct.dummy, %struct.dummy* %p %b = load half, half* %q @@ -871,10 +860,9 @@ define void @test_insertvalue(%struct.dummy* %p, half* %q) { } ; CHECK-ALL-LABEL: test_extractvalue: -; CHECK-ALL-NEXT: .fnstart -; CHECK-ALL-NEXT: ldrh -; CHECK-ALL-NEXT: strh -; CHECK-ALL-NEXT: bx lr +; CHECK-ALL: .fnstart +; CHECK-ALL: ldrh +; CHECK-ALL: strh define void @test_extractvalue(%struct.dummy* %p, half* %q) { %a = load %struct.dummy, %struct.dummy* %p %b = extractvalue %struct.dummy %a, 1 @@ -882,10 +870,11 @@ define void @test_extractvalue(%struct.dummy* %p, half* %q) { ret void } -; CHECK-FP16-LABEL: test_struct_return: +; CHECK-ALL-LABEL: test_struct_return: ; CHECK-FP16: vcvtb.f32.f16 -; CHECK-LIBCALL-LABEL: test_struct_return: -; CHECK-LIBCALL: bl __gnu_h2f_ieee +; CHECK-VFP-LIBCALL: bl __aeabi_h2f +; CHECK-NOVFP-DAG: ldr +; CHECK-NOVFP-DAG: ldrh define %struct.dummy @test_struct_return(%struct.dummy* %p) { %a = load %struct.dummy, %struct.dummy* %p ret %struct.dummy %a @@ -893,7 +882,7 @@ define %struct.dummy @test_struct_return(%struct.dummy* %p) { ; CHECK-ALL-LABEL: test_struct_arg: ; CHECK-ALL-NEXT: .fnstart -; CHECK-ALL-NEXT: mov r0, r1 +; CHECK-NOVFP-NEXT: mov r0, r1 ; CHECK-ALL-NEXT: bx lr define half @test_struct_arg(%struct.dummy %p) { %a = extractvalue %struct.dummy %p, 1 diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll index 25fbf9070cb6..73d5c36a9c2f 100644 --- a/test/CodeGen/ARM/fp16.ll +++ b/test/CodeGen/ARM/fp16.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s | FileCheck %s -; RUN: llc -mattr=+vfp3,+fp16 < %s | FileCheck --check-prefix=CHECK-FP16 %s -; RUN: llc -mtriple=armv8-eabihf < %s | FileCheck --check-prefix=CHECK-ARMV8 %s -; RUN: llc -mtriple=thumbv7m-eabi < %s | FileCheck --check-prefix=CHECK-SOFTFLOAT %s +; RUN: llc -mtriple=armv7a--none-eabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-HARDFLOAT-EABI %s +; RUN: llc -mtriple=armv7a--none-gnueabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-HARDFLOAT-GNU %s +; RUN: llc -mattr=+vfp3,+fp16 < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-FP16 %s +; RUN: llc -mtriple=armv8-eabihf < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARMV8 %s +; RUN: llc -mtriple=thumbv7m-eabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SOFTFLOAT-EABI %s +; RUN: llc -mtriple=thumbv7m-gnueabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SOFTFLOAT-GNU %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" target triple = "armv7---eabihf" @@ -12,41 +14,45 @@ target triple = "armv7---eabihf" define void @foo() nounwind { ; CHECK-LABEL: foo: -; CHECK-FP16-LABEL: foo: -; CHECK-ARMV8-LABEL: foo: -; CHECK-SOFTFLOAT-LABEL: foo: entry: %0 = load i16, i16* @x, align 2 %1 = load i16, i16* @y, align 2 %2 = tail call float @llvm.convert.from.fp16.f32(i16 %0) -; CHECK: __gnu_h2f_ieee +; CHECK-HARDFLOAT-EABI: __aeabi_h2f +; CHECK-HARDFLOAT-GNU: __gnu_h2f_ieee ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-ARMv8: vcvtb.f32.f16 -; CHECK-SOFTFLOAT: __gnu_h2f_ieee +; CHECK-SOFTFLOAT-EABI: __aeabi_h2f +; CHECK-SOFTFLOAT-GNU: __gnu_h2f_ieee %3 = tail call float @llvm.convert.from.fp16.f32(i16 %1) -; CHECK: __gnu_h2f_ieee +; CHECK-HARDFLOAT-EABI: __aeabi_h2f +; CHECK-HARDFLOAT-GNU: __gnu_h2f_ieee ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-ARMV8: vcvtb.f32.f16 -; CHECK-SOFTFLOAT: __gnu_h2f_ieee +; CHECK-SOFTFLOAT-EABI: __aeabi_h2f +; CHECK-SOFTFLOAT-GNU: __gnu_h2f_ieee %4 = fadd float %2, %3 %5 = tail call i16 @llvm.convert.to.fp16.f32(float %4) -; CHECK: __gnu_f2h_ieee +; CHECK-HARDFLOAT-EABI: __aeabi_f2h +; CHECK-HARDFLOAT-GNU: __gnu_f2h_ieee ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-ARMV8: vcvtb.f16.f32 -; CHECK-SOFTFLOAT: __gnu_f2h_ieee +; CHECK-SOFTFLOAT-EABI: __aeabi_f2h +; CHECK-SOFTFLOAT-GNU: __gnu_f2h_ieee store i16 %5, i16* @x, align 2 ret void } define double @test_from_fp16(i16 %in) { ; CHECK-LABEL: test_from_fp16: -; CHECK-FP16-LABEL: test_from_fp16: -; CHECK-ARMV8-LABEL: test_from_fp16: -; CHECK-SOFTFLOAT-LABEL: test_from_fp16: %val = call double @llvm.convert.from.fp16.f64(i16 %in) -; CHECK: bl __gnu_h2f_ieee -; CHECK: vmov [[TMP:s[0-9]+]], r0 -; CHECK: vcvt.f64.f32 d0, [[TMP]] +; CHECK-HARDFLOAT-EABI: bl __aeabi_h2f +; CHECK-HARDFLOAT-EABI: vmov [[TMP:s[0-9]+]], r0 +; CHECK-HARDFLOAT-EABI: vcvt.f64.f32 {{d[0-9]+}}, [[TMP]] + +; CHECK-HARDFLOAT-GNU: bl __gnu_h2f_ieee +; CHECK-HARDFLOAT-GNU: vmov [[TMP:s[0-9]+]], r0 +; CHECK-HARDFLOAT-GNU: vcvt.f64.f32 {{d[0-9]+}}, [[TMP]] ; CHECK-FP16: vmov [[TMP16:s[0-9]+]], r0 ; CHECK-FP16: vcvtb.f32.f16 [[TMP32:s[0-9]+]], [[TMP16]] @@ -55,25 +61,29 @@ define double @test_from_fp16(i16 %in) { ; CHECK-ARMV8: vmov [[TMP:s[0-9]+]], r0 ; CHECK-ARMV8: vcvtb.f64.f16 d0, [[TMP]] -; CHECK-SOFTFLOAT: bl __gnu_h2f_ieee -; CHECK-SOFTFLOAT: bl __aeabi_f2d +; CHECK-SOFTFLOAT-EABI: bl __aeabi_h2f +; CHECK-SOFTFLOAT-EABI: bl __aeabi_f2d + +; CHECK-SOFTFLOAT-GNU: bl __gnu_h2f_ieee +; CHECK-SOFTFLOAT-GNU: bl __aeabi_f2d ret double %val } define i16 @test_to_fp16(double %in) { ; CHECK-LABEL: test_to_fp16: -; CHECK-FP16-LABEL: test_to_fp16: -; CHECK-ARMV8-LABEL: test_to_fp16: -; CHECK-SOFTFLOAT-LABEL: test_to_fp16: %val = call i16 @llvm.convert.to.fp16.f64(double %in) -; CHECK: bl __aeabi_d2h +; CHECK-HARDFLOAT-EABI: bl __aeabi_d2h + +; CHECK-HARDFLOAT-GNU: bl __aeabi_d2h ; CHECK-FP16: bl __aeabi_d2h ; CHECK-ARMV8: vcvtb.f16.f64 [[TMP:s[0-9]+]], d0 ; CHECK-ARMV8: vmov r0, [[TMP]] -; CHECK-SOFTFLOAT: bl __aeabi_d2h +; CHECK-SOFTFLOAT-EABI: bl __aeabi_d2h + +; CHECK-SOFTFLOAT-GNU: bl __aeabi_d2h ret i16 %val } diff --git a/test/CodeGen/ARM/fparith.ll b/test/CodeGen/ARM/fparith.ll index cc880148da85..824824429db1 100644 --- a/test/CodeGen/ARM/fparith.ll +++ b/test/CodeGen/ARM/fparith.ll @@ -56,7 +56,7 @@ entry: ret float %tmp1 } -define double @f8(double %a) { +define arm_aapcs_vfpcc double @f8(double %a) { ;CHECK-LABEL: f8: ;CHECK: vneg.f64 entry: @@ -90,7 +90,7 @@ entry: declare float @fabsf(float) -define double @f12(double %a) { +define arm_aapcs_vfpcc double @f12(double %a) { ;CHECK-LABEL: f12: ;CHECK: vabs.f64 entry: diff --git a/test/CodeGen/ARM/gep-optimization.ll b/test/CodeGen/ARM/gep-optimization.ll new file mode 100644 index 000000000000..ce5af66d56ce --- /dev/null +++ b/test/CodeGen/ARM/gep-optimization.ll @@ -0,0 +1,77 @@ +; RUN: llc < %s -mtriple=armv7a-eabi | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-AT2 +; RUN: llc < %s -mtriple=thumbv7m-eabi | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-AT2 +; RUN: llc < %s -mtriple=thumbv6m-eabi | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T1 + +; This test checks that various kinds of getelementptr are all optimised to a +; simple multiply plus add, with the add being done by a register offset if the +; result is used in a load. + +; CHECK-LABEL: calc_1d: +; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84 +; CHECK-AT2: mla r0, r1, [[REG1]], r0 +; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]] +; CHECK-T1: adds r0, r0, [[REG2]] +define i32* @calc_1d(i32* %p, i32 %n) { +entry: + %mul = mul nsw i32 %n, 21 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %mul + ret i32* %add.ptr +} + +; CHECK-LABEL: load_1d: +; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84 +; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}} +; CHECK: ldr r0, [r0, [[REG2]]] +define i32 @load_1d(i32* %p, i32 %n) #1 { +entry: + %mul = mul nsw i32 %n, 21 + %arrayidx = getelementptr inbounds i32, i32* %p, i32 %mul + %0 = load i32, i32* %arrayidx, align 4 + ret i32 %0 +} + +; CHECK-LABEL: calc_2d_a: +; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84 +; CHECK-AT2: mla r0, r1, [[REG1]], r0 +; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]] +; CHECK-T1: adds r0, r0, [[REG2]] +define i32* @calc_2d_a([100 x i32]* %p, i32 %n) { +entry: + %mul = mul nsw i32 %n, 21 + %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %p, i32 0, i32 %mul + ret i32* %arrayidx1 +} + +; CHECK-LABEL: load_2d_a: +; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84 +; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}} +; CHECK: ldr r0, [r0, [[REG2]]] +define i32 @load_2d_a([100 x i32]* %p, i32 %n) #1 { +entry: + %mul = mul nsw i32 %n, 21 + %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %p, i32 0, i32 %mul + %0 = load i32, i32* %arrayidx1, align 4 + ret i32 %0 +} + +; CHECK-LABEL: calc_2d_b: +; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84 +; CHECK-AT2: mla r0, r1, [[REG1]], r0 +; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]] +; CHECK-T1: adds r0, r0, [[REG2]] +define i32* @calc_2d_b([21 x i32]* %p, i32 %n) { +entry: + %arrayidx1 = getelementptr inbounds [21 x i32], [21 x i32]* %p, i32 %n, i32 0 + ret i32* %arrayidx1 +} + +; CHECK-LABEL: load_2d_b: +; CHECK: mov{{s?}} [[REG1:r[0-9]+]], #84 +; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}} +; CHECK: ldr r0, [r0, [[REG2]]] +define i32 @load_2d_b([21 x i32]* %p, i32 %n) { +entry: + %arrayidx1 = getelementptr inbounds [21 x i32], [21 x i32]* %p, i32 %n, i32 0 + %0 = load i32, i32* %arrayidx1, align 4 + ret i32 %0 +} diff --git a/test/CodeGen/ARM/global-merge-1.ll b/test/CodeGen/ARM/global-merge-1.ll index d4d9b0f9d1f3..a3cbe8aec098 100644 --- a/test/CodeGen/ARM/global-merge-1.ll +++ b/test/CodeGen/ARM/global-merge-1.ll @@ -11,16 +11,16 @@ ; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2 ; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2 ; MERGE-NOT: .zerofill __DATA,__bss,_foo,20,2 -; MERGE: .zerofill __DATA,__bss,__MergedGlobals,60,4 +; MERGE: .zerofill __DATA,__bss,l__MergedGlobals,60,4 ; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2 ; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2 ; MERGE-NOT: .zerofill __DATA,__bss,_foo,20,2 -; NO-MERGE-NOT: .zerofill __DATA,__bss,__MergedGlobals,60,4 +; NO-MERGE-NOT: .zerofill __DATA,__bss,l__MergedGlobals,60,4 ; NO-MERGE: .zerofill __DATA,__bss,_bar,20,2 ; NO-MERGE: .zerofill __DATA,__bss,_baz,20,2 ; NO-MERGE: .zerofill __DATA,__bss,_foo,20,2 -; NO-MERGE-NOT: .zerofill __DATA,__bss,__MergedGlobals,60,4 +; NO-MERGE-NOT: .zerofill __DATA,__bss,l__MergedGlobals,60,4 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios3.0.0" diff --git a/test/CodeGen/ARM/global-merge-external.ll b/test/CodeGen/ARM/global-merge-external.ll new file mode 100644 index 000000000000..a9e0d199705a --- /dev/null +++ b/test/CodeGen/ARM/global-merge-external.ll @@ -0,0 +1,46 @@ +; RUN: llc < %s -mtriple=arm-eabi -arm-global-merge | FileCheck %s --check-prefix=CHECK-MERGE +; RUN: llc < %s -mtriple=arm-eabi -arm-global-merge -global-merge-on-external=true | FileCheck %s --check-prefix=CHECK-MERGE +; RUN: llc < %s -mtriple=arm-eabi -arm-global-merge -global-merge-on-external=false | FileCheck %s --check-prefix=CHECK-NO-MERGE +; RUN: llc < %s -mtriple=arm-macho -arm-global-merge | FileCheck %s --check-prefix=CHECK-NO-MERGE + +@x = global i32 0, align 4 +@y = global i32 0, align 4 +@z = global i32 0, align 4 + +define void @f1(i32 %a1, i32 %a2) { +;CHECK: f1: +;CHECK: ldr {{r[0-9]+}}, [[LABEL1:\.LCPI[0-9]+_[0-9]]] +;CHECK: [[LABEL1]]: +;CHECK-MERGE: .long .L_MergedGlobals +;CHECK-NO-MERGE: .long {{_?x}} + store i32 %a1, i32* @x, align 4 + store i32 %a2, i32* @y, align 4 + ret void +} + +define void @g1(i32 %a1, i32 %a2) { +;CHECK: g1: +;CHECK: ldr {{r[0-9]+}}, [[LABEL2:\.LCPI[0-9]+_[0-9]]] +;CHECK: [[LABEL2]]: +;CHECK-MERGE: .long .L_MergedGlobals +;CHECK-NO-MERGE: .long {{_?y}} + store i32 %a1, i32* @y, align 4 + store i32 %a2, i32* @z, align 4 + ret void +} + +;CHECK-NO-MERGE-NOT: .globl .L_MergedGlobals + +;CHECK-MERGE: .type .L_MergedGlobals,%object +;CHECK-MERGE: .local .L_MergedGlobals +;CHECK-MERGE: .comm .L_MergedGlobals,12,4 + +;CHECK-MERGE: .globl x +;CHECK-MERGE: x = .L_MergedGlobals +;CHECK-MERGE: .size x, 4 +;CHECK-MERGE: .globl y +;CHECK-MERGE: y = .L_MergedGlobals+4 +;CHECK-MERGE: .size y, 4 +;CHECK-MERGE: .globl z +;CHECK-MERGE: z = .L_MergedGlobals+8 +;CHECK-MERGE: .size z, 4 diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index bab96dadce55..e6aa2db744d5 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -60,16 +60,13 @@ define i32 @test1() { ; LinuxPIC-LABEL: test1: ; LinuxPIC: ldr r0, .LCPI0_0 -; LinuxPIC: ldr r1, .LCPI0_1 ; LinuxPIC: .LPC0_0: -; LinuxPIC: add r0, pc, r0 -; LinuxPIC: ldr r0, [r1, r0] +; LinuxPIC: ldr r0, [pc, r0] ; LinuxPIC: ldr r0, [r0] ; LinuxPIC: bx lr ; LinuxPIC: .align 2 ; LinuxPIC: .LCPI0_0: -; LinuxPIC: .long _GLOBAL_OFFSET_TABLE_-(.LPC0_0+8) -; LinuxPIC: .LCPI0_1: -; LinuxPIC: .long G(GOT) +; LinuxPIC: .Ltmp0: +; LinuxPIC: .long G(GOT_PREL)-((.LPC0_0+8)-.Ltmp0) diff --git a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll index 4e6924fe5b6b..a44c9721d6c1 100644 --- a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll +++ b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll @@ -14,15 +14,15 @@ entry: br i1 undef, label %for.end, label %for.body ; Before if conversion, we have -; for.body -> lor.lhs.false.i (62) -; -> for.cond.backedge (62) -; lor.lhs.false.i -> for.cond.backedge (1048575) -; -> cond.false.i (1) +; for.body -> lor.lhs.false.i (50%) +; -> for.cond.backedge (50%) +; lor.lhs.false.i -> for.cond.backedge (100%) +; -> cond.false.i (0%) ; Afer if conversion, we have -; for.body -> for.cond.backedge (130023362) -; -> cond.false.i (62) +; for.body -> for.cond.backedge (100%) +; -> cond.false.i (0%) ; CHECK: BB#1: derived from LLVM BB %for.body -; CHECK: Successors according to CFG: BB#2(130023362) BB#4(62) +; CHECK: Successors according to CFG: BB#2(0x7ffffc00 / 0x80000000 = 100.00%) BB#4(0x00000400 / 0x80000000 = 0.00%) for.body: br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1 diff --git a/test/CodeGen/ARM/ifcvt-branch-weight.ll b/test/CodeGen/ARM/ifcvt-branch-weight.ll index 41d78e53acc7..0de039cde23c 100644 --- a/test/CodeGen/ARM/ifcvt-branch-weight.ll +++ b/test/CodeGen/ARM/ifcvt-branch-weight.ll @@ -19,7 +19,7 @@ bb: br i1 %9, label %return, label %bb2 ; CHECK: BB#2: derived from LLVM BB %bb2 -; CHECK: Successors according to CFG: BB#3(192) BB#4(192) +; CHECK: Successors according to CFG: BB#3({{[0-9a-fx/= ]+}}50.00%) BB#4({{[0-9a-fx/= ]+}}50.00%) bb2: %v10 = icmp eq i32 %3, 16 diff --git a/test/CodeGen/ARM/ifcvt-iter-indbr.ll b/test/CodeGen/ARM/ifcvt-iter-indbr.ll index 75e9d77d7920..a96b6e8a1e83 100644 --- a/test/CodeGen/ARM/ifcvt-iter-indbr.ll +++ b/test/CodeGen/ARM/ifcvt-iter-indbr.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false | FileCheck %s +; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -print-machineinstrs=if-converter 2>&1 | FileCheck --check-prefix=CHECK-PROB %s declare i32 @foo(i32) declare i8* @bar(i32, i8*, i8*) @@ -27,6 +28,11 @@ declare i8* @bar(i32, i8*, i8*) ; CHECK-NEXT: movw r0, #4567 ; CHECK-NEXT: [[FOOCALL]]: ; CHECK-NEXT: blx _foo +; +; CHECK-PROB: BB#0: +; CHECK-PROB: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}50.00%) BB#2({{[0-9a-fx/= ]+}}25.00%) BB#4({{[0-9a-fx/= ]+}}25.00%) +; CHECK-PROB: BB#1: +; CHECK-PROB: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}75.00%) BB#4({{[0-9a-fx/= ]+}}25.00%) define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) { entry: diff --git a/test/CodeGen/ARM/ifcvt4.ll b/test/CodeGen/ARM/ifcvt4.ll index 8c6825aeda97..0a6b99fb89b3 100644 --- a/test/CodeGen/ARM/ifcvt4.ll +++ b/test/CodeGen/ARM/ifcvt4.ll @@ -1,10 +1,8 @@ ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -; Do not if-convert when branches go to the different loops. ; CHECK-LABEL: t: -; CHECK-NOT: subgt -; CHECK-NOT: suble -; Don't use +; CHECK: subgt +; CHECK: suble define i32 @t(i32 %a, i32 %b) { entry: %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index 3aa2139cc03a..9fb8abde6130 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -13,10 +13,10 @@ entry: define i32 @t1(i32 %a, i32 %b) { ; A8-LABEL: t1: -; A8: poplt {r7, pc} +; A8: bxlt lr ; SWIFT-LABEL: t1: -; SWIFT: pop {r7, pc} +; SWIFT: bxlt lr ; SWIFT: pop {r7, pc} entry: %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index 78901930e4b2..668069751cf1 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -3,7 +3,7 @@ define void @foo(i32 %X, i32 %Y) { entry: ; CHECK: cmpne -; CHECK: pophi +; CHECK: bxhi lr %tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1] %tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1] %tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/ifcvt8.ll b/test/CodeGen/ARM/ifcvt8.ll index ca9a5c63cda6..e8b7f6926396 100644 --- a/test/CodeGen/ARM/ifcvt8.ll +++ b/test/CodeGen/ARM/ifcvt8.ll @@ -5,7 +5,9 @@ declare void @abort() define fastcc void @t(%struct.SString* %word, i8 signext %c) { -; CHECK: popne +; CHECK-NOT: pop +; CHECK: bxne +; CHECK-NOT: pop entry: %tmp1 = icmp eq %struct.SString* %word, null ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %cond_false diff --git a/test/CodeGen/ARM/inlineasm-switch-mode.ll b/test/CodeGen/ARM/inlineasm-switch-mode.ll index 65fea114d7de..6035612788d8 100644 --- a/test/CodeGen/ARM/inlineasm-switch-mode.ll +++ b/test/CodeGen/ARM/inlineasm-switch-mode.ll @@ -15,8 +15,8 @@ define hidden i32 @bah(i8* %start) #0 align 2 { ; ARM: $t ; ARM-NEXT: 48 1c -; THUMB: $a +; THUMB: $a{{.*}}: ; THUMB-NEXT: 04 70 ; THUMB-NEXT: 2d e5 -; THUMB: $t +; THUMB: $t{{.*}}: ; THUMB-NEXT: 48 1c adds r0, r1, #1 diff --git a/test/CodeGen/ARM/ldm-stm-base-materialization.ll b/test/CodeGen/ARM/ldm-stm-base-materialization.ll new file mode 100644 index 000000000000..a3231f95f478 --- /dev/null +++ b/test/CodeGen/ARM/ldm-stm-base-materialization.ll @@ -0,0 +1,93 @@ +; RUN: llc -mtriple armv7a-none-eabi -mattr=-neon < %s -verify-machineinstrs -o - | FileCheck %s + +; Thumb1 (thumbv6m) is tested in tests/Thumb + +@a = external global i32* +@b = external global i32* + +; Function Attrs: nounwind +define void @foo24() #0 { +entry: +; CHECK-LABEL: foo24: +; We use '[rl0-9]*' to allow 'r0'..'r12', 'lr' +; CHECK: movt [[LB:[rl0-9]+]], :upper16:b +; CHECK: movt [[SB:[rl0-9]+]], :upper16:a +; CHECK: add [[NLB:[rl0-9]+]], [[LB]], #4 +; CHECK: add [[NSB:[rl0-9]+]], [[SB]], #4 +; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]], [[R5:[rl0-9]+]], [[R6:[rl0-9]+]]} +; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]} + %0 = load i32*, i32** @a, align 4 + %arrayidx = getelementptr inbounds i32, i32* %0, i32 1 + %1 = bitcast i32* %arrayidx to i8* + %2 = load i32*, i32** @b, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1 + %3 = bitcast i32* %arrayidx1 to i8* + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %3, i32 24, i32 4, i1 false) + ret void +} + +define void @foo28() #0 { +entry: +; CHECK-LABEL: foo28: +; CHECK: movt [[LB:[rl0-9]+]], :upper16:b +; CHECK: movt [[SB:[rl0-9]+]], :upper16:a +; CHECK: add [[NLB:[rl0-9]+]], [[LB]], #4 +; CHECK: add [[NSB:[rl0-9]+]], [[SB]], #4 +; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]]} +; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]]} +; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]} +; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]} + %0 = load i32*, i32** @a, align 4 + %arrayidx = getelementptr inbounds i32, i32* %0, i32 1 + %1 = bitcast i32* %arrayidx to i8* + %2 = load i32*, i32** @b, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1 + %3 = bitcast i32* %arrayidx1 to i8* + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %3, i32 28, i32 4, i1 false) + ret void +} + +define void @foo32() #0 { +entry: +; CHECK-LABEL: foo32: +; CHECK: movt [[LB:[rl0-9]+]], :upper16:b +; CHECK: movt [[SB:[rl0-9]+]], :upper16:a +; CHECK: add [[NLB:[rl0-9]+]], [[LB]], #4 +; CHECK: add [[NSB:[rl0-9]+]], [[SB]], #4 +; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]} +; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]} +; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]} +; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]} + %0 = load i32*, i32** @a, align 4 + %arrayidx = getelementptr inbounds i32, i32* %0, i32 1 + %1 = bitcast i32* %arrayidx to i8* + %2 = load i32*, i32** @b, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1 + %3 = bitcast i32* %arrayidx1 to i8* + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %3, i32 32, i32 4, i1 false) + ret void +} + +define void @foo36() #0 { +entry: +; CHECK-LABEL: foo36: +; CHECK: movt [[LB:[rl0-9]+]], :upper16:b +; CHECK: movt [[SB:[rl0-9]+]], :upper16:a +; CHECK: add [[NLB:[rl0-9]+]], [[LB]], #4 +; CHECK: add [[NSB:[rl0-9]+]], [[SB]], #4 +; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]} +; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]} +; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]], [[R5:[rl0-9]+]]} +; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]]} + %0 = load i32*, i32** @a, align 4 + %arrayidx = getelementptr inbounds i32, i32* %0, i32 1 + %1 = bitcast i32* %arrayidx to i8* + %2 = load i32*, i32** @b, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %2, i32 1 + %3 = bitcast i32* %arrayidx1 to i8* + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %3, i32 36, i32 4, i1 false) + ret void +} + +; Function Attrs: nounwind +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1 diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index 5411618ed86d..b2596346bfa1 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=A8 -check-prefix=CHECK +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs | FileCheck %s -check-prefix=A8 -check-prefix=CHECK ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK ; rdar://6949835 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK @@ -112,10 +112,10 @@ entry: } ; CHECK-LABEL: strd_spill_ldrd_reload: -; A8: strd r1, r0, [sp] -; M3: strd r1, r0, [sp] -; BASIC: strd r1, r0, [sp] -; GREEDY: strd r0, r1, [sp] +; A8: strd r1, r0, [sp, #-8]! +; M3: strd r1, r0, [sp, #-8]! +; BASIC: strd r1, r0, [sp, #-8]! +; GREEDY: strd r0, r1, [sp, #-8]! ; CHECK: @ InlineAsm Start ; CHECK: @ InlineAsm End ; A8: ldrd r2, r1, [sp] @@ -131,5 +131,53 @@ define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) { ret void } +declare void @extfunc2(i32*, i32, i32) + +; CHECK-LABEL: ldrd_postupdate_dec: +; CHECK: ldrd r1, r2, [r0], #-8 +; CHECK-NEXT: bl{{x?}} _extfunc +define void @ldrd_postupdate_dec(i32* %p0) { + %p0.1 = getelementptr i32, i32* %p0, i32 1 + %v0 = load i32, i32* %p0 + %v1 = load i32, i32* %p0.1 + %p1 = getelementptr i32, i32* %p0, i32 -2 + call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) + ret void +} + +; CHECK-LABEL: ldrd_postupdate_inc: +; CHECK: ldrd r1, r2, [r0], #8 +; CHECK-NEXT: bl{{x?}} _extfunc +define void @ldrd_postupdate_inc(i32* %p0) { + %p0.1 = getelementptr i32, i32* %p0, i32 1 + %v0 = load i32, i32* %p0 + %v1 = load i32, i32* %p0.1 + %p1 = getelementptr i32, i32* %p0, i32 2 + call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) + ret void +} + +; CHECK-LABEL: strd_postupdate_dec: +; CHECK: strd r1, r2, [r0], #-8 +; CHECK-NEXT: bx lr +define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) { + %p0.1 = getelementptr i32, i32* %p0, i32 1 + store i32 %v0, i32* %p0 + store i32 %v1, i32* %p0.1 + %p1 = getelementptr i32, i32* %p0, i32 -2 + ret i32* %p1 +} + +; CHECK-LABEL: strd_postupdate_inc: +; CHECK: strd r1, r2, [r0], #8 +; CHECK-NEXT: bx lr +define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) { + %p0.1 = getelementptr i32, i32* %p0, i32 1 + store i32 %v0, i32* %p0 + store i32 %v1, i32* %p0.1 + %p1 = getelementptr i32, i32* %p0, i32 2 + ret i32* %p1 +} + declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/ARM/legalize-unaligned-load.ll b/test/CodeGen/ARM/legalize-unaligned-load.ll new file mode 100644 index 000000000000..fa5b21aa4a23 --- /dev/null +++ b/test/CodeGen/ARM/legalize-unaligned-load.ll @@ -0,0 +1,35 @@ +; RUN: llc -O3 -code-model=default -relocation-model=default -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s +; Check that we respect the existing chain between loads and stores when we +; legalize unaligned loads. +; Test case from PR24669. + +; Make sure the loads happen before the stores. +; CHECK-LABEL: get_set_complex: +; CHECK-NOT: str +; CHECK: ldr +; CHECK-NOT: str +; CHECK: ldr +; CHECK: str +; CHECK: bx +define i32 @get_set_complex({ float, float }* noalias nocapture %retptr, + { i8*, i32 }** noalias nocapture readnone %excinfo, + i8* noalias nocapture readnone %env, + [38 x i8]* nocapture %arg.rec, + float %arg.val.0, float %arg.val.1) +{ +entry: + %inserted.real = insertvalue { float, float } undef, float %arg.val.0, 0 + %inserted.imag = insertvalue { float, float } %inserted.real, float %arg.val.1, 1 + %.15 = getelementptr inbounds [38 x i8], [38 x i8]* %arg.rec, i32 0, i32 10 + %.16 = bitcast i8* %.15 to { float, float }* + %.17 = bitcast i8* %.15 to float* + %.18 = load float, float* %.17, align 1 + %.19 = getelementptr inbounds [38 x i8], [38 x i8]* %arg.rec, i32 0, i32 14 + %tmp = bitcast i8* %.19 to float* + %.20 = load float, float* %tmp, align 1 + %inserted.real.1 = insertvalue { float, float } undef, float %.18, 0 + %inserted.imag.1 = insertvalue { float, float } %inserted.real.1, float %.20, 1 + store { float, float } %inserted.imag, { float, float }* %.16, align 1 + store { float, float } %inserted.imag.1, { float, float }* %retptr, align 4 + ret i32 0 +} diff --git a/test/CodeGen/ARM/load-global.ll b/test/CodeGen/ARM/load-global.ll index 34748bc848bd..eade2fda3705 100644 --- a/test/CodeGen/ARM/load-global.ll +++ b/test/CodeGen/ARM/load-global.ll @@ -4,6 +4,7 @@ ; RUN: llc < %s -mtriple=thumbv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC_T ; RUN: llc < %s -mtriple=armv7-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC_V7 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX +; RUN: llc < %s -mtriple=thumbv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX_T @G = external global i32 @@ -40,11 +41,14 @@ define i32 @test1() { ; LINUX: test1 ; LINUX: ldr r0, .LCPI0_0 -; LINUX: ldr r1, .LCPI0_1 -; LINUX: add r0, pc, r0 -; LINUX: ldr r0, [r1, r0] +; LINUX: ldr r0, [pc, r0] ; LINUX: ldr r0, [r0] -; LINUX: .long G(GOT) +; LINUX: .long G(GOT_PREL)-((.LPC0_0+8)-.Ltmp0) + +; LINUX_T: ldr r0, .LCPI0_0 +; LINUX_T: add r0, pc +; LINUX_T: ldr r0, [r0] +; LINUX_T: ldr r0, [r0] %tmp = load i32, i32* @G ret i32 %tmp } diff --git a/test/CodeGen/ARM/load-store-flags.ll b/test/CodeGen/ARM/load-store-flags.ll index 5825a30109d0..95d9b484a0a7 100644 --- a/test/CodeGen/ARM/load-store-flags.ll +++ b/test/CodeGen/ARM/load-store-flags.ll @@ -6,7 +6,7 @@ define void @test_base_kill(i32 %v0, i32 %v1, i32* %addr) { ; CHECK-LABEL: test_base_kill: ; CHECK: adds [[NEWBASE:r[0-9]+]], r2, #4 -; CHECK: stm.w [[NEWBASE]], {r0, r1, r2} +; CHECK: stm [[NEWBASE]]!, {r0, r1, r2} %addr.1 = getelementptr i32, i32* %addr, i32 1 store i32 %v0, i32* %addr.1 @@ -27,7 +27,7 @@ define void @test_base_kill(i32 %v0, i32 %v1, i32* %addr) { define void @test_base_kill_mid(i32 %v0, i32* %addr, i32 %v1) { ; CHECK-LABEL: test_base_kill_mid: ; CHECK: adds [[NEWBASE:r[0-9]+]], r1, #4 -; CHECK: stm.w [[NEWBASE]], {r0, r1, r2} +; CHECK: stm [[NEWBASE]]!, {r0, r1, r2} %addr.1 = getelementptr i32, i32* %addr, i32 1 store i32 %v0, i32* %addr.1 diff --git a/test/CodeGen/ARM/load.ll b/test/CodeGen/ARM/load.ll index 3b2d637cb26e..b8f3003755a0 100644 --- a/test/CodeGen/ARM/load.ll +++ b/test/CodeGen/ARM/load.ll @@ -1,35 +1,564 @@ -; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv6m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T1 +; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2 -define i32 @f1(i8* %p) { + +; Register offset + +; CHECK-LABEL: ldrsb_rr +; CHECK: ldrsb r0, [r0, r1] +define i32 @ldrsb_rr(i8* %p, i32 %n) { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %n + %0 = load i8, i8* %arrayidx, align 1 + %conv = sext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrsh_rr +; CHECK-T1: lsls r1, r1, #1 +; CHECK-T1: ldrsh r0, [r0, r1] +; CHECK-T2: ldrsh.w r0, [r0, r1, lsl #1] +define i32 @ldrsh_rr(i16* %p, i32 %n) { +entry: + %arrayidx = getelementptr inbounds i16, i16* %p, i32 %n + %0 = load i16, i16* %arrayidx, align 2 + %conv = sext i16 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrb_rr +; CHECK: ldrb r0, [r0, r1] +define i32 @ldrb_rr(i8* %p, i32 %n) { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %n + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrh_rr +; CHECK-T1: lsls r1, r1, #1 +; CHECK-T1: ldrh r0, [r0, r1] +; CHECK-T2: ldrh.w r0, [r0, r1, lsl #1] +define i32 @ldrh_rr(i16* %p, i32 %n) { +entry: + %arrayidx = getelementptr inbounds i16, i16* %p, i32 %n + %0 = load i16, i16* %arrayidx, align 2 + %conv = zext i16 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldr_rr +; CHECK-T1: lsls r1, r1, #2 +; CHECK-T1: ldr r0, [r0, r1] +; CHECK-T2: ldr.w r0, [r0, r1, lsl #2] +define i32 @ldr_rr(i32* %p, i32 %n) { +entry: + %arrayidx = getelementptr inbounds i32, i32* %p, i32 %n + %0 = load i32, i32* %arrayidx, align 4 + ret i32 %0 +} + +; CHECK-LABEL: strb_rr +; CHECK: strb r2, [r0, r1] +define void @strb_rr(i8* %p, i32 %n, i32 %x) { +entry: + %conv = trunc i32 %x to i8 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %n + store i8 %conv, i8* %arrayidx, align 1 + ret void +} + +; CHECK-LABEL: strh_rr +; CHECK-T1: lsls r1, r1, #1 +; CHECK-T1: strh r2, [r0, r1] +; CHECK-T2: strh.w r2, [r0, r1, lsl #1] +define void @strh_rr(i16* %p, i32 %n, i32 %x) { +entry: + %conv = trunc i32 %x to i16 + %arrayidx = getelementptr inbounds i16, i16* %p, i32 %n + store i16 %conv, i16* %arrayidx, align 2 + ret void +} + +; CHECK-LABEL: str_rr +; CHECK-T1: lsls r1, r1, #2 +; CHECK-T1: str r2, [r0, r1] +; CHECK-T2: str.w r2, [r0, r1, lsl #2] +define void @str_rr(i32* %p, i32 %n, i32 %x) { +entry: + %arrayidx = getelementptr inbounds i32, i32* %p, i32 %n + store i32 %x, i32* %arrayidx, align 4 + ret void +} + + +; Immediate offset of zero + +; CHECK-LABEL: ldrsb_ri_zero +; CHECK-T1: ldrb r0, [r0] +; CHECK-T1: sxtb r0, r0 +; CHECK-T2: ldrsb.w r0, [r0] +define i32 @ldrsb_ri_zero(i8* %p) { +entry: + %0 = load i8, i8* %p, align 1 + %conv = sext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrsh_ri_zero +; CHECK-T1: ldrh r0, [r0] +; CHECK-T1: sxth r0, r0 +; CHECK-T2: ldrsh.w r0, [r0] +define i32 @ldrsh_ri_zero(i16* %p) { +entry: + %0 = load i16, i16* %p, align 2 + %conv = sext i16 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrb_ri_zero +; CHECK: ldrb r0, [r0] +define i32 @ldrb_ri_zero(i8* %p) { +entry: + %0 = load i8, i8* %p, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrh_ri_zero +; CHECK: ldrh r0, [r0] +define i32 @ldrh_ri_zero(i16* %p) { +entry: + %0 = load i16, i16* %p, align 2 + %conv = zext i16 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldr_ri_zero +; CHECK: ldr r0, [r0] +define i32 @ldr_ri_zero(i32* %p) { +entry: + %0 = load i32, i32* %p, align 4 + ret i32 %0 +} + +; CHECK-LABEL: strb_ri_zero +; CHECK: strb r1, [r0] +define void @strb_ri_zero(i8* %p, i32 %x) { +entry: + %conv = trunc i32 %x to i8 + store i8 %conv, i8* %p, align 1 + ret void +} + +; CHECK-LABEL: strh_ri_zero +; CHECK: strh r1, [r0] +define void @strh_ri_zero(i16* %p, i32 %x) { +entry: + %conv = trunc i32 %x to i16 + store i16 %conv, i16* %p, align 2 + ret void +} + +; CHECK-LABEL: str_ri_zero +; CHECK: str r1, [r0] +define void @str_ri_zero(i32* %p, i32 %x) { +entry: + store i32 %x, i32* %p, align 4 + ret void +} + + +; Maximum Thumb-1 immediate offset + +; CHECK-LABEL: ldrsb_ri_t1_max +; CHECK-T1: movs r1, #31 +; CHECK-T1: ldrsb r0, [r0, r1] +; CHECK-T2: ldrsb.w r0, [r0, #31] +define i32 @ldrsb_ri_t1_max(i8* %p) { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 31 + %0 = load i8, i8* %arrayidx, align 1 + %conv = sext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrsh_ri_t1_max +; CHECK-T1: movs r1, #62 +; CHECK-T1: ldrsh r0, [r0, r1] +; CHECK-T2: ldrsh.w r0, [r0, #62] +define i32 @ldrsh_ri_t1_max(i16* %p) { +entry: + %arrayidx = getelementptr inbounds i16, i16* %p, i32 31 + %0 = load i16, i16* %arrayidx, align 2 + %conv = sext i16 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrb_ri_t1_max +; CHECK: ldrb r0, [r0, #31] +define i32 @ldrb_ri_t1_max(i8* %p) { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 31 + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrh_ri_t1_max +; CHECK: ldrh r0, [r0, #62] +define i32 @ldrh_ri_t1_max(i16* %p) { +entry: + %arrayidx = getelementptr inbounds i16, i16* %p, i32 31 + %0 = load i16, i16* %arrayidx, align 2 + %conv = zext i16 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldr_ri_t1_max +; CHECK: ldr r0, [r0, #124] +define i32 @ldr_ri_t1_max(i32* %p) { +entry: + %arrayidx = getelementptr inbounds i32, i32* %p, i32 31 + %0 = load i32, i32* %arrayidx, align 4 + ret i32 %0 +} + +; CHECK-LABEL: strb_ri_t1_max +; CHECK: strb r1, [r0, #31] +define void @strb_ri_t1_max(i8* %p, i32 %x) { +entry: + %conv = trunc i32 %x to i8 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 31 + store i8 %conv, i8* %arrayidx, align 1 + ret void +} + +; CHECK-LABEL: strh_ri_t1_max +; CHECK: strh r1, [r0, #62] +define void @strh_ri_t1_max(i16* %p, i32 %x) { +entry: + %conv = trunc i32 %x to i16 + %arrayidx = getelementptr inbounds i16, i16* %p, i32 31 + store i16 %conv, i16* %arrayidx, align 2 + ret void +} + +; CHECK-LABEL: str_ri_t1_max +; CHECK: str r1, [r0, #124] +define void @str_ri_t1_max(i32* %p, i32 %x) { +entry: + %arrayidx = getelementptr inbounds i32, i32* %p, i32 31 + store i32 %x, i32* %arrayidx, align 4 + ret void +} + + +; One past maximum Thumb-1 immediate offset + +; CHECK-LABEL: ldrsb_ri_t1_too_big +; CHECK-T1: movs r1, #32 +; CHECK-T1: ldrsb r0, [r0, r1] +; CHECK-T2: ldrsb.w r0, [r0, #32] +define i32 @ldrsb_ri_t1_too_big(i8* %p) { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 32 + %0 = load i8, i8* %arrayidx, align 1 + %conv = sext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrsh_ri_t1_too_big +; CHECK-T1: movs r1, #64 +; CHECK-T1: ldrsh r0, [r0, r1] +; CHECK-T2: ldrsh.w r0, [r0, #64] +define i32 @ldrsh_ri_t1_too_big(i16* %p) { +entry: + %arrayidx = getelementptr inbounds i16, i16* %p, i32 32 + %0 = load i16, i16* %arrayidx, align 2 + %conv = sext i16 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrb_ri_t1_too_big +; CHECK-T1: movs r1, #32 +; CHECK-T1: ldrb r0, [r0, r1] +; CHECK-T2: ldrb.w r0, [r0, #32] +define i32 @ldrb_ri_t1_too_big(i8* %p) { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 32 + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrh_ri_t1_too_big +; CHECK-T1: movs r1, #64 +; CHECK-T1: ldrh r0, [r0, r1] +; CHECK-T2: ldrh.w r0, [r0, #64] +define i32 @ldrh_ri_t1_too_big(i16* %p) { entry: - %tmp = load i8, i8* %p ; <i8> [#uses=1] - %tmp1 = sext i8 %tmp to i32 ; <i32> [#uses=1] - ret i32 %tmp1 + %arrayidx = getelementptr inbounds i16, i16* %p, i32 32 + %0 = load i16, i16* %arrayidx, align 2 + %conv = zext i16 %0 to i32 + ret i32 %conv } -define i32 @f2(i8* %p) { +; CHECK-LABEL: ldr_ri_t1_too_big +; CHECK-T1: movs r1, #128 +; CHECK-T1: ldr r0, [r0, r1] +; CHECK-T2: ldr.w r0, [r0, #128] +define i32 @ldr_ri_t1_too_big(i32* %p) { entry: - %tmp = load i8, i8* %p ; <i8> [#uses=1] - %tmp2 = zext i8 %tmp to i32 ; <i32> [#uses=1] - ret i32 %tmp2 + %arrayidx = getelementptr inbounds i32, i32* %p, i32 32 + %0 = load i32, i32* %arrayidx, align 4 + ret i32 %0 } -define i32 @f3(i16* %p) { +; CHECK-LABEL: strb_ri_t1_too_big +; CHECK-T1: movs r2, #32 +; CHECK-T1: strb r1, [r0, r2] +; CHECK-T2: strb.w r1, [r0, #32] +define void @strb_ri_t1_too_big(i8* %p, i32 %x) { entry: - %tmp = load i16, i16* %p ; <i16> [#uses=1] - %tmp3 = sext i16 %tmp to i32 ; <i32> [#uses=1] - ret i32 %tmp3 + %conv = trunc i32 %x to i8 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 32 + store i8 %conv, i8* %arrayidx, align 1 + ret void } -define i32 @f4(i16* %p) { +; CHECK-LABEL: strh_ri_t1_too_big +; CHECK-T1: movs r2, #64 +; CHECK-T1: strh r1, [r0, r2] +; CHECK-T2: strh.w r1, [r0, #64] +define void @strh_ri_t1_too_big(i16* %p, i32 %x) { entry: - %tmp = load i16, i16* %p ; <i16> [#uses=1] - %tmp4 = zext i16 %tmp to i32 ; <i32> [#uses=1] - ret i32 %tmp4 + %conv = trunc i32 %x to i16 + %arrayidx = getelementptr inbounds i16, i16* %p, i32 32 + store i16 %conv, i16* %arrayidx, align 2 + ret void } -; CHECK: ldrsb -; CHECK: ldrb -; CHECK: ldrsh -; CHECK: ldrh +; CHECK-LABEL: str_ri_t1_too_big +; CHECK-T1: movs r2, #128 +; CHECK-T1: str r1, [r0, r2] +; CHECK-T2: str.w r1, [r0, #128] +define void @str_ri_t1_too_big(i32* %p, i32 %x) { +entry: + %arrayidx = getelementptr inbounds i32, i32* %p, i32 32 + store i32 %x, i32* %arrayidx, align 4 + ret void +} + + +; Maximum Thumb-2 immediate offset + +; CHECK-LABEL: ldrsb_ri_t2_max +; CHECK-T1: ldr r1, .LCP +; CHECK-T1: ldrsb r0, [r0, r1] +; CHECK-T2: ldrsb.w r0, [r0, #4095] +define i32 @ldrsb_ri_t2_max(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095 + %0 = load i8, i8* %add.ptr, align 1 + %conv = sext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrsh_ri_t2_max +; CHECK-T1: ldr r1, .LCP +; CHECK-T1: ldrsh r0, [r0, r1] +; CHECK-T2: ldrsh.w r0, [r0, #4095] +define i32 @ldrsh_ri_t2_max(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095 + %0 = bitcast i8* %add.ptr to i16* + %1 = load i16, i16* %0, align 2 + %conv = sext i16 %1 to i32 + ret i32 %conv +} +; CHECK-LABEL: ldrb_ri_t2_max +; CHECK-T1: ldr r1, .LCP +; CHECK-T1: ldrb r0, [r0, r1] +; CHECK-T2: ldrb.w r0, [r0, #4095] +define i32 @ldrb_ri_t2_max(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095 + %0 = load i8, i8* %add.ptr, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrh_ri_t2_max +; CHECK-T1: ldr r1, .LCP +; CHECK-T1: ldrh r0, [r0, r1] +; CHECK-T2: ldrh.w r0, [r0, #4095] +define i32 @ldrh_ri_t2_max(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095 + %0 = bitcast i8* %add.ptr to i16* + %1 = load i16, i16* %0, align 2 + %conv = zext i16 %1 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldr_ri_t2_max +; CHECK-T1: ldr r1, .LCP +; CHECK-T1: ldr r0, [r0, r1] +; CHECK-T2: ldr.w r0, [r0, #4095] +define i32 @ldr_ri_t2_max(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095 + %0 = bitcast i8* %add.ptr to i32* + %1 = load i32, i32* %0, align 4 + ret i32 %1 +} + +; CHECK-LABEL: strb_ri_t2_max +; CHECK-T1: ldr r2, .LCP +; CHECK-T1: strb r1, [r0, r2] +; CHECK-T2: strb.w r1, [r0, #4095] +define void @strb_ri_t2_max(i8* %p, i32 %x) { +entry: + %conv = trunc i32 %x to i8 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095 + store i8 %conv, i8* %add.ptr, align 1 + ret void +} + +; CHECK-LABEL: strh_ri_t2_max +; CHECK-T1: ldr r2, .LCP +; CHECK-T1: strh r1, [r0, r2] +; CHECK-T2: strh.w r1, [r0, #4095] +define void @strh_ri_t2_max(i8* %p, i32 %x) { +entry: + %conv = trunc i32 %x to i16 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095 + %0 = bitcast i8* %add.ptr to i16* + store i16 %conv, i16* %0, align 2 + ret void +} + +; CHECK-LABEL: str_ri_t2_max +; CHECK-T1: ldr r2, .LCP +; CHECK-T1: str r1, [r0, r2] +; CHECK-T2: str.w r1, [r0, #4095] +define void @str_ri_t2_max(i8* %p, i32 %x) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4095 + %0 = bitcast i8* %add.ptr to i32* + store i32 %x, i32* %0, align 4 + ret void +} + + +; One past maximum Thumb-2 immediate offset + +; CHECK-LABEL: ldrsb_ri_t2_too_big +; CHECK-T1: movs r1, #1 +; CHECK-T1: lsls r1, r1, #12 +; CHECK-T2: mov.w r1, #4096 +; CHECK: ldrsb r0, [r0, r1] +define i32 @ldrsb_ri_t2_too_big(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096 + %0 = load i8, i8* %add.ptr, align 1 + %conv = sext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrsh_ri_t2_too_big +; CHECK-T1: movs r1, #1 +; CHECK-T1: lsls r1, r1, #12 +; CHECK-T2: mov.w r1, #4096 +; CHECK: ldrsh r0, [r0, r1] +define i32 @ldrsh_ri_t2_too_big(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096 + %0 = bitcast i8* %add.ptr to i16* + %1 = load i16, i16* %0, align 2 + %conv = sext i16 %1 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrb_ri_t2_too_big +; CHECK-T1: movs r1, #1 +; CHECK-T1: lsls r1, r1, #12 +; CHECK-T2: mov.w r1, #4096 +; CHECK: ldrb r0, [r0, r1] +define i32 @ldrb_ri_t2_too_big(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096 + %0 = load i8, i8* %add.ptr, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldrh_ri_t2_too_big +; CHECK-T1: movs r1, #1 +; CHECK-T1: lsls r1, r1, #12 +; CHECK-T2: mov.w r1, #4096 +; CHECK: ldrh r0, [r0, r1] +define i32 @ldrh_ri_t2_too_big(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096 + %0 = bitcast i8* %add.ptr to i16* + %1 = load i16, i16* %0, align 2 + %conv = zext i16 %1 to i32 + ret i32 %conv +} + +; CHECK-LABEL: ldr_ri_t2_too_big +; CHECK-T1: movs r1, #1 +; CHECK-T1: lsls r1, r1, #12 +; CHECK-T2: mov.w r1, #4096 +; CHECK: ldr r0, [r0, r1] +define i32 @ldr_ri_t2_too_big(i8* %p) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096 + %0 = bitcast i8* %add.ptr to i32* + %1 = load i32, i32* %0, align 4 + ret i32 %1 +} + +; CHECK-LABEL: strb_ri_t2_too_big +; CHECK-T1: movs r2, #1 +; CHECK-T1: lsls r2, r2, #12 +; CHECK-T2: mov.w r2, #4096 +; CHECK: strb r1, [r0, r2] +define void @strb_ri_t2_too_big(i8* %p, i32 %x) { +entry: + %conv = trunc i32 %x to i8 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096 + store i8 %conv, i8* %add.ptr, align 1 + ret void +} + +; CHECK-LABEL: strh_ri_t2_too_big +; CHECK-T1: movs r2, #1 +; CHECK-T1: lsls r2, r2, #12 +; CHECK-T2: mov.w r2, #4096 +; CHECK: strh r1, [r0, r2] +define void @strh_ri_t2_too_big(i8* %p, i32 %x) { +entry: + %conv = trunc i32 %x to i16 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096 + %0 = bitcast i8* %add.ptr to i16* + store i16 %conv, i16* %0, align 2 + ret void +} + +; CHECK-LABEL: str_ri_t2_too_big +; CHECK-T1: movs r2, #1 +; CHECK-T1: lsls r2, r2, #12 +; CHECK-T2: mov.w r2, #4096 +; CHECK: str r1, [r0, r2] +define void @str_ri_t2_too_big(i8* %p, i32 %x) { +entry: + %add.ptr = getelementptr inbounds i8, i8* %p, i32 4096 + %0 = bitcast i8* %add.ptr to i32* + store i32 %x, i32* %0, align 4 + ret void +} diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll index 1f92ff4e1192..611cba6ed1fc 100644 --- a/test/CodeGen/ARM/machine-cse-cmp.ll +++ b/test/CodeGen/ARM/machine-cse-cmp.ll @@ -27,7 +27,7 @@ define void @f2() nounwind ssp { entry: ; CHECK-LABEL: f2: ; CHECK: cmp -; CHECK: poplt +; CHECK: bxlt ; CHECK-NOT: cmp ; CHECK: movle %0 = load i32, i32* @foo, align 4 diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll index 4ea26e1c59a3..d874884dcb39 100644 --- a/test/CodeGen/ARM/memcpy-inline.ll +++ b/test/CodeGen/ARM/memcpy-inline.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -pre-RA-sched=source -disable-post-ra | FileCheck %s -; RUN: llc < %s -mtriple=thumbv6m-apple-ios -mcpu=cortex-m0 -pre-RA-sched=source -disable-post-ra | FileCheck %s -check-prefix=CHECK-T1 +; RUN: llc < %s -mtriple=thumbv6m-apple-ios -mcpu=cortex-m0 -pre-RA-sched=source -disable-post-ra -mattr=+strict-align | FileCheck %s -check-prefix=CHECK-T1 %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } @src = external global %struct.x diff --git a/test/CodeGen/ARM/memcpy-ldm-stm.ll b/test/CodeGen/ARM/memcpy-ldm-stm.ll new file mode 100644 index 000000000000..2ebe7ed5b146 --- /dev/null +++ b/test/CodeGen/ARM/memcpy-ldm-stm.ll @@ -0,0 +1,94 @@ +; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | \ +; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECKV6 +; RUN: llc -mtriple=thumbv6m-eabi -O=0 -verify-machineinstrs %s -o - | \ +; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECKV6 +; RUN: llc -mtriple=thumbv7a-eabi -mattr=-neon -verify-machineinstrs %s -o - | \ +; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECKV7 +; RUN: llc -mtriple=armv7a-eabi -mattr=-neon -verify-machineinstrs %s -o - | \ +; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECKV7 + +@d = external global [64 x i32] +@s = external global [64 x i32] + +; Function Attrs: nounwind +define void @t1() #0 { +entry: +; CHECK-LABEL: t1: +; CHECKV6: ldr [[LB:r[0-7]]], +; CHECKV6-NEXT: ldr [[SB:r[0-7]]], +; We use '[rl0-9]+' to allow 'r0'..'r12', 'lr' +; CHECKV7: movt [[LB:[rl0-9]+]], :upper16:d +; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s +; CHECK-NEXT: ldm{{(\.w)?}} [[LB]]!, +; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, +; Think of the monstrosity '{{\[}}[[LB]]]' as '[ [[LB]] ]' without the spaces. +; CHECK-NEXT: ldrb{{(\.w)?}} {{.*}}, {{\[}}[[LB]]] +; CHECK-NEXT: strb{{(\.w)?}} {{.*}}, {{\[}}[[SB]]] + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([64 x i32]* @s to i8*), i8* bitcast ([64 x i32]* @d to i8*), i32 17, i32 4, i1 false) + ret void +} + +; Function Attrs: nounwind +define void @t2() #0 { +entry: +; CHECK-LABEL: t2: +; CHECKV6: ldr [[LB:r[0-7]]], +; CHECKV6-NEXT: ldr [[SB:r[0-7]]], +; CHECKV7: movt [[LB:[rl0-9]+]], :upper16:d +; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s +; CHECK-NEXT: ldm{{(\.w)?}} [[LB]]!, +; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, +; CHECK-NEXT: ldrh{{(\.w)?}} {{.*}}, {{\[}}[[LB]]] +; CHECK-NEXT: ldrb{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #2] +; CHECK-NEXT: strb{{(\.w)?}} {{.*}}, {{\[}}[[SB]], #2] +; CHECK-NEXT: strh{{(\.w)?}} {{.*}}, {{\[}}[[SB]]] + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* bitcast ([64 x i32]* @s to i8*), i8* bitcast ([64 x i32]* @d to i8*), i32 15, i32 4, i1 false) + ret void +} + +; PR23768 +%struct.T = type { i8, i64, i8 } + +@copy = external global %struct.T, align 8 +@etest = external global %struct.T, align 8 + +define void @t3() { + call void @llvm.memcpy.p0i8.p0i8.i32( + i8* getelementptr inbounds (%struct.T, %struct.T* @copy, i32 0, i32 0), + i8* getelementptr inbounds (%struct.T, %struct.T* @etest, i32 0, i32 0), + i32 24, i32 8, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32( + i8* getelementptr inbounds (%struct.T, %struct.T* @copy, i32 0, i32 0), + i8* getelementptr inbounds (%struct.T, %struct.T* @etest, i32 0, i32 0), + i32 24, i32 8, i1 false) + ret void +} + +%struct.S = type { [12 x i32] } + +; CHECK-LABEL: test3 +define void @test3(%struct.S* %d, %struct.S* %s) #0 { + %1 = bitcast %struct.S* %d to i8* + %2 = bitcast %struct.S* %s to i8* + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %2, i32 48, i32 4, i1 false) +; 3 ldm/stm pairs in v6; 2 in v7 +; CHECK: ldm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST1:{.*}]] +; CHECK: stm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST1]] +; CHECK: ldm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST2:{.*}]] +; CHECK: stm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST2]] +; CHECKV6: ldm {{r[0-7]!?}}, [[REGLIST3:{.*}]] +; CHECKV6: stm {{r[0-7]!?}}, [[REGLIST3]] +; CHECKV7-NOT: ldm +; CHECKV7-NOT: stm + %arrayidx = getelementptr inbounds %struct.S, %struct.S* %s, i32 0, i32 0, i32 1 + tail call void @g(i32* %arrayidx) #3 + ret void +} + +declare void @g(i32*) + +; Set "no-frame-pointer-elim" to increase register pressure +attributes #0 = { "no-frame-pointer-elim"="true" } + +; Function Attrs: nounwind +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1 diff --git a/test/CodeGen/ARM/memfunc.ll b/test/CodeGen/ARM/memfunc.ll index 5223983a7f30..66743f3e9d5e 100644 --- a/test/CodeGen/ARM/memfunc.ll +++ b/test/CodeGen/ARM/memfunc.ll @@ -1,79 +1,95 @@ -; RUN: llc < %s -mtriple=armv7-apple-ios -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-IOS --check-prefix=CHECK -; RUN: llc < %s -mtriple=thumbv7m-none-macho -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-DARWIN --check-prefix=CHECK -; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK -; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK +; RUN: llc < %s -mtriple=armv7-apple-ios -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-IOS +; RUN: llc < %s -mtriple=thumbv7m-none-macho -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-DARWIN +; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI define void @f1(i8* %dest, i8* %src) { entry: ; CHECK-LABEL: f1 - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: bl memmove call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 0, i1 false) - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 0, i1 false) ; EABI memset swaps arguments ; CHECK-IOS: mov r1, #1 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: movs r1, #1 - ; CHECK-DARWIN: memset + ; CHECK-DARWIN: bl _memset ; CHECK-EABI: mov r2, #1 - ; CHECK-EABI: __aeabi_memset + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 0, i1 false) ; EABI uses memclr if value set to 0 ; CHECK-IOS: mov r1, #0 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: movs r1, #0 - ; CHECK-DARWIN: memset - ; CHECK-EABI: __aeabi_memclr + ; CHECK-DARWIN: bl _memset + ; CHECK-EABI: bl __aeabi_memclr + ; CHECK-GNUEABI: bl memset call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 0, i1 false) - + ; EABI uses aligned function variants if possible - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove4 + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove4 + ; CHECK-GNUEABI: bl memmove call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 4, i1 false) - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy4 + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy4 + ; CHECK-GNUEABI: bl memcpy call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 4, i1 false) - ; CHECK-IOS: memset - ; CHECK-DARWIN: memset - ; CHECK-EABI: __aeabi_memset4 + ; CHECK-IOS: bl _memset + ; CHECK-DARWIN: bl _memset + ; CHECK-EABI: bl __aeabi_memset4 + ; CHECK-GNUEABI: bl memset call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 4, i1 false) - ; CHECK-IOS: memset - ; CHECK-DARWIN: memset - ; CHECK-EABI: __aeabi_memclr4 + ; CHECK-IOS: bl _memset + ; CHECK-DARWIN: bl _memset + ; CHECK-EABI: bl __aeabi_memclr4 + ; CHECK-GNUEABI: bl memset call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 4, i1 false) - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove8 + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove8 + ; CHECK-GNUEABI: bl memmove call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 8, i1 false) - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy8 + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy8 + ; CHECK-GNUEABI: bl memcpy call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 500, i32 8, i1 false) - ; CHECK-IOS: memset - ; CHECK-DARWIN: memset - ; CHECK-EABI: __aeabi_memset8 + ; CHECK-IOS: bl _memset + ; CHECK-DARWIN: bl _memset + ; CHECK-EABI: bl __aeabi_memset8 + ; CHECK-GNUEABI: bl memset call void @llvm.memset.p0i8.i32(i8* %dest, i8 1, i32 500, i32 8, i1 false) - ; CHECK-IOS: memset - ; CHECK-DARWIN: memset - ; CHECK-EABI: __aeabi_memclr8 + ; CHECK-IOS: bl _memset + ; CHECK-DARWIN: bl _memset + ; CHECK-EABI: bl __aeabi_memclr8 + ; CHECK-GNUEABI: bl memset call void @llvm.memset.p0i8.i32(i8* %dest, i8 0, i32 500, i32 8, i1 false) unreachable @@ -86,32 +102,38 @@ entry: ; IOS (ARMv7) should 8-byte align, others should 4-byte align ; CHECK-IOS: add r1, sp, #32 - ; CHECK-IOS: memmove + ; CHECK-IOS: bl _memmove ; CHECK-DARWIN: add r1, sp, #28 - ; CHECK-DARWIN: memmove + ; CHECK-DARWIN: bl _memmove ; CHECK-EABI: add r1, sp, #28 - ; CHECK-EABI: __aeabi_memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: add r1, sp, #28 + ; CHECK-GNUEABI: bl memmove %arr0 = alloca [9 x i8], align 1 %0 = bitcast [9 x i8]* %arr0 to i8* call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) ; CHECK: add r1, sp, #16 - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy %arr1 = alloca [9 x i8], align 1 %1 = bitcast [9 x i8]* %arr1 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) ; CHECK-IOS: mov r0, sp ; CHECK-IOS: mov r1, #1 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: add r0, sp, #4 ; CHECK-DARWIN: movs r1, #1 - ; CHECK-DARWIN: memset + ; CHECK-DARWIN: bl _memset ; CHECK-EABI: add r0, sp, #4 ; CHECK-EABI: mov r2, #1 - ; CHECK-EABI: __aeabi_memset + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: add r0, sp, #4 + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset %arr2 = alloca [9 x i8], align 1 %2 = bitcast [9 x i8]* %arr2 to i8* call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) @@ -125,28 +147,32 @@ entry: ; CHECK-LABEL: f3 ; CHECK: {{add(.w)? r1, sp, #17|sub(.w)? r1, r7, #15}} - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: bl memmove %arr0 = alloca [7 x i8], align 1 %0 = bitcast [7 x i8]* %arr0 to i8* call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r1, sp, #10}} - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy %arr1 = alloca [7 x i8], align 1 %1 = bitcast [7 x i8]* %arr1 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r0, sp, #3}} ; CHECK-IOS: mov r1, #1 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: movs r1, #1 - ; CHECK-DARWIN: memset + ; CHECK-DARWIN: bl _memset ; CHECK-EABI: mov r2, #1 - ; CHECK-EABI: __aeabi_memset + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset %arr2 = alloca [7 x i8], align 1 %2 = bitcast [7 x i8]* %arr2 to i8* call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) @@ -160,28 +186,32 @@ entry: ; CHECK-LABEL: f4 ; CHECK: {{add(.w)? r., sp, #23|sub(.w)? r., r7, #17}} - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: bl memmove %arr0 = alloca [9 x i8], align 1 %0 = getelementptr inbounds [9 x i8], [9 x i8]* %arr0, i32 0, i32 4 call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(10|14)}} - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy %arr1 = alloca [9 x i8], align 1 %1 = getelementptr inbounds [9 x i8], [9 x i8]* %arr1, i32 0, i32 4 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(1|5)}} ; CHECK-IOS: mov r1, #1 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: movs r1, #1 - ; CHECK-DARWIN: memset + ; CHECK-DARWIN: bl _memset ; CHECK-EABI: mov r2, #1 - ; CHECK-EABI: __aeabi_memset + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset %arr2 = alloca [9 x i8], align 1 %2 = getelementptr inbounds [9 x i8], [9 x i8]* %arr2, i32 0, i32 4 call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) @@ -195,28 +225,32 @@ entry: ; CHECK-LABEL: f5 ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}} - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: bl memmove %arr0 = alloca [13 x i8], align 1 %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 1 call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(10|14)}} - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy %arr1 = alloca [13 x i8], align 1 %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 1 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(1|5)}} ; CHECK-IOS: mov r1, #1 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: movs r1, #1 - ; CHECK-DARWIN: memset + ; CHECK-DARWIN: bl _memset ; CHECK-EABI: mov r2, #1 - ; CHECK-EABI: __aeabi_memset + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset %arr2 = alloca [13 x i8], align 1 %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 1 call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) @@ -230,28 +264,32 @@ entry: ; CHECK-LABEL: f6 ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #25}} - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: bl memmove %arr0 = alloca [13 x i8], align 1 %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 %i call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(10|14)}} - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy %arr1 = alloca [13 x i8], align 1 %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 %i call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(1|5)}} ; CHECK-IOS: mov r1, #1 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: movs r1, #1 - ; CHECK-DARWIN: memset + ; CHECK-DARWIN: bl _memset ; CHECK-EABI: mov r2, #1 - ; CHECK-EABI: __aeabi_memset + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset %arr2 = alloca [13 x i8], align 1 %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 %i call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) @@ -265,28 +303,32 @@ entry: ; CHECK-LABEL: f7 ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}} - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: bl memmove %arr0 = alloca [13 x i8], align 1 %0 = getelementptr [13 x i8], [13 x i8]* %arr0, i32 0, i32 4 call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(10|14)}} - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy %arr1 = alloca [13 x i8], align 1 %1 = getelementptr [13 x i8], [13 x i8]* %arr1, i32 0, i32 4 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(1|5)}} ; CHECK-IOS: mov r1, #1 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: movs r1, #1 - ; CHECK-DARWIN: memset + ; CHECK-DARWIN: bl _memset ; CHECK-EABI: mov r2, #1 - ; CHECK-EABI: __aeabi_memset + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset %arr2 = alloca [13 x i8], align 1 %2 = getelementptr [13 x i8], [13 x i8]* %arr2, i32 0, i32 4 call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) @@ -300,28 +342,32 @@ entry: ; CHECK-LABEL: f8 ; CHECK: {{add(.w)? r., sp, #27|sub(.w)? r., r7, #21}} - ; CHECK-IOS: memmove - ; CHECK-DARWIN: memmove - ; CHECK-EABI: __aeabi_memmove + ; CHECK-IOS: bl _memmove + ; CHECK-DARWIN: bl _memmove + ; CHECK-EABI: bl __aeabi_memmove + ; CHECK-GNUEABI: bl memmove %arr0 = alloca [13 x i8], align 1 %0 = getelementptr inbounds [13 x i8], [13 x i8]* %arr0, i32 0, i32 16 call void @llvm.memmove.p0i8.p0i8.i32(i8* %dest, i8* %0, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(10|14)}} - ; CHECK-IOS: memcpy - ; CHECK-DARWIN: memcpy - ; CHECK-EABI: __aeabi_memcpy + ; CHECK-IOS: bl _memcpy + ; CHECK-DARWIN: bl _memcpy + ; CHECK-EABI: bl __aeabi_memcpy + ; CHECK-GNUEABI: bl memcpy %arr1 = alloca [13 x i8], align 1 %1 = getelementptr inbounds [13 x i8], [13 x i8]* %arr1, i32 0, i32 16 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %1, i32 %n, i32 0, i1 false) ; CHECK: {{add(.w)? r., sp, #(1|5)}} ; CHECK-IOS: mov r1, #1 - ; CHECK-IOS: memset + ; CHECK-IOS: bl _memset ; CHECK-DARWIN: movs r1, #1 - ; CHECK-DARWIN: memset + ; CHECK-DARWIN: bl _memset ; CHECK-EABI: mov r2, #1 - ; CHECK-EABI: __aeabi_memset + ; CHECK-EABI: bl __aeabi_memset + ; CHECK-GNUEABI: mov r1, #1 + ; CHECK-GNUEABI: bl memset %arr2 = alloca [13 x i8], align 1 %2 = getelementptr inbounds [13 x i8], [13 x i8]* %arr2, i32 0, i32 16 call void @llvm.memset.p0i8.i32(i8* %2, i8 1, i32 %n, i32 0, i1 false) @@ -357,6 +403,7 @@ entry: ; CHECK-IOS: .align 3 ; CHECK-DARWIN: .align 2 ; CHECK-EABI: .align 2 +; CHECK-GNUEABI: .align 2 ; CHECK: arr2: ; CHECK: {{\.section.+foo,bar}} ; CHECK-NOT: .align diff --git a/test/CodeGen/ARM/minmax.ll b/test/CodeGen/ARM/minmax.ll new file mode 100644 index 000000000000..78e8922fba0e --- /dev/null +++ b/test/CodeGen/ARM/minmax.ll @@ -0,0 +1,193 @@ +; RUN: llc < %s -mtriple=armv8-linux-gnu -mattr=+neon | FileCheck %s + +; CHECK-LABEL: t1 +; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <4 x i32> @t1(<4 x i32> %a, <4 x i32> %b) { + %t1 = icmp sgt <4 x i32> %a, %b + %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %t2 +} + +; CHECK-LABEL: t2 +; CHECK: vmin.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <4 x i32> @t2(<4 x i32> %a, <4 x i32> %b) { + %t1 = icmp slt <4 x i32> %a, %b + %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %t2 +} + +; CHECK-LABEL: t3 +; CHECK: vmax.u32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <4 x i32> @t3(<4 x i32> %a, <4 x i32> %b) { + %t1 = icmp ugt <4 x i32> %a, %b + %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %t2 +} + +; CHECK-LABEL: t4 +; CHECK: vmin.u32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <4 x i32> @t4(<4 x i32> %a, <4 x i32> %b) { + %t1 = icmp ult <4 x i32> %a, %b + %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b + ret <4 x i32> %t2 +} + +; CHECK-LABEL: t5 +; CHECK: vmax.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <2 x i32> @t5(<2 x i32> %a, <2 x i32> %b) { + %t1 = icmp sgt <2 x i32> %a, %b + %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b + ret <2 x i32> %t2 +} + +; CHECK-LABEL: t6 +; CHECK: vmin.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <2 x i32> @t6(<2 x i32> %a, <2 x i32> %b) { + %t1 = icmp slt <2 x i32> %a, %b + %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b + ret <2 x i32> %t2 +} + +; CHECK-LABEL: t7 +; CHECK: vmax.u32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <2 x i32> @t7(<2 x i32> %a, <2 x i32> %b) { + %t1 = icmp ugt <2 x i32> %a, %b + %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b + ret <2 x i32> %t2 +} + +; CHECK-LABEL: t8 +; CHECK: vmin.u32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <2 x i32> @t8(<2 x i32> %a, <2 x i32> %b) { + %t1 = icmp ult <2 x i32> %a, %b + %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b + ret <2 x i32> %t2 +} + +; CHECK-LABEL: t9 +; CHECK: vmax.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <8 x i16> @t9(<8 x i16> %a, <8 x i16> %b) { + %t1 = icmp sgt <8 x i16> %a, %b + %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %t2 +} + +; CHECK-LABEL: t10 +; CHECK: vmin.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <8 x i16> @t10(<8 x i16> %a, <8 x i16> %b) { + %t1 = icmp slt <8 x i16> %a, %b + %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %t2 +} + +; CHECK-LABEL: t11 +; CHECK: vmax.u16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <8 x i16> @t11(<8 x i16> %a, <8 x i16> %b) { + %t1 = icmp ugt <8 x i16> %a, %b + %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %t2 +} + +; CHECK-LABEL: t12 +; CHECK: vmin.u16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <8 x i16> @t12(<8 x i16> %a, <8 x i16> %b) { + %t1 = icmp ult <8 x i16> %a, %b + %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b + ret <8 x i16> %t2 +} + +; CHECK-LABEL: t13 +; CHECK: vmax.s16 +define <4 x i16> @t13(<4 x i16> %a, <4 x i16> %b) { + %t1 = icmp sgt <4 x i16> %a, %b + %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b + ret <4 x i16> %t2 +} + +; CHECK-LABEL: t14 +; CHECK: vmin.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <4 x i16> @t14(<4 x i16> %a, <4 x i16> %b) { + %t1 = icmp slt <4 x i16> %a, %b + %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b + ret <4 x i16> %t2 +} + +; CHECK-LABEL: t15 +; CHECK: vmax.u16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <4 x i16> @t15(<4 x i16> %a, <4 x i16> %b) { + %t1 = icmp ugt <4 x i16> %a, %b + %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b + ret <4 x i16> %t2 +} + +; CHECK-LABEL: t16 +; CHECK: vmin.u16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <4 x i16> @t16(<4 x i16> %a, <4 x i16> %b) { + %t1 = icmp ult <4 x i16> %a, %b + %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b + ret <4 x i16> %t2 +} + +; CHECK-LABEL: t17 +; CHECK: vmax.s8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <16 x i8> @t17(<16 x i8> %a, <16 x i8> %b) { + %t1 = icmp sgt <16 x i8> %a, %b + %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %t2 +} + +; CHECK-LABEL: t18 +; CHECK: vmin.s8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <16 x i8> @t18(<16 x i8> %a, <16 x i8> %b) { + %t1 = icmp slt <16 x i8> %a, %b + %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %t2 +} + +; CHECK-LABEL: t19 +; CHECK: vmax.u8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <16 x i8> @t19(<16 x i8> %a, <16 x i8> %b) { + %t1 = icmp ugt <16 x i8> %a, %b + %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %t2 +} + +; CHECK-LABEL: t20 +; CHECK: vmin.u8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} +define <16 x i8> @t20(<16 x i8> %a, <16 x i8> %b) { + %t1 = icmp ult <16 x i8> %a, %b + %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b + ret <16 x i8> %t2 +} + +; CHECK-LABEL: t21 +; CHECK: vmax.s8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <8 x i8> @t21(<8 x i8> %a, <8 x i8> %b) { + %t1 = icmp sgt <8 x i8> %a, %b + %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b + ret <8 x i8> %t2 +} + +; CHECK-LABEL: t22 +; CHECK: vmin.s8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <8 x i8> @t22(<8 x i8> %a, <8 x i8> %b) { + %t1 = icmp slt <8 x i8> %a, %b + %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b + ret <8 x i8> %t2 +} + +; CHECK-LABEL: t23 +; CHECK: vmax.u8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <8 x i8> @t23(<8 x i8> %a, <8 x i8> %b) { + %t1 = icmp ugt <8 x i8> %a, %b + %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b + ret <8 x i8> %t2 +} + +; CHECK-LABEL: t24 +; CHECK: vmin.u8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +define <8 x i8> @t24(<8 x i8> %a, <8 x i8> %b) { + %t1 = icmp ult <8 x i8> %a, %b + %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b + ret <8 x i8> %t2 +} diff --git a/test/CodeGen/ARM/neon_minmax.ll b/test/CodeGen/ARM/neon_minmax.ll index 84e4b303c16d..883522a829a5 100644 --- a/test/CodeGen/ARM/neon_minmax.ll +++ b/test/CodeGen/ARM/neon_minmax.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=-neon %s -o - define float @fmin_ole(float %x) nounwind { ;CHECK-LABEL: fmin_ole: diff --git a/test/CodeGen/ARM/neon_spill.ll b/test/CodeGen/ARM/neon_spill.ll index 04f08f43840f..f9282f93f4d2 100644 --- a/test/CodeGen/ARM/neon_spill.ll +++ b/test/CodeGen/ARM/neon_spill.ll @@ -22,7 +22,7 @@ declare arm_aapcs_vfpcc %2* @func3(%2*, %2*, i32) declare arm_aapcs_vfpcc %2** @func4() define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 { - call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind + call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind %2 = call arm_aapcs_vfpcc %0** @func2() nounwind %3 = load %0*, %0** %2, align 4 store float 0.000000e+00, float* undef, align 4 @@ -40,10 +40,10 @@ define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 { %10 = fmul float undef, 2.000000e+05 %11 = fadd float %10, -1.000000e+05 store float %11, float* undef, align 4 - call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind + call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind ret void } -declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind declare arm_aapcs_vfpcc i32 @rand() diff --git a/test/CodeGen/ARM/neon_vabs.ll b/test/CodeGen/ARM/neon_vabs.ll index 7a02512198be..d32e7b78879b 100644 --- a/test/CodeGen/ARM/neon_vabs.ll +++ b/test/CodeGen/ARM/neon_vabs.ll @@ -89,3 +89,41 @@ define <2 x i32> @test10(<2 x i32> %a) nounwind { %abs = select <2 x i1> %b, <2 x i32> %tmp1neg, <2 x i32> %a ret <2 x i32> %abs } + +;; Check that absdiff patterns as emitted by log2 shuffles are +;; matched by VABD. + +define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind { +; CHECK-LABEL: test11: +; CHECK: vabdl.u16 q + %zext1 = zext <4 x i16> %a to <4 x i32> + %zext2 = zext <4 x i16> %b to <4 x i32> + %diff = sub <4 x i32> %zext1, %zext2 + %shift1 = ashr <4 x i32> %diff, <i32 31, i32 31, i32 31, i32 31> + %add1 = add <4 x i32> %shift1, %diff + %res = xor <4 x i32> %shift1, %add1 + ret <4 x i32> %res +} +define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind { +; CHECK-LABEL: test12: +; CHECK: vabdl.u8 q + %zext1 = zext <8 x i8> %a to <8 x i16> + %zext2 = zext <8 x i8> %b to <8 x i16> + %diff = sub <8 x i16> %zext1, %zext2 + %shift1 = ashr <8 x i16> %diff,<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> + %add1 = add <8 x i16> %shift1, %diff + %res = xor <8 x i16> %shift1, %add1 + ret <8 x i16> %res +} + +define <2 x i64> @test13(<2 x i32> %a, <2 x i32> %b) nounwind { +; CHECK-LABEL: test13: +; CHECK: vabdl.u32 q + %zext1 = zext <2 x i32> %a to <2 x i64> + %zext2 = zext <2 x i32> %b to <2 x i64> + %diff = sub <2 x i64> %zext1, %zext2 + %shift1 = ashr <2 x i64> %diff,<i64 63, i64 63> + %add1 = add <2 x i64> %shift1, %diff + %res = xor <2 x i64> %shift1, %add1 + ret <2 x i64> %res +} diff --git a/test/CodeGen/ARM/neon_vshl_minint.ll b/test/CodeGen/ARM/neon_vshl_minint.ll new file mode 100644 index 000000000000..769eff845fd6 --- /dev/null +++ b/test/CodeGen/ARM/neon_vshl_minint.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s + +define <1 x i64> @vshl_minint() #0 { + entry: + ; CHECK-LABEL: vshl_minint + ; CHECK: vldr + ; CHECK: vshl.u64 + %vshl.i = tail call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> undef, <1 x i64> <i64 -9223372036854775808>) + ret <1 x i64> %vshl.i +} + +declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>) diff --git a/test/CodeGen/ARM/out-of-registers.ll b/test/CodeGen/ARM/out-of-registers.ll index a83923db0b30..891319881f45 100644 --- a/test/CodeGen/ARM/out-of-registers.ll +++ b/test/CodeGen/ARM/out-of-registers.ll @@ -8,7 +8,7 @@ target triple = "thumbv7-none-linux-gnueabi" define void @foo(float* nocapture %A) #0 { %1= bitcast float* %A to i8* - %2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32(i8* %1, i32 4) + %2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0i8(i8* %1, i32 4) %3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 0 %divp_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %3 %4 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 1 @@ -17,7 +17,7 @@ define void @foo(float* nocapture %A) #0 { %div8p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %5 %6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 3 %div13p_vec = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %6 - tail call void @llvm.arm.neon.vst4.v4f32(i8* %1, <4 x float> %divp_vec, <4 x float> %div3p_vec, <4 x float> %div8p_vec, <4 x float> %div13p_vec, i32 4) + tail call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %1, <4 x float> %divp_vec, <4 x float> %div3p_vec, <4 x float> %div8p_vec, <4 x float> %div13p_vec, i32 4) ret void } @@ -27,8 +27,8 @@ declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #1 ; Function Attrs: nounwind readonly ; Function Attrs: nounwind -declare void @llvm.arm.neon.vst4.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) #1 -declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32(i8*, i32) #2 +declare void @llvm.arm.neon.vst4.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) #1 +declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32.p0i8(i8*, i32) #2 ; Function Attrs: nounwind diff --git a/test/CodeGen/ARM/pr25317.ll b/test/CodeGen/ARM/pr25317.ll new file mode 100644 index 000000000000..6770c6f84ecd --- /dev/null +++ b/test/CodeGen/ARM/pr25317.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv7--linux-gnueabihf" + +; CHECK-LABEL: f: +; CHECK: str lr, [r0] +define void @f(i32* %p) { + call void asm sideeffect "str lr, $0", "=*o"(i32* %p) + ret void +}
\ No newline at end of file diff --git a/test/CodeGen/ARM/pr25838.ll b/test/CodeGen/ARM/pr25838.ll new file mode 100644 index 000000000000..0aa95fd2d720 --- /dev/null +++ b/test/CodeGen/ARM/pr25838.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s +; PR25838 + +target triple = "armv7--linux-android" + +%0 = type { i32, i32 } + +define i32 @foo(%0* readonly) { + br i1 undef, label %12, label %2 + +; <label>:2 + %3 = trunc i64 undef to i32 + %4 = icmp eq i32 undef, 0 + br i1 %4, label %5, label %9 + +; <label>:5 + %6 = icmp slt i32 %3, 0 + %7 = sub nsw i32 0, %3 + %8 = select i1 %6, i32 %7, i32 %3 + br label %12 + +; <label>:9 + br i1 undef, label %12, label %10 + +; <label>:10 + %11 = tail call i32 @bar(i32 undef) + unreachable + +; <label>:12 + %13 = phi i32 [ %8, %5 ], [ 0, %1 ], [ undef, %9 ] + ret i32 %13 +} + +declare i32 @bar(i32) diff --git a/test/CodeGen/ARM/rbit.ll b/test/CodeGen/ARM/rbit.ll index 41f866fc8d2f..a2bfeca75526 100644 --- a/test/CodeGen/ARM/rbit.ll +++ b/test/CodeGen/ARM/rbit.ll @@ -18,3 +18,14 @@ entry: } declare i32 @llvm.arm.rbit(i32) + +declare i32 @llvm.bitreverse.i32(i32) readnone + +; CHECK-LABEL: rbit_generic +; CHECK: rbit r0, r0 +define i32 @rbit_generic(i32 %t) { +entry: + %rbit = call i32 @llvm.bitreverse.i32(i32 %t) + ret i32 %rbit +} + diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 507ee48cafc2..d02f5f883795 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -24,7 +24,7 @@ entry: %2 = getelementptr inbounds %struct.int32x4_t, %struct.int32x4_t* %vT1ptr, i32 0, i32 0 ; <<4 x i32>*> [#uses=1] %3 = load <4 x i32>, <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1] - %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] + %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] %6 = bitcast <8 x i16> %5 to <2 x double> ; <<2 x double>> [#uses=2] %7 = extractelement <2 x double> %6, i32 0 ; <double> [#uses=1] %8 = bitcast double %7 to <4 x i16> ; <<4 x i16>> [#uses=1] @@ -40,7 +40,7 @@ entry: %trunc_16 = trunc <4 x i32> %16 to <4 x i16> %17 = shufflevector <4 x i16> %trunc_15, <4 x i16> %trunc_16, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; <<8 x i16>> [#uses=1] %18 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1] - tail call void @llvm.arm.neon.vst1.v8i16(i8* %18, <8 x i16> %17, i32 1) + tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %18, <8 x i16> %17, i32 1) ret void } @@ -60,17 +60,17 @@ entry: %2 = getelementptr inbounds %struct.int16x8_t, %struct.int16x8_t* %vT1ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] %3 = load <8 x i16>, <8 x i16>* %2, align 16 ; <<8 x i16>> [#uses=1] %4 = bitcast i16* %i_ptr to i8* ; <i8*> [#uses=1] - %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] + %5 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %4, i32 1) ; <<8 x i16>> [#uses=1] %6 = getelementptr inbounds i16, i16* %i_ptr, i32 8 ; <i16*> [#uses=1] %7 = bitcast i16* %6 to i8* ; <i8*> [#uses=1] - %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %7, i32 1) ; <<8 x i16>> [#uses=1] + %8 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %7, i32 1) ; <<8 x i16>> [#uses=1] %9 = mul <8 x i16> %1, %5 ; <<8 x i16>> [#uses=1] %10 = mul <8 x i16> %3, %8 ; <<8 x i16>> [#uses=1] %11 = bitcast i16* %o_ptr to i8* ; <i8*> [#uses=1] - tail call void @llvm.arm.neon.vst1.v8i16(i8* %11, <8 x i16> %9, i32 1) + tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %11, <8 x i16> %9, i32 1) %12 = getelementptr inbounds i16, i16* %o_ptr, i32 8 ; <i16*> [#uses=1] %13 = bitcast i16* %12 to i8* ; <i8*> [#uses=1] - tail call void @llvm.arm.neon.vst1.v8i16(i8* %13, <8 x i16> %10, i32 1) + tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %13, <8 x i16> %10, i32 1) ret void } @@ -81,14 +81,14 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ; CHECK: vmov r ; CHECK-NOT: vmov d ; CHECK: vst3.8 - %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] + %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1] %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 ; <<8 x i8>> [#uses=1] %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 1 ; <<8 x i8>> [#uses=1] %tmp5 = sub <8 x i8> %tmp3, %tmp4 %tmp6 = add <8 x i8> %tmp2, %tmp3 ; <<8 x i8>> [#uses=1] %tmp7 = mul <8 x i8> %tmp4, %tmp2 - tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1) + tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7, i32 1) ret <8 x i8> %tmp4 } @@ -101,10 +101,10 @@ entry: ; CHECK-NOT: vmov ; CHECK: bne %tmp1 = bitcast i32* %in to i8* ; <i8*> [#uses=1] - %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp1, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] %tmp3 = getelementptr inbounds i32, i32* %in, i32 8 ; <i32*> [#uses=1] %tmp4 = bitcast i32* %tmp3 to i8* ; <i8*> [#uses=1] - %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp4, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] %tmp8 = bitcast i32* %out to i8* ; <i8*> [#uses=1] br i1 undef, label %return1, label %return2 @@ -120,7 +120,7 @@ return1: %tmp39 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] %tmp6 = add <4 x i32> %tmp52, %tmp ; <<4 x i32>> [#uses=1] %tmp7 = add <4 x i32> %tmp57, %tmp39 ; <<4 x i32>> [#uses=1] - tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1) + tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1) ret void return2: @@ -131,7 +131,7 @@ return2: %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] %tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] %tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1] - tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1) + tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1) call void @llvm.trap() unreachable } @@ -147,7 +147,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { ; CHECK: vadd.i16 %tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1] %tmp1 = load <8 x i16>, <8 x i16>* %B ; <<8 x i16>> [#uses=2] - %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2] + %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) ; <%struct.__neon_int16x8x2_t> [#uses=2] %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 ; <<8 x i16>> [#uses=1] %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 ; <<8 x i16>> [#uses=1] %tmp5 = add <8 x i16> %tmp3, %tmp4 ; <<8 x i16>> [#uses=1] @@ -160,7 +160,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]] ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} %tmp1 = load <8 x i8>, <8 x i8>* %B ; <<8 x i8>> [#uses=2] - %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] + %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1] %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 ; <<8 x i8>> [#uses=1] %tmp5 = add <8 x i8> %tmp3, %tmp4 ; <<8 x i8>> [#uses=1] @@ -178,14 +178,14 @@ entry: ; CHECK: vuzp.32 q[[Q1]], q[[Q0]] ; CHECK: vst1.32 %0 = bitcast i32* %iptr to i8* ; <i8*> [#uses=2] - %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] + %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] %tmp57 = extractvalue %struct.__neon_int32x4x2_t %1, 0 ; <<4 x i32>> [#uses=1] %tmp60 = extractvalue %struct.__neon_int32x4x2_t %1, 1 ; <<4 x i32>> [#uses=1] %2 = bitcast i32* %optr to i8* ; <i8*> [#uses=2] - tail call void @llvm.arm.neon.vst2.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1) - %3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %0, i32 1) ; <<4 x i32>> [#uses=1] + tail call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1) + %3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8* %0, i32 1) ; <<4 x i32>> [#uses=1] %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> ; <<4 x i32>> [#uses=1] - tail call void @llvm.arm.neon.vst1.v4i32(i8* %2, <4 x i32> %4, i32 1) + tail call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %2, <4 x i32> %4, i32 1) ret void } @@ -307,43 +307,43 @@ bb14: ; preds = %bb6 ; This test crashes the coalescer because live variables were not updated properly. define <8 x i8> @t11(i8* %A1, i8* %A2, i8* %A3, i8* %A4, i8* %A5, i8* %A6, i8* %A7, i8* %A8, i8* %B) nounwind { - %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] %tmp2d = extractvalue %struct.__neon_int8x8x3_t %tmp1d, 0 ; <<8 x i8>> [#uses=1] - %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] + %tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=1] %tmp2f = extractvalue %struct.__neon_int8x8x3_t %tmp1f, 0 ; <<8 x i8>> [#uses=1] %tmp2bd = add <8 x i8> zeroinitializer, %tmp2d ; <<8 x i8>> [#uses=1] %tmp2abcd = mul <8 x i8> zeroinitializer, %tmp2bd ; <<8 x i8>> [#uses=1] %tmp2ef = sub <8 x i8> zeroinitializer, %tmp2f ; <<8 x i8>> [#uses=1] %tmp2efgh = mul <8 x i8> %tmp2ef, undef ; <<8 x i8>> [#uses=2] - call void @llvm.arm.neon.vst3.v8i8(i8* %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A2, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp2efgh, i32 1) %tmp2 = sub <8 x i8> %tmp2efgh, %tmp2abcd ; <<8 x i8>> [#uses=1] %tmp7 = mul <8 x i8> undef, %tmp2 ; <<8 x i8>> [#uses=1] - tail call void @llvm.arm.neon.vst3.v8i8(i8* %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7, i32 1) + tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %B, <8 x i8> undef, <8 x i8> undef, <8 x i8> %tmp7, i32 1) ret <8 x i8> undef } -declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly +declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8*, i32) nounwind readonly -declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly +declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone -declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4i32(i8*, <4 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) +declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind -declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly -declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8*, i32) nounwind readonly +declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8*, i32) nounwind readonly -declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly +declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly -declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly -declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/rotate.ll b/test/CodeGen/ARM/rotate.ll new file mode 100644 index 000000000000..f3f7de2160fb --- /dev/null +++ b/test/CodeGen/ARM/rotate.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=thumbv8--linux-gnueabihf | FileCheck %s + +;; This used to cause a backend crash about not being able to +;; select ROTL. Make sure if generates the basic VSHL/VSHR. +define <2 x i64> @testcase(<2 x i64>* %in) { +; CHECK-LABEL: testcase +; CHECK: vshl.i64 +; CHECK: vshr.u64 + %1 = load <2 x i64>, <2 x i64>* %in + %2 = lshr <2 x i64> %1, <i64 8, i64 8> + %3 = shl <2 x i64> %1, <i64 56, i64 56> + %4 = or <2 x i64> %2, %3 + ret <2 x i64> %4 +} diff --git a/test/CodeGen/ARM/sat-arith.ll b/test/CodeGen/ARM/sat-arith.ll new file mode 100644 index 000000000000..4844ed1bd21e --- /dev/null +++ b/test/CodeGen/ARM/sat-arith.ll @@ -0,0 +1,63 @@ +; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s -check-prefix=ARM -check-prefix=CHECK +; RUN: llc -O1 -mtriple=thumbv7-none-none-eabi %s -o - | FileCheck %s -check-prefix=THUMB -check-prefix=CHECK + +; CHECK-LABEL: qadd +define i32 @qadd() nounwind { +; CHECK-DAG: mov{{s?}} [[R0:.*]], #8 +; CHECK-DAG: mov{{s?}} [[R1:.*]], #128 +; CHECK-ARM: qadd [[R0]], [[R1]], [[R0]] +; CHECK-THRUMB: qadd [[R0]], [[R0]], [[R1]] + %tmp = call i32 @llvm.arm.qadd(i32 128, i32 8) + ret i32 %tmp +} + +; CHECK-LABEL: qsub +define i32 @qsub() nounwind { +; CHECK-DAG: mov{{s?}} [[R0:.*]], #8 +; CHECK-DAG: mov{{s?}} [[R1:.*]], #128 +; CHECK-ARM: qsub [[R0]], [[R1]], [[R0]] +; CHECK-THRUMB: qadd [[R0]], [[R1]], [[R0]] + %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8) + ret i32 %tmp +} + +; upper-bound of the immediate argument +; CHECK-LABEL: ssat1 +define i32 @ssat1() nounwind { +; CHECK: mov{{s?}} [[R0:.*]], #128 +; CHECK: ssat [[R1:.*]], #32, [[R0]] + %tmp = call i32 @llvm.arm.ssat(i32 128, i32 32) + ret i32 %tmp +} + +; lower-bound of the immediate argument +; CHECK-LABEL: ssat2 +define i32 @ssat2() nounwind { +; CHECK: mov{{s?}} [[R0:.*]], #128 +; CHECK: ssat [[R1:.*]], #1, [[R0]] + %tmp = call i32 @llvm.arm.ssat(i32 128, i32 1) + ret i32 %tmp +} + +; upper-bound of the immediate argument +; CHECK-LABEL: usat1 +define i32 @usat1() nounwind { +; CHECK: mov{{s?}} [[R0:.*]], #128 +; CHECK: usat [[R1:.*]], #31, [[R0]] + %tmp = call i32 @llvm.arm.usat(i32 128, i32 31) + ret i32 %tmp +} + +; lower-bound of the immediate argument +; CHECK-LABEL: usat2 +define i32 @usat2() nounwind { +; CHECK: mov{{s?}} [[R0:.*]], #128 +; CHECK: usat [[R1:.*]], #0, [[R0]] + %tmp = call i32 @llvm.arm.usat(i32 128, i32 0) + ret i32 %tmp +} + +declare i32 @llvm.arm.qadd(i32, i32) nounwind +declare i32 @llvm.arm.qsub(i32, i32) nounwind +declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone +declare i32 @llvm.arm.usat(i32, i32) nounwind readnone diff --git a/test/CodeGen/ARM/sched-it-debug-nodes.ll b/test/CodeGen/ARM/sched-it-debug-nodes.ll deleted file mode 100644 index 7906e7c7581e..000000000000 --- a/test/CodeGen/ARM/sched-it-debug-nodes.ll +++ /dev/null @@ -1,88 +0,0 @@ -; RUN: llc -mtriple thumbv7 -print-before=post-RA-sched -print-after=post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s - -; ModuleID = '<stdin>' -target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv7" - -%struct.s = type opaque - -; Function Attrs: nounwind -define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 { -entry: - tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !19, metadata !28), !dbg !29 - tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !20, metadata !28), !dbg !29 - tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !21, metadata !28), !dbg !29 - tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !22, metadata !28), !dbg !29 - %cmp = icmp ult i32 %n, 4, !dbg !30 - br i1 %cmp, label %return, label %if.end, !dbg !32 - -if.end: ; preds = %entry - tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !33 - br label %return, !dbg !34 - -return: ; preds = %entry, %if.end - %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] - ret i32 %retval.0, !dbg !35 -} - -; NOTE: This is checking that the register in the DEBUG_VALUE node is not -; accidentally being marked as KILL. The DBG_VALUE node gets introduced in -; If-Conversion, and gets bundled into the IT block. The Post RA Scheduler -; attempts to schedule the Machine Instr, and tries to tag the register in the -; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or -; hopefully, triggering an assert). - -; CHECK: BUNDLE %ITSTATE<imp-def,dead> -; CHECK: * DBG_VALUE %R1, %noreg, !"u" -; CHECK-NOT: * DBG_VALUE %R1<kill>, %noreg, !"u" - -declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 - -; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind readnone } -attributes #3 = { nounwind } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!23, !24, !25, !26} -!llvm.ident = !{!27} - -!0 = !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) -!1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") -!2 = !{} -!3 = !{!4} -!4 = !DISubprogram(name: "f", scope: !5, file: !5, line: 9, type: !6, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, function: i32 (%struct.s*, i32, i8*, i32)* @f, variables: !18) -!5 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") -!6 = !DISubroutineType(types: !7) -!7 = !{!8, !9, !12, !13, !17} -!8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 32, align: 32) -!10 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !5, line: 5, baseType: !11) -!11 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !5, line: 5, flags: DIFlagFwdDecl) -!12 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) -!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 32, align: 32) -!14 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !15) -!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !5, line: 2, baseType: !16) -!16 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) -!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !5, line: 3, baseType: !12) -!18 = !{!19, !20, !21, !22} -!19 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "s", arg: 1, scope: !4, file: !5, line: 9, type: !9) -!20 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "u", arg: 2, scope: !4, file: !5, line: 9, type: !12) -!21 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "b", arg: 3, scope: !4, file: !5, line: 9, type: !13) -!22 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "n", arg: 4, scope: !4, file: !5, line: 9, type: !17) -!23 = !{i32 2, !"Dwarf Version", i32 4} -!24 = !{i32 2, !"Debug Info Version", i32 3} -!25 = !{i32 1, !"wchar_size", i32 4} -!26 = !{i32 1, !"min_enum_size", i32 4} -!27 = !{!"clang version 3.7.0 (llvm/trunk 237059)"} -!28 = !DIExpression() -!29 = !DILocation(line: 9, scope: !4) -!30 = !DILocation(line: 10, scope: !31) -!31 = distinct !DILexicalBlock(scope: !4, file: !5, line: 10) -!32 = !DILocation(line: 10, scope: !4) -!33 = !DILocation(line: 13, scope: !4) -!34 = !DILocation(line: 14, scope: !4) -!35 = !DILocation(line: 15, scope: !4) diff --git a/test/CodeGen/ARM/setjmp_longjmp.ll b/test/CodeGen/ARM/setjmp_longjmp.ll new file mode 100644 index 000000000000..7100175a97a4 --- /dev/null +++ b/test/CodeGen/ARM/setjmp_longjmp.ll @@ -0,0 +1,113 @@ +; RUN: llc %s -o - | FileCheck %s +target triple = "armv7-apple-ios" + +declare i32 @llvm.eh.sjlj.setjmp(i8*) +declare void @llvm.eh.sjlj.longjmp(i8*) +@g = external global i32 + +declare void @may_throw() +declare i32 @__gxx_personality_sj0(...) +declare i8* @__cxa_begin_catch(i8*) +declare void @__cxa_end_catch() +declare i32 @llvm.eh.typeid.for(i8*) +declare i8* @llvm.frameaddress(i32) +declare i8* @llvm.stacksave() +@_ZTIPKc = external constant i8* + +; CHECK-LABEL: foobar +; +; setjmp sequence: +; CHECK: add [[PCREG:r[0-9]+]], pc, #8 +; CHECK-NEXT: str [[PCREG]], {{\[}}[[BUFREG:r[0-9]+]], #4] +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: add pc, pc, #0 +; CHECK-NEXT: mov r0, #1 +; +; longjmp sequence: +; CHECK: ldr sp, [{{\s*}}[[BUFREG:r[0-9]+]], #8] +; CHECK-NEXT: ldr [[DESTREG:r[0-9]+]], {{\[}}[[BUFREG]], #4] +; CHECK-NEXT: ldr r7, {{\[}}[[BUFREG]]{{\]}} +; CHECK-NEXT: bx [[DESTREG]] +define void @foobar() { +entry: + %buf = alloca [5 x i8*], align 4 + %arraydecay = getelementptr inbounds [5 x i8*], [5 x i8*]* %buf, i32 0, i32 0 + %bufptr = bitcast i8** %arraydecay to i8* + ; Note: This is simplified, in reality you have to store the framepointer + + ; stackpointer in the buffer as well for this to be legal! + %setjmpres = call i32 @llvm.eh.sjlj.setjmp(i8* %bufptr) + %tobool = icmp ne i32 %setjmpres, 0 + br i1 %tobool, label %if.then, label %if.else + +if.then: + store volatile i32 1, i32* @g, align 4 + br label %if.end + +if.else: + store volatile i32 0, i32* @g, align 4 + call void @llvm.eh.sjlj.longjmp(i8* %bufptr) + unreachable + +if.end: + ret void +} + +; CHECK-LABEL: combine_sjlj_eh_and_setjmp_longjmp +; Check that we can mix sjlj exception handling with __builtin_setjmp +; and __builtin_longjmp. +; +; setjmp sequence: +; CHECK: add [[PCREG:r[0-9]+]], pc, #8 +; CHECK-NEXT: str [[PCREG]], {{\[}}[[BUFREG:r[0-9]+]], #4] +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: add pc, pc, #0 +; CHECK-NEXT: mov r0, #1 +; +; longjmp sequence: +; CHECK: ldr sp, [{{\s*}}[[BUFREG:r[0-9]+]], #8] +; CHECK-NEXT: ldr [[DESTREG:r[0-9]+]], {{\[}}[[BUFREG]], #4] +; CHECK-NEXT: ldr r7, {{\[}}[[BUFREG]]{{\]}} +; CHECK-NEXT: bx [[DESTREG]] +define void @combine_sjlj_eh_and_setjmp_longjmp() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) { +entry: + %buf = alloca [5 x i8*], align 4 + invoke void @may_throw() to label %try.cont unwind label %lpad + +lpad: + %0 = landingpad { i8*, i32 } catch i8* bitcast (i8** @_ZTIPKc to i8*) + %1 = extractvalue { i8*, i32 } %0, 1 + %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIPKc to i8*)) #3 + %matches = icmp eq i32 %1, %2 + br i1 %matches, label %catch, label %eh.resume + +catch: + %3 = extractvalue { i8*, i32 } %0, 0 + %4 = tail call i8* @__cxa_begin_catch(i8* %3) #3 + store volatile i32 0, i32* @g, align 4 + %5 = bitcast [5 x i8*]* %buf to i8* + %arraydecay = getelementptr inbounds [5 x i8*], [5 x i8*]* %buf, i64 0, i64 0 + %6 = tail call i8* @llvm.frameaddress(i32 0) + store i8* %6, i8** %arraydecay, align 16 + %7 = tail call i8* @llvm.stacksave() + %8 = getelementptr [5 x i8*], [5 x i8*]* %buf, i64 0, i64 2 + store i8* %7, i8** %8, align 16 + %9 = call i32 @llvm.eh.sjlj.setjmp(i8* %5) + %tobool = icmp eq i32 %9, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: + store volatile i32 2, i32* @g, align 4 + call void @__cxa_end_catch() #3 + br label %try.cont + +if.else: + store volatile i32 1, i32* @g, align 4 + call void @llvm.eh.sjlj.longjmp(i8* %5) + unreachable + +eh.resume: + resume { i8*, i32 } %0 + +try.cont: + ret void +} diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index 6f5c0e8279a9..5d44eb0f11d1 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -1,14 +1,14 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9 +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-ARM +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-ARM +; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB ; rdar://8576755 define i32 @test1(i32 %X, i32 %Y, i8 %sh) { -; A8-LABEL: test1: -; A8: add r0, r0, r1, lsl r2 - -; A9-LABEL: test1: -; A9: add r0, r0, r1, lsl r2 +; CHECK-LABEL: test1: +; CHECK-ARM: add r0, r0, r1, lsl r2 +; CHECK-THUMB: lsls r1, r2 +; CHECK-THUMB: add r0, r1 %shift.upgrd.1 = zext i8 %sh to i32 %A = shl i32 %Y, %shift.upgrd.1 %B = add i32 %X, %A @@ -16,11 +16,10 @@ define i32 @test1(i32 %X, i32 %Y, i8 %sh) { } define i32 @test2(i32 %X, i32 %Y, i8 %sh) { -; A8-LABEL: test2: -; A8: bic r0, r0, r1, asr r2 - -; A9-LABEL: test2: -; A9: bic r0, r0, r1, asr r2 +; CHECK-LABEL: test2: +; CHECK-ARM: bic r0, r0, r1, asr r2 +; CHECK-THUMB: asrs r1, r2 +; CHECK-THUMB: bics r0, r1 %shift.upgrd.2 = zext i8 %sh to i32 %A = ashr i32 %Y, %shift.upgrd.2 %B = xor i32 %A, -1 @@ -30,14 +29,9 @@ define i32 @test2(i32 %X, i32 %Y, i8 %sh) { define i32 @test3(i32 %base, i32 %base2, i32 %offset) { entry: -; A8-LABEL: test3: -; A8: ldr r0, [r0, r2, lsl #2] -; A8: ldr r1, [r1, r2, lsl #2] - -; lsl #2 is free -; A9-LABEL: test3: -; A9: ldr r0, [r0, r2, lsl #2] -; A9: ldr r1, [r1, r2, lsl #2] +; CHECK-LABEL: test3: +; CHECK: ldr{{(.w)?}} r0, [r0, r2, lsl #2] +; CHECK: ldr{{(.w)?}} r1, [r1, r2, lsl #2] %tmp1 = shl i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 %tmp3 = inttoptr i32 %tmp2 to i32* @@ -53,17 +47,11 @@ declare i8* @malloc(...) define fastcc void @test4(i16 %addr) nounwind { entry: -; A8-LABEL: test4: -; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] -; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A8: str [[REG]], [r0, r1, lsl #2] -; A8-NOT: str [[REG]], [r0] - -; A9-LABEL: test4: -; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] -; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A9: str [[REG]], [r0, r1, lsl #2] -; A9-NOT: str [[REG]], [r0] +; CHECK-LABEL: test4: +; CHECK: ldr{{(.w)?}} [[REG:r[0-9]+]], [r0, r1, lsl #2] +; CHECK-NOT: ldr{{(.w)?}} [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; CHECK: str{{(.w)?}} [[REG]], [r0, r1, lsl #2] +; CHECK-NOT: str{{(.w)?}} [[REG]], [r0] %0 = tail call i8* (...) @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* %2 = sext i16 %addr to i32 @@ -73,3 +61,181 @@ entry: store i32 %5, i32* %3, align 4 ret void } + +define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) { +entry: +; CHECK-LABEL: test_orr_extract_from_mul_1 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-ARM: orr r0, r1, r0 +; CHECK-THUMB: muls r1, r2, r1 +; CHECk-THUMB: orrs r0, r1 + %mul = mul i32 %y, 63767 + %or = or i32 %mul, %x + ret i32 %or +} + +define i32 @test_orr_extract_from_mul_2(i32 %x, i32 %y) { +; CHECK-LABEL: test_orr_extract_from_mul_2 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: orr{{(.w)?}} r0, r0, r1, lsl #1 +entry: + %mul1 = mul i32 %y, 127534 + %or = or i32 %mul1, %x + ret i32 %or +} + +define i32 @test_orr_extract_from_mul_3(i32 %x, i32 %y) { +; CHECK-LABEL: test_orr_extract_from_mul_3 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: orr{{(.w)?}} r0, r0, r1, lsl #2 +entry: + %mul1 = mul i32 %y, 255068 + %or = or i32 %mul1, %x + ret i32 %or +} + +define i32 @test_orr_extract_from_mul_4(i32 %x, i32 %y) { +; CHECK-LABEL: test_orr_extract_from_mul_4 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: orr{{(.w)?}} r0, r0, r1, lsl #3 +entry: + %mul1 = mul i32 %y, 510136 + %or = or i32 %mul1, %x + ret i32 %or +} + +define i32 @test_orr_extract_from_mul_5(i32 %x, i32 %y) { +; CHECK-LABEL: test_orr_extract_from_mul_5 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: orr{{(.w)?}} r0, r0, r1, lsl #4 +entry: + %mul1 = mul i32 %y, 1020272 + %or = or i32 %mul1, %x + ret i32 %or +} + +define i32 @test_orr_extract_from_mul_6(i32 %x, i32 %y) { +; CHECK-LABEL: test_orr_extract_from_mul_6 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: orr{{(.w)?}} r0, r0, r1, lsl #16 +entry: + %mul = mul i32 %y, -115933184 + %or = or i32 %mul, %x + ret i32 %or +} + +define i32 @test_load_extract_from_mul_1(i8* %x, i32 %y) { +; CHECK-LABEL: test_load_extract_from_mul_1 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: ldrb r0, [r0, r1] +entry: + %mul = mul i32 %y, 63767 + %arrayidx = getelementptr inbounds i8, i8* %x, i32 %mul + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +define i32 @test_load_extract_from_mul_2(i8* %x, i32 %y) { +; CHECK-LABEL: test_load_extract_from_mul_2 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: ldrb{{(.w)?}} r0, [r0, r1, lsl #1] +entry: + %mul1 = mul i32 %y, 127534 + %arrayidx = getelementptr inbounds i8, i8* %x, i32 %mul1 + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +define i32 @test_load_extract_from_mul_3(i8* %x, i32 %y) { +; CHECK-LABEL: test_load_extract_from_mul_3 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: ldrb{{(.w)?}} r0, [r0, r1, lsl #2] +entry: + %mul1 = mul i32 %y, 255068 + %arrayidx = getelementptr inbounds i8, i8* %x, i32 %mul1 + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +define i32 @test_load_extract_from_mul_4(i8* %x, i32 %y) { +; CHECK-LABEL: test_load_extract_from_mul_4 +; CHECK: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK: ldrb{{(.w)?}} r0, [r0, r1, lsl #3] +entry: + %mul1 = mul i32 %y, 510136 + %arrayidx = getelementptr inbounds i8, i8* %x, i32 %mul1 + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +define i32 @test_load_extract_from_mul_5(i8* %x, i32 %y) { +; CHECK-LABEL: test_load_extract_from_mul_5 +; CHECK-ARM: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-ARM: ldrb r0, [r0, r1, lsl #4] +; CHECK-THUMB: movw r2, #37232 +; CHECK-THUMB: movt r2, #15 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK-THUMB: ldrb r0, [r0, r1] +entry: + %mul1 = mul i32 %y, 1020272 + %arrayidx = getelementptr inbounds i8, i8* %x, i32 %mul1 + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + +define i32 @test_load_extract_from_mul_6(i8* %x, i32 %y) { +; CHECK-LABEL: test_load_extract_from_mul_6 +; CHECK-ARM: movw r2, #63767 +; CHECK-ARM: mul r1, r1, r2 +; CHECK-ARM: ldrb r0, [r0, r1, lsl #16] +; CHECK-THUMB: movs r2, #0 +; CHECK-THUMB: movt r2, #63767 +; CHECK-THUMB: muls r1, r2, r1 +; CHECK-THUMB: ldrb r0, [r0, r1] +entry: + %mul = mul i32 %y, -115933184 + %arrayidx = getelementptr inbounds i8, i8* %x, i32 %mul + %0 = load i8, i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + ret i32 %conv +} + + +define void @test_well_formed_dag(i32 %in1, i32 %in2, i32* %addr) { +; CHECK-LABEL: test_well_formed_dag: +; CHECK-ARM: movw [[SMALL_CONST:r[0-9]+]], #675 +; CHECK-ARM: mul [[SMALL_PROD:r[0-9]+]], r0, [[SMALL_CONST]] +; CHECK-ARM: add {{r[0-9]+}}, r1, [[SMALL_PROD]], lsl #7 + + %mul.small = mul i32 %in1, 675 + store i32 %mul.small, i32* %addr + %mul.big = mul i32 %in1, 86400 + %add = add i32 %in2, %mul.big + store i32 %add, i32* %addr + ret void +} diff --git a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll index c7f47b0962dc..a1abef9605ca 100644 --- a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll +++ b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll @@ -77,8 +77,8 @@ declare void @terminatev() ; CHECK: blx __Znwm ; CHECK: {{.*}}@ %entry.do.body.i.i.i_crit_edge ; CHECK: str r0, [sp, [[OFFSET:#[0-9]+]]] -; CHECK: ldr [[R0:r[0-9]+]], [sp, [[OFFSET]]] ; CHECK: {{.*}}@ %do.body.i.i.i +; CHECK: ldr [[R0:r[0-9]+]], [sp, [[OFFSET]]] ; CHECK: cbz [[R0]] %"class.std::__1::basic_string" = type { %"class.std::__1::__compressed_pair" } diff --git a/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll b/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll index 5d015738623a..b44b447b3dff 100644 --- a/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll +++ b/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll @@ -2,6 +2,7 @@ ; RUN: llc -mtriple=armv7-apple-ios -O1 < %s | FileCheck %s ; RUN: llc -mtriple=armv7-apple-ios -O2 < %s | FileCheck %s ; RUN: llc -mtriple=armv7-apple-ios -O3 < %s | FileCheck %s +; RUN: llc -mtriple=armv7k-apple-ios < %s | FileCheck %s ; SjLjEHPrepare shouldn't crash when lowering empty structs. ; diff --git a/test/CodeGen/ARM/softfp-fabs-fneg.ll b/test/CodeGen/ARM/softfp-fabs-fneg.ll new file mode 100644 index 000000000000..b608fb840218 --- /dev/null +++ b/test/CodeGen/ARM/softfp-fabs-fneg.ll @@ -0,0 +1,41 @@ +; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK +; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv7--" + +define double @f(double %a) { + ; CHECK-LABEL: f: + ; CHECK: bfc r1, #31, #1 + ; CHECK-NEXT: bx lr + %x = call double @llvm.fabs.f64(double %a) readnone + ret double %x +} + +define float @g(float %a) { + ; CHECK-LABEL: g: + ; CHECK-THUMB: bic r0, r0, #-2147483648 + ; CHECK-ARM: bfc r0, #31, #1 + ; CHECK-NEXT: bx lr + %x = call float @llvm.fabs.f32(float %a) readnone + ret float %x +} + +define double @h(double %a) { + ; CHECK-LABEL: h: + ; CHECK: eor r1, r1, #-2147483648 + ; CHECK-NEXT: bx lr + %x = fsub nsz double -0.0, %a + ret double %x +} + +define float @i(float %a) { + ; CHECK-LABEL: i: + ; CHECK: eor r0, r0, #-2147483648 + ; CHECK-NEXT: bx lr + %x = fsub nsz float -0.0, %a + ret float %x +} + +declare double @llvm.fabs.f64(double) readnone +declare float @llvm.fabs.f32(float) readnone diff --git a/test/CodeGen/ARM/special-reg-mcore.ll b/test/CodeGen/ARM/special-reg-mcore.ll index 686da0f6b839..45e6db9e78fe 100644 --- a/test/CodeGen/ARM/special-reg-mcore.ll +++ b/test/CodeGen/ARM/special-reg-mcore.ll @@ -3,7 +3,7 @@ ; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE ; ACORE: LLVM ERROR: Invalid register name "control". -; M3CORE: LLVM ERROR: Invalid register name "control". +; M3CORE: LLVM ERROR: Invalid register name "xpsr_nzcvqg". define i32 @read_mclass_registers() nounwind { entry: diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index 1a102e3d971f..845018ebb0e7 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -7,7 +7,7 @@ %quux = type { i32 (...)**, %baz*, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } -declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly +declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly define void @aaa(%quuz* %this, i8* %block) { ; CHECK-LABEL: aaa: @@ -18,30 +18,30 @@ entry: %aligned_vec = alloca <4 x float>, align 16 %"alloca point" = bitcast i32 0 to i32 %vecptr = bitcast <4 x float>* %aligned_vec to i8* - %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind ; <<4 x float>> [#uses=1] + %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %vecptr, i32 1) nounwind ; <<4 x float>> [#uses=1] store float 6.300000e+01, float* undef, align 4 - %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] + %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] store float 0.000000e+00, float* undef, align 4 - %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] - %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] + %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 - %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind store float 0.000000e+00, float* undef, align 4 %val173 = load <4 x float>, <4 x float>* undef ; <<4 x float>> [#uses=1] br label %bb4 diff --git a/test/CodeGen/ARM/ssat-lower.ll b/test/CodeGen/ARM/ssat-lower.ll new file mode 100644 index 000000000000..9f0cd0364bcf --- /dev/null +++ b/test/CodeGen/ARM/ssat-lower.ll @@ -0,0 +1,11 @@ +; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s + +; immediate argument < lower-bound +; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat +define i32 @ssat1() nounwind { + %tmp = call i32 @llvm.arm.ssat(i32 128, i32 0) + ret i32 %tmp +} + +declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone diff --git a/test/CodeGen/ARM/ssat-upper.ll b/test/CodeGen/ARM/ssat-upper.ll new file mode 100644 index 000000000000..e53f82b3efa3 --- /dev/null +++ b/test/CodeGen/ARM/ssat-upper.ll @@ -0,0 +1,11 @@ +; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s + +; immediate argument > upper-bound +; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat +define i32 @ssat1() nounwind { + %tmp = call i32 @llvm.arm.ssat(i32 128, i32 33) + ret i32 %tmp +} + +declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone diff --git a/test/CodeGen/ARM/subtarget-no-movt.ll b/test/CodeGen/ARM/subtarget-no-movt.ll new file mode 100644 index 000000000000..cb61bde3f9c0 --- /dev/null +++ b/test/CodeGen/ARM/subtarget-no-movt.ll @@ -0,0 +1,45 @@ +; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - | FileCheck -check-prefix=NO-OPTION %s +; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=-no-movt | FileCheck -check-prefix=USE-MOVT %s +; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=+no-movt | FileCheck -check-prefix=NO-USE-MOVT %s +; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 | FileCheck -check-prefix=NO-OPTION %s +; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=-no-movt | FileCheck -check-prefix=USE-MOVT %s +; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=+no-movt | FileCheck -check-prefix=NO-USE-MOVT %s + +; NO-OPTION-LABEL: {{_?}}foo0 +; NO-OPTION: ldr [[R0:r[0-9]+]], [[L0:.*]] +; NO-OPTION: [[L0]]: +; NO-OPTION: .long 2296237089 + +; USE-MOVT-LABEL: {{_?}}foo0 +; USE-MOVT: movw [[R0:r[0-9]+]], #52257 +; USE-MOVT: movt [[R0]], #35037 + +; NO-USE-MOVT-LABEL: {{_?}}foo0 +; NO-USE-MOVT: ldr [[R0:r[0-9]+]], [[L0:.*]] +; NO-USE-MOVT: [[L0]]: +; NO-USE-MOVT: .long 2296237089 + +define i32 @foo0(i32 %a) #0 { + %1 = xor i32 -1998730207, %a + ret i32 %1 +} + +; NO-OPTION-LABEL: {{_?}}foo1 +; NO-OPTION: movw [[R0:r[0-9]+]], #52257 +; NO-OPTION: movt [[R0]], #35037 + +; USE-MOVT-LABEL: {{_?}}foo1 +; USE-MOVT: movw [[R0:r[0-9]+]], #52257 +; USE-MOVT: movt [[R0]], #35037 + +; NO-USE-MOVT-LABEL: {{_?}}foo1 +; NO-USE-MOVT: ldr [[R0:r[0-9]+]], [[L0:.*]] +; NO-USE-MOVT: [[L0]]: +; NO-USE-MOVT: .long 2296237089 + +define i32 @foo1(i32 %a) { + %1 = xor i32 -1998730207, %a + ret i32 %1 +} + +attributes #0 = { "target-features"="+no-movt" } diff --git a/test/CodeGen/ARM/tail-merge-branch-weight.ll b/test/CodeGen/ARM/tail-merge-branch-weight.ll index 95b0a202e7ff..f83f28815793 100644 --- a/test/CodeGen/ARM/tail-merge-branch-weight.ll +++ b/test/CodeGen/ARM/tail-merge-branch-weight.ll @@ -9,7 +9,7 @@ ; = 0.2 * 0.4 + 0.8 * 0.7 = 0.64 ; CHECK: # Machine code for function test0: -; CHECK: Successors according to CFG: BB#{{[0-9]+}}(13) BB#{{[0-9]+}}(24) +; CHECK: Successors according to CFG: BB#{{[0-9]+}}({{[0-9a-fx/= ]+}}20.00%) BB#{{[0-9]+}}({{[0-9a-fx/= ]+}}80.00%) ; CHECK: BB#{{[0-9]+}}: ; CHECK: BB#{{[0-9]+}}: ; CHECK: # End machine code for function test0. diff --git a/test/CodeGen/ARM/taildup-branch-weight.ll b/test/CodeGen/ARM/taildup-branch-weight.ll index 64e0f4bcdefc..6f8d245e74a0 100644 --- a/test/CodeGen/ARM/taildup-branch-weight.ll +++ b/test/CodeGen/ARM/taildup-branch-weight.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck %s ; CHECK: Machine code for function test0: -; CHECK: Successors according to CFG: BB#1(4) BB#2(124) +; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}3.12%) BB#2({{[0-9a-fx/= ]+}}96.88%) define void @test0(i32 %a, i32 %b, i32* %c, i32* %d) { entry: @@ -30,7 +30,7 @@ B4: !0 = !{!"branch_weights", i32 4, i32 124} ; CHECK: Machine code for function test1: -; CHECK: Successors according to CFG: BB#1(8) BB#2(248) +; CHECK: Successors according to CFG: BB#2(0x7c000000 / 0x80000000 = 96.88%) BB#1(0x04000000 / 0x80000000 = 3.12%) @g0 = common global i32 0, align 4 diff --git a/test/CodeGen/ARM/test-sharedidx.ll b/test/CodeGen/ARM/test-sharedidx.ll index 377996c4c3c8..db32f18d82c0 100644 --- a/test/CodeGen/ARM/test-sharedidx.ll +++ b/test/CodeGen/ARM/test-sharedidx.ll @@ -20,8 +20,8 @@ entry: for.body: ; preds = %entry, %for.body.3 ; CHECK: %for.body -; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! -; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! +; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]! +; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]! %i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ] %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.09 %0 = load i8, i8* %arrayidx, align 1 @@ -42,8 +42,8 @@ for.end: ; preds = %for.body, %for.body for.body.1: ; preds = %for.body ; CHECK: %for.body.1 -; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! -; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! +; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]! +; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]! %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %add5 %2 = load i8, i8* %arrayidx.1, align 1 %conv6.1 = zext i8 %2 to i32 @@ -59,9 +59,6 @@ for.body.1: ; preds = %for.body br i1 %cmp.1, label %for.body.2, label %for.end for.body.2: ; preds = %for.body.1 -; CHECK: %for.body.2 -; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! -; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %add5.1 %4 = load i8, i8* %arrayidx.2, align 1 %conv6.2 = zext i8 %4 to i32 @@ -78,8 +75,8 @@ for.body.2: ; preds = %for.body.1 for.body.3: ; preds = %for.body.2 ; CHECK: %for.body.3 -; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! -; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! +; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]! +; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]! %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %add5.2 %6 = load i8, i8* %arrayidx.3, align 1 %conv6.3 = zext i8 %6 to i32 diff --git a/test/CodeGen/ARM/thumb-alignment.ll b/test/CodeGen/ARM/thumb-alignment.ll index c11d4b6da3c9..b9ddfbb714d1 100644 --- a/test/CodeGen/ARM/thumb-alignment.ll +++ b/test/CodeGen/ARM/thumb-alignment.ll @@ -23,7 +23,7 @@ define i32* @bar() { ; CHECK: .globl baz ; CHECK-NEXT: .align 2 -; CHECK: adr.w +; CHECK: tbb define i32 @baz() { %1 = load i32, i32* @c, align 4 switch i32 %1, label %7 [ diff --git a/test/CodeGen/ARM/thumb1-ldst-opt.ll b/test/CodeGen/ARM/thumb1-ldst-opt.ll new file mode 100644 index 000000000000..eb82385de0c5 --- /dev/null +++ b/test/CodeGen/ARM/thumb1-ldst-opt.ll @@ -0,0 +1,27 @@ +; RUN: llc -stop-after block-placement -o /dev/null %s | FileCheck %s + +target triple = "thumbv6m-none-none" + +define i32* @foo(i32* readonly %p0) { +entry: + %add.ptr = getelementptr inbounds i32, i32* %p0, i32 10 + %arrayidx = getelementptr inbounds i32, i32* %p0, i32 13 + %0 = load i32, i32* %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %p0, i32 12 + %1 = load i32, i32* %arrayidx1, align 4 + %add = add nsw i32 %1, %0 + %arrayidx2 = getelementptr inbounds i32, i32* %p0, i32 11 + %2 = load i32, i32* %arrayidx2, align 4 + %add3 = add nsw i32 %add, %2 + %3 = load i32, i32* %add.ptr, align 4 + %add5 = add nsw i32 %add3, %3 + tail call void @g(i32 %add5) + ret i32* %p0 +} + +declare void @g(i32) + +; CHECK-LABEL: name: foo +; CHECK: [[BASE:%r[0-7]]], {{.*}} tADDi8 +; CHECK-NOT: [[BASE]] = tLDMIA_UPD {{.*}} [[BASE]] +; CHECK: tLDMIA killed [[BASE]], {{.*}} def [[BASE]] diff --git a/test/CodeGen/ARM/thumb1_return_sequence.ll b/test/CodeGen/ARM/thumb1_return_sequence.ll index 9c62faeaa684..67d1cad2cf68 100644 --- a/test/CodeGen/ARM/thumb1_return_sequence.ll +++ b/test/CodeGen/ARM/thumb1_return_sequence.ll @@ -23,11 +23,22 @@ entry: ; -------- ; CHECK-V4T: add sp, ; CHECK-V4T-NEXT: pop {[[SAVED]]} -; CHECK-V4T-NEXT: mov r12, r3 -; CHECK-V4T-NEXT: pop {r3} -; CHECK-V4T-NEXT: mov lr, r3 -; CHECK-V4T-NEXT: mov r3, r12 -; CHECK-V4T: bx lr +; The ISA for v4 does not support pop pc, so make sure we do not emit +; one even when we do not need to update SP. +; CHECK-V4T-NOT: pop {pc} +; We may only use lo register to pop, but in that case, all the scratch +; ones are used. +; r12 is the only register we are allowed to clobber for AAPCS. +; Use it to save a lo register. +; CHECK-V4T-NEXT: mov [[TEMP_REG:r12]], [[POP_REG:r[0-7]]] +; Pop the value of LR. +; CHECK-V4T-NEXT: pop {[[POP_REG]]} +; Copy the value of LR in the right register. +; CHECK-V4T-NEXT: mov lr, [[POP_REG]] +; Restore the value that was in the register we used to pop the value of LR. +; CHECK-V4T-NEXT: mov [[POP_REG]], [[TEMP_REG]] +; Return. +; CHECK-V4T-NEXT: bx lr ; CHECK-V5T: pop {[[SAVED]], pc} } @@ -53,19 +64,19 @@ entry: ; Epilogue ; -------- ; CHECK-V4T: pop {[[SAVED]]} -; CHECK-V4T-NEXT: mov r12, r3 -; CHECK-V4T-NEXT: pop {r3} +; CHECK-V4T-NEXT: mov r12, [[POP_REG:r[0-7]]] +; CHECK-V4T-NEXT: pop {[[POP_REG]]} ; CHECK-V4T-NEXT: add sp, -; CHECK-V4T-NEXT: mov lr, r3 -; CHECK-V4T-NEXT: mov r3, r12 +; CHECK-V4T-NEXT: mov lr, [[POP_REG]] +; CHECK-V4T-NEXT: mov [[POP_REG]], r12 ; CHECK-V4T: bx lr ; CHECK-V5T: add sp, ; CHECK-V5T-NEXT: pop {[[SAVED]]} -; CHECK-V5T-NEXT: mov r12, r3 -; CHECK-V5T-NEXT: pop {r3} +; CHECK-V5T-NEXT: mov r12, [[POP_REG:r[0-7]]] +; CHECK-V5T-NEXT: pop {[[POP_REG]]} ; CHECK-V5T-NEXT: add sp, -; CHECK-V5T-NEXT: mov lr, r3 -; CHECK-V5T-NEXT: mov r3, r12 +; CHECK-V5T-NEXT: mov lr, [[POP_REG]] +; CHECK-V5T-NEXT: mov [[POP_REG]], r12 ; CHECK-V5T-NEXT: bx lr } @@ -95,8 +106,13 @@ entry: ; Epilogue ; -------- ; CHECK-V4T: pop {[[SAVED]]} -; CHECK-V4T: pop {r3} -; CHECK-V4T: bx r3 +; The ISA for v4 does not support pop pc, so make sure we do not emit +; one even when we do not need to update SP. +; CHECK-V4T-NOT: pop {pc} +; Pop the value of LR into a scratch lo register other than r0 (it is +; used for the return value). +; CHECK-V4T-NEXT: pop {[[POP_REG:r[1-3]]]} +; CHECK-V4T-NEXT: bx [[POP_REG]] ; CHECK-V5T: pop {[[SAVED]], pc} } @@ -148,14 +164,18 @@ entry: ; -------- ; CHECK-V4T: add sp, ; CHECK-V4T-NEXT: pop {[[SAVED]]} -; CHECK-V4T-NEXT: pop {r3} +; Only r1 to r3 are available to pop LR. +; r0 is used for the return value. +; CHECK-V4T-NEXT: pop {[[POP_REG:r[1-3]]]} ; CHECK-V4T-NEXT: add sp, -; CHECK-V4T-NEXT: bx r3 +; CHECK-V4T-NEXT: bx [[POP_REG]] ; CHECK-V5T: add sp, ; CHECK-V5T-NEXT: pop {[[SAVED]]} -; CHECK-V5T-NEXT: pop {r3} +; Only r1 to r3 are available to pop LR. +; r0 is used for the return value. +; CHECK-V5T-NEXT: pop {[[POP_REG:r[1-3]]]} ; CHECK-V5T-NEXT: add sp, -; CHECK-V5T-NEXT: bx r3 +; CHECK-V5T-NEXT: bx [[POP_REG]] } ; CHECK-V4T-LABEL: noframe @@ -191,13 +211,17 @@ entry: ; Epilogue ; -------- ; CHECK-V4T: pop {[[SAVED]]} -; CHECK-V4T-NEXT: pop {r3} +; Only r1 to r3 are available to pop LR. +; r0 is used for the return value. +; CHECK-V4T-NEXT: pop {[[POP_REG:r[1-3]]]} ; CHECK-V4T-NEXT: add sp, -; CHECK-V4T-NEXT: bx r3 +; CHECK-V4T-NEXT: bx [[POP_REG]] ; CHECK-V5T: pop {[[SAVED]]} -; CHECK-V5T-NEXT: pop {r3} +; Only r1 to r3 are available to pop LR. +; r0 is used for the return value. +; CHECK-V5T-NEXT: pop {[[POP_REG:r[1-3]]]} ; CHECK-V5T-NEXT: add sp, -; CHECK-V5T-NEXT: bx r3 +; CHECK-V5T-NEXT: bx [[POP_REG]] } declare void @llvm.va_start(i8*) nounwind diff --git a/test/CodeGen/ARM/thumb2-it-block.ll b/test/CodeGen/ARM/thumb2-it-block.ll index 2675a733da97..aaefc0a14863 100644 --- a/test/CodeGen/ARM/thumb2-it-block.ll +++ b/test/CodeGen/ARM/thumb2-it-block.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck -check-prefix CHECK-V7 %s -; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s -check-prefix CHECK-V8 +; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s ; PR11107 define i32 @test(i32 %a, i32 %b) { @@ -14,17 +14,13 @@ entry: ret i32 %add } -; CHECK-V7: cmp -; CHECK-V7-NEXT: it mi -; CHECK-V7-NEXT: rsbmi -; CHECK-V7-NEXT: cmp -; CHECK-V7-NEXT: it mi -; CHECK-V7-NEXT: rsbmi +; CHECK: cmp +; CHECK-NEXT: it mi +; We shouldn't need to check for the extra 's' here; tRSB should be printed as +; "rsb" inside an IT block, not "rsbs". +; CHECK-NEXT: rsb{{s?}}mi +; CHECK-NEXT: cmp +; CHECK-NEXT: it mi +; CHECK-NEXT: rsb{{s?}}mi -; CHECK-V8: cmp -; CHECK-V8-NEXT: bpl -; CHECK-V8: rsbs -; CHECK-V8: cmp -; CHECK-V8-NEXT: bpl -; CHECK-V8: rsbs diff --git a/test/CodeGen/ARM/thumb_indirect_calls.ll b/test/CodeGen/ARM/thumb_indirect_calls.ll index 9f1950c743c0..67346c6fde9c 100644 --- a/test/CodeGen/ARM/thumb_indirect_calls.ll +++ b/test/CodeGen/ARM/thumb_indirect_calls.ll @@ -3,7 +3,7 @@ @f = common global void (i32)* null, align 4 -; CHECK-LABEL foo: +; CHECK-LABEL: foo: define void @foo(i32 %x) { entry: %0 = load void (i32)*, void (i32)** @f, align 4 @@ -21,7 +21,7 @@ entry: ; CHECK-V5T: blx [[CALLEE]] } -; CHECK-LABEL bar: +; CHECK-LABEL: bar: define void @bar(void (i32)* nocapture %g, i32 %x, void (i32)* nocapture %h) { entry: tail call void %g(i32 %x) @@ -37,4 +37,3 @@ entry: ; CHECK-V5T: blx ; CHECK-V5T: blx } - diff --git a/test/CodeGen/ARM/tls-models.ll b/test/CodeGen/ARM/tls-models.ll index 42c1ba911028..f3c58f74ebf7 100644 --- a/test/CodeGen/ARM/tls-models.ll +++ b/test/CodeGen/ARM/tls-models.ll @@ -1,5 +1,11 @@ -; RUN: llc -march=arm -mtriple=arm-linux-gnueabi < %s | FileCheck -check-prefix=CHECK-NONPIC %s -; RUN: llc -march=arm -mtriple=arm-linux-gnueabi -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-PIC %s +; RUN: llc -march=arm -mtriple=arm-linux-gnueabi < %s \ +; RUN: | FileCheck -check-prefix=CHECK-NONPIC -check-prefix=COMMON %s +; RUN: llc -march=arm -mtriple=arm-linux-gnueabi -relocation-model=pic < %s \ +; RUN: | FileCheck -check-prefix=CHECK-PIC -check-prefix=COMMON %s +; RUN: llc -emulated-tls -march=arm -mtriple=arm-linux-gnueabi < %s \ +; RUN: | FileCheck -check-prefix=EMUNONPIC -check-prefix=EMU -check-prefix=COMMON %s +; RUN: llc -emulated-tls -march=arm -mtriple=arm-linux-gnueabi -relocation-model=pic < %s \ +; RUN: | FileCheck -check-prefix=EMUPIC -check-prefix=EMU -check-prefix=COMMON %s @external_gd = external thread_local global i32 @@ -20,23 +26,23 @@ define i32* @f1() { entry: ret i32* @external_gd + ; COMMON-LABEL: f1: ; Non-PIC code can use initial-exec, PIC code has to use general dynamic. - ; CHECK-NONPIC-LABEL: f1: ; CHECK-NONPIC: external_gd(GOTTPOFF) - ; CHECK-PIC-LABEL: f1: ; CHECK-PIC: external_gd(TLSGD) + ; EMU: __emutls_get_address } define i32* @f2() { entry: ret i32* @internal_gd + ; COMMON-LABEL: f2: ; Non-PIC code can use local exec, PIC code can use local dynamic, ; but that is not implemented, so falls back to general dynamic. - ; CHECK-NONPIC-LABEL: f2: ; CHECK-NONPIC: internal_gd(TPOFF) - ; CHECK-PIC-LABEL: f2: ; CHECK-PIC: internal_gd(TLSGD) + ; EMU: __emutls_get_address } @@ -46,24 +52,24 @@ define i32* @f3() { entry: ret i32* @external_ld + ; COMMON-LABEL: f3: ; Non-PIC code can use initial exec, PIC should use local dynamic, ; but that is not implemented, so falls back to general dynamic. - ; CHECK-NONPIC-LABEL: f3: ; CHECK-NONPIC: external_ld(GOTTPOFF) - ; CHECK-PIC-LABEL: f3: ; CHECK-PIC: external_ld(TLSGD) + ; EMU: __emutls_get_address } define i32* @f4() { entry: ret i32* @internal_ld + ; COMMON-LABEL: f4: ; Non-PIC code can use local exec, PIC code can use local dynamic, ; but that is not implemented, so it falls back to general dynamic. - ; CHECK-NONPIC-LABEL: f4: ; CHECK-NONPIC: internal_ld(TPOFF) - ; CHECK-PIC-LABEL: f4: ; CHECK-PIC: internal_ld(TLSGD) + ; EMU: __emutls_get_address } @@ -73,22 +79,22 @@ define i32* @f5() { entry: ret i32* @external_ie + ; COMMON-LABEL: f5: ; Non-PIC and PIC code will use initial exec as specified. - ; CHECK-NONPIC-LABEL: f5: ; CHECK-NONPIC: external_ie(GOTTPOFF) - ; CHECK-PIC-LABEL: f5: ; CHECK-PIC: external_ie(GOTTPOFF) + ; EMU: __emutls_get_address } define i32* @f6() { entry: ret i32* @internal_ie + ; COMMON-LABEL: f6: ; Non-PIC code can use local exec, PIC code use initial exec as specified. - ; CHECK-NONPIC-LABEL: f6: ; CHECK-NONPIC: internal_ie(TPOFF) - ; CHECK-PIC-LABEL: f6: ; CHECK-PIC: internal_ie(GOTTPOFF) + ; EMU: __emutls_get_address } @@ -98,20 +104,52 @@ define i32* @f7() { entry: ret i32* @external_le + ; COMMON-LABEL: f7: ; Non-PIC and PIC code will use local exec as specified. - ; CHECK-NONPIC-LABEL: f7: ; CHECK-NONPIC: external_le(TPOFF) - ; CHECK-PIC-LABEL: f7: ; CHECK-PIC: external_le(TPOFF) + ; EMU: __emutls_get_address } define i32* @f8() { entry: ret i32* @internal_le + ; COMMON-LABEL: f8: ; Non-PIC and PIC code will use local exec as specified. - ; CHECK-NONPIC-LABEL: f8: ; CHECK-NONPIC: internal_le(TPOFF) - ; CHECK-PIC-LABEL: f8: ; CHECK-PIC: internal_le(TPOFF) + ; EMU: __emutls_get_address } + + +; ----- emulated specified ----- + +; External declaration has no initializer. +; Internal definition has initializer. + +; EMU-NOT: __emutls_t.external_gd +; EMU-NOT: __emutls_v.external_gd +; EMU: .align 2 +; EMU-LABEL: __emutls_v.internal_gd: +; EMU-NEXT: .long 4 +; EMU-NEXT: .long 4 +; EMU-NEXT: .long 0 +; EMU-NEXT: .long __emutls_t.internal_gd +; EMU-LABEL: __emutls_t.internal_gd: +; EMU-NEXT: .long 42 +; EMU-NOT: __emutls_t.external_gd + +; __emutls_t and __emutls_v are the same for PIC and non-PIC modes. + +; EMU-NOT: __emutls_t.external_gd +; EMU-NOT: __emutls_v.external_gd +; EMU: .align 2 +; EMU-LABEL: __emutls_v.internal_le: +; EMU-NEXT: .long 4 +; EMU-NEXT: .long 4 +; EMU-NEXT: .long 0 +; EMU-NEXT: .long __emutls_t.internal_le +; EMU-LABEL: __emutls_t.internal_le: +; EMU-NEXT: .long 42 +; EMU-NOT: __emutls_t.external_le diff --git a/test/CodeGen/ARM/tls3.ll b/test/CodeGen/ARM/tls3.ll index 7e17b13a3c99..94cadeedd938 100644 --- a/test/CodeGen/ARM/tls3.ll +++ b/test/CodeGen/ARM/tls3.ll @@ -1,11 +1,34 @@ ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ ; RUN: grep "tbss" +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=NOEMU +; RUN: llc < %s -emulated-tls -march=arm -mtriple=arm-linux-gnueabi | \ +; RUN: FileCheck %s -check-prefix=CHECK -check-prefix=EMU %struct.anon = type { i32, i32 } -@teste = internal thread_local global %struct.anon zeroinitializer ; <%struct.anon*> [#uses=1] +@teste = internal thread_local global %struct.anon zeroinitializer ; <%struct.anon*> [#uses=1] define i32 @main() { entry: - %tmp2 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @teste, i32 0, i32 0), align 8 ; <i32> [#uses=1] - ret i32 %tmp2 + %tmp2 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @teste, i32 0, i32 0), align 8 ; <i32> [#uses=1] + ret i32 %tmp2 } + +; CHECK-LABEL: main: +; NOEMU-NOT: __emutls_get_address + +; NOEMU: .section .tbss +; NOEMU-LABEL: teste: +; NOEMU-NEXT: .zero 8 + +; CHECK-NOT: __emutls_t.teste + +; EMU: .align 2 +; EMU-LABEL: __emutls_v.teste: +; EMU-NEXT: .long 8 +; EMU-NEXT: .long 4 +; EMU-NEXT: .long 0 +; EMU-NEXT: .long 0 + +; CHECK-NOT: teste: +; CHECK-NOT: __emutls_t.teste diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index 0be3917ffa26..4e16bda6c4d9 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=arm-eabi -pre-RA-sched=source %s -o - \ +; RUN: llc -mtriple=arm-eabi -pre-RA-sched=source -mattr=+strict-align %s -o - \ ; RUN: | FileCheck %s -check-prefix=EXPANDED -; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 -mattr=-neon -arm-strict-align -pre-RA-sched=source %s -o - \ +; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 -mattr=-neon,+strict-align -pre-RA-sched=source %s -o - \ ; RUN: | FileCheck %s -check-prefix=EXPANDED ; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 %s -o - \ diff --git a/test/CodeGen/ARM/unaligned_load_store_vfp.ll b/test/CodeGen/ARM/unaligned_load_store_vfp.ll new file mode 100644 index 000000000000..90d17e19c286 --- /dev/null +++ b/test/CodeGen/ARM/unaligned_load_store_vfp.ll @@ -0,0 +1,98 @@ +; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s + +define float @test_load_s32_float(i32* %addr) { +; CHECK-LABEL: test_load_s32_float: +; CHECK: ldr [[TMP:r[0-9]+]], [r0] +; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]] +; CHECK: vcvt.f32.s32 s0, [[RES_INT]] + + %val = load i32, i32* %addr, align 1 + %res = sitofp i32 %val to float + ret float %res +} + +define double @test_load_s32_double(i32* %addr) { +; CHECK-LABEL: test_load_s32_double: +; CHECK: ldr [[TMP:r[0-9]+]], [r0] +; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]] +; CHECK: vcvt.f64.s32 d0, [[RES_INT]] + + %val = load i32, i32* %addr, align 1 + %res = sitofp i32 %val to double + ret double %res +} + +define float @test_load_u32_float(i32* %addr) { +; CHECK-LABEL: test_load_u32_float: +; CHECK: ldr [[TMP:r[0-9]+]], [r0] +; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]] +; CHECK: vcvt.f32.u32 s0, [[RES_INT]] + + %val = load i32, i32* %addr, align 1 + %res = uitofp i32 %val to float + ret float %res +} + +define double @test_load_u32_double(i32* %addr) { +; CHECK-LABEL: test_load_u32_double: +; CHECK: ldr [[TMP:r[0-9]+]], [r0] +; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]] +; CHECK: vcvt.f64.u32 d0, [[RES_INT]] + + %val = load i32, i32* %addr, align 1 + %res = uitofp i32 %val to double + ret double %res +} + +define void @test_store_f32(float %in, float* %addr) { +; CHECK-LABEL: test_store_f32: +; CHECK: vmov [[TMP:r[0-9]+]], s0 +; CHECK: str [[TMP]], [r0] + + store float %in, float* %addr, align 1 + ret void +} + +define void @test_store_float_s32(float %in, i32* %addr) { +; CHECK-LABEL: test_store_float_s32: +; CHECK: vcvt.s32.f32 [[TMP:s[0-9]+]], s0 +; CHECK: vmov [[TMP_INT:r[0-9]+]], [[TMP]] +; CHECK: str [[TMP_INT]], [r0] + + %val = fptosi float %in to i32 + store i32 %val, i32* %addr, align 1 + ret void +} + +define void @test_store_double_s32(double %in, i32* %addr) { +; CHECK-LABEL: test_store_double_s32: +; CHECK: vcvt.s32.f64 [[TMP:s[0-9]+]], d0 +; CHECK: vmov [[TMP_INT:r[0-9]+]], [[TMP]] +; CHECK: str [[TMP_INT]], [r0] + + %val = fptosi double %in to i32 + store i32 %val, i32* %addr, align 1 + ret void +} + +define void @test_store_float_u32(float %in, i32* %addr) { +; CHECK-LABEL: test_store_float_u32: +; CHECK: vcvt.u32.f32 [[TMP:s[0-9]+]], s0 +; CHECK: vmov [[TMP_INT:r[0-9]+]], [[TMP]] +; CHECK: str [[TMP_INT]], [r0] + + %val = fptoui float %in to i32 + store i32 %val, i32* %addr, align 1 + ret void +} + +define void @test_store_double_u32(double %in, i32* %addr) { +; CHECK-LABEL: test_store_double_u32: +; CHECK: vcvt.u32.f64 [[TMP:s[0-9]+]], d0 +; CHECK: vmov [[TMP_INT:r[0-9]+]], [[TMP]] +; CHECK: str [[TMP_INT]], [r0] + + %val = fptoui double %in to i32 + store i32 %val, i32* %addr, align 1 + ret void +} diff --git a/test/CodeGen/ARM/usat-lower.ll b/test/CodeGen/ARM/usat-lower.ll new file mode 100644 index 000000000000..58d3bba5a1f8 --- /dev/null +++ b/test/CodeGen/ARM/usat-lower.ll @@ -0,0 +1,11 @@ +; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s + +; immediate argument < lower-bound +; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat +define i32 @usat1() nounwind { + %tmp = call i32 @llvm.arm.usat(i32 128, i32 -1) + ret i32 %tmp +} + +declare i32 @llvm.arm.usat(i32, i32) nounwind readnone diff --git a/test/CodeGen/ARM/usat-upper.ll b/test/CodeGen/ARM/usat-upper.ll new file mode 100644 index 000000000000..84ad694725b4 --- /dev/null +++ b/test/CodeGen/ARM/usat-upper.ll @@ -0,0 +1,11 @@ +; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s + +; immediate argument > upper-bound +; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat +define i32 @usat1() nounwind { + %tmp = call i32 @llvm.arm.usat(i32 128, i32 32) + ret i32 %tmp +} + +declare i32 @llvm.arm.usat(i32, i32) nounwind readnone diff --git a/test/CodeGen/ARM/v7k-abi-align.ll b/test/CodeGen/ARM/v7k-abi-align.ll new file mode 100644 index 000000000000..e9b67f22edf2 --- /dev/null +++ b/test/CodeGen/ARM/v7k-abi-align.ll @@ -0,0 +1,152 @@ +; RUN: llc -mtriple=thumbv7k-apple-watchos2.0 -o - %s | FileCheck %s + +%struct = type { i8, i64, i8, double, i8, <2 x float>, i8, <4 x float> } + +define i32 @test_i64_align() { +; CHECK-LABEL: test_i64_align: +; CHECL: movs r0, #8 + ret i32 ptrtoint(i64* getelementptr(%struct, %struct* null, i32 0, i32 1) to i32) +} + +define i32 @test_f64_align() { +; CHECK-LABEL: test_f64_align: +; CHECL: movs r0, #24 + ret i32 ptrtoint(double* getelementptr(%struct, %struct* null, i32 0, i32 3) to i32) +} + +define i32 @test_v2f32_align() { +; CHECK-LABEL: test_v2f32_align: +; CHECL: movs r0, #40 + ret i32 ptrtoint(<2 x float>* getelementptr(%struct, %struct* null, i32 0, i32 5) to i32) +} + +define i32 @test_v4f32_align() { +; CHECK-LABEL: test_v4f32_align: +; CHECL: movs r0, #64 + ret i32 ptrtoint(<4 x float>* getelementptr(%struct, %struct* null, i32 0, i32 7) to i32) +} + +; Key point here is than an extra register has to be saved so that the DPRs end +; up in an aligned location (as prologue/epilogue inserter had calculated). +define void @test_dpr_unwind_align() { +; CHECK-LABEL: test_dpr_unwind_align: +; CHECK: push {r5, r6, r7, lr} +; CHECK-NOT: sub sp +; CHECK: vpush {d8, d9} +; CHECK: .cfi_offset d9, -24 +; CHECK: .cfi_offset d8, -32 +; [...] +; CHECK: bl _test_i64_align +; CHECK-NOT: add sp, +; CHECK: vpop {d8, d9} +; CHECK-NOT: add sp, +; CHECK: pop {r5, r6, r7, pc} + + call void asm sideeffect "", "~{r6},~{d8},~{d9}"() + + ; Whatever + call i32 @test_i64_align() + ret void +} + +; This time, there's no viable way to tack CS-registers onto the list: a real SP +; adjustment needs to be performed to put d8 and d9 where they should be. +define void @test_dpr_unwind_align_manually() { +; CHECK-LABEL: test_dpr_unwind_align_manually: +; CHECK: push {r4, r5, r6, r7, lr} +; CHECK-NOT: sub sp +; CHECK: push.w {r8, r11} +; CHECK: sub sp, #4 +; CHECK: vpush {d8, d9} +; CHECK: .cfi_offset d9, -40 +; CHECK: .cfi_offset d8, -48 +; [...] +; CHECK: bl _test_i64_align +; CHECK-NOT: add sp, +; CHECK: vpop {d8, d9} +; CHECK: add sp, #4 +; CHECK: pop.w {r8, r11} +; CHECK: pop {r4, r5, r6, r7, pc} + + call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{d8},~{d9}"() + + ; Whatever + call i32 @test_i64_align() + ret void +} + +; If there's only a CS1 area, the sub should be in the right place: +define void @test_dpr_unwind_align_just_cs1() { +; CHECK-LABEL: test_dpr_unwind_align_just_cs1: +; CHECK: push {r4, r5, r6, r7, lr} +; CHECK: sub sp, #4 +; CHECK: vpush {d8, d9} +; CHECK: .cfi_offset d9, -32 +; CHECK: .cfi_offset d8, -40 +; CHECK: sub sp, #8 +; [...] +; CHECK: bl _test_i64_align +; CHECK: add sp, #8 +; CHECK: vpop {d8, d9} +; CHECK: add sp, #4 +; CHECK: pop {r4, r5, r6, r7, pc} + + call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{d8},~{d9}"() + + ; Whatever + call i32 @test_i64_align() + ret void +} + +; If there are no DPRs, we shouldn't try to align the stack in stages anyway +define void @test_dpr_unwind_align_no_dprs() { +; CHECK-LABEL: test_dpr_unwind_align_no_dprs: +; CHECK: push {r4, r5, r6, r7, lr} +; CHECK: sub sp, #12 +; [...] +; CHECK: bl _test_i64_align +; CHECK: add sp, #12 +; CHECK: pop {r4, r5, r6, r7, pc} + + call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7}"() + + ; Whatever + call i32 @test_i64_align() + ret void +} + +; 128-bit vectors should use 128-bit (i.e. correctly aligned) slots on +; the stack. +define <4 x float> @test_v128_stack_pass([8 x double], float, <4 x float> %in) { +; CHECK-LABEL: test_v128_stack_pass: +; CHECK: add r[[ADDR:[0-9]+]], sp, #16 +; CHECK: vld1.64 {d0, d1}, [r[[ADDR]]:128] + + ret <4 x float> %in +} + +declare void @varargs(i32, ...) + +; When varargs are enabled, we go down a different route. Still want 128-bit +; alignment though. +define void @test_v128_stack_pass_varargs(<4 x float> %in) { +; CHECK-LABEL: test_v128_stack_pass_varargs: +; CHECK: add r[[ADDR:[0-9]+]], sp, #16 +; CHECK: vst1.64 {d0, d1}, [r[[ADDR]]:128] + + call void(i32, ...) @varargs(i32 undef, [3 x i32] undef, float undef, <4 x float> %in) + ret void +} + +; To be compatible with AAPCS's va_start model (store r0-r3 at incoming SP, give +; a single pointer), 64-bit quantities must be pass +define i64 @test_64bit_gpr_align(i32, i64 %r2_r3, i32 %sp) { +; CHECK-LABEL: test_64bit_gpr_align: +; CHECK: ldr [[RHS:r[0-9]+]], [sp] +; CHECK: adds r0, [[RHS]], r2 +; CHECK: adc r1, r3, #0 + + %ext = zext i32 %sp to i64 + %sum = add i64 %ext, %r2_r3 + ret i64 %sum +} diff --git a/test/CodeGen/ARM/v7k-libcalls.ll b/test/CodeGen/ARM/v7k-libcalls.ll new file mode 100644 index 000000000000..a1dfb07ca614 --- /dev/null +++ b/test/CodeGen/ARM/v7k-libcalls.ll @@ -0,0 +1,154 @@ +; RUN: llc -mtriple=armv7k-apple-watchos2.0 -mcpu=cortex-a7 < %s | FileCheck %s + +define arm_aapcs_vfpcc float @t1(float %a, float %b) { +entry: +; CHECK: t1 +; CHECK-NOT: vmov +; CHECK: vadd.f32 + %a.addr = alloca float, align 4 + %b.addr = alloca float, align 4 + store float %a, float* %a.addr, align 4 + store float %b, float* %b.addr, align 4 + %0 = load float, float* %a.addr, align 4 + %1 = load float, float* %b.addr, align 4 + %add = fadd float %0, %1 + ret float %add +} + +define arm_aapcs_vfpcc double @t2(double %a, double %b) { +entry: +; CHECK: t2 +; CHECK-NOT: vmov +; CHECK: vadd.f64 + %a.addr = alloca double, align 8 + %b.addr = alloca double, align 8 + store double %a, double* %a.addr, align 8 + store double %b, double* %b.addr, align 8 + %0 = load double, double* %a.addr, align 8 + %1 = load double, double* %b.addr, align 8 + %add = fadd double %0, %1 + ret double %add +} + +define arm_aapcs_vfpcc i64 @t3(double %ti) { +entry: +; CHECK-LABEL: t3: +; CHECK-NOT: vmov +; CHECK: bl ___fixunsdfdi + %conv = fptoui double %ti to i64 + ret i64 %conv +} + +define arm_aapcs_vfpcc i64 @t4(double %ti) { +entry: +; CHECK-LABEL: t4: +; CHECK-NOT: vmov +; CHECK: bl ___fixdfdi + %conv = fptosi double %ti to i64 + ret i64 %conv +} + +define arm_aapcs_vfpcc double @t5(i64 %ti) { +entry: +; CHECK-LABEL: t5: +; CHECK: bl ___floatundidf +; CHECK-NOT: vmov +; CHECK: pop + %conv = uitofp i64 %ti to double + ret double %conv +} + +define arm_aapcs_vfpcc double @t6(i64 %ti) { +entry: +; CHECK-LABEL: t6: +; CHECK: bl ___floatdidf +; CHECK-NOT: vmov +; CHECK: pop + %conv = sitofp i64 %ti to double + ret double %conv +} + +define arm_aapcs_vfpcc float @t7(i64 %ti) { +entry: +; CHECK-LABEL: t7: +; CHECK: bl ___floatundisf +; CHECK-NOT: vmov +; CHECK: pop + %conv = uitofp i64 %ti to float + ret float %conv +} + +define arm_aapcs_vfpcc float @t8(i64 %ti) { +entry: +; CHECK-LABEL: t8: +; CHECK: bl ___floatdisf +; CHECK-NOT: vmov +; CHECK: pop + %conv = sitofp i64 %ti to float + ret float %conv +} + +define arm_aapcs_vfpcc double @t9(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %a, float %b) { +entry: +; CHECK-LABEL: t9: +; CHECK-NOT: vmov +; CHECK: vldr + %add = fadd float %a, %b + %conv = fpext float %add to double + ret double %conv +} + +define arm_aapcs_vfpcc double @t10(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %a, float %b, double %c) { +entry: +; CHECK-LABEL: t10: +; CHECK-NOT: vmov +; CHECK: vldr + %add = fadd double %a, %c + ret double %add +} + +define arm_aapcs_vfpcc float @t11(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, float %a, double %b, float %c) { +entry: +; CHECK-LABEL: t11: +; CHECK: vldr + %add = fadd float %a, %c + ret float %add +} + +; rdar://16039676 +define arm_aapcs_vfpcc double @t12(double %a, double %b) { +entry: +; CHECK-LABEL: t12: +; CHECK: vstr + %add = fadd double %a, %b + %sub = fsub double %a, %b + %call = tail call arm_aapcs_vfpcc double @x(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double %add, float 0.000000e+00, double %sub) + ret double %call +} + +define arm_aapcs_vfpcc double @t13(double %x) { +entry: +; CHECK-LABEL: t13: +; CHECK-NOT: vmov +; CHECK: bl ___sincos_stret + %call = tail call arm_aapcs_vfpcc double @cos(double %x) + %call1 = tail call arm_aapcs_vfpcc double @sin(double %x) + %mul = fmul double %call, %call1 + ret double %mul +} + +define arm_aapcs_vfpcc double @t14(double %x) { +; CHECK-LABEL: t14: +; CHECK-NOT: vmov +; CHECK: b ___exp10 + %__exp10 = tail call double @__exp10(double %x) #1 + ret double %__exp10 +} + +declare arm_aapcs_vfpcc double @x(double, double, double, double, double, double, double, float, double) +declare arm_aapcs_vfpcc double @cos(double) #0 +declare arm_aapcs_vfpcc double @sin(double) #0 +declare double @__exp10(double) + +attributes #0 = { readnone } +attributes #1 = { readonly } diff --git a/test/CodeGen/ARM/v7k-sincos.ll b/test/CodeGen/ARM/v7k-sincos.ll new file mode 100644 index 000000000000..b89d4dc8120b --- /dev/null +++ b/test/CodeGen/ARM/v7k-sincos.ll @@ -0,0 +1,16 @@ +; RUN: llc -mtriple=thumbv7k-apple-watchos2.0 -o - %s | FileCheck %s + +declare double @sin(double) nounwind readnone +declare double @cos(double) nounwind readnone + +define double @test_stret(double %in) { +; CHECK-LABEL: test_stret: +; CHECK: blx ___sincos_stret +; CHECK-NOT: ldr +; CHECK: vadd.f64 d0, d0, d1 + + %sin = call double @sin(double %in) + %cos = call double @cos(double %in) + %sum = fadd double %sin, %cos + ret double %sum +} diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll index 2cd33cf3a422..e34b3e5e365a 100644 --- a/test/CodeGen/ARM/vcge.ll +++ b/test/CodeGen/ARM/vcge.ll @@ -196,8 +196,8 @@ entry: %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %4 = add <8 x i16> %3, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %5 = trunc <8 x i16> %4 to <8 x i8> - tail call void @llvm.arm.neon.vst1.v8i8(i8* undef, <8 x i8> %5, i32 1) + tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* undef, <8 x i8> %5, i32 1) unreachable } -declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind diff --git a/test/CodeGen/ARM/vcombine.ll b/test/CodeGen/ARM/vcombine.ll index 9491c15aef58..fc171889f5f8 100644 --- a/test/CodeGen/ARM/vcombine.ll +++ b/test/CodeGen/ARM/vcombine.ll @@ -2,11 +2,15 @@ ; RUN: llc -mtriple=armeb-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -; CHECK: vcombine8 -; CHECK-LE: vmov r0, r1, d16 -; CHECK-LE: vmov r2, r3, d17 -; CHECK-BE: vmov r1, r0, d16 -; CHECK-BE: vmov r3, r2, d17 +; CHECK-LABEL: vcombine8 +; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0] +; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] + +; CHECK-LE-DAG: vmov r0, r1, [[LD0]] +; CHECK-LE-DAG: vmov r2, r3, [[LD1]] + +; CHECK-BE-DAG: vmov r1, r0, d16 +; CHECK-BE-DAG: vmov r3, r2, d17 %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -14,11 +18,15 @@ define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -; CHECK: vcombine16 -; CHECK-LE: vmov r0, r1, d16 -; CHECK-LE: vmov r2, r3, d17 -; CHECK-BE: vmov r1, r0, d16 -; CHECK-BE: vmov r3, r2, d17 +; CHECK-LABEL: vcombine16 +; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0] +; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] + +; CHECK-LE-DAG: vmov r0, r1, [[LD0]] +; CHECK-LE-DAG: vmov r2, r3, [[LD1]] + +; CHECK-BE-DAG: vmov r1, r0, d16 +; CHECK-BE-DAG: vmov r3, r2, d17 %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -26,9 +34,14 @@ define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -; CHECK: vcombine32 -; CHECK-LE: vmov r0, r1, d16 -; CHECK-LE: vmov r2, r3, d17 +; CHECK-LABEL: vcombine32 + +; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0] +; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] + +; CHECK-LE: vmov r0, r1, [[LD0]] +; CHECK-LE: vmov r2, r3, [[LD1]] + ; CHECK-BE: vmov r1, r0, d16 ; CHECK-BE: vmov r3, r2, d17 %tmp1 = load <2 x i32>, <2 x i32>* %A @@ -38,9 +51,14 @@ define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind { -; CHECK: vcombinefloat -; CHECK-LE: vmov r0, r1, d16 -; CHECK-LE: vmov r2, r3, d17 +; CHECK-LABEL: vcombinefloat + +; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0] +; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] + +; CHECK-LE: vmov r0, r1, [[LD0]] +; CHECK-LE: vmov r2, r3, [[LD1]] + ; CHECK-BE: vmov r1, r0, d16 ; CHECK-BE: vmov r3, r2, d17 %tmp1 = load <2 x float>, <2 x float>* %A @@ -50,11 +68,15 @@ define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind { } define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -; CHECK: vcombine64 -; CHECK-LE: vmov r0, r1, d16 -; CHECK-LE: vmov r2, r3, d17 -; CHECK-BE: vmov r1, r0, d16 -; CHECK-BE: vmov r3, r2, d17 +; CHECK-LABEL: vcombine64 +; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0] +; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1] + +; CHECK-LE: vmov r0, r1, [[LD0]] +; CHECK-LE: vmov r2, r3, [[LD1]] + +; CHECK-BE: vmov r1, r0, [[LD0]] +; CHECK-BE: vmov r3, r2, [[LD1]] %tmp1 = load <1 x i64>, <1 x i64>* %A %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32> <i32 0, i32 1> diff --git a/test/CodeGen/ARM/vcvt_combine.ll b/test/CodeGen/ARM/vcvt_combine.ll index 0c856e8d7617..9a8f084d2303 100644 --- a/test/CodeGen/ARM/vcvt_combine.ll +++ b/test/CodeGen/ARM/vcvt_combine.ll @@ -1,95 +1,64 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s -@in = global float 0x400921FA00000000, align 4 - ; Test signed conversion. -; CHECK: t0 -; CHECK-NOT: vmul -define void @t0() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> +; CHECK-LABEL: @t0 +; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #2 +; CHECK: bx lr +define <2 x i32> @t0(<2 x float> %in) { + %mul.i = fmul <2 x float> %in, <float 4.0, float 4.0> %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> - tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } -declare void @foo_int32x2_t(<2 x i32>) - ; Test unsigned conversion. -; CHECK: t1 -; CHECK-NOT: vmul -define void @t1() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> +; CHECK-LABEL: @t1 +; CHECK: vcvt.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #3 +; CHECK: bx lr +define <2 x i32> @t1(<2 x float> %in) { + %mul.i = fmul <2 x float> %in, <float 8.0, float 8.0> %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32> - tail call void @foo_uint32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } -declare void @foo_uint32x2_t(<2 x i32>) - ; Test which should not fold due to non-power of 2. -; CHECK: t2 +; CHECK-LABEL: @t2 ; CHECK: vmul -define void @t2() nounwind { +; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} +; CHECK: bx lr +define <2 x i32> @t2(<2 x float> %in) { entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000> + %mul.i = fmul <2 x float> %in, <float 0x401B333340000000, float 0x401B333340000000> %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> - tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } ; Test which should not fold due to power of 2 out of range. -; CHECK: t3 +; CHECK-LABEL: @t3 ; CHECK: vmul -define void @t3() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000> +; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} +; CHECK: bx lr +define <2 x i32> @t3(<2 x float> %in) { + %mul.i = fmul <2 x float> %in, <float 0x4200000000000000, float 0x4200000000000000> %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> - tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } ; Test which case where const is max power of 2 (i.e., 2^32). -; CHECK: t4 -; CHECK-NOT: vmul -define void @t4() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000> +; CHECK-LABEL: @t4 +; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #32 +; CHECK: bx lr +define <2 x i32> @t4(<2 x float> %in) { + %mul.i = fmul <2 x float> %in, <float 0x41F0000000000000, float 0x41F0000000000000> %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> - tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } ; Test quadword. -; CHECK: t5 -; CHECK-NOT: vmul -define void @t5() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1 - %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2 - %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %tmp, i32 3 - %mul.i = fmul <4 x float> %vecinit6.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00> +; CHECK-LABEL: @t5 +; CHECK: vcvt.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}, #3 +; CHECK: bx lr +define <4 x i32> @t5(<4 x float> %in) { + %mul.i = fmul <4 x float> %in, <float 8.0, float 8.0, float 8.0, float 8.0> %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32> - tail call void @foo_int32x4_t(<4 x i32> %vcvt.i) nounwind - ret void + ret <4 x i32> %vcvt.i } - -declare void @foo_int32x4_t(<4 x i32>) diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll index 8c6e4ba35054..8511dbcb6876 100644 --- a/test/CodeGen/ARM/vdiv_combine.ll +++ b/test/CodeGen/ARM/vdiv_combine.ll @@ -136,3 +136,20 @@ define <2 x double> @fix_i64_to_double(<2 x i64> %in) { ret <2 x double> %shift } +; Don't combine with 8 lanes. Just make sure things don't crash. +; CHECK-LABEL: test7 +define <8 x float> @test7(<8 x i32> %in) nounwind { +entry: + %vcvt.i = sitofp <8 x i32> %in to <8 x float> + %div.i = fdiv <8 x float> %vcvt.i, <float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0> + ret <8 x float> %div.i +} + +; Can combine splat with an undef. +; CHECK-LABEL: test8 +; CHECK: vcvt.f32.s32 q{{[0-9]+}}, q{{[0-9]+}}, #1 +define <4 x float> @test8(<4 x i32> %in) { + %vcvt.i = sitofp <4 x i32> %in to <4 x float> + %div.i = fdiv <4 x float> %vcvt.i, <float 2.0, float 2.0, float 2.0, float undef> + ret <4 x float> %div.i +} diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll index 36eebbfc4650..25c4807d9862 100644 --- a/test/CodeGen/ARM/vdup.ll +++ b/test/CodeGen/ARM/vdup.ll @@ -364,3 +364,19 @@ define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) { %sub = fsub <4 x float> %splat.splat, %p ret <4 x float> %sub } + +; Also make sure we don't barf on variable-index extractelts, where we almost +; could have generated a vdup. + +define <8 x i8> @check_i8_varidx(<16 x i8> %v, i32 %idx) { +; CHECK-LABEL: check_i8_varidx: +; CHECK: mov r[[FP:[0-9]+]], sp +; CHECK: ldr r[[IDX:[0-9]+]], [r[[FP]], #4] +; CHECK: mov r[[SPCOPY:[0-9]+]], sp +; CHECK: vst1.64 {d{{.*}}, d{{.*}}}, [r[[SPCOPY]]:128], r[[IDX]] +; CHECK: vld1.8 {d{{.*}}[]}, [r[[SPCOPY]]] + %x = extractelement <16 x i8> %v, i32 %idx + %1 = insertelement <8 x i8> undef, i8 %x, i32 0 + %2 = insertelement <8 x i8> %1, i8 %x, i32 1 + ret <8 x i8> %2 +} diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll index 29f4bb972a24..2ef2a0697ec9 100644 --- a/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -78,11 +78,11 @@ entry: %2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = add <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %4 = trunc <8 x i16> %3 to <8 x i8> - tail call void @llvm.arm.neon.vst1.v8i8(i8* undef, <8 x i8> %4, i32 1) + tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* undef, <8 x i8> %4, i32 1) unreachable } -declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind ; Test that loads and stores of i64 vector elements are handled as f64 values ; so they are not split up into i32 values. Radar 8755338. diff --git a/test/CodeGen/ARM/vector-load.ll b/test/CodeGen/ARM/vector-load.ll index 17f134f458a2..a638c2bdb9be 100644 --- a/test/CodeGen/ARM/vector-load.ll +++ b/test/CodeGen/ARM/vector-load.ll @@ -238,12 +238,12 @@ define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) { define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) { ;CHECK-LABEL: zextload_v8i8tov8i32_fake_update: -;CHECK: ldr.w r[[PTRREG:[0-9]+]], [r0] +;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] ;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32] ;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16 -;CHECK: str.w r[[INCREG]], [r0] ;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}} ;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}} +;CHECK: str r[[INCREG]], [r0] %A = load <4 x i8>*, <4 x i8>** %ptr %lA = load <4 x i8>, <4 x i8>* %A, align 4 %inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4 diff --git a/test/CodeGen/ARM/vector-store.ll b/test/CodeGen/ARM/vector-store.ll index 30baa9a20ddc..161bbf1d0fde 100644 --- a/test/CodeGen/ARM/vector-store.ll +++ b/test/CodeGen/ARM/vector-store.ll @@ -228,9 +228,9 @@ define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) { ;CHECK: ldr.w r9, [sp] ;CHECK: vmov {{d[0-9]+}}, r3, r9 ;CHECK: vmov {{d[0-9]+}}, r1, r2 +;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] ;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}} ;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}} -;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] ;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32] %A = load <4 x i8>*, <4 x i8>** %ptr %trunc = trunc <4 x i32> %val to <4 x i8> @@ -243,10 +243,10 @@ define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) ;CHECK: ldr.w r9, [sp] ;CHECK: vmov {{d[0-9]+}}, r3, r9 ;CHECK: vmov {{d[0-9]+}}, r1, r2 -;CHECK: movs [[IMM16:r[0-9]+]], #16 +;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] ;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}} ;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}} -;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] +;CHECK: movs [[IMM16:r[0-9]+]], #16 ;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]] ;CHECK: str r[[PTRREG]], [r0] %A = load <4 x i8>*, <4 x i8>** %ptr diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index 72ecf0ef0626..394ecfb281fc 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextd: @@ -196,3 +196,35 @@ define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16> store <4 x i16> %tmp7, <4 x i16>* %dest, align 4 ret void } + +define <4 x i32> @test_reverse_and_extract(<2 x i32>* %A) { +entry: + ; CHECK-LABEL: test_reverse_and_extract + ; CHECK-NOT: vtrn + ; CHECK: vrev + ; CHECK: vext + %tmp1 = load <2 x i32>, <2 x i32>* %A + %0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 0> + ret <4 x i32> %0 +} + +define <4 x i32> @test_dup_and_extract(<2 x i32>* %A) { +entry: + ; CHECK-LABEL: test_dup_and_extract + ; CHECK-NOT: vtrn + ; CHECK: vdup + ; CHECK: vext + %tmp1 = load <2 x i32>, <2 x i32>* %A + %0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1> + ret <4 x i32> %0 +} + +define <4 x i32> @test_zip_and_extract(<2 x i32>* %A) { +entry: + ; CHECK-LABEL: test_zip_and_extract + ; CHECK: vzip + ; CHECK: vext + %tmp1 = load <2 x i32>, <2 x i32>* %A + %0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 1> + ret <4 x i32> %0 +} diff --git a/test/CodeGen/ARM/vfp-reg-stride.ll b/test/CodeGen/ARM/vfp-reg-stride.ll new file mode 100644 index 000000000000..c5339db68e30 --- /dev/null +++ b/test/CodeGen/ARM/vfp-reg-stride.ll @@ -0,0 +1,42 @@ +; RUN: llc -mcpu=swift -mtriple=thumbv7s-apple-ios -o - %s | FileCheck %s --check-prefix=CHECK-STRIDE4 +; RUN: llc -mcpu=swift -mtriple=thumbv7k-apple-watchos -o - %s | FileCheck %s --check-prefix=CHECK-STRIDE4-WATCH +; RUN: llc -mcpu=cortex-a57 -mtriple=thumbv7-linux-gnueabihf -o - %s | FileCheck %s --check-prefix=CHECK-GENERIC + +define void @test_reg_stride(double %a, double %b) { +; CHECK-STRIDE4-LABEL: test_reg_stride: +; CHECK-STRIDE4-DAG: vmov d16, r +; CHECK-STRIDE4-DAG: vmov d18, r + +; CHECK-STRIDE4-WATCH-LABEL: test_reg_stride: +; CHECK-STRIDE4-WATCH-DAG: vmov.f64 d16, d +; CHECK-STRIDE4-WATCH-DAG: vmov.f64 d18, d + +; CHECK-GENERIC-LABEL: test_reg_stride: +; CHECK-GENERIC-DAG: vmov.f64 d16, {{d[01]}} +; CHECK-GENERIC-DAG: vmov.f64 d17, {{d[01]}} + + call void asm "", "~{r0},~{r1},~{d0},~{d1}"() + call arm_aapcs_vfpcc void @eat_doubles(double %a, double %b) + ret void +} + +define void @test_stride_minsize(float %a, float %b) minsize { +; CHECK-STRIDE4-LABEL: test_stride_minsize: +; CHECK-STRIDE4: vmov d2, {{r[01]}} +; CHECK-STRIDE4: vmov d3, {{r[01]}} + +; CHECK-STRIDE4-WATCH-LABEL: test_stride_minsize: +; CHECK-STRIDE4-WATCH-DAG: vmov.f32 s4, {{s[01]}} +; CHECK-STRIDE4-WATCH-DAG: vmov.f32 s8, {{s[01]}} + +; CHECK-GENERIC-LABEL: test_stride_minsize: +; CHECK-GENERIC-DAG: vmov.f32 s4, {{s[01]}} +; CHECK-GENERIC-DAG: vmov.f32 s6, {{s[01]}} + call void asm "", "~{r0},~{r1},~{s0},~{s1},~{d0},~{d1}"() + call arm_aapcs_vfpcc void @eat_floats(float %a, float %b) + ret void +} + + +declare arm_aapcs_vfpcc void @eat_doubles(double, double) +declare arm_aapcs_vfpcc void @eat_floats(float, float) diff --git a/test/CodeGen/ARM/vfp-regs-dwarf.ll b/test/CodeGen/ARM/vfp-regs-dwarf.ll index eca0c26e5562..1b2055e5aff1 100644 --- a/test/CodeGen/ARM/vfp-regs-dwarf.ll +++ b/test/CodeGen/ARM/vfp-regs-dwarf.ll @@ -10,7 +10,7 @@ ; the layout of the VFP registers correctly. The fact that the numbers are ; monotonic in memory is also a nice property to have. -define void @stack_offsets() { +define void @stack_offsets() !dbg !4 { ; CHECK-LABEL: stack_offsets: ; CHECK: vpush {d13} ; CHECK: vpush {d11} @@ -31,11 +31,11 @@ define void @stack_offsets() { !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!8, !9} -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) !1 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build") !2 = !{} !3 = !{!4} -!4 = !DISubprogram(name: "bar", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @stack_offsets, variables: !2) +!4 = distinct !DISubprogram(name: "bar", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build") !6 = !DISubroutineType(types: !7) !7 = !{null} diff --git a/test/CodeGen/ARM/vld-vst-upgrade.ll b/test/CodeGen/ARM/vld-vst-upgrade.ll new file mode 100644 index 000000000000..fe868f6cb078 --- /dev/null +++ b/test/CodeGen/ARM/vld-vst-upgrade.ll @@ -0,0 +1,139 @@ +; RUN: llc -mtriple=arm-eabi -mattr=+neon < %s | FileCheck %s + +%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> } +%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> } +%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } + +; vld[1234] auto-upgrade tests + +; CHECK-LABEL: test_vld1_upgrade: +; CHECK: vld1.32 {d16}, [r0] +define <2 x i32> @test_vld1_upgrade(i8* %ptr) { + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %ptr, i32 1) + ret <2 x i32> %tmp1 +} + +declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) nounwind readonly + +; CHECK-LABEL: test_vld2_upgrade: +; CHECK: vld2.32 {d16, d17}, [r0] +define %struct.__neon_int32x2x2_t @test_vld2_upgrade(i8* %ptr) { + %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %ptr, i32 1) + ret %struct.__neon_int32x2x2_t %tmp1 +} + +declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8*, i32) nounwind readonly + +; CHECK-LABEL: test_vld3_upgrade: +; CHECK: vld3.32 {d16, d17, d18}, [r1] +define %struct.__neon_int32x2x3_t @test_vld3_upgrade(i8* %ptr) { + %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %ptr, i32 1) + ret %struct.__neon_int32x2x3_t %tmp1 +} + +declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*, i32) nounwind readonly + +; CHECK-LABEL: test_vld4_upgrade: +; CHECK: vld4.32 {d16, d17, d18, d19}, [r1] +define %struct.__neon_int32x2x4_t @test_vld4_upgrade(i8* %ptr) { + %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %ptr, i32 1) + ret %struct.__neon_int32x2x4_t %tmp1 +} + +declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*, i32) nounwind readonly + +; vld[234]lane auto-upgrade tests + +; CHECK-LABEL: test_vld2lane_upgrade: +; CHECK: vld2.32 {d16[1], d17[1]}, [r0] +define %struct.__neon_int32x2x2_t @test_vld2lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B) { + %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, i32 1, i32 1) + ret %struct.__neon_int32x2x2_t %tmp1 +} + +declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly + +; CHECK-LABEL: test_vld3lane_upgrade: +; CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r1] +define %struct.__neon_int32x2x3_t @test_vld3lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) { + %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1, i32 1) + ret %struct.__neon_int32x2x3_t %tmp1 +} + +declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly + +; CHECK-LABEL: test_vld4lane_upgrade: +; CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r1] +define %struct.__neon_int32x2x4_t @test_vld4lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) { + %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1, i32 1) + ret %struct.__neon_int32x2x4_t %tmp1 +} + +declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly + +; vst[1234] auto-upgrade tests + +; CHECK-LABEL: test_vst1_upgrade: +; CHECK: vst1.32 {d16}, [r0] +define void @test_vst1_upgrade(i8* %ptr, <2 x i32> %A) { + call void @llvm.arm.neon.vst1.v2i32(i8* %ptr, <2 x i32> %A, i32 1) + ret void +} + +declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind + +; CHECK-LABEL: test_vst2_upgrade: +; CHECK: vst2.32 {d16, d17}, [r0] +define void @test_vst2_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B) { + call void @llvm.arm.neon.vst2.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, i32 1) + ret void +} + +declare void @llvm.arm.neon.vst2.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind + +; CHECK-LABEL: test_vst3_upgrade: +; CHECK: vst3.32 {d16, d17, d18}, [r0] +define void @test_vst3_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) { + call void @llvm.arm.neon.vst3.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1) + ret void +} + +declare void @llvm.arm.neon.vst3.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind + +; CHECK-LABEL: test_vst4_upgrade: +; CHECK: vst4.32 {d16, d17, d18, d19}, [r0] +define void @test_vst4_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) { + call void @llvm.arm.neon.vst4.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1) + ret void +} + +declare void @llvm.arm.neon.vst4.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind + +; vst[234]lane auto-upgrade tests + +; CHECK-LABEL: test_vst2lane_upgrade: +; CHECK: vst2.32 {d16[1], d17[1]}, [r0] +define void @test_vst2lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B) { + call void @llvm.arm.neon.vst2lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, i32 1, i32 1) + ret void +} + +declare void @llvm.arm.neon.vst2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind + +; CHECK-LABEL: test_vst3lane_upgrade: +; CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0] +define void @test_vst3lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C) { + call void @llvm.arm.neon.vst3lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32 1, i32 1) + ret void +} + +declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind + +; CHECK-LABEL: test_vst4lane_upgrade: +; CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0] +define void @test_vst4lane_upgrade(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) { + call void @llvm.arm.neon.vst4lane.v2i32(i8* %ptr, <2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32 1, i32 1) + ret void +} + +declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index 8064ea4a320a..bdb384769741 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -7,7 +7,7 @@ define <8 x i8> @vld1i8(i8* %A) nounwind { ;CHECK-LABEL: vld1i8: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld1.8 {d16}, [r0:64] - %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16) + %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %A, i32 16) ret <8 x i8> %tmp1 } @@ -15,7 +15,7 @@ define <4 x i16> @vld1i16(i16* %A) nounwind { ;CHECK-LABEL: vld1i16: ;CHECK: vld1.16 %tmp0 = bitcast i16* %A to i8* - %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) + %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1) ret <4 x i16> %tmp1 } @@ -25,7 +25,7 @@ define <4 x i16> @vld1i16_update(i16** %ptr) nounwind { ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]! %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* - %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) + %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1) %tmp2 = getelementptr i16, i16* %A, i32 4 store i16* %tmp2, i16** %ptr ret <4 x i16> %tmp1 @@ -35,7 +35,7 @@ define <2 x i32> @vld1i32(i32* %A) nounwind { ;CHECK-LABEL: vld1i32: ;CHECK: vld1.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1) ret <2 x i32> %tmp1 } @@ -45,7 +45,7 @@ define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind { ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* - %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1) %tmp2 = getelementptr i32, i32* %A, i32 %inc store i32* %tmp2, i32** %ptr ret <2 x i32> %tmp1 @@ -55,7 +55,7 @@ define <2 x float> @vld1f(float* %A) nounwind { ;CHECK-LABEL: vld1f: ;CHECK: vld1.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1) + %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32.p0i8(i8* %tmp0, i32 1) ret <2 x float> %tmp1 } @@ -63,7 +63,7 @@ define <1 x i64> @vld1i64(i64* %A) nounwind { ;CHECK-LABEL: vld1i64: ;CHECK: vld1.64 %tmp0 = bitcast i64* %A to i8* - %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1) + %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %tmp0, i32 1) ret <1 x i64> %tmp1 } @@ -71,7 +71,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { ;CHECK-LABEL: vld1Qi8: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld1.8 {d16, d17}, [r0:64] - %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) + %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %A, i32 8) ret <16 x i8> %tmp1 } @@ -80,7 +80,7 @@ define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { ;CHECK-LABEL: vld1Qi8_update: ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]! %A = load i8*, i8** %ptr - %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) + %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %A, i32 8) %tmp2 = getelementptr i8, i8* %A, i32 16 store i8* %tmp2, i8** %ptr ret <16 x i8> %tmp1 @@ -91,7 +91,7 @@ define <8 x i16> @vld1Qi16(i16* %A) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld1.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32) + %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %tmp0, i32 32) ret <8 x i16> %tmp1 } @@ -99,7 +99,7 @@ define <4 x i32> @vld1Qi32(i32* %A) nounwind { ;CHECK-LABEL: vld1Qi32: ;CHECK: vld1.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1) + %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8* %tmp0, i32 1) ret <4 x i32> %tmp1 } @@ -107,7 +107,7 @@ define <4 x float> @vld1Qf(float* %A) nounwind { ;CHECK-LABEL: vld1Qf: ;CHECK: vld1.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1) + %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %tmp0, i32 1) ret <4 x float> %tmp1 } @@ -115,7 +115,7 @@ define <2 x i64> @vld1Qi64(i64* %A) nounwind { ;CHECK-LABEL: vld1Qi64: ;CHECK: vld1.64 %tmp0 = bitcast i64* %A to i8* - %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1) + %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %tmp0, i32 1) ret <2 x i64> %tmp1 } @@ -123,28 +123,28 @@ define <2 x double> @vld1Qf64(double* %A) nounwind { ;CHECK-LABEL: vld1Qf64: ;CHECK: vld1.64 %tmp0 = bitcast double* %A to i8* - %tmp1 = call <2 x double> @llvm.arm.neon.vld1.v2f64(i8* %tmp0, i32 1) + %tmp1 = call <2 x double> @llvm.arm.neon.vld1.v2f64.p0i8(i8* %tmp0, i32 1) ret <2 x double> %tmp1 } -declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*, i32) nounwind readonly -declare <4 x i16> @llvm.arm.neon.vld1.v4i16(i8*, i32) nounwind readonly -declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) nounwind readonly -declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly -declare <1 x i64> @llvm.arm.neon.vld1.v1i64(i8*, i32) nounwind readonly +declare <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8*, i32) nounwind readonly +declare <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8*, i32) nounwind readonly +declare <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) nounwind readonly +declare <2 x float> @llvm.arm.neon.vld1.v2f32.p0i8(i8*, i32) nounwind readonly +declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8*, i32) nounwind readonly -declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8*, i32) nounwind readonly -declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly -declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly -declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly -declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly -declare <2 x double> @llvm.arm.neon.vld1.v2f64(i8*, i32) nounwind readonly +declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8*, i32) nounwind readonly +declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly +declare <4 x i32> @llvm.arm.neon.vld1.v4i32.p0i8(i8*, i32) nounwind readonly +declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly +declare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8*, i32) nounwind readonly +declare <2 x double> @llvm.arm.neon.vld1.v2f64.p0i8(i8*, i32) nounwind readonly ; Radar 8355607 ; Do not crash if the vld1 result is not used. define void @unused_vld1_result() { entry: - %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) + %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) call void @llvm.trap() unreachable } diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index 391b49152cd9..1ca16587bd91 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -15,7 +15,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { ;CHECK-LABEL: vld2i8: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld2.8 {d16, d17}, [r0:64] - %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8) + %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1 %tmp4 = add <8 x i8> %tmp2, %tmp3 @@ -27,7 +27,7 @@ define <4 x i16> @vld2i16(i16* %A) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld2.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32) + %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0i8(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -38,7 +38,7 @@ define <2 x i32> @vld2i32(i32* %A) nounwind { ;CHECK-LABEL: vld2i32: ;CHECK: vld2.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -49,7 +49,7 @@ define <2 x float> @vld2f(float* %A) nounwind { ;CHECK-LABEL: vld2f: ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1 %tmp4 = fadd <2 x float> %tmp2, %tmp3 @@ -62,7 +62,7 @@ define <2 x float> @vld2f_update(float** %ptr) nounwind { ;CHECK: vld2.32 {d16, d17}, [r1]! %A = load float*, float** %ptr %tmp0 = bitcast float* %A to i8* - %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1 %tmp4 = fadd <2 x float> %tmp2, %tmp3 @@ -76,7 +76,7 @@ define <1 x i64> @vld2i64(i64* %A) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld1.64 {d16, d17}, [r0:128] %tmp0 = bitcast i64* %A to i8* - %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 32) + %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0i8(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -87,7 +87,7 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind { ;CHECK-LABEL: vld2Qi8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] - %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8) + %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1 %tmp4 = add <16 x i8> %tmp2, %tmp3 @@ -99,7 +99,7 @@ define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld2Qi8_update: ;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1 %A = load i8*, i8** %ptr - %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16) + %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8* %A, i32 16) %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1 %tmp4 = add <16 x i8> %tmp2, %tmp3 @@ -113,7 +113,7 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 16) + %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0i8(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -125,7 +125,7 @@ define <4 x i32> @vld2Qi32(i32* %A) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 64) + %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8* %tmp0, i32 64) %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -136,20 +136,20 @@ define <4 x float> @vld2Qf(float* %A) nounwind { ;CHECK-LABEL: vld2Qf: ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1 %tmp4 = fadd <4 x float> %tmp2, %tmp3 ret <4 x float> %tmp4 } -declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8*, i32) nounwind readonly -declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8*, i32) nounwind readonly -declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8*, i32) nounwind readonly -declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8*, i32) nounwind readonly -declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8*, i32) nounwind readonly +declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0i8(i8*, i32) nounwind readonly -declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8*, i32) nounwind readonly -declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8*, i32) nounwind readonly -declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8*, i32) nounwind readonly -declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly +declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0i8(i8*, i32) nounwind readonly diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index 0d14179ba73a..c3e8ee8691fd 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -16,7 +16,7 @@ define <8 x i8> @vld3i8(i8* %A) nounwind { ;CHECK-LABEL: vld3i8: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld3.8 {d16, d17, d18}, [r0:64] - %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32) + %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 32) %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 %tmp4 = add <8 x i8> %tmp2, %tmp3 @@ -27,7 +27,7 @@ define <4 x i16> @vld3i16(i16* %A) nounwind { ;CHECK-LABEL: vld3i16: ;CHECK: vld3.16 %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -40,7 +40,7 @@ define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind { ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -53,7 +53,7 @@ define <2 x i32> @vld3i32(i32* %A) nounwind { ;CHECK-LABEL: vld3i32: ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 2 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -64,7 +64,7 @@ define <2 x float> @vld3f(float* %A) nounwind { ;CHECK-LABEL: vld3f: ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 2 %tmp4 = fadd <2 x float> %tmp2, %tmp3 @@ -76,7 +76,7 @@ define <1 x i64> @vld3i64(i64* %A) nounwind { ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld1.64 {d16, d17, d18}, [r0:64] %tmp0 = bitcast i64* %A to i8* - %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16) + %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -87,7 +87,7 @@ define <1 x i64> @vld3i64_update(i64** %ptr, i64* %A) nounwind { ;CHECK-LABEL: vld3i64_update: ;CHECK: vld1.64 {d16, d17, d18}, [r1:64]! %tmp0 = bitcast i64* %A to i8* - %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16) + %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8* %tmp0, i32 16) %tmp5 = getelementptr i64, i64* %A, i32 3 store i64* %tmp5, i64** %ptr %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 @@ -101,7 +101,7 @@ define <16 x i8> @vld3Qi8(i8* %A) nounwind { ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld3.8 {d16, d18, d20}, [r0:64]! ;CHECK: vld3.8 {d17, d19, d21}, [r0:64] - %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32) + %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8.p0i8(i8* %A, i32 32) %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2 %tmp4 = add <16 x i8> %tmp2, %tmp3 @@ -113,7 +113,7 @@ define <8 x i16> @vld3Qi16(i16* %A) nounwind { ;CHECK: vld3.16 ;CHECK: vld3.16 %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 2 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -125,7 +125,7 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind { ;CHECK: vld3.32 ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -139,7 +139,7 @@ define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind { ;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]! %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -153,20 +153,20 @@ define <4 x float> @vld3Qf(float* %A) nounwind { ;CHECK: vld3.32 ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 2 %tmp4 = fadd <4 x float> %tmp2, %tmp3 ret <4 x float> %tmp4 } -declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly -declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8*, i32) nounwind readonly -declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*, i32) nounwind readonly -declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8*, i32) nounwind readonly -declare %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8*, i32) nounwind readonly +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8*, i32) nounwind readonly -declare %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8*, i32) nounwind readonly -declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8*, i32) nounwind readonly -declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8*, i32) nounwind readonly -declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8*, i32) nounwind readonly +declare %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32.p0i8(i8*, i32) nounwind readonly diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll index 575e0fa717fb..10570039a9d2 100644 --- a/test/CodeGen/ARM/vld4.ll +++ b/test/CodeGen/ARM/vld4.ll @@ -15,7 +15,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { ;CHECK-LABEL: vld4i8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] - %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8) + %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 %tmp4 = add <8 x i8> %tmp2, %tmp3 @@ -27,7 +27,7 @@ define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld4i8_update: ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1 %A = load i8*, i8** %ptr - %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16) + %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8* %A, i32 16) %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 %tmp4 = add <8 x i8> %tmp2, %tmp3 @@ -41,7 +41,7 @@ define <4 x i16> @vld4i16(i16* %A) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16) + %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0i8(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -53,7 +53,7 @@ define <2 x i32> @vld4i32(i32* %A) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32) + %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0i8(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -64,7 +64,7 @@ define <2 x float> @vld4f(float* %A) nounwind { ;CHECK-LABEL: vld4f: ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 2 %tmp4 = fadd <2 x float> %tmp2, %tmp3 @@ -76,7 +76,7 @@ define <1 x i64> @vld4i64(i64* %A) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i64* %A to i8* - %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64) + %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8* %tmp0, i32 64) %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -87,7 +87,7 @@ define <1 x i64> @vld4i64_update(i64** %ptr, i64* %A) nounwind { ;CHECK-LABEL: vld4i64_update: ;CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]! %tmp0 = bitcast i64* %A to i8* - %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64) + %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8* %tmp0, i32 64) %tmp5 = getelementptr i64, i64* %A, i32 4 store i64* %tmp5, i64** %ptr %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 @@ -101,7 +101,7 @@ define <16 x i8> @vld4Qi8(i8* %A) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! ;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256] - %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64) + %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0i8(i8* %A, i32 64) %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2 %tmp4 = add <16 x i8> %tmp2, %tmp3 @@ -114,7 +114,7 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind { ;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! ;CHECK: vld4.16 {d17, d19, d21, d23}, [r0] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -128,7 +128,7 @@ define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind { ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]! %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8) + %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8* %tmp0, i32 8) %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -142,7 +142,7 @@ define <4 x i32> @vld4Qi32(i32* %A) nounwind { ;CHECK: vld4.32 ;CHECK: vld4.32 %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -154,20 +154,20 @@ define <4 x float> @vld4Qf(float* %A) nounwind { ;CHECK: vld4.32 ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* - %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0i8(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2 %tmp4 = fadd <4 x float> %tmp2, %tmp3 ret <4 x float> %tmp4 } -declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8*, i32) nounwind readonly -declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8*, i32) nounwind readonly -declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*, i32) nounwind readonly -declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8*, i32) nounwind readonly -declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8*, i32) nounwind readonly +declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8*, i32) nounwind readonly -declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8*, i32) nounwind readonly -declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8*, i32) nounwind readonly -declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8*, i32) nounwind readonly -declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8*, i32) nounwind readonly +declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0i8(i8*, i32) nounwind readonly +declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0i8(i8*, i32) nounwind readonly diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll index 09304d87d53b..c115a3863d0d 100644 --- a/test/CodeGen/ARM/vlddup.ll +++ b/test/CodeGen/ARM/vlddup.ll @@ -66,7 +66,7 @@ define <8 x i8> @vld2dupi8(i8* %A) nounwind { ;CHECK-LABEL: vld2dupi8: ;Check the (default) alignment value. ;CHECK: vld2.8 {d16[], d17[]}, [r0] - %tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) + %tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) %tmp1 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 0 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 1 @@ -80,7 +80,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind { ;Check that a power-of-two alignment smaller than the total size of the memory ;being loaded is ignored. ;CHECK: vld2.16 {d16[], d17[]}, [r0] - %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) + %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer %tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1 @@ -95,7 +95,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { ;CHECK: vld2.16 {d16[], d17[]}, [r1]! %A = load i16*, i16** %ptr %A2 = bitcast i16* %A to i8* - %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %A2, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) + %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %A2, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer %tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1 @@ -110,7 +110,7 @@ define <2 x i32> @vld2dupi32(i8* %A) nounwind { ;CHECK-LABEL: vld2dupi32: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld2.32 {d16[], d17[]}, [r0:64] - %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16) + %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16) %tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer %tmp3 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 1 @@ -119,9 +119,9 @@ define <2 x i32> @vld2dupi32(i8* %A) nounwind { ret <2 x i32> %tmp5 } -declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly -declare %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly -declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly +declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly +declare %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> } @@ -131,7 +131,7 @@ define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld3dupi8_update: ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1 %A = load i8*, i8** %ptr - %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8) + %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8) %tmp1 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 0 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 1 @@ -149,7 +149,7 @@ define <4 x i16> @vld3dupi16(i8* %A) nounwind { ;CHECK-LABEL: vld3dupi16: ;Check the (default) alignment value. VLD3 does not support alignment. ;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0] - %tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8) + %tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8) %tmp1 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 0 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 1 @@ -161,8 +161,8 @@ define <4 x i16> @vld3dupi16(i8* %A) nounwind { ret <4 x i16> %tmp8 } -declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly -declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly +declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly %struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @@ -173,7 +173,7 @@ define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind { ;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]! %A = load i16*, i16** %ptr %A2 = bitcast i16* %A to i8* - %tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %A2, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1) + %tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8* %A2, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1) %tmp1 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 0 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 1 @@ -195,7 +195,7 @@ define <2 x i32> @vld4dupi32(i8* %A) nounwind { ;Check the alignment value. An 8-byte alignment is allowed here even though ;it is smaller than the total size of the memory being loaded. ;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64] - %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8) + %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8) %tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 1 @@ -210,5 +210,5 @@ define <2 x i32> @vld4dupi32(i8* %A) nounwind { ret <2 x i32> %tmp11 } -declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly -declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly +declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index ac2be7f87f53..2c14bc2d8f4e 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -102,7 +102,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] %tmp1 = load <8 x i8>, <8 x i8>* %B - %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) + %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -115,7 +115,7 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) + %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1 %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -127,7 +127,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld2.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1 %tmp5 = add <2 x i32> %tmp3, %tmp4 @@ -141,7 +141,7 @@ define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind { %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1 %tmp5 = add <2 x i32> %tmp3, %tmp4 @@ -155,7 +155,7 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32.p0i8(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1 %tmp5 = fadd <2 x float> %tmp3, %tmp4 @@ -168,7 +168,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) + %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -181,7 +181,7 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) + %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32.p0i8(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -193,21 +193,21 @@ define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32.p0i8(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1 %tmp5 = fadd <4 x float> %tmp3, %tmp4 ret <4 x float> %tmp5 } -declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly -declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly -declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly -declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8*, <2 x float>, <2 x float>, i32, i32) nounwind readonly +declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly +declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly +declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32.p0i8(i8*, <2 x float>, <2 x float>, i32, i32) nounwind readonly -declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly -declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly -declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind readonly +declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32.p0i8(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly +declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32.p0i8(i8*, <4 x float>, <4 x float>, i32, i32) nounwind readonly %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> } @@ -222,7 +222,7 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vld3lanei8: ;CHECK: vld3.8 %tmp1 = load <8 x i8>, <8 x i8>* %B - %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2 @@ -237,7 +237,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) + %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 2 @@ -251,7 +251,7 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 2 @@ -265,7 +265,7 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32.p0i8(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 2 @@ -280,7 +280,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) + %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2 @@ -296,7 +296,7 @@ define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounw %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) + %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2 @@ -312,7 +312,7 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3, i32 1) + %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32.p0i8(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3, i32 1) %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2 @@ -326,7 +326,7 @@ define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32.p0i8(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2 @@ -335,14 +335,14 @@ define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind { ret <4 x float> %tmp7 } -declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly -declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly -declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly -declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly +declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly +declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32.p0i8(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly -declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly -declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly -declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly +declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32.p0i8(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly +declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32.p0i8(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @@ -358,7 +358,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32] %tmp1 = load <8 x i8>, <8 x i8>* %B - %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) + %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 @@ -375,7 +375,7 @@ define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]! %A = load i8*, i8** %ptr %tmp1 = load <8 x i8>, <8 x i8>* %B - %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) + %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 @@ -395,7 +395,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4) + %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4) %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 2 @@ -413,7 +413,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8) + %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 2 @@ -429,7 +429,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32.p0i8(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 2 @@ -446,7 +446,7 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16) + %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16.p0i8(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16) %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 2 @@ -463,7 +463,7 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) + %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32.p0i8(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 2 @@ -479,7 +479,7 @@ define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32.p0i8(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 2 @@ -490,14 +490,14 @@ define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind { ret <4 x float> %tmp9 } -declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly -declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly -declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly -declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly +declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8.p0i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly +declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0i8(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0i8(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly +declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32.p0i8(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind readonly -declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly -declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly -declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly +declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16.p0i8(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32.p0i8(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly +declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32.p0i8(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly ; Radar 8776599: If one of the operands to a QQQQ REG_SEQUENCE is a register ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because @@ -511,7 +511,7 @@ define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { %tmp65 = shl i128 %tmp64, 64 %ins67 = or i128 %tmp65, 0 %tmp78 = bitcast i128 %ins67 to <8 x i16> - %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2) + %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2) %tmp3 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 0 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 1 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 2 diff --git a/test/CodeGen/ARM/vminmaxnm-safe.ll b/test/CodeGen/ARM/vminmaxnm-safe.ll new file mode 100644 index 000000000000..ce1aab2dbcec --- /dev/null +++ b/test/CodeGen/ARM/vminmaxnm-safe.ll @@ -0,0 +1,396 @@ +; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 | FileCheck %s + +; vectors + +define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind { +; CHECK-LABEL: vmaxnmq: +; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B + %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x float> %tmp3 +} + +define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind { +; CHECK-LABEL: vmaxnmd: +; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind { +; CHECK-LABEL: vminnmq: +; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B + %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) + ret <4 x float> %tmp3 +} + +define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind { +; CHECK-LABEL: vminnmd: +; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B + %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) + ret <2 x float> %tmp3 +} + +; scalars + +define float @fp-armv8_vminnm_o(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vminnm_o": +; CHECK-NOT: vminnm.f32 + %cmp = fcmp olt float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define double @fp-armv8_vminnm_ole(double %a, double %b) { +; CHECK-LABEL: "fp-armv8_vminnm_ole": +; CHECK-NOT: vminnm.f64 + %cmp = fcmp ole double %a, %b + %cond = select i1 %cmp, double %a, double %b + ret double %cond +} + +define float @fp-armv8_vminnm_o_rev(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vminnm_o_rev": +; CHECK-NOT: vminnm.f32 + %cmp = fcmp ogt float %a, %b + %cond = select i1 %cmp, float %b, float %a + ret float %cond +} + +define double @fp-armv8_vminnm_oge_rev(double %a, double %b) { +; CHECK-LABEL: "fp-armv8_vminnm_oge_rev": +; CHECK-NOT: vminnm.f64 + %cmp = fcmp oge double %a, %b + %cond = select i1 %cmp, double %b, double %a + ret double %cond +} + +define float @fp-armv8_vminnm_u(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vminnm_u": +; CHECK-NOT: vminnm.f32 + %cmp = fcmp ult float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vminnm_ule(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vminnm_ule": +; CHECK-NOT: vminnm.f32 + %cmp = fcmp ule float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vminnm_u_rev(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vminnm_u_rev": +; CHECK-NOT: vminnm.f32 + %cmp = fcmp ugt float %a, %b + %cond = select i1 %cmp, float %b, float %a + ret float %cond +} + +define double @fp-armv8_vminnm_uge_rev(double %a, double %b) { +; CHECK-LABEL: "fp-armv8_vminnm_uge_rev": +; CHECK-NOT: vminnm.f64 + %cmp = fcmp uge double %a, %b + %cond = select i1 %cmp, double %b, double %a + ret double %cond +} + +define float @fp-armv8_vmaxnm_o(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_o": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp ogt float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vmaxnm_oge(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_oge": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp oge float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_o_rev": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp olt float %a, %b + %cond = select i1 %cmp, float %b, float %a + ret float %cond +} + +define float @fp-armv8_vmaxnm_ole_rev(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_ole_rev": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp ole float %a, %b + %cond = select i1 %cmp, float %b, float %a + ret float %cond +} + +define float @fp-armv8_vmaxnm_u(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_u": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp ugt float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vmaxnm_uge(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_uge": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp uge float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_u_rev": +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp ult float %a, %b + %cond = select i1 %cmp, float %b, float %a + ret float %cond +} + +define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_ule_rev": +; CHECK-NOT: vmaxnm.f64 + %cmp = fcmp ule double %a, %b + %cond = select i1 %cmp, double %b, double %a + ret double %cond +} + +; known non-NaNs + +define float @fp-armv8_vminnm_NNNo(float %a) { +; CHECK-LABEL: "fp-armv8_vminnm_NNNo": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp olt float %a, 12. + %cond1 = select i1 %cmp1, float %a, float 12. + %cmp2 = fcmp olt float 34., %cond1 + %cond2 = select i1 %cmp2, float 34., float %cond1 + ret float %cond2 +} + +define double @fp-armv8_vminnm_NNNole(double %a) { +; CHECK-LABEL: "fp-armv8_vminnm_NNNole": +; CHECK: vminnm.f64 +; CHECK-NOT: vminnm.f64 + %cmp1 = fcmp ole double %a, 34. + %cond1 = select i1 %cmp1, double %a, double 34. + %cmp2 = fcmp ole double 56., %cond1 + %cond2 = select i1 %cmp2, double 56., double %cond1 + ret double %cond2 +} + +define float @fp-armv8_vminnm_NNNo_rev(float %a) { +; CHECK-LABEL: "fp-armv8_vminnm_NNNo_rev": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp ogt float %a, 56. + %cond1 = select i1 %cmp1, float 56., float %a + %cmp2 = fcmp ogt float 78., %cond1 + %cond2 = select i1 %cmp2, float %cond1, float 78. + ret float %cond2 +} + +define double @fp-armv8_vminnm_NNNoge_rev(double %a) { +; CHECK-LABEL: "fp-armv8_vminnm_NNNoge_rev": +; CHECK: vminnm.f64 +; CHECK-NOT: vminnm.f64 + %cmp1 = fcmp oge double %a, 78. + %cond1 = select i1 %cmp1, double 78., double %a + %cmp2 = fcmp oge double 90., %cond1 + %cond2 = select i1 %cmp2, double %cond1, double 90. + ret double %cond2 +} + +define float @fp-armv8_vminnm_NNNu(float %b) { +; CHECK-LABEL: "fp-armv8_vminnm_NNNu": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp ult float 12., %b + %cond1 = select i1 %cmp1, float 12., float %b + %cmp2 = fcmp ult float %cond1, 34. + %cond2 = select i1 %cmp2, float %cond1, float 34. + ret float %cond2 +} + +define float @fp-armv8_vminnm_NNNule(float %b) { +; CHECK-LABEL: "fp-armv8_vminnm_NNNule": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp ule float 34., %b + %cond1 = select i1 %cmp1, float 34., float %b + %cmp2 = fcmp ule float %cond1, 56. + %cond2 = select i1 %cmp2, float %cond1, float 56. + ret float %cond2 +} + +define float @fp-armv8_vminnm_NNNu_rev(float %b) { +; CHECK-LABEL: "fp-armv8_vminnm_NNNu_rev": +; CHECK: vminnm.f32 +; CHECK-NOT: vminnm.f32 + %cmp1 = fcmp ugt float 56., %b + %cond1 = select i1 %cmp1, float %b, float 56. + %cmp2 = fcmp ugt float %cond1, 78. + %cond2 = select i1 %cmp2, float 78., float %cond1 + ret float %cond2 +} + +define double @fp-armv8_vminnm_NNNuge_rev(double %b) { +; CHECK-LABEL: "fp-armv8_vminnm_NNNuge_rev": +; CHECK: vminnm.f64 +; CHECK-NOT: vminnm.f64 + %cmp1 = fcmp uge double 78., %b + %cond1 = select i1 %cmp1, double %b, double 78. + %cmp2 = fcmp uge double %cond1, 90. + %cond2 = select i1 %cmp2, double 90., double %cond1 + ret double %cond2 +} + +define float @fp-armv8_vmaxnm_NNNo(float %a) { +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp ogt float %a, 12. + %cond1 = select i1 %cmp1, float %a, float 12. + %cmp2 = fcmp ogt float 34., %cond1 + %cond2 = select i1 %cmp2, float 34., float %cond1 + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNoge(float %a) { +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNoge": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp oge float %a, 34. + %cond1 = select i1 %cmp1, float %a, float 34. + %cmp2 = fcmp oge float 56., %cond1 + %cond2 = select i1 %cmp2, float 56., float %cond1 + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNo_rev(float %a) { +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo_rev": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp olt float %a, 56. + %cond1 = select i1 %cmp1, float 56., float %a + %cmp2 = fcmp olt float 78., %cond1 + %cond2 = select i1 %cmp2, float %cond1, float 78. + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNole_rev(float %a) { +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNole_rev": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp ole float %a, 78. + %cond1 = select i1 %cmp1, float 78., float %a + %cmp2 = fcmp ole float 90., %cond1 + %cond2 = select i1 %cmp2, float %cond1, float 90. + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNu(float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu": +; CHECK: vmaxnm.f32 +; CHEC-NOT: vmaxnm.f32 + %cmp1 = fcmp ugt float 12., %b + %cond1 = select i1 %cmp1, float 12., float %b + %cmp2 = fcmp ugt float %cond1, 34. + %cond2 = select i1 %cmp2, float %cond1, float 34. + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNuge(float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNuge": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp uge float 34., %b + %cond1 = select i1 %cmp1, float 34., float %b + %cmp2 = fcmp uge float %cond1, 56. + %cond2 = select i1 %cmp2, float %cond1, float 56. + ret float %cond2 +} + +define float @fp-armv8_vmaxnm_NNNu_rev(float %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu_rev": +; CHECK: vmaxnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp ult float 56., %b + %cond1 = select i1 %cmp1, float %b, float 56. + %cmp2 = fcmp ult float %cond1, 78. + %cond2 = select i1 %cmp2, float 78., float %cond1 + ret float %cond2 +} + +define double @fp-armv8_vmaxnm_NNNule_rev( double %b) { +; CHECK-LABEL: "fp-armv8_vmaxnm_NNNule_rev": +; CHECK: vmaxnm.f64 +; CHECK-NOT: vmaxnm.f64 + %cmp1 = fcmp ule double 78., %b + %cond1 = select i1 %cmp1, double %b, double 78. + %cmp2 = fcmp ule double %cond1, 90. + %cond2 = select i1 %cmp2, double 90., double %cond1 + ret double %cond2 +} + +define float @fp-armv8_vminmaxnm_0(float %a) { +; CHECK-LABEL: "fp-armv8_vminmaxnm_0": +; CHECK-NOT: vminnm.f32 +; CHECK: vmaxnm.f32 + %cmp1 = fcmp ult float %a, 0. + %cond1 = select i1 %cmp1, float %a, float 0. + %cmp2 = fcmp ogt float %cond1, 0. + %cond2 = select i1 %cmp2, float %cond1, float 0. + ret float %cond2 +} + +define float @fp-armv8_vminmaxnm_neg0(float %a) { +; CHECK-LABEL: "fp-armv8_vminmaxnm_neg0": +; CHECK: vminnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp olt float %a, -0. + %cond1 = select i1 %cmp1, float %a, float -0. + %cmp2 = fcmp ugt float %cond1, -0. + %cond2 = select i1 %cmp2, float %cond1, float -0. + ret float %cond2 +} + +define float @fp-armv8_vminmaxnm_e_0(float %a) { +; CHECK-LABEL: "fp-armv8_vminmaxnm_e_0": +; CHECK-NOT: vminnm.f32 +; CHECK: vmaxnm.f32 + %cmp1 = fcmp nsz ole float 0., %a + %cond1 = select i1 %cmp1, float 0., float %a + %cmp2 = fcmp nsz uge float 0., %cond1 + %cond2 = select i1 %cmp2, float 0., float %cond1 + ret float %cond2 +} + +define float @fp-armv8_vminmaxnm_e_neg0(float %a) { +; CHECK-LABEL: "fp-armv8_vminmaxnm_e_neg0": +; CHECK: vminnm.f32 +; CHECK-NOT: vmaxnm.f32 + %cmp1 = fcmp nsz ule float -0., %a + %cond1 = select i1 %cmp1, float -0., float %a + %cmp2 = fcmp nsz oge float -0., %cond1 + %cond2 = select i1 %cmp2, float -0., float %cond1 + ret float %cond2 +} + +declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone +declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone +declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone +declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/vminmaxnm.ll b/test/CodeGen/ARM/vminmaxnm.ll index 3632ffd00213..a6803fc78d8c 100644 --- a/test/CodeGen/ARM/vminmaxnm.ll +++ b/test/CodeGen/ARM/vminmaxnm.ll @@ -1,219 +1,147 @@ -; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 | FileCheck %s -; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 \ -; RUN: -enable-no-nans-fp-math -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST - -; vectors - -define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind { -; CHECK-LABEL: vmaxnmq: -; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>, <4 x float>* %A - %tmp2 = load <4 x float>, <4 x float>* %B - %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) - ret <4 x float> %tmp3 -} - -define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind { -; CHECK-LABEL: vmaxnmd: -; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>, <2 x float>* %A - %tmp2 = load <2 x float>, <2 x float>* %B - %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) - ret <2 x float> %tmp3 -} - -define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind { -; CHECK-LABEL: vminnmq: -; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} - %tmp1 = load <4 x float>, <4 x float>* %A - %tmp2 = load <4 x float>, <4 x float>* %B - %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) - ret <4 x float> %tmp3 -} - -define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind { -; CHECK-LABEL: vminnmd: -; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} - %tmp1 = load <2 x float>, <2 x float>* %A - %tmp2 = load <2 x float>, <2 x float>* %B - %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) - ret <2 x float> %tmp3 -} +; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck %s ; scalars define float @fp-armv8_vminnm_o(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_o": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_o": -; CHECK-NOT: vminnm.f32 - %cmp = fcmp olt float %a, %b +; CHECK-NOT: vcmp +; CHECK: vminnm.f32 + %cmp = fcmp fast olt float %a, %b %cond = select i1 %cmp, float %a, float %b ret float %cond } define double @fp-armv8_vminnm_ole(double %a, double %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_ole": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f64 ; CHECK-LABEL: "fp-armv8_vminnm_ole": -; CHECK-NOT: vminnm.f64 - %cmp = fcmp ole double %a, %b +; CHECK-NOT: vcmp +; CHECK: vminnm.f64 + %cmp = fcmp fast ole double %a, %b %cond = select i1 %cmp, double %a, double %b ret double %cond } define float @fp-armv8_vminnm_o_rev(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_o_rev": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_o_rev": -; CHECK-NOT: vminnm.f32 - %cmp = fcmp ogt float %a, %b +; CHECK-NOT: vcmp +; CHECK: vminnm.f32 + %cmp = fcmp fast ogt float %a, %b %cond = select i1 %cmp, float %b, float %a ret float %cond } define double @fp-armv8_vminnm_oge_rev(double %a, double %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_oge_rev": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f64 ; CHECK-LABEL: "fp-armv8_vminnm_oge_rev": -; CHECK-NOT: vminnm.f64 - %cmp = fcmp oge double %a, %b +; CHECK-NOT: vcmp +; CHECK: vminnm.f64 + %cmp = fcmp fast oge double %a, %b %cond = select i1 %cmp, double %b, double %a ret double %cond } define float @fp-armv8_vminnm_u(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_u": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_u": -; CHECK-NOT: vminnm.f32 - %cmp = fcmp ult float %a, %b +; CHECK-NOT: vcmp +; CHECK: vminnm.f32 + %cmp = fcmp fast ult float %a, %b %cond = select i1 %cmp, float %a, float %b ret float %cond } define float @fp-armv8_vminnm_ule(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_ule": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_ule": -; CHECK-NOT: vminnm.f32 - %cmp = fcmp ule float %a, %b +; CHECK-NOT: vcmp +; CHECK: vminnm.f32 + %cmp = fcmp fast ule float %a, %b %cond = select i1 %cmp, float %a, float %b ret float %cond } define float @fp-armv8_vminnm_u_rev(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_u_rev": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_u_rev": -; CHECK-NOT: vminnm.f32 - %cmp = fcmp ugt float %a, %b +; CHECK-NOT: vcmp +; CHECK: vminnm.f32 + %cmp = fcmp fast ugt float %a, %b %cond = select i1 %cmp, float %b, float %a ret float %cond } define double @fp-armv8_vminnm_uge_rev(double %a, double %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_uge_rev": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f64 ; CHECK-LABEL: "fp-armv8_vminnm_uge_rev": -; CHECK-NOT: vminnm.f64 - %cmp = fcmp uge double %a, %b +; CHECK-NOT: vcmp +; CHECK: vminnm.f64 + %cmp = fcmp fast uge double %a, %b %cond = select i1 %cmp, double %b, double %a ret double %cond } define float @fp-armv8_vmaxnm_o(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_o": -; CHECK-NOT: vmaxnm.f32 - %cmp = fcmp ogt float %a, %b +; CHECK-NOT: vcmp +; CHECK: vmaxnm.f32 + %cmp = fcmp fast ogt float %a, %b %cond = select i1 %cmp, float %a, float %b ret float %cond } define float @fp-armv8_vmaxnm_oge(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_oge": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_oge": -; CHECK-NOT: vmaxnm.f32 - %cmp = fcmp oge float %a, %b +; CHECK-NOT: vcmp +; CHECK: vmaxnm.f32 + %cmp = fcmp fast oge float %a, %b %cond = select i1 %cmp, float %a, float %b ret float %cond } define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o_rev": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_o_rev": -; CHECK-NOT: vmaxnm.f32 - %cmp = fcmp olt float %a, %b +; CHECK-NOT: vcmp +; CHECK: vmaxnm.f32 + %cmp = fcmp fast olt float %a, %b %cond = select i1 %cmp, float %b, float %a ret float %cond } define float @fp-armv8_vmaxnm_ole_rev(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_ole_rev": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_ole_rev": -; CHECK-NOT: vmaxnm.f32 - %cmp = fcmp ole float %a, %b +; CHECK-NOT: vcmp +; CHECK: vmaxnm.f32 + %cmp = fcmp fast ole float %a, %b %cond = select i1 %cmp, float %b, float %a ret float %cond } define float @fp-armv8_vmaxnm_u(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_u": -; CHECK-NOT: vmaxnm.f32 - %cmp = fcmp ugt float %a, %b +; CHECK-NOT: vcmp +; CHECK: vmaxnm.f32 + %cmp = fcmp fast ugt float %a, %b %cond = select i1 %cmp, float %a, float %b ret float %cond } define float @fp-armv8_vmaxnm_uge(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_uge": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_uge": -; CHECK-NOT: vmaxnm.f32 - %cmp = fcmp uge float %a, %b +; CHECK-NOT: vcmp +; CHECK: vmaxnm.f32 + %cmp = fcmp fast uge float %a, %b %cond = select i1 %cmp, float %a, float %b ret float %cond } define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u_rev": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_u_rev": -; CHECK-NOT: vmaxnm.f32 - %cmp = fcmp ult float %a, %b +; CHECK-NOT: vcmp +; CHECK: vmaxnm.f32 + %cmp = fcmp fast ult float %a, %b %cond = select i1 %cmp, float %b, float %a ret float %cond } define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_ule_rev": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vmaxnm.f64 ; CHECK-LABEL: "fp-armv8_vmaxnm_ule_rev": -; CHECK-NOT: vmaxnm.f64 - %cmp = fcmp ule double %a, %b +; CHECK-NOT: vcmp +; CHECK: vmaxnm.f64 + %cmp = fcmp fast ule double %a, %b %cond = select i1 %cmp, double %b, double %a ret double %cond } @@ -221,285 +149,225 @@ define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) { ; known non-NaNs define float @fp-armv8_vminnm_NNNo(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNo": -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_NNNo": ; CHECK: vminnm.f32 -; CHECK-NOT: vminnm.f32 - %cmp1 = fcmp olt float %a, 12. +; CHECK: vminnm.f32 + %cmp1 = fcmp fast olt float %a, 12. %cond1 = select i1 %cmp1, float %a, float 12. - %cmp2 = fcmp olt float 34., %cond1 + %cmp2 = fcmp fast olt float 34., %cond1 %cond2 = select i1 %cmp2, float 34., float %cond1 ret float %cond2 } define double @fp-armv8_vminnm_NNNole(double %a) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNole": -; CHECK-FAST: vminnm.f64 -; CHECK-FAST: vminnm.f64 ; CHECK-LABEL: "fp-armv8_vminnm_NNNole": ; CHECK: vminnm.f64 -; CHECK-NOT: vminnm.f64 - %cmp1 = fcmp ole double %a, 34. +; CHECK: vminnm.f64 + %cmp1 = fcmp fast ole double %a, 34. %cond1 = select i1 %cmp1, double %a, double 34. - %cmp2 = fcmp ole double 56., %cond1 + %cmp2 = fcmp fast ole double 56., %cond1 %cond2 = select i1 %cmp2, double 56., double %cond1 ret double %cond2 } define float @fp-armv8_vminnm_NNNo_rev(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNo_rev": -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_NNNo_rev": ; CHECK: vminnm.f32 -; CHECK-NOT: vminnm.f32 - %cmp1 = fcmp ogt float %a, 56. +; CHECK: vminnm.f32 + %cmp1 = fcmp fast ogt float %a, 56. %cond1 = select i1 %cmp1, float 56., float %a - %cmp2 = fcmp ogt float 78., %cond1 + %cmp2 = fcmp fast ogt float 78., %cond1 %cond2 = select i1 %cmp2, float %cond1, float 78. ret float %cond2 } define double @fp-armv8_vminnm_NNNoge_rev(double %a) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNoge_rev": -; CHECK-FAST: vminnm.f64 -; CHECK-FAST: vminnm.f64 ; CHECK-LABEL: "fp-armv8_vminnm_NNNoge_rev": ; CHECK: vminnm.f64 -; CHECK-NOT: vminnm.f64 - %cmp1 = fcmp oge double %a, 78. +; CHECK: vminnm.f64 + %cmp1 = fcmp fast oge double %a, 78. %cond1 = select i1 %cmp1, double 78., double %a - %cmp2 = fcmp oge double 90., %cond1 + %cmp2 = fcmp fast oge double 90., %cond1 %cond2 = select i1 %cmp2, double %cond1, double 90. ret double %cond2 } define float @fp-armv8_vminnm_NNNu(float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNu": -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_NNNu": ; CHECK: vminnm.f32 -; CHECK-NOT: vminnm.f32 - %cmp1 = fcmp ult float 12., %b +; CHECK: vminnm.f32 + %cmp1 = fcmp fast ult float 12., %b %cond1 = select i1 %cmp1, float 12., float %b - %cmp2 = fcmp ult float %cond1, 34. + %cmp2 = fcmp fast ult float %cond1, 34. %cond2 = select i1 %cmp2, float %cond1, float 34. ret float %cond2 } define float @fp-armv8_vminnm_NNNule(float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNule": -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_NNNule": ; CHECK: vminnm.f32 -; CHECK-NOT: vminnm.f32 - %cmp1 = fcmp ule float 34., %b +; CHECK: vminnm.f32 + %cmp1 = fcmp fast ule float 34., %b %cond1 = select i1 %cmp1, float 34., float %b - %cmp2 = fcmp ule float %cond1, 56. + %cmp2 = fcmp fast ule float %cond1, 56. %cond2 = select i1 %cmp2, float %cond1, float 56. ret float %cond2 } define float @fp-armv8_vminnm_NNNu_rev(float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNu_rev": -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vminnm.f32 ; CHECK-LABEL: "fp-armv8_vminnm_NNNu_rev": ; CHECK: vminnm.f32 -; CHECK-NOT: vminnm.f32 - %cmp1 = fcmp ugt float 56., %b +; CHECK: vminnm.f32 + %cmp1 = fcmp fast ugt float 56., %b %cond1 = select i1 %cmp1, float %b, float 56. - %cmp2 = fcmp ugt float %cond1, 78. + %cmp2 = fcmp fast ugt float %cond1, 78. %cond2 = select i1 %cmp2, float 78., float %cond1 ret float %cond2 } define double @fp-armv8_vminnm_NNNuge_rev(double %b) { -; CHECK-FAST-LABEL: "fp-armv8_vminnm_NNNuge_rev": -; CHECK-FAST: vminnm.f64 -; CHECK-FAST: vminnm.f64 ; CHECK-LABEL: "fp-armv8_vminnm_NNNuge_rev": ; CHECK: vminnm.f64 -; CHECK-NOT: vminnm.f64 - %cmp1 = fcmp uge double 78., %b +; CHECK: vminnm.f64 + %cmp1 = fcmp fast uge double 78., %b %cond1 = select i1 %cmp1, double %b, double 78. - %cmp2 = fcmp uge double %cond1, 90. + %cmp2 = fcmp fast uge double %cond1, 90. %cond2 = select i1 %cmp2, double 90., double %cond1 ret double %cond2 } define float @fp-armv8_vmaxnm_NNNo(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNo": -; CHECK-FAST: vmaxnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo": ; CHECK: vmaxnm.f32 -; CHECK-NOT: vmaxnm.f32 - %cmp1 = fcmp ogt float %a, 12. +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast ogt float %a, 12. %cond1 = select i1 %cmp1, float %a, float 12. - %cmp2 = fcmp ogt float 34., %cond1 + %cmp2 = fcmp fast ogt float 34., %cond1 %cond2 = select i1 %cmp2, float 34., float %cond1 ret float %cond2 } define float @fp-armv8_vmaxnm_NNNoge(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNoge": -; CHECK-FAST: vmaxnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_NNNoge": ; CHECK: vmaxnm.f32 -; CHECK-NOT: vmaxnm.f32 - %cmp1 = fcmp oge float %a, 34. +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast oge float %a, 34. %cond1 = select i1 %cmp1, float %a, float 34. - %cmp2 = fcmp oge float 56., %cond1 + %cmp2 = fcmp fast oge float 56., %cond1 %cond2 = select i1 %cmp2, float 56., float %cond1 ret float %cond2 } define float @fp-armv8_vmaxnm_NNNo_rev(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNo_rev": -; CHECK-FAST: vmaxnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo_rev": ; CHECK: vmaxnm.f32 -; CHECK-NOT: vmaxnm.f32 - %cmp1 = fcmp olt float %a, 56. +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast olt float %a, 56. %cond1 = select i1 %cmp1, float 56., float %a - %cmp2 = fcmp olt float 78., %cond1 + %cmp2 = fcmp fast olt float 78., %cond1 %cond2 = select i1 %cmp2, float %cond1, float 78. ret float %cond2 } define float @fp-armv8_vmaxnm_NNNole_rev(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNole_rev": -; CHECK-FAST: vmaxnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_NNNole_rev": ; CHECK: vmaxnm.f32 -; CHECK-NOT: vmaxnm.f32 - %cmp1 = fcmp ole float %a, 78. +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast ole float %a, 78. %cond1 = select i1 %cmp1, float 78., float %a - %cmp2 = fcmp ole float 90., %cond1 + %cmp2 = fcmp fast ole float 90., %cond1 %cond2 = select i1 %cmp2, float %cond1, float 90. ret float %cond2 } define float @fp-armv8_vmaxnm_NNNu(float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNu": -; CHECK-FAST: vmaxnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu": ; CHECK: vmaxnm.f32 -; CHEC-NOT: vmaxnm.f32 - %cmp1 = fcmp ugt float 12., %b +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast ugt float 12., %b %cond1 = select i1 %cmp1, float 12., float %b - %cmp2 = fcmp ugt float %cond1, 34. + %cmp2 = fcmp fast ugt float %cond1, 34. %cond2 = select i1 %cmp2, float %cond1, float 34. ret float %cond2 } define float @fp-armv8_vmaxnm_NNNuge(float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNuge": -; CHECK-FAST: vmaxnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_NNNuge": ; CHECK: vmaxnm.f32 -; CHECK-NOT: vmaxnm.f32 - %cmp1 = fcmp uge float 34., %b +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast uge float 34., %b %cond1 = select i1 %cmp1, float 34., float %b - %cmp2 = fcmp uge float %cond1, 56. + %cmp2 = fcmp fast uge float %cond1, 56. %cond2 = select i1 %cmp2, float %cond1, float 56. ret float %cond2 } define float @fp-armv8_vmaxnm_NNNu_rev(float %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNu_rev": -; CHECK-FAST: vmaxnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu_rev": ; CHECK: vmaxnm.f32 -; CHECK-NOT: vmaxnm.f32 - %cmp1 = fcmp ult float 56., %b +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast ult float 56., %b %cond1 = select i1 %cmp1, float %b, float 56. - %cmp2 = fcmp ult float %cond1, 78. + %cmp2 = fcmp fast ult float %cond1, 78. %cond2 = select i1 %cmp2, float 78., float %cond1 ret float %cond2 } define double @fp-armv8_vmaxnm_NNNule_rev( double %b) { -; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_NNNule_rev": -; CHECK-FAST: vmaxnm.f64 -; CHECK-FAST: vmaxnm.f64 ; CHECK-LABEL: "fp-armv8_vmaxnm_NNNule_rev": ; CHECK: vmaxnm.f64 -; CHECK-NOT: vmaxnm.f64 - %cmp1 = fcmp ule double 78., %b +; CHECK: vmaxnm.f64 + %cmp1 = fcmp fast ule double 78., %b %cond1 = select i1 %cmp1, double %b, double 78. - %cmp2 = fcmp ule double %cond1, 90. + %cmp2 = fcmp fast ule double %cond1, 90. %cond2 = select i1 %cmp2, double 90., double %cond1 ret double %cond2 } define float @fp-armv8_vminmaxnm_0(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_0": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vminmaxnm_0": -; CHECK-NOT: vminnm.f32 +; CHECK-NOT: vcmp +; CHECK: vminnm.f32 ; CHECK: vmaxnm.f32 - %cmp1 = fcmp olt float %a, 0. + %cmp1 = fcmp fast olt float %a, 0. %cond1 = select i1 %cmp1, float %a, float 0. - %cmp2 = fcmp ogt float %cond1, 0. + %cmp2 = fcmp fast ogt float %cond1, 0. %cond2 = select i1 %cmp2, float %cond1, float 0. ret float %cond2 } define float @fp-armv8_vminmaxnm_neg0(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_neg0": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vminmaxnm_neg0": +; CHECK-NOT: vcmp ; CHECK: vminnm.f32 -; CHECK-NOT: vmaxnm.f32 - %cmp1 = fcmp olt float %a, -0. +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast olt float %a, -0. %cond1 = select i1 %cmp1, float %a, float -0. - %cmp2 = fcmp ogt float %cond1, -0. + %cmp2 = fcmp fast ugt float %cond1, -0. %cond2 = select i1 %cmp2, float %cond1, float -0. ret float %cond2 } define float @fp-armv8_vminmaxnm_e_0(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_e_0": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vminmaxnm_e_0": -; CHECK-NOT: vminnm.f32 +; CHECK-NOT: vcmp +; CHECK: vminnm.f32 ; CHECK: vmaxnm.f32 - %cmp1 = fcmp ule float 0., %a + %cmp1 = fcmp fast ule float 0., %a %cond1 = select i1 %cmp1, float 0., float %a - %cmp2 = fcmp uge float 0., %cond1 + %cmp2 = fcmp fast uge float 0., %cond1 %cond2 = select i1 %cmp2, float 0., float %cond1 ret float %cond2 } define float @fp-armv8_vminmaxnm_e_neg0(float %a) { -; CHECK-FAST-LABEL: "fp-armv8_vminmaxnm_e_neg0": -; CHECK-FAST-NOT: vcmp -; CHECK-FAST: vminnm.f32 -; CHECK-FAST: vmaxnm.f32 ; CHECK-LABEL: "fp-armv8_vminmaxnm_e_neg0": +; CHECK-NOT: vcmp ; CHECK: vminnm.f32 -; CHECK-NOT: vmaxnm.f32 - %cmp1 = fcmp ule float -0., %a +; CHECK: vmaxnm.f32 + %cmp1 = fcmp fast ule float -0., %a %cond1 = select i1 %cmp1, float -0., float %a - %cmp2 = fcmp uge float -0., %cond1 + %cmp2 = fcmp fast oge float -0., %cond1 %cond2 = select i1 %cmp2, float -0., float %cond1 ret float %cond2 } diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index b7a23b7bb59c..b1b4f1a940d4 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -393,8 +393,8 @@ entry: %sub.i = sub <4 x i32> %add.i185, zeroinitializer %add.i = add <4 x i32> %sub.i, zeroinitializer %vmovn.i = trunc <4 x i32> %add.i to <4 x i16> - tail call void @llvm.arm.neon.vst1.v4i16(i8* undef, <4 x i16> %vmovn.i, i32 2) + tail call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* undef, <4 x i16> %vmovn.i, i32 2) unreachable } -declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4i16(i8*, <4 x i16>, i32) nounwind diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index c3e41cacde4c..0455190b4c9d 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -447,7 +447,7 @@ entry: %0 = trunc i32 %mul to i8 %1 = insertelement <8 x i8> undef, i8 %0, i32 0 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer - %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %src, i32 1) + %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %src, i32 1) %4 = bitcast <16 x i8> %3 to <2 x double> %5 = extractelement <2 x double> %4, i32 1 %6 = bitcast double %5 to <8 x i8> @@ -459,13 +459,13 @@ entry: %12 = add <8 x i16> %7, %11 %13 = mul <8 x i16> %12, %8 %14 = bitcast i16* %dst to i8* - tail call void @llvm.arm.neon.vst1.v8i16(i8* %14, <8 x i16> %13, i32 2) + tail call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %14, <8 x i16> %13, i32 2) ret void } -declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8*, i32) nounwind readonly +declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8*, i32) nounwind readonly -declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind ; Take advantage of the Cortex-A8 multiplier accumulator forward. @@ -480,7 +480,7 @@ entry: %0 = trunc i32 %mul to i8 %1 = insertelement <8 x i8> undef, i8 %0, i32 0 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer - %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %src, i32 1) + %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %src, i32 1) %4 = bitcast <16 x i8> %3 to <2 x double> %5 = extractelement <2 x double> %4, i32 1 %6 = bitcast double %5 to <8 x i8> @@ -502,7 +502,7 @@ entry: %0 = trunc i32 %mul to i8 %1 = insertelement <8 x i8> undef, i8 %0, i32 0 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer - %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %src, i32 1) + %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %src, i32 1) %4 = bitcast <16 x i8> %3 to <2 x double> %5 = extractelement <2 x double> %4, i32 1 %6 = bitcast double %5 to <8 x i8> @@ -559,7 +559,7 @@ for.body33.lr.ph: ; preds = %for.body for.body33: ; preds = %for.body33, %for.body33.lr.ph %add45 = add i32 undef, undef - %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* undef, i32 1) + %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* undef, i32 1) %0 = load i32*, i32** undef, align 4 %shuffle.i250 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer %1 = bitcast <1 x i64> %shuffle.i250 to <8 x i8> diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll index e362ce36f8ba..6ddf9850cfcb 100644 --- a/test/CodeGen/ARM/vpadd.ll +++ b/test/CodeGen/ARM/vpadd.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpaddi8: diff --git a/test/CodeGen/ARM/vselect_imax.ll b/test/CodeGen/ARM/vselect_imax.ll index 0eb051036d99..85c8c5cfcda1 100644 --- a/test/CodeGen/ARM/vselect_imax.ll +++ b/test/CodeGen/ARM/vselect_imax.ll @@ -3,16 +3,13 @@ ; Make sure that ARM backend with NEON handles vselect. define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) { -; CHECK: vcgt.s32 [[QR:q[0-9]+]], [[Q1:q[0-9]+]], [[Q2:q[0-9]+]] -; CHECK: vbsl [[QR]], [[Q1]], [[Q2]] +; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} %cmpres = icmp sgt <4 x i32> %a, %b %maxres = select <4 x i1> %cmpres, <4 x i32> %a, <4 x i32> %b store <4 x i32> %maxres, <4 x i32>* %m ret void } -; We adjusted the cost model of the following selects. When we improve code -; lowering we also need to adjust the cost. %T0_10 = type <16 x i16> %T1_10 = type <16 x i1> ; CHECK-LABEL: func_blend10: @@ -21,10 +18,10 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2, %v0 = load %T0_10, %T0_10* %loadaddr %v1 = load %T0_10, %T0_10* %loadaddr2 %c = icmp slt %T0_10 %v0, %v1 -; CHECK: vbsl -; CHECK: vbsl +; CHECK: vmin.s16 +; CHECK: vmin.s16 ; COST: func_blend10 -; COST: cost of 40 {{.*}} select +; COST: cost of 2 {{.*}} select %r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1 store %T0_10 %r, %T0_10* %storeaddr ret void @@ -37,10 +34,10 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2, %v0 = load %T0_14, %T0_14* %loadaddr %v1 = load %T0_14, %T0_14* %loadaddr2 %c = icmp slt %T0_14 %v0, %v1 -; CHECK: vbsl -; CHECK: vbsl +; CHECK: vmin.s32 +; CHECK: vmin.s32 ; COST: func_blend14 -; COST: cost of 41 {{.*}} select +; COST: cost of 2 {{.*}} select %r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1 store %T0_14 %r, %T0_14* %storeaddr ret void @@ -50,17 +47,20 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2, ; CHECK-LABEL: func_blend15: define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2, %T1_15* %blend, %T0_15* %storeaddr) { -; CHECK: vbsl -; CHECK: vbsl +; CHECK: vmin.s32 +; CHECK: vmin.s32 %v0 = load %T0_15, %T0_15* %loadaddr %v1 = load %T0_15, %T0_15* %loadaddr2 %c = icmp slt %T0_15 %v0, %v1 ; COST: func_blend15 -; COST: cost of 82 {{.*}} select +; COST: cost of 4 {{.*}} select %r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1 store %T0_15 %r, %T0_15* %storeaddr ret void } + +; We adjusted the cost model of the following selects. When we improve code +; lowering we also need to adjust the cost. %T0_18 = type <4 x i64> %T1_18 = type <4 x i1> ; CHECK-LABEL: func_blend18: diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll index f605fa4d6003..404129a7e6ad 100644 --- a/test/CodeGen/ARM/vst1.ll +++ b/test/CodeGen/ARM/vst1.ll @@ -5,7 +5,7 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vst1.8 {d16}, [r0:64] %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16) + call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, i32 16) ret void } @@ -14,7 +14,7 @@ define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst1.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - call void @llvm.arm.neon.vst1.v4i16(i8* %tmp0, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, i32 1) ret void } @@ -23,7 +23,7 @@ define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst1.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - call void @llvm.arm.neon.vst1.v2i32(i8* %tmp0, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, i32 1) ret void } @@ -32,7 +32,7 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst1.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1) ret void } @@ -43,7 +43,7 @@ define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind { %A = load float*, float** %ptr %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1) %tmp2 = getelementptr float, float* %A, i32 2 store float* %tmp2, float** %ptr ret void @@ -54,7 +54,7 @@ define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst1.64 %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>, <1 x i64>* %B - call void @llvm.arm.neon.vst1.v1i64(i8* %tmp0, <1 x i64> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, i32 1) ret void } @@ -63,7 +63,7 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst1.8 {d16, d17}, [r0:64] %tmp1 = load <16 x i8>, <16 x i8>* %B - call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8) + call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, i32 8) ret void } @@ -73,7 +73,7 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst1.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32) + call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32) ret void } @@ -84,7 +84,7 @@ define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 8) + call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 8) %tmp2 = getelementptr i16, i16* %A, i32 %inc store i16* %tmp2, i16** %ptr ret void @@ -95,7 +95,7 @@ define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst1.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - call void @llvm.arm.neon.vst1.v4i32(i8* %tmp0, <4 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, i32 1) ret void } @@ -104,7 +104,7 @@ define void @vst1Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst1.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - call void @llvm.arm.neon.vst1.v4f32(i8* %tmp0, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, i32 1) ret void } @@ -113,7 +113,7 @@ define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind { ;CHECK: vst1.64 %tmp0 = bitcast i64* %A to i8* %tmp1 = load <2 x i64>, <2 x i64>* %B - call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1) ret void } @@ -122,19 +122,19 @@ define void @vst1Qf64(double* %A, <2 x double>* %B) nounwind { ;CHECK: vst1.64 %tmp0 = bitcast double* %A to i8* %tmp1 = load <2 x double>, <2 x double>* %B - call void @llvm.arm.neon.vst1.v2f64(i8* %tmp0, <2 x double> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.p0i8.v2f64(i8* %tmp0, <2 x double> %tmp1, i32 1) ret void } -declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind -declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) nounwind -declare void @llvm.arm.neon.vst1.v1i64(i8*, <1 x i64>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4i16(i8*, <4 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v2i32(i8*, <2 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v2f32(i8*, <2 x float>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v1i64(i8*, <1 x i64>, i32) nounwind -declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) nounwind -declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind -declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>, i32) nounwind -declare void @llvm.arm.neon.vst1.v2f64(i8*, <2 x double>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4i32(i8*, <4 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v2i64(i8*, <2 x i64>, i32) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v2f64(i8*, <2 x double>, i32) nounwind diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll index 17c8a4bdad9b..e0846ff512ea 100644 --- a/test/CodeGen/ARM/vst2.ll +++ b/test/CodeGen/ARM/vst2.ll @@ -5,7 +5,7 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst2.8 {d16, d17}, [r0:64] %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) + call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) ret void } @@ -15,7 +15,7 @@ define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { ;CHECK: vst2.8 {d16, d17}, [r1], r2 %A = load i8*, i8** %ptr %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4) + call void @llvm.arm.neon.vst2.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4) %tmp2 = getelementptr i8, i8* %A, i32 %inc store i8* %tmp2, i8** %ptr ret void @@ -27,7 +27,7 @@ define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32) + call void @llvm.arm.neon.vst2.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32) ret void } @@ -36,7 +36,7 @@ define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst2.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - call void @llvm.arm.neon.vst2.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } @@ -45,7 +45,7 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - call void @llvm.arm.neon.vst2.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } @@ -55,7 +55,7 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst1.64 {d16, d17}, [r0:128] %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>, <1 x i64>* %B - call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32) + call void @llvm.arm.neon.vst2.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32) ret void } @@ -66,7 +66,7 @@ define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind { %A = load i64*, i64** %ptr %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>, <1 x i64>* %B - call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8) + call void @llvm.arm.neon.vst2.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8) %tmp2 = getelementptr i64, i64* %A, i32 2 store i64* %tmp2, i64** %ptr ret void @@ -77,7 +77,7 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = load <16 x i8>, <16 x i8>* %B - call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8) + call void @llvm.arm.neon.vst2.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8) ret void } @@ -87,7 +87,7 @@ define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16) + call void @llvm.arm.neon.vst2.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16) ret void } @@ -97,7 +97,7 @@ define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64) + call void @llvm.arm.neon.vst2.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64) ret void } @@ -106,7 +106,7 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - call void @llvm.arm.neon.vst2.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } @@ -114,7 +114,7 @@ define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vst2update: ;CHECK: vst2.16 {d16, d17}, [r0]! %tmp1 = load <4 x i16>, <4 x i16>* %B - tail call void @llvm.arm.neon.vst2.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2) + tail call void @llvm.arm.neon.vst2.p0i8.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2) %t5 = getelementptr inbounds i8, i8* %out, i32 16 ret i8* %t5 } @@ -123,18 +123,18 @@ define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp ali ;CHECK-LABEL: vst2update2: ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]! %tmp1 = load <4 x float>, <4 x float>* %this - call void @llvm.arm.neon.vst2.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind + call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind %tmp2 = getelementptr inbounds i8, i8* %out, i32 32 ret i8* %tmp2 } -declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind -declare void @llvm.arm.neon.vst2.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst2.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst2.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind -declare void @llvm.arm.neon.vst2.v1i64(i8*, <1 x i64>, <1 x i64>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, i32) nounwind -declare void @llvm.arm.neon.vst2.v16i8(i8*, <16 x i8>, <16 x i8>, i32) nounwind -declare void @llvm.arm.neon.vst2.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index 691ee3bd28f3..d70d59579009 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -6,7 +6,7 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { ;This test runs at -O0 so do not check for specific register numbers. ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32) + call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32) ret void } @@ -15,7 +15,7 @@ define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst3.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) ret void } @@ -24,7 +24,7 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } @@ -35,7 +35,7 @@ define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind { %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) %tmp2 = getelementptr i32, i32* %A, i32 6 store i32* %tmp2, i32** %ptr ret void @@ -46,7 +46,7 @@ define void @vst3f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - call void @llvm.arm.neon.vst3.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } @@ -57,7 +57,7 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>, <1 x i64>* %B - call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16) + call void @llvm.arm.neon.vst3.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16) ret void } @@ -67,7 +67,7 @@ define void @vst3i64_update(i64** %ptr, <1 x i64>* %B) nounwind { %A = load i64*, i64** %ptr %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>, <1 x i64>* %B - call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) %tmp2 = getelementptr i64, i64* %A, i32 3 store i64* %tmp2, i64** %ptr ret void @@ -80,7 +80,7 @@ define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]! ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] %tmp1 = load <16 x i8>, <16 x i8>* %B - call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32) + call void @llvm.arm.neon.vst3.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32) ret void } @@ -90,7 +90,7 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst3.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ret void } @@ -102,7 +102,7 @@ define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind { %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) %tmp2 = getelementptr i16, i16* %A, i32 24 store i16* %tmp2, i16** %ptr ret void @@ -114,7 +114,7 @@ define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - call void @llvm.arm.neon.vst3.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) ret void } @@ -124,17 +124,17 @@ define void @vst3Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - call void @llvm.arm.neon.vst3.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } -declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind -declare void @llvm.arm.neon.vst3.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst3.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst3.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind -declare void @llvm.arm.neon.vst3.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind -declare void @llvm.arm.neon.vst3.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind -declare void @llvm.arm.neon.vst3.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst3.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst3.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst3.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll index c343c6c86959..188955102290 100644 --- a/test/CodeGen/ARM/vst4.ll +++ b/test/CodeGen/ARM/vst4.ll @@ -5,7 +5,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) + call void @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) ret void } @@ -15,7 +15,7 @@ define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { ;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2 %A = load i8*, i8** %ptr %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16) + call void @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16) %tmp2 = getelementptr i8, i8* %A, i32 %inc store i8* %tmp2, i8** %ptr ret void @@ -27,7 +27,7 @@ define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16) + call void @llvm.arm.neon.vst4.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16) ret void } @@ -37,7 +37,7 @@ define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32) + call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32) ret void } @@ -46,7 +46,7 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - call void @llvm.arm.neon.vst4.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } @@ -56,7 +56,7 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>, <1 x i64>* %B - call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64) + call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64) ret void } @@ -66,7 +66,7 @@ define void @vst4i64_update(i64** %ptr, <1 x i64>* %B) nounwind { %A = load i64*, i64** %ptr %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>, <1 x i64>* %B - call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) %tmp2 = getelementptr i64, i64* %A, i32 4 store i64* %tmp2, i64** %ptr ret void @@ -78,7 +78,7 @@ define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! ;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256] %tmp1 = load <16 x i8>, <16 x i8>* %B - call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64) + call void @llvm.arm.neon.vst4.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64) ret void } @@ -89,7 +89,7 @@ define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4.16 {d17, d19, d21, d23}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst4.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ret void } @@ -99,7 +99,7 @@ define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst4.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - call void @llvm.arm.neon.vst4.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) ret void } @@ -109,7 +109,7 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } @@ -121,19 +121,19 @@ define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind { %A = load float*, float** %ptr %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) %tmp2 = getelementptr float, float* %A, i32 16 store float* %tmp2, float** %ptr ret void } -declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind -declare void @llvm.arm.neon.vst4.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst4.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst4.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind -declare void @llvm.arm.neon.vst4.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind -declare void @llvm.arm.neon.vst4.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind -declare void @llvm.arm.neon.vst4.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind -declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind -declare void @llvm.arm.neon.vst4.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind +declare void @llvm.arm.neon.vst4.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) nounwind diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index a4575417bce5..7e130ea01b64 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -110,7 +110,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) + call void @llvm.arm.neon.vst2lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) ret void } @@ -120,7 +120,7 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) + call void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) ret void } @@ -131,7 +131,7 @@ define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind { %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2) + call void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2) %tmp2 = getelementptr i16, i16* %A, i32 %inc store i16* %tmp2, i16** %ptr ret void @@ -142,7 +142,7 @@ define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst2.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - call void @llvm.arm.neon.vst2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst2lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) ret void } @@ -151,7 +151,7 @@ define void @vst2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - call void @llvm.arm.neon.vst2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst2lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) ret void } @@ -161,7 +161,7 @@ define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2.16 {d17[1], d19[1]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) + call void @llvm.arm.neon.vst2lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) ret void } @@ -171,7 +171,7 @@ define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) + call void @llvm.arm.neon.vst2lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) ret void } @@ -180,24 +180,24 @@ define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - call void @llvm.arm.neon.vst2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1) + call void @llvm.arm.neon.vst2lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1) ret void } -declare void @llvm.arm.neon.vst2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind -declare void @llvm.arm.neon.vst2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind -declare void @llvm.arm.neon.vst2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind -declare void @llvm.arm.neon.vst2lane.v2f32(i8*, <2 x float>, <2 x float>, i32, i32) nounwind +declare void @llvm.arm.neon.vst2lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind +declare void @llvm.arm.neon.vst2lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind +declare void @llvm.arm.neon.vst2lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind +declare void @llvm.arm.neon.vst2lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, i32, i32) nounwind -declare void @llvm.arm.neon.vst2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind -declare void @llvm.arm.neon.vst2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind -declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind +declare void @llvm.arm.neon.vst2lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind +declare void @llvm.arm.neon.vst2lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind +declare void @llvm.arm.neon.vst2lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst3lanei8: ;CHECK: vst3.8 %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst3lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ret void } @@ -207,7 +207,7 @@ define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) + call void @llvm.arm.neon.vst3lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) ret void } @@ -216,7 +216,7 @@ define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - call void @llvm.arm.neon.vst3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst3lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) ret void } @@ -225,7 +225,7 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - call void @llvm.arm.neon.vst3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst3lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) ret void } @@ -235,7 +235,7 @@ define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8) + call void @llvm.arm.neon.vst3lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8) ret void } @@ -244,7 +244,7 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1) + call void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1) ret void } @@ -255,7 +255,7 @@ define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1) + call void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1) %tmp2 = getelementptr i32, i32* %A, i32 3 store i32* %tmp2, i32** %ptr ret void @@ -266,18 +266,18 @@ define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - call void @llvm.arm.neon.vst3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst3lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) ret void } -declare void @llvm.arm.neon.vst3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind -declare void @llvm.arm.neon.vst3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind -declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind -declare void @llvm.arm.neon.vst3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind +declare void @llvm.arm.neon.vst3lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind +declare void @llvm.arm.neon.vst3lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind +declare void @llvm.arm.neon.vst3lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind +declare void @llvm.arm.neon.vst3lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind -declare void @llvm.arm.neon.vst3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind -declare void @llvm.arm.neon.vst3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind -declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind +declare void @llvm.arm.neon.vst3lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind +declare void @llvm.arm.neon.vst3lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind +declare void @llvm.arm.neon.vst3lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { @@ -285,7 +285,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) + call void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) ret void } @@ -295,7 +295,7 @@ define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! %A = load i8*, i8** %ptr %tmp1 = load <8 x i8>, <8 x i8>* %B - call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) + call void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp2 = getelementptr i8, i8* %A, i32 4 store i8* %tmp2, i8** %ptr ret void @@ -306,7 +306,7 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>, <4 x i16>* %B - call void @llvm.arm.neon.vst4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst4lane.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1) ret void } @@ -316,7 +316,7 @@ define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>, <2 x i32>* %B - call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16) + call void @llvm.arm.neon.vst4lane.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16) ret void } @@ -325,7 +325,7 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>, <2 x float>* %B - call void @llvm.arm.neon.vst4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst4lane.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1) ret void } @@ -335,7 +335,7 @@ define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>, <8 x i16>* %B - call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16) + call void @llvm.arm.neon.vst4lane.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16) ret void } @@ -345,7 +345,7 @@ define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>, <4 x i32>* %B - call void @llvm.arm.neon.vst4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) + call void @llvm.arm.neon.vst4lane.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) ret void } @@ -354,7 +354,7 @@ define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>, <4 x float>* %B - call void @llvm.arm.neon.vst4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst4lane.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1) ret void } @@ -365,11 +365,11 @@ define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind ret <8 x i16> %r } -declare void @llvm.arm.neon.vst4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind -declare void @llvm.arm.neon.vst4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind -declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind -declare void @llvm.arm.neon.vst4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind +declare void @llvm.arm.neon.vst4lane.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind +declare void @llvm.arm.neon.vst4lane.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind +declare void @llvm.arm.neon.vst4lane.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind +declare void @llvm.arm.neon.vst4lane.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind -declare void @llvm.arm.neon.vst4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind -declare void @llvm.arm.neon.vst4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind -declare void @llvm.arm.neon.vst4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind +declare void @llvm.arm.neon.vst4lane.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind +declare void @llvm.arm.neon.vst4lane.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind +declare void @llvm.arm.neon.vst4lane.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll index 7b83dfdaf229..36bcde22731d 100644 --- a/test/CodeGen/ARM/vtrn.ll +++ b/test/CodeGen/ARM/vtrn.ll @@ -20,11 +20,11 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vtrni8_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vtrn.8 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vtrn.8 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B @@ -52,11 +52,11 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vtrni16_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vtrn.16 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vtrn.16 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = load <4 x i16>, <4 x i16>* %B @@ -84,11 +84,11 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: vtrni32_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vtrn.32 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vtrn.32 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = load <2 x i32>, <2 x i32>* %B @@ -116,11 +116,11 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind { ; CHECK-LABEL: vtrnf_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vtrn.32 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vtrn.32 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = load <2 x float>, <2 x float>* %B @@ -281,11 +281,11 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vtrni8_undef_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vtrn.8 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vtrn.8 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B @@ -325,3 +325,77 @@ define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef> ret <16 x i16> %tmp3 } + +define <8 x i16> @vtrn_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) { +entry: + ; CHECK-LABEL: vtrn_lower_shufflemask_undef + ; CHECK: vtrn + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 5, i32 3, i32 7> + ret <8 x i16> %0 +} + +; Here we get a build_vector node, where all the incoming extract_element +; values do modify the type. However, we get different input types, as some of +; them get truncated from i32 to i8 (from comparing cmp0 with cmp1) and some of +; them get truncated from i16 to i8 (from comparing cmp2 with cmp3). +define <8 x i8> @vtrn_mismatched_builvector0(<8 x i8> %tr0, <8 x i8> %tr1, + <4 x i32> %cmp0, <4 x i32> %cmp1, + <4 x i16> %cmp2, <4 x i16> %cmp3) { + ; CHECK-LABEL: vtrn_mismatched_builvector0 + ; CHECK: vmovn.i32 + ; CHECK: vtrn + ; CHECK: vbsl + %c0 = icmp ult <4 x i32> %cmp0, %cmp1 + %c1 = icmp ult <4 x i16> %cmp2, %cmp3 + %c = shufflevector <4 x i1> %c0, <4 x i1> %c1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> + %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1 + ret <8 x i8> %rv +} + +; Here we get a build_vector node, where half the incoming extract_element +; values do not modify the type (the values form cmp2), but half of them do +; (from the icmp operation). +define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1, + <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) { + ; CHECK-LABEL: vtrn_mismatched_builvector1 + ; We need to extend the 4 x i8 to 4 x i16 in order to perform the vtrn + ; CHECK: vmovl + ; CHECK: vtrn.8 + ; CHECK: vbsl + %cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4 + %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1> + %c0 = icmp ult <4 x i32> %cmp0, %cmp1 + %c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> + %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1 + ret <8 x i8> %rv +} + +; Negative test that should not generate a vtrn +define void @lower_twice_no_vtrn(<4 x i16>* %A, <4 x i16>* %B, <8 x i16>* %C) { +entry: + ; CHECK-LABEL: lower_twice_no_vtrn + ; CHECK: @ BB#0: + ; CHECK-NOT: vtrn + ; CHECK: mov pc, lr + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 5, i32 3, i32 7, i32 1, i32 5, i32 3, i32 7> + store <8 x i16> %0, <8 x i16>* %C + ret void +} + +; Negative test that should not generate a vtrn +define void @upper_twice_no_vtrn(<4 x i16>* %A, <4 x i16>* %B, <8 x i16>* %C) { +entry: + ; CHECK-LABEL: upper_twice_no_vtrn + ; CHECK: @ BB#0: + ; CHECK-NOT: vtrn + ; CHECK: mov pc, lr + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 6, i32 0, i32 4, i32 2, i32 6> + store <8 x i16> %0, <8 x i16>* %C + ret void +} diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll index 5510634b0668..04499e77fde6 100644 --- a/test/CodeGen/ARM/vuzp.ll +++ b/test/CodeGen/ARM/vuzp.ll @@ -20,11 +20,11 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vuzpi8_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vuzp.8 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vuzp.8 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B @@ -52,11 +52,11 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vuzpi16_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vuzp.16 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vuzp.16 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = load <4 x i16>, <4 x i16>* %B @@ -220,11 +220,11 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vuzpi8_undef_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vuzp.8 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vuzp.8 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B @@ -264,3 +264,109 @@ define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15> ret <16 x i16> %tmp3 } + +define <8 x i16> @vuzp_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) { +entry: + ; CHECK-LABEL: vuzp_lower_shufflemask_undef + ; CHECK: vuzp + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 3, i32 5, i32 7> + ret <8 x i16> %0 +} + +define <4 x i32> @vuzp_lower_shufflemask_zeroed(<2 x i32>* %A, <2 x i32>* %B) { +entry: + ; CHECK-LABEL: vuzp_lower_shufflemask_zeroed + ; CHECK-NOT: vtrn + ; CHECK: vuzp + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 0, i32 1, i32 3> + ret <4 x i32> %0 +} + +define void @vuzp_rev_shufflemask_vtrn(<2 x i32>* %A, <2 x i32>* %B, <4 x i32>* %C) { +entry: + ; CHECK-LABEL: vuzp_rev_shufflemask_vtrn + ; CHECK-NOT: vtrn + ; CHECK: vuzp + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 0, i32 2> + store <4 x i32> %0, <4 x i32>* %C + ret void +} + +define <8 x i8> @vuzp_trunc(<8 x i8> %in0, <8 x i8> %in1, <8 x i32> %cmp0, <8 x i32> %cmp1) { +; In order to create the select we need to truncate the vcgt result from a vector of i32 to a vector of i8. +; This results in a build_vector with mismatched types. We will generate two vmovn.i32 instructions to +; truncate from i32 to i16 and one vuzp to perform the final truncation for i8. +; CHECK-LABEL: vuzp_trunc +; CHECK: vmovn.i32 +; CHECK: vmovn.i32 +; CHECK: vuzp +; CHECK: vbsl + %c = icmp ult <8 x i32> %cmp0, %cmp1 + %res = select <8 x i1> %c, <8 x i8> %in0, <8 x i8> %in1 + ret <8 x i8> %res +} + +; Shuffle the result from the compare with a <4 x i8>. +; We need to extend the loaded <4 x i8> to <4 x i16>. Otherwise we wouldn't be able +; to perform the vuzp and get the vbsl mask. +define <8 x i8> @vuzp_trunc_and_shuffle(<8 x i8> %tr0, <8 x i8> %tr1, + <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) { +; CHECK-LABEL: vuzp_trunc_and_shuffle +; CHECK: vmovl +; CHECK: vuzp +; CHECK: vbsl + %cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4 + %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1> + %c0 = icmp ult <4 x i32> %cmp0, %cmp1 + %c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1 + ret <8 x i8> %rv +} + +; Use an undef value for the <4 x i8> that is being shuffled with the compare result. +; This produces a build_vector with some of the operands undefs. +define <8 x i8> @vuzp_trunc_and_shuffle_undef_right(<8 x i8> %tr0, <8 x i8> %tr1, + <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) { +; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_right +; CHECK: vuzp +; CHECK: vbsl + %cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4 + %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1> + %c0 = icmp ult <4 x i32> %cmp0, %cmp1 + %c = shufflevector <4 x i1> %c0, <4 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1 + ret <8 x i8> %rv +} + +define <8 x i8> @vuzp_trunc_and_shuffle_undef_left(<8 x i8> %tr0, <8 x i8> %tr1, + <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i8> *%cmp2_ptr) { +; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_left +; CHECK: vuzp +; CHECK: vbsl + %cmp2_load = load <4 x i8>, <4 x i8> * %cmp2_ptr, align 4 + %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1> + %c0 = icmp ult <4 x i32> %cmp0, %cmp1 + %c = shufflevector <4 x i1> undef, <4 x i1> %c0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1 + ret <8 x i8> %rv +} + +; We're using large data types here, and we have to fill with undef values until we +; get some vector size that we can represent. +define <10 x i8> @vuzp_wide_type(<10 x i8> %tr0, <10 x i8> %tr1, + <5 x i32> %cmp0, <5 x i32> %cmp1, <5 x i8> *%cmp2_ptr) { +; CHECK-LABEL: vuzp_wide_type +; CHECK: vbsl + %cmp2_load = load <5 x i8>, <5 x i8> * %cmp2_ptr, align 4 + %cmp2 = trunc <5 x i8> %cmp2_load to <5 x i1> + %c0 = icmp ult <5 x i32> %cmp0, %cmp1 + %c = shufflevector <5 x i1> %c0, <5 x i1> %cmp2, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> + %rv = select <10 x i1> %c, <10 x i8> %tr0, <10 x i8> %tr1 + ret <10 x i8> %rv +} diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll index 1d9f59aeda0b..259b484f5f8e 100644 --- a/test/CodeGen/ARM/vzip.ll +++ b/test/CodeGen/ARM/vzip.ll @@ -20,11 +20,11 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vzipi8_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vzip.8 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vzip.8 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B @@ -52,11 +52,11 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vzipi16_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vzip.16 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vzip.16 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = load <4 x i16>, <4 x i16>* %B @@ -220,11 +220,11 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vzipi8_undef_Qres: ; CHECK: @ BB#0: -; CHECK-NEXT: vldr d17, [r1] -; CHECK-NEXT: vldr d16, [r0] -; CHECK-NEXT: vzip.8 d16, d17 -; CHECK-NEXT: vmov r0, r1, d16 -; CHECK-NEXT: vmov r2, r3, d17 +; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] +; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] +; CHECK-NEXT: vzip.8 [[LDR0]], [[LDR1]] +; CHECK-NEXT: vmov r0, r1, [[LDR0]] +; CHECK-NEXT: vmov r2, r3, [[LDR1]] ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B @@ -264,3 +264,55 @@ define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31> ret <32 x i8> %tmp3 } + +define <8 x i16> @vzip_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) { +entry: + ; CHECK-LABEL: vzip_lower_shufflemask_undef + ; CHECK: vzip + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7> + ret <8 x i16> %0 +} + +define <4 x i32> @vzip_lower_shufflemask_zeroed(<2 x i32>* %A) { +entry: + ; CHECK-LABEL: vzip_lower_shufflemask_zeroed + ; CHECK-NOT: vtrn + ; CHECK: vzip + %tmp1 = load <2 x i32>, <2 x i32>* %A + %0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 0, i32 1, i32 0> + ret <4 x i32> %0 +} + +define <4 x i32> @vzip_lower_shufflemask_vuzp(<2 x i32>* %A) { +entry: + ; CHECK-LABEL: vzip_lower_shufflemask_vuzp + ; CHECK-NOT: vuzp + ; CHECK: vzip + %tmp1 = load <2 x i32>, <2 x i32>* %A + %0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 0> + ret <4 x i32> %0 +} + +define void @vzip_undef_rev_shufflemask_vtrn(<2 x i32>* %A, <4 x i32>* %B) { +entry: + ; CHECK-LABEL: vzip_undef_rev_shufflemask_vtrn + ; CHECK-NOT: vtrn + ; CHECK: vzip + %tmp1 = load <2 x i32>, <2 x i32>* %A + %0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 0> + store <4 x i32> %0, <4 x i32>* %B + ret void +} + +define void @vzip_vext_factor(<8 x i16>* %A, <4 x i16>* %B) { +entry: + ; CHECK-LABEL: vzip_vext_factor + ; CHECK: vext.16 d16, d16, d17, #3 + ; CHECK: vzip + %tmp1 = load <8 x i16>, <8 x i16>* %A + %0 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 4, i32 5, i32 3> + store <4 x i16> %0, <4 x i16>* %B + ret void +} |