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-rw-r--r--test/CodeGen/ARM/ARMLoadStoreDBG.mir1
-rw-r--r--test/CodeGen/ARM/acle-intrinsics-v5.ll110
-rw-r--r--test/CodeGen/ARM/acle-intrinsics.ll481
-rw-r--r--test/CodeGen/ARM/alloca-align.ll24
-rw-r--r--test/CodeGen/ARM/cmp1-peephole-thumb.mir3
-rw-r--r--test/CodeGen/ARM/cmp2-peephole-thumb.mir5
-rw-r--r--test/CodeGen/ARM/dbg-range-extension.mir5
-rw-r--r--test/CodeGen/ARM/sat-arith.ll63
-rw-r--r--test/CodeGen/ARM/vabs.ll38
-rw-r--r--test/CodeGen/ARM/xray-armv6-attribute-instrumentation.ll6
-rw-r--r--test/CodeGen/ARM/xray-armv7-attribute-instrumentation.ll7
11 files changed, 666 insertions, 77 deletions
diff --git a/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/test/CodeGen/ARM/ARMLoadStoreDBG.mir
index 0e6f80bfb48b..cf5388ac1ccb 100644
--- a/test/CodeGen/ARM/ARMLoadStoreDBG.mir
+++ b/test/CodeGen/ARM/ARMLoadStoreDBG.mir
@@ -118,7 +118,6 @@ stack:
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
body: |
bb.0.entry:
- successors: %bb.1, %bb.2.if.end
liveins: %r0, %r1, %r2, %r3, %lr, %r7
DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
diff --git a/test/CodeGen/ARM/acle-intrinsics-v5.ll b/test/CodeGen/ARM/acle-intrinsics-v5.ll
new file mode 100644
index 000000000000..407bea148863
--- /dev/null
+++ b/test/CodeGen/ARM/acle-intrinsics-v5.ll
@@ -0,0 +1,110 @@
+; RUN: llc -O1 -mtriple=armv5te-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=armv7-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=thumbv7-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=thumbv6t2-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=thumbv7em-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=thumbv8m.main-none-none-eabi -mattr=+dsp %s -o - | FileCheck %s
+define i32 @smulbb(i32 %a, i32 %b) {
+; CHECK-LABEL: smulbb
+; CHECK: smulbb r0, r0, r1
+ %tmp = call i32 @llvm.arm.smulbb(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smulbt(i32 %a, i32 %b) {
+; CHECK-LABEL: smulbt
+; CHECK: smulbt r0, r0, r1
+ %tmp = call i32 @llvm.arm.smulbt(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smultb(i32 %a, i32 %b) {
+; CHECK-LABEL: smultb
+; CHECK: smultb r0, r0, r1
+ %tmp = call i32 @llvm.arm.smultb(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smultt(i32 %a, i32 %b) {
+; CHECK-LABEL: smultt
+; CHECK: smultt r0, r0, r1
+ %tmp = call i32 @llvm.arm.smultt(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smulwb(i32 %a, i32 %b) {
+; CHECK-LABEL: smulwb
+; CHECK: smulwb r0, r0, r1
+ %tmp = call i32 @llvm.arm.smulwb(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smulwt(i32 %a, i32 %b) {
+; CHECK-LABEL: smulwt
+; CHECK: smulwt r0, r0, r1
+ %tmp = call i32 @llvm.arm.smulwt(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @acc_mults(i32 %a, i32 %b, i32 %acc) {
+; CHECK-LABEL: acc_mults
+; CHECK: smlabb r2, r0, r1, r2
+; CHECK: smlabt r2, r0, r1, r2
+; CHECK: smlatb r2, r0, r1, r2
+; CHECK: smlatt r2, r0, r1, r2
+; CHECK: smlawb r2, r0, r1, r2
+; CHECK: smlawt r0, r0, r1, r2
+ %acc1 = call i32 @llvm.arm.smlabb(i32 %a, i32 %b, i32 %acc)
+ %acc2 = call i32 @llvm.arm.smlabt(i32 %a, i32 %b, i32 %acc1)
+ %acc3 = call i32 @llvm.arm.smlatb(i32 %a, i32 %b, i32 %acc2)
+ %acc4 = call i32 @llvm.arm.smlatt(i32 %a, i32 %b, i32 %acc3)
+ %acc5 = call i32 @llvm.arm.smlawb(i32 %a, i32 %b, i32 %acc4)
+ %acc6 = call i32 @llvm.arm.smlawt(i32 %a, i32 %b, i32 %acc5)
+ ret i32 %acc6
+}
+
+define i32 @qadd(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qadd
+; CHECK: qadd r0, r0, r1
+ %tmp = call i32 @llvm.arm.qadd(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @qsub(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qsub
+; CHECK: qsub r0, r0, r1
+ %tmp = call i32 @llvm.arm.qsub(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @qdadd(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qdadd
+; CHECK: qdadd r0, r0, r1
+ %dbl = call i32 @llvm.arm.qadd(i32 %a, i32 %a)
+ %add = call i32 @llvm.arm.qadd(i32 %dbl, i32 %b)
+ ret i32 %add
+}
+
+define i32 @qdsub(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qdsub
+; CHECK: qdsub r0, r0, r1
+ %dbl = call i32 @llvm.arm.qadd(i32 %b, i32 %b)
+ %add = call i32 @llvm.arm.qsub(i32 %a, i32 %dbl)
+ ret i32 %add
+}
+
+declare i32 @llvm.arm.smulbb(i32 %a, i32 %b) nounwind readnone
+declare i32 @llvm.arm.smulbt(i32 %a, i32 %b) nounwind readnone
+declare i32 @llvm.arm.smultb(i32 %a, i32 %b) nounwind readnone
+declare i32 @llvm.arm.smultt(i32 %a, i32 %b) nounwind readnone
+declare i32 @llvm.arm.smulwb(i32 %a, i32 %b) nounwind readnone
+declare i32 @llvm.arm.smulwt(i32 %a, i32 %b) nounwind readnone
+declare i32 @llvm.arm.smlabb(i32, i32, i32) nounwind
+declare i32 @llvm.arm.smlabt(i32, i32, i32) nounwind
+declare i32 @llvm.arm.smlatb(i32, i32, i32) nounwind
+declare i32 @llvm.arm.smlatt(i32, i32, i32) nounwind
+declare i32 @llvm.arm.smlawb(i32, i32, i32) nounwind
+declare i32 @llvm.arm.smlawt(i32, i32, i32) nounwind
+declare i32 @llvm.arm.qadd(i32, i32) nounwind
+declare i32 @llvm.arm.qsub(i32, i32) nounwind
diff --git a/test/CodeGen/ARM/acle-intrinsics.ll b/test/CodeGen/ARM/acle-intrinsics.ll
new file mode 100644
index 000000000000..0c20744e126b
--- /dev/null
+++ b/test/CodeGen/ARM/acle-intrinsics.ll
@@ -0,0 +1,481 @@
+; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=armv7-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=thumbv7-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=thumbv6t2-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=thumbv7em-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=thumbv8m.main-none-none-eabi -mattr=+dsp %s -o - | FileCheck %s
+
+
+; upper-bound of the immediate argument
+define i32 @ssat1(i32 %a) nounwind {
+; CHECK-LABEL: ssat1
+; CHECK: ssat r0, #32, r0
+ %tmp = call i32 @llvm.arm.ssat(i32 %a, i32 32)
+ ret i32 %tmp
+}
+
+; lower-bound of the immediate argument
+define i32 @ssat2(i32 %a) nounwind {
+; CHECK-LABEL: ssat2
+; CHECK: ssat r0, #1, r0
+ %tmp = call i32 @llvm.arm.ssat(i32 %a, i32 1)
+ ret i32 %tmp
+}
+
+; upper-bound of the immediate argument
+define i32 @usat1(i32 %a) nounwind {
+; CHECK-LABEL: usat1
+; CHECK: usat r0, #31, r0
+ %tmp = call i32 @llvm.arm.usat(i32 %a, i32 31)
+ ret i32 %tmp
+}
+
+; lower-bound of the immediate argument
+define i32 @usat2(i32 %a) nounwind {
+; CHECK-LABEL: usat2
+; CHECK: usat r0, #0, r0
+ %tmp = call i32 @llvm.arm.usat(i32 %a, i32 0)
+ ret i32 %tmp
+}
+
+define i32 @ssat16 (i32 %a) nounwind {
+; CHECK-LABEL: ssat16
+; CHECK: ssat16 r0, #1, r0
+; CHECK: ssat16 r0, #16, r0
+ %tmp = call i32 @llvm.arm.ssat16(i32 %a, i32 1)
+ %tmp2 = call i32 @llvm.arm.ssat16(i32 %tmp, i32 16)
+ ret i32 %tmp2
+}
+
+define i32 @usat16(i32 %a) nounwind {
+; CHECK-LABEL: usat16
+; CHECK: usat16 r0, #0, r0
+; CHECK: usat16 r0, #15, r0
+ %tmp = call i32 @llvm.arm.usat16(i32 %a, i32 0)
+ %tmp2 = call i32 @llvm.arm.usat16(i32 %tmp, i32 15)
+ ret i32 %tmp2
+}
+
+define i32 @pack_unpack(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: pack_unpack
+; CHECK: sxtab16 r0, r0, r1
+; CHECK: sxtb16 r0, r0
+; CHECK: uxtab16 r0, r1, r0
+; CHECK: uxtb16 r0, r0
+ %tmp = call i32 @llvm.arm.sxtab16(i32 %a, i32 %b)
+ %tmp1 = call i32 @llvm.arm.sxtb16(i32 %tmp)
+ %tmp2 = call i32 @llvm.arm.uxtab16(i32 %b, i32 %tmp1)
+ %tmp3 = call i32 @llvm.arm.uxtb16(i32 %tmp2)
+ ret i32 %tmp3
+}
+
+define i32 @sel(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: sel
+; CHECK sel r0, r0, r1
+ %tmp = call i32 @llvm.arm.sel(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @qadd8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qadd8
+; CHECK: qadd8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.qadd8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @qsub8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qsub8
+; CHECK: qsub8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.qsub8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @sadd8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: sadd8
+; CHECK: sadd8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.sadd8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @shadd8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: shadd8
+; CHECK: shadd8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.shadd8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @shsub8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: shsub8
+; CHECK: shsub8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.shsub8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @ssub8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: ssub8
+; CHECK: ssub8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.ssub8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uadd8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uadd8
+; CHECK: uadd8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uadd8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uhadd8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uhadd8
+; CHECK: uhadd8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uhadd8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uhsub8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uhsub8
+; CHECK: uhsub8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uhsub8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uqadd8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uqadd8
+; CHECK: uqadd8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uqadd8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uqsub8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uqsub8
+; CHECK: uqsub8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uqsub8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @usub8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: usub8
+; CHECK: usub8 r0, r0, r1
+ %tmp = call i32 @llvm.arm.usub8(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @usad(i32 %a, i32 %b, i32 %c) nounwind {
+; CHECK-LABEL: usad
+; CHECK: usad8 r0, r0, r1
+; CHECK: usada8 r0, r0, r1, r2
+ %tmp = call i32 @llvm.arm.usad8(i32 %a, i32 %b)
+ %tmp1 = call i32 @llvm.arm.usada8(i32 %tmp, i32 %b, i32 %c)
+ ret i32 %tmp1
+}
+
+define i32 @qadd16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qadd16
+; CHECK: qadd16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.qadd16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @qasx(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qasx
+; CHECK: qasx r0, r0, r1
+ %tmp = call i32 @llvm.arm.qasx(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @qsax(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qsax
+; CHECK: qsax r0, r0, r1
+ %tmp = call i32 @llvm.arm.qsax(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @qsub16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: qsub16
+; CHECK: qsub16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.qsub16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @sadd16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: sadd16
+; CHECK: sadd16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.sadd16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @sasx(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: sasx
+; CHECK: sasx r0, r0, r1
+ %tmp = call i32 @llvm.arm.sasx(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @shadd16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: shadd16
+; CHECK: shadd16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.shadd16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @shasx(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: shasx
+; CHECK: shasx r0, r0, r1
+ %tmp = call i32 @llvm.arm.shasx(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @shsax(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: shsax
+; CHECK: shsax r0, r0, r1
+ %tmp = call i32 @llvm.arm.shsax(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @shsub16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: shsub16
+; CHECK: shsub16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.shsub16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @ssax(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: ssax
+; CHECK: ssax r0, r0, r1
+ %tmp = call i32 @llvm.arm.ssax(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @ssub16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: ssub16
+; CHECK: ssub16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.ssub16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uadd16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uadd16
+; CHECK: uadd16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uadd16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uasx(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uasx
+; CHECK: uasx r0, r0, r1
+ %tmp = call i32 @llvm.arm.uasx(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uhadd16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uhadd16
+; CHECK: uhadd16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uhadd16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uhasx(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uhasx
+; CHECK: uhasx r0, r0, r1
+ %tmp = call i32 @llvm.arm.uhasx(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uhsax(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uhsax
+; CHECK: uhsax r0, r0, r1
+ %tmp = call i32 @llvm.arm.uhsax(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uhsub16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uhsub16
+; CHECK: uhsub16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uhsub16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uqadd16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uqadd16
+; CHECK: uqadd16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uqadd16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uqasx(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uqasx
+; CHECK: uqasx r0, r0, r1
+ %tmp = call i32 @llvm.arm.uqasx(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uqsax(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uqsax
+; CHECK: uqsax r0, r0, r1
+ %tmp = call i32 @llvm.arm.uqsax(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @uqsub16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: uqsub16
+; CHECK: uqsub16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.uqsub16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @usax(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: usax
+; CHECK: usax r0, r0, r1
+ %tmp = call i32 @llvm.arm.usax(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @usub16(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: usub16
+; CHECK: usub16 r0, r0, r1
+ %tmp = call i32 @llvm.arm.usub16(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smlad(i32 %a, i32 %b, i32 %c) nounwind {
+; CHECK-LABEL: smlad
+; CHECK: smlad r0, r0, r1, r2
+ %tmp = call i32 @llvm.arm.smlad(i32 %a, i32 %b, i32 %c)
+ ret i32 %tmp
+}
+
+define i32 @smladx(i32 %a, i32 %b, i32 %c) nounwind {
+; CHECK-LABEL: smladx
+; CHECK: smladx r0, r0, r1, r2
+ %tmp = call i32 @llvm.arm.smladx(i32 %a, i32 %b, i32 %c)
+ ret i32 %tmp
+}
+
+define i64 @smlald(i32 %a, i32 %b, i64 %c) nounwind {
+; CHECK-LABEL: smlald
+; CHECK: smlald r2, r3, r0, r1
+ %tmp = call i64 @llvm.arm.smlald(i32 %a, i32 %b, i64 %c)
+ ret i64 %tmp
+}
+
+define i64 @smlaldx(i32 %a, i32 %b, i64 %c) nounwind {
+; CHECK-LABEL: smlaldx
+; CHECK: smlaldx r2, r3, r0, r1
+ %tmp = call i64 @llvm.arm.smlaldx(i32 %a, i32 %b, i64 %c)
+ ret i64 %tmp
+}
+
+define i32 @smlsd(i32 %a, i32 %b, i32 %c) nounwind {
+; CHECK-LABEL: smlsd
+; CHECK: smlsd r0, r0, r1, r2
+ %tmp = call i32 @llvm.arm.smlsd(i32 %a, i32 %b, i32 %c)
+ ret i32 %tmp
+}
+
+define i32 @smlsdx(i32 %a, i32 %b, i32 %c) nounwind {
+; CHECK-LABEL: smlsdx
+; CHECK: smlsdx r0, r0, r1, r2
+ %tmp = call i32 @llvm.arm.smlsdx(i32 %a, i32 %b, i32 %c)
+ ret i32 %tmp
+}
+
+define i64 @smlsld(i32 %a, i32 %b, i64 %c) nounwind {
+; CHECK-LABEL: smlsld
+; CHECK: smlsld r2, r3, r0, r1
+ %tmp = call i64 @llvm.arm.smlsld(i32 %a, i32 %b, i64 %c)
+ ret i64 %tmp
+}
+
+define i64 @smlsldx(i32 %a, i32 %b, i64 %c) nounwind {
+; CHECK-LABEL: smlsldx
+; CHECK: smlsldx r2, r3, r0, r1
+ %tmp = call i64 @llvm.arm.smlsldx(i32 %a, i32 %b, i64 %c)
+ ret i64 %tmp
+}
+
+define i32 @smuad(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: smuad
+; CHECK: smuad r0, r0, r1
+ %tmp = call i32 @llvm.arm.smuad(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smuadx(i32 %a, i32 %b) nounwind {
+;CHECK-LABEL: smuadx
+; CHECK: smuadx r0, r0, r1
+ %tmp = call i32 @llvm.arm.smuadx(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smusd(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: smusd
+; CHECK: smusd r0, r0, r1
+ %tmp = call i32 @llvm.arm.smusd(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+define i32 @smusdx(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: smusdx
+; CHECK: smusdx r0, r0, r1
+ %tmp = call i32 @llvm.arm.smusdx(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
+declare i32 @llvm.arm.usat(i32, i32) nounwind readnone
+declare i32 @llvm.arm.ssat16(i32, i32) nounwind
+declare i32 @llvm.arm.usat16(i32, i32) nounwind
+declare i32 @llvm.arm.sxtab16(i32, i32)
+declare i32 @llvm.arm.sxtb16(i32)
+declare i32 @llvm.arm.uxtab16(i32, i32)
+declare i32 @llvm.arm.uxtb16(i32)
+declare i32 @llvm.arm.sel(i32, i32) nounwind
+declare i32 @llvm.arm.qadd8(i32, i32) nounwind
+declare i32 @llvm.arm.qsub8(i32, i32) nounwind
+declare i32 @llvm.arm.sadd8(i32, i32) nounwind
+declare i32 @llvm.arm.shadd8(i32, i32) nounwind
+declare i32 @llvm.arm.shsub8(i32, i32) nounwind
+declare i32 @llvm.arm.ssub8(i32, i32) nounwind
+declare i32 @llvm.arm.uadd8(i32, i32) nounwind
+declare i32 @llvm.arm.uhadd8(i32, i32) nounwind
+declare i32 @llvm.arm.uhsub8(i32, i32) nounwind
+declare i32 @llvm.arm.uqadd8(i32, i32) nounwind
+declare i32 @llvm.arm.uqsub8(i32, i32) nounwind
+declare i32 @llvm.arm.usub8(i32, i32) nounwind
+declare i32 @llvm.arm.usad8(i32, i32) nounwind readnone
+declare i32 @llvm.arm.usada8(i32, i32, i32) nounwind readnone
+declare i32 @llvm.arm.qadd16(i32, i32) nounwind
+declare i32 @llvm.arm.qasx(i32, i32) nounwind
+declare i32 @llvm.arm.qsax(i32, i32) nounwind
+declare i32 @llvm.arm.qsub16(i32, i32) nounwind
+declare i32 @llvm.arm.sadd16(i32, i32) nounwind
+declare i32 @llvm.arm.sasx(i32, i32) nounwind
+declare i32 @llvm.arm.shadd16(i32, i32) nounwind
+declare i32 @llvm.arm.shasx(i32, i32) nounwind
+declare i32 @llvm.arm.shsax(i32, i32) nounwind
+declare i32 @llvm.arm.shsub16(i32, i32) nounwind
+declare i32 @llvm.arm.ssax(i32, i32) nounwind
+declare i32 @llvm.arm.ssub16(i32, i32) nounwind
+declare i32 @llvm.arm.uadd16(i32, i32) nounwind
+declare i32 @llvm.arm.uasx(i32, i32) nounwind
+declare i32 @llvm.arm.usax(i32, i32) nounwind
+declare i32 @llvm.arm.uhadd16(i32, i32) nounwind
+declare i32 @llvm.arm.uhasx(i32, i32) nounwind
+declare i32 @llvm.arm.uhsax(i32, i32) nounwind
+declare i32 @llvm.arm.uhsub16(i32, i32) nounwind
+declare i32 @llvm.arm.uqadd16(i32, i32) nounwind
+declare i32 @llvm.arm.uqasx(i32, i32) nounwind
+declare i32 @llvm.arm.uqsax(i32, i32) nounwind
+declare i32 @llvm.arm.uqsub16(i32, i32) nounwind
+declare i32 @llvm.arm.usub16(i32, i32) nounwind
+declare i32 @llvm.arm.smlad(i32, i32, i32) nounwind
+declare i32 @llvm.arm.smladx(i32, i32, i32) nounwind
+declare i64 @llvm.arm.smlald(i32, i32, i64) nounwind
+declare i64 @llvm.arm.smlaldx(i32, i32, i64) nounwind
+declare i32 @llvm.arm.smlsd(i32, i32, i32) nounwind
+declare i32 @llvm.arm.smlsdx(i32, i32, i32) nounwind
+declare i64 @llvm.arm.smlsld(i32, i32, i64) nounwind
+declare i64 @llvm.arm.smlsldx(i32, i32, i64) nounwind
+declare i32 @llvm.arm.smuad(i32, i32) nounwind
+declare i32 @llvm.arm.smuadx(i32, i32) nounwind
+declare i32 @llvm.arm.smusd(i32, i32) nounwind
+declare i32 @llvm.arm.smusdx(i32, i32) nounwind
diff --git a/test/CodeGen/ARM/alloca-align.ll b/test/CodeGen/ARM/alloca-align.ll
new file mode 100644
index 000000000000..3bba156f0ee0
--- /dev/null
+++ b/test/CodeGen/ARM/alloca-align.ll
@@ -0,0 +1,24 @@
+; RUN: llc -o - %s | FileCheck %s
+target triple="arm--"
+
+@glob = external global i32*
+
+declare void @bar(i32*, [20000 x i8]* byval)
+
+; CHECK-LABEL: foo:
+; We should see the stack getting additional alignment
+; CHECK: sub sp, sp, #16
+; CHECK: bic sp, sp, #31
+; And a base pointer getting used.
+; CHECK: mov r6, sp
+; Which is passed to the call
+; CHECK: add [[REG:r[0-9]+]], r6, #19456
+; CHECK: add r0, [[REG]], #536
+; CHECK: bl bar
+define void @foo([20000 x i8]* %addr) {
+ %tmp = alloca [4 x i32], align 32
+ %tmp0 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
+ call void @bar(i32* %tmp0, [20000 x i8]* byval %addr)
+ ret void
+}
+
diff --git a/test/CodeGen/ARM/cmp1-peephole-thumb.mir b/test/CodeGen/ARM/cmp1-peephole-thumb.mir
index 5ace58fd0658..3e87ced0ee57 100644
--- a/test/CodeGen/ARM/cmp1-peephole-thumb.mir
+++ b/test/CodeGen/ARM/cmp1-peephole-thumb.mir
@@ -55,7 +55,6 @@ frameInfo:
# CHECK-NOT: tCMPi8
body: |
bb.0.entry:
- successors: %bb.1.entry(0x40000000), %bb.2.entry(0x40000000)
liveins: %r0, %r1
%1 = COPY %r1
@@ -67,8 +66,6 @@ body: |
tBcc %bb.2.entry, 0, %cpsr
bb.1.entry:
- successors: %bb.2.entry(0x80000000)
-
bb.2.entry:
%5 = PHI %4, %bb.1.entry, %3, %bb.0.entry
diff --git a/test/CodeGen/ARM/cmp2-peephole-thumb.mir b/test/CodeGen/ARM/cmp2-peephole-thumb.mir
index 6e9ca70f1741..a31086d2113e 100644
--- a/test/CodeGen/ARM/cmp2-peephole-thumb.mir
+++ b/test/CodeGen/ARM/cmp2-peephole-thumb.mir
@@ -76,7 +76,6 @@ stack:
# CHECK-NEXT: tCMPi8
body: |
bb.0.entry:
- successors: %bb.1.if.then(0x40000000), %bb.2.if.end(0x40000000)
liveins: %r0, %r1
%1 = COPY %r1
@@ -88,15 +87,11 @@ body: |
tB %bb.1.if.then, 14, _
bb.1.if.then:
- successors: %bb.3.return(0x80000000)
-
%4, %cpsr = tMOVi8 42, 14, _
tSTRspi killed %4, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval)
tB %bb.3.return, 14, _
bb.2.if.end:
- successors: %bb.3.return(0x80000000)
-
%3, %cpsr = tMOVi8 1, 14, _
tSTRspi killed %3, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval)
diff --git a/test/CodeGen/ARM/dbg-range-extension.mir b/test/CodeGen/ARM/dbg-range-extension.mir
index 466f69396948..a79607705c1c 100644
--- a/test/CodeGen/ARM/dbg-range-extension.mir
+++ b/test/CodeGen/ARM/dbg-range-extension.mir
@@ -209,7 +209,6 @@ stack:
- { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '%r4' }
body: |
bb.0.entry:
- successors: %bb.5.if.end, %bb.1.if.then
liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr
%sp = frame-setup STMDB_UPD %sp, 14, _, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
@@ -232,7 +231,6 @@ body: |
Bcc %bb.5.if.end, 0, killed %cpsr
bb.1.if.then:
- successors: %bb.3.for.cond
liveins: %r4, %r5
%r0 = MOVi 12, 14, _, _, debug-location !26
@@ -245,7 +243,6 @@ body: |
B %bb.3.for.cond
bb.2.for.body:
- successors: %bb.3.for.cond
liveins: %r4, %r5, %r6, %r7
%r1 = ADDrr %r5, %r7, 14, _, _, debug-location !36
@@ -255,7 +252,6 @@ body: |
DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
bb.3.for.cond:
- successors: %bb.2.for.body, %bb.4.for.cond.cleanup
liveins: %r4, %r5, %r6, %r7
DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
@@ -263,7 +259,6 @@ body: |
Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33
bb.4.for.cond.cleanup:
- successors: %bb.5.if.end
liveins: %r4, %r5, %r6
%r0 = MOVr %r5, 14, _, _, debug-location !34
diff --git a/test/CodeGen/ARM/sat-arith.ll b/test/CodeGen/ARM/sat-arith.ll
deleted file mode 100644
index 4844ed1bd21e..000000000000
--- a/test/CodeGen/ARM/sat-arith.ll
+++ /dev/null
@@ -1,63 +0,0 @@
-; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s -check-prefix=ARM -check-prefix=CHECK
-; RUN: llc -O1 -mtriple=thumbv7-none-none-eabi %s -o - | FileCheck %s -check-prefix=THUMB -check-prefix=CHECK
-
-; CHECK-LABEL: qadd
-define i32 @qadd() nounwind {
-; CHECK-DAG: mov{{s?}} [[R0:.*]], #8
-; CHECK-DAG: mov{{s?}} [[R1:.*]], #128
-; CHECK-ARM: qadd [[R0]], [[R1]], [[R0]]
-; CHECK-THRUMB: qadd [[R0]], [[R0]], [[R1]]
- %tmp = call i32 @llvm.arm.qadd(i32 128, i32 8)
- ret i32 %tmp
-}
-
-; CHECK-LABEL: qsub
-define i32 @qsub() nounwind {
-; CHECK-DAG: mov{{s?}} [[R0:.*]], #8
-; CHECK-DAG: mov{{s?}} [[R1:.*]], #128
-; CHECK-ARM: qsub [[R0]], [[R1]], [[R0]]
-; CHECK-THRUMB: qadd [[R0]], [[R1]], [[R0]]
- %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
- ret i32 %tmp
-}
-
-; upper-bound of the immediate argument
-; CHECK-LABEL: ssat1
-define i32 @ssat1() nounwind {
-; CHECK: mov{{s?}} [[R0:.*]], #128
-; CHECK: ssat [[R1:.*]], #32, [[R0]]
- %tmp = call i32 @llvm.arm.ssat(i32 128, i32 32)
- ret i32 %tmp
-}
-
-; lower-bound of the immediate argument
-; CHECK-LABEL: ssat2
-define i32 @ssat2() nounwind {
-; CHECK: mov{{s?}} [[R0:.*]], #128
-; CHECK: ssat [[R1:.*]], #1, [[R0]]
- %tmp = call i32 @llvm.arm.ssat(i32 128, i32 1)
- ret i32 %tmp
-}
-
-; upper-bound of the immediate argument
-; CHECK-LABEL: usat1
-define i32 @usat1() nounwind {
-; CHECK: mov{{s?}} [[R0:.*]], #128
-; CHECK: usat [[R1:.*]], #31, [[R0]]
- %tmp = call i32 @llvm.arm.usat(i32 128, i32 31)
- ret i32 %tmp
-}
-
-; lower-bound of the immediate argument
-; CHECK-LABEL: usat2
-define i32 @usat2() nounwind {
-; CHECK: mov{{s?}} [[R0:.*]], #128
-; CHECK: usat [[R1:.*]], #0, [[R0]]
- %tmp = call i32 @llvm.arm.usat(i32 128, i32 0)
- ret i32 %tmp
-}
-
-declare i32 @llvm.arm.qadd(i32, i32) nounwind
-declare i32 @llvm.arm.qsub(i32, i32) nounwind
-declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
-declare i32 @llvm.arm.usat(i32, i32) nounwind readnone
diff --git a/test/CodeGen/ARM/vabs.ll b/test/CodeGen/ARM/vabs.ll
index 38c6d6c28aed..4295b32d25fc 100644
--- a/test/CodeGen/ARM/vabs.ll
+++ b/test/CodeGen/ARM/vabs.ll
@@ -8,6 +8,22 @@ define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
ret <8 x i8> %tmp2
}
+define <8 x i8> @vabss8_fold(<8 x i8>* %A) nounwind {
+; CHECK-LABEL: vabss8_fold:
+; CHECK: vldr d16, .LCPI1_0
+; CHECK: .LCPI1_0:
+; CHECK-NEXT: .byte 128 @ 0x80
+; CHECK-NEXT: .byte 127 @ 0x7f
+; CHECK-NEXT: .byte 1 @ 0x1
+; CHECK-NEXT: .byte 0 @ 0x0
+; CHECK-NEXT: .byte 1 @ 0x1
+; CHECK-NEXT: .byte 127 @ 0x7f
+; CHECK-NEXT: .byte 128 @ 0x80
+; CHECK-NEXT: .byte 1 @ 0x1
+ %tmp1 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> <i8 -128, i8 -127, i8 -1, i8 0, i8 1, i8 127, i8 128, i8 255>)
+ ret <8 x i8> %tmp1
+}
+
define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
;CHECK-LABEL: vabss16:
;CHECK: vabs.s16
@@ -16,6 +32,18 @@ define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
ret <4 x i16> %tmp2
}
+define <4 x i16> @vabss16_fold() nounwind {
+; CHECK-LABEL: vabss16_fold:
+; CHECK: vldr d16, .LCPI3_0
+; CHECK: .LCPI3_0:
+; CHECK-NEXT: .short 32768 @ 0x8000
+; CHECK-NEXT: .short 32767 @ 0x7fff
+; CHECK-NEXT: .short 255 @ 0xff
+; CHECK-NEXT: .short 32768 @ 0x8000
+ %tmp1 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> <i16 -32768, i16 -32767, i16 255, i16 32768>)
+ ret <4 x i16> %tmp1
+}
+
define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
;CHECK-LABEL: vabss32:
;CHECK: vabs.s32
@@ -24,6 +52,16 @@ define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
ret <2 x i32> %tmp2
}
+define <2 x i32> @vabss32_fold() nounwind {
+; CHECK-LABEL: vabss32_fold:
+; CHECK: vldr d16, .LCPI5_0
+; CHECK: .LCPI5_0:
+; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
+; CHECK-NEXT: .long 2147483648 @ 0x80000000
+ %tmp1 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> <i32 -2147483647, i32 2147483648>)
+ ret <2 x i32> %tmp1
+}
+
define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
;CHECK-LABEL: vabsf32:
;CHECK: vabs.f32
diff --git a/test/CodeGen/ARM/xray-armv6-attribute-instrumentation.ll b/test/CodeGen/ARM/xray-armv6-attribute-instrumentation.ll
index 93c3cb14fb73..5e3c45c3454d 100644
--- a/test/CodeGen/ARM/xray-armv6-attribute-instrumentation.ll
+++ b/test/CodeGen/ARM/xray-armv6-attribute-instrumentation.ll
@@ -25,7 +25,13 @@ define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always"
}
; CHECK: .p2align 4
; CHECK-NEXT: .long {{.*}}Lxray_synthetic_0
+; CHECK-NEXT: .long {{.*}}Lxray_fn_idx_synth_0
; CHECK-NEXT: .section {{.*}}xray_instr_map{{.*}}
; CHECK-LABEL: Lxray_synthetic_0:
; CHECK: .long {{.*}}Lxray_sled_0
; CHECK: .long {{.*}}Lxray_sled_1
+; CHECK-LABEL: Lxray_synthetic_end0:
+; CHECK: .section {{.*}}xray_fn_idx{{.*}}
+; CHECK-LABEL: Lxray_fn_idx_synth_0:
+; CHECK: .long {{.*}}Lxray_synthetic_0
+; CHECK-NEXT: .long {{.*}}Lxray_synthetic_end0
diff --git a/test/CodeGen/ARM/xray-armv7-attribute-instrumentation.ll b/test/CodeGen/ARM/xray-armv7-attribute-instrumentation.ll
index d14590b88679..739151fbdd5e 100644
--- a/test/CodeGen/ARM/xray-armv7-attribute-instrumentation.ll
+++ b/test/CodeGen/ARM/xray-armv7-attribute-instrumentation.ll
@@ -25,7 +25,14 @@ define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always"
}
; CHECK: .p2align 4
; CHECK-NEXT: .long {{.*}}Lxray_synthetic_0
+; CHECK-NEXT: .long {{.*}}Lxray_fn_idx_synth_0
; CHECK-NEXT: .section {{.*}}xray_instr_map{{.*}}
; CHECK-LABEL: Lxray_synthetic_0:
; CHECK: .long {{.*}}Lxray_sled_0
; CHECK: .long {{.*}}Lxray_sled_1
+; CHECK-LABEL: Lxray_synthetic_end0:
+; CHECK: .section {{.*}}xray_fn_idx{{.*}}
+; CHECK-LABEL: Lxray_fn_idx_synth_0:
+; CHECK: .long {{.*}}xray_synthetic_0
+; CHECK-NEXT: .long {{.*}}xray_synthetic_end0
+
generated by cgit v1.3 (git 2.53.0) at 2026-09-07 00:59:01 +0000