diff options
Diffstat (limited to 'test/CodeGen/MIR')
182 files changed, 6420 insertions, 706 deletions
diff --git a/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir b/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir new file mode 100644 index 000000000000..cf7572ecad37 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir @@ -0,0 +1,31 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the .cfi_def_cfa operands +# correctly. + +--- | + + declare void @foo() + + define void @trivial_fp_func() { + entry: + call void @foo() + ret void + } + +... +--- +name: trivial_fp_func +body: | + bb.0.entry: + liveins: %lr, %fp, %lr, %fp + + %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2 + %fp = frame-setup ADDXri %sp, 0, 0 + ; CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16 + frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16 + frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8 + frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16 + BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp + %sp, %fp, %lr = LDPXpost %sp, 2 + RET_ReallyLR +... diff --git a/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir b/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir new file mode 100644 index 000000000000..b7bac2682c70 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir @@ -0,0 +1,23 @@ +# RUN: not llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @var_i32 = global i32 42 + @var_i64 = global i64 0 + + define i32 @sub_small() { + entry: + %val32 = load i32, i32* @var_i32 + ret i32 %val32 + } + +... +--- +name: sub_small +body: | + bb.0.entry: + %x8 = ADRP target-flags(aarch64-page) @var_i32 + ; CHECK: [[@LINE+1]]:60: expected the name of the target flag + %w0 = LDRWui killed %x8, target-flags(aarch64-pageoff, ) @var_i32 + RET_ReallyLR implicit %w0 +... diff --git a/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir b/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir new file mode 100644 index 000000000000..d4145b8961df --- /dev/null +++ b/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir @@ -0,0 +1,23 @@ +# RUN: not llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @var_i32 = global i32 42 + @var_i64 = global i64 0 + + define i32 @sub_small() { + entry: + %val32 = load i32, i32* @var_i32 + ret i32 %val32 + } + +... +--- +name: sub_small +body: | + bb.0.entry: + %x8 = ADRP target-flags(aarch64-page) @var_i32 + ; CHECK: [[@LINE+1]]:60: use of undefined target flag 'ncc' + %w0 = LDRWui killed %x8, target-flags(aarch64-pageoff, ncc) @var_i32 + RET_ReallyLR implicit %w0 +... diff --git a/test/CodeGen/MIR/AArch64/lit.local.cfg b/test/CodeGen/MIR/AArch64/lit.local.cfg new file mode 100644 index 000000000000..f4f77c5aa312 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/lit.local.cfg @@ -0,0 +1,8 @@ +import re + +if not 'AArch64' in config.root.targets: + config.unsupported = True + +# For now we don't test arm64-win32. +if re.search(r'cygwin|mingw32|win32|windows-gnu|windows-msvc', config.target_triple): + config.unsupported = True diff --git a/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir b/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir new file mode 100644 index 000000000000..e23a352dff21 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir @@ -0,0 +1,28 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser can parse multiple register machine +# operands before '='. + +--- | + + declare void @foo() + + define void @trivial_fp_func() { + entry: + call void @foo() + ret void + } + +... +--- +name: trivial_fp_func +body: | + bb.0.entry: + liveins: %lr, %fp, %lr, %fp + + %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2 + %fp = frame-setup ADDXri %sp, 0, 0 + BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp + ; CHECK: %sp, %fp, %lr = LDPXpost %sp, 2 + %sp, %fp, %lr = LDPXpost %sp, 2 + RET_ReallyLR +... diff --git a/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir b/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir new file mode 100644 index 000000000000..9471516db647 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir @@ -0,0 +1,41 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s + +--- | + @var = global i64 0 + @local_addr = global i64* null + + define void @stack_local() { + entry: + %local_var = alloca i64 + %val = load i64, i64* @var + store i64 %val, i64* %local_var + store i64* %local_var, i64** @local_addr + ret void + } +... +--- +name: stack_local +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64common } + - { id: 1, class: gpr64 } + - { id: 2, class: gpr64common } + - { id: 3, class: gpr64common } +frameInfo: + maxAlignment: 8 +# CHECK-LABEL: stack_local +# CHECK: stack: +# CHECK_NEXT: { id:0, name:local_var, offset:0, size:8, alignment:8, local-offset: -8 } +stack: + - { id: 0,name: local_var,offset: 0,size: 8,alignment: 8, local-offset: -8 } +body: | + bb.0.entry: + %0 = ADRP @var + %1 = LDRXui killed %0, @var :: (load 8 from @var) + STRXui killed %1, %stack.0.local_var, 0 :: (store 8 into %ir.local_var) + %2 = ADRP @local_addr + %3 = ADDXri %stack.0.local_var, 0, 0 + STRXui killed %3, killed %2, @local_addr :: (store 8 into @local_addr) + RET_ReallyLR +... diff --git a/test/CodeGen/MIR/AArch64/target-flags.mir b/test/CodeGen/MIR/AArch64/target-flags.mir new file mode 100644 index 000000000000..e96fce7c2f2b --- /dev/null +++ b/test/CodeGen/MIR/AArch64/target-flags.mir @@ -0,0 +1,39 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s + +--- | + + @var_i32 = global i32 42 + @var_i64 = global i64 0 + + define void @sub_small() { + entry: + %val32 = load i32, i32* @var_i32 + %newval32 = sub i32 %val32, 4095 + store i32 %newval32, i32* @var_i32 + %val64 = load i64, i64* @var_i64 + %newval64 = sub i64 %val64, 52 + store i64 %newval64, i64* @var_i64 + ret void + } + +... +--- +name: sub_small +body: | + bb.0.entry: + ; CHECK: %x8 = ADRP target-flags(aarch64-page) @var_i32 + ; CHECK-NEXT: %x9 = ADRP target-flags(aarch64-page) @var_i64 + ; CHECK-NEXT: %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 + ; CHECK-NEXT: %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64 + ; CHECK: STRWui killed %w10, killed %x8, target-flags(aarch64-nc) @var_i32 + ; CHECK: STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64 + %x8 = ADRP target-flags(aarch64-page) @var_i32 + %x9 = ADRP target-flags(aarch64-page) @var_i64 + %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 + %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64 + %w10 = SUBWri killed %w10, 4095, 0 + %x11 = SUBXri killed %x11, 52, 0 + STRWui killed %w10, killed %x8, target-flags(aarch64-nc) @var_i32 + STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64 + RET_ReallyLR +... diff --git a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir new file mode 100644 index 000000000000..34793880a60b --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir @@ -0,0 +1,64 @@ +# RUN: not llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + %struct.foo = type { float, [5 x i32] } + + @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 + + define void @float(float addrspace(1)* %out, i32 %index) #0 { + entry: + %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index + %1 = load float, float addrspace(2)* %0 + store float %1, float addrspace(1)* %out + ret void + } + + declare { i1, i64 } @llvm.SI.if(i1) + + declare { i1, i64 } @llvm.SI.else(i64) + + declare i64 @llvm.SI.break(i64) + + declare i64 @llvm.SI.if.break(i1, i64) + + declare i64 @llvm.SI.else.break(i64, i64) + + declare i1 @llvm.SI.loop(i64) + + declare void @llvm.SI.end.cf(i64) + + attributes #0 = { "target-cpu"="SI" } + +... +--- +name: float +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + maxAlignment: 8 +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr2_sgpr3 = S_GETPC_B64 + ; CHECK: [[@LINE+1]]:45: expected the name of the target index + %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc + %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc + %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc + %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 + %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc + %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc + %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc + %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc + %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc + %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc + %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec + BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + S_ENDPGM +... diff --git a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir new file mode 100644 index 000000000000..e20cf376414a --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir @@ -0,0 +1,64 @@ +# RUN: not llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + %struct.foo = type { float, [5 x i32] } + + @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 + + define void @float(float addrspace(1)* %out, i32 %index) #0 { + entry: + %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index + %1 = load float, float addrspace(2)* %0 + store float %1, float addrspace(1)* %out + ret void + } + + declare { i1, i64 } @llvm.SI.if(i1) + + declare { i1, i64 } @llvm.SI.else(i64) + + declare i64 @llvm.SI.break(i64) + + declare i64 @llvm.SI.if.break(i1, i64) + + declare i64 @llvm.SI.else.break(i64, i64) + + declare i1 @llvm.SI.loop(i64) + + declare void @llvm.SI.end.cf(i64) + + attributes #0 = { "target-cpu"="SI" } + +... +--- +name: float +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + maxAlignment: 8 +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr2_sgpr3 = S_GETPC_B64 + ; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start' + %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc + %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc + %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc + %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 + %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc + %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc + %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc + %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc + %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc + %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc + %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec + BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + S_ENDPGM +... diff --git a/test/CodeGen/MIR/AMDGPU/lit.local.cfg b/test/CodeGen/MIR/AMDGPU/lit.local.cfg new file mode 100644 index 000000000000..2a665f06be72 --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'AMDGPU' in config.root.targets: + config.unsupported = True diff --git a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir new file mode 100644 index 000000000000..839fd3212c61 --- /dev/null +++ b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir @@ -0,0 +1,104 @@ +# RUN: llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s | FileCheck %s +# This test verifies that the MIR parser can parse target index operands. + +--- | + + %struct.foo = type { float, [5 x i32] } + + @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 + + define void @float(float addrspace(1)* %out, i32 %index) #0 { + entry: + %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index + %1 = load float, float addrspace(2)* %0 + store float %1, float addrspace(1)* %out + ret void + } + + define void @float2(float addrspace(1)* %out, i32 %index) #0 { + entry: + %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index + %1 = load float, float addrspace(2)* %0 + store float %1, float addrspace(1)* %out + ret void + } + + declare { i1, i64 } @llvm.SI.if(i1) + + declare { i1, i64 } @llvm.SI.else(i64) + + declare i64 @llvm.SI.break(i64) + + declare i64 @llvm.SI.if.break(i1, i64) + + declare i64 @llvm.SI.else.break(i64, i64) + + declare i1 @llvm.SI.loop(i64) + + declare void @llvm.SI.end.cf(i64) + + attributes #0 = { "target-cpu"="SI" } + +... +--- +name: float +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + maxAlignment: 8 +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr2_sgpr3 = S_GETPC_B64 + ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc + %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc + %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc + %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc + %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 + %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc + %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc + %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc + %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc + %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc + %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc + %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec + BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + S_ENDPGM +... +--- +name: float2 +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + maxAlignment: 8 +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr2_sgpr3 = S_GETPC_B64 + ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc + %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc + %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc + %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc + %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 + %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc + %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc + %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc + %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc + %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc + %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc + %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec + BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + S_ENDPGM +... diff --git a/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir b/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir new file mode 100644 index 000000000000..e351713dc290 --- /dev/null +++ b/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir @@ -0,0 +1,165 @@ +# RUN: llc -start-after machine-cp -stop-after=if-converter -mtriple=thumbv7 %s -o /dev/null 2>&1 | FileCheck %s +--- | + ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' + target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv7" + + %struct.s = type opaque + + ; Function Attrs: nounwind + define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 { + entry: + tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !18, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !19, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !20, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28 + %cmp = icmp ult i32 %n, 4, !dbg !29 + br i1 %cmp, label %return, label %if.end, !dbg !31 + + if.end: ; preds = %entry + tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32 + br label %return, !dbg !33 + + return: ; preds = %if.end, %entry + %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] + ret i32 %retval.0, !dbg !34 + } + + declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 + + ; Function Attrs: nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 + + attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #2 = { nounwind readnone } + attributes #3 = { nounwind } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!22, !23, !24, !25} + !llvm.ident = !{!26} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") + !2 = !{} + !3 = !{!4} + !4 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, variables: !17) + !5 = !DISubroutineType(types: !6) + !6 = !{!7, !8, !11, !12, !16} + !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 32, align: 32) + !9 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !1, line: 5, baseType: !10) + !10 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !1, line: 5, flags: DIFlagFwdDecl) + !11 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) + !12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 32, align: 32) + !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14) + !14 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !1, line: 2, baseType: !15) + !15 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) + !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !1, line: 3, baseType: !11) + !17 = !{!18, !19, !20, !21} + !18 = !DILocalVariable(name: "s", arg: 1, scope: !4, file: !1, line: 9, type: !8) + !19 = !DILocalVariable(name: "u", arg: 2, scope: !4, file: !1, line: 9, type: !11) + !20 = !DILocalVariable(name: "b", arg: 3, scope: !4, file: !1, line: 9, type: !12) + !21 = !DILocalVariable(name: "n", arg: 4, scope: !4, file: !1, line: 9, type: !16) + !22 = !{i32 2, !"Dwarf Version", i32 4} + !23 = !{i32 2, !"Debug Info Version", i32 3} + !24 = !{i32 1, !"wchar_size", i32 4} + !25 = !{i32 1, !"min_enum_size", i32 4} + !26 = !{!"clang version 3.7.0 (llvm/trunk 237059)"} + !27 = !DIExpression() + !28 = !DILocation(line: 9, scope: !4) + !29 = !DILocation(line: 10, scope: !30) + !30 = distinct !DILexicalBlock(scope: !4, file: !1, line: 10) + !31 = !DILocation(line: 10, scope: !4) + !32 = !DILocation(line: 13, scope: !4) + !33 = !DILocation(line: 14, scope: !4) + !34 = !DILocation(line: 15, scope: !4) + +... +--- +name: f +alignment: 1 +exposesReturnsTwice: false +hasInlineAsm: false +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: false +liveins: + - { reg: '%r0' } + - { reg: '%r2' } + - { reg: '%r3' } +calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', + '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', + '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', + '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', + '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', + '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', + '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', + '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', + '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', + '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', + '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', + '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', + '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', + '%d11_d12_d13_d14' ] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 8 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '%bb.2.if.end' + restorePoint: '%bb.2.if.end' +stack: + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } + - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } +body: | + bb.0.entry: + successors: %bb.1, %bb.2.if.end + liveins: %r0, %r2, %r3, %lr, %r7 + + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 + t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 + t2Bcc %bb.2.if.end, 2, killed %cpsr + + bb.1: + liveins: %lr, %r7 + + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + %r0 = t2MOVi -1, 14, _, _ + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + tBX_RET 14, _, implicit %r0, debug-location !34 + + bb.2.if.end: + liveins: %r0, %r2, %r3, %r7, %lr + + %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr + frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8 + frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4 + frame-setup CFI_INSTRUCTION .cfi_offset %r7, -8 + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 + %r1 = COPY killed %r2, debug-location !32 + %r2 = COPY killed %r3, debug-location !32 + tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 + %r0 = t2MOVi 0, 14, _, _ + %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + tBX_RET 14, _, implicit %r0, debug-location !34 +# Verify that the DBG_VALUE is ignored. +# CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 + +... diff --git a/test/CodeGen/MIR/ARM/bundled-instructions.mir b/test/CodeGen/MIR/ARM/bundled-instructions.mir new file mode 100644 index 000000000000..814c4e188ea5 --- /dev/null +++ b/test/CodeGen/MIR/ARM/bundled-instructions.mir @@ -0,0 +1,75 @@ +# RUN: llc -mtriple thumbv7-apple-ios -start-after block-placement -stop-after block-placement -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the bundled machine instructions +# and 'internal' register flags correctly. + +--- | + + define i32 @test1(i32 %a) { + entry: + %cmp = icmp sgt i32 %a, -78 + %. = zext i1 %cmp to i32 + ret i32 %. + } + + define i32 @test2(i32 %a) { + entry: + %cmp = icmp sgt i32 %a, -78 + %. = zext i1 %cmp to i32 + ret i32 %. + } + +... +--- +name: test1 +tracksRegLiveness: true +liveins: + - { reg: '%r0' } +body: | + bb.0.entry: + liveins: %r0 + ; CHECK-LABEL: name: test1 + ; CHECK: %r1 = t2MOVi 0, 14, _, _ + ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr + ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { + ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate + ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate + ; CHECK-NEXT: } + ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, _ + ; CHECK-NEXT: tBX_RET 14, _, implicit killed %r0 + %r1 = t2MOVi 0, 14, _, _ + t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr + BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { + t2IT 12, 8, implicit-def %itstate + %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate + } + %r0 = tMOVr killed %r1, 14, _ + tBX_RET 14, _, implicit killed %r0 +... +--- +name: test2 +tracksRegLiveness: true +liveins: + - { reg: '%r0' } +body: | + bb.0.entry: + liveins: %r0 + + ; Verify that the next machine instruction can be on the same line as + ; '{' or '}'. + + ; CHECK-LABEL: name: test2 + ; CHECK: %r1 = t2MOVi 0, 14, _, _ + ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr + ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { + ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate + ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate + ; CHECK-NEXT: } + ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, _ + ; CHECK-NEXT: tBX_RET 14, _, implicit killed %r0 + %r1 = t2MOVi 0, 14, _, _ + t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr + BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { t2IT 12, 8, implicit-def %itstate + %r1 = t2MOVi 1, 12, killed %cpsr, _, internal implicit killed %itstate + } %r0 = tMOVr killed %r1, 14, _ + tBX_RET 14, _, implicit killed %r0 +... diff --git a/test/CodeGen/MIR/ARM/cfi-same-value.mir b/test/CodeGen/MIR/ARM/cfi-same-value.mir new file mode 100644 index 000000000000..f9850abe0463 --- /dev/null +++ b/test/CodeGen/MIR/ARM/cfi-same-value.mir @@ -0,0 +1,80 @@ +# RUN: llc -mtriple=arm-linux-unknown-gnueabi -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s + +--- | + declare void @dummy_use(i32*, i32) + + define void @test_basic() #0 { + entry: + %mem = alloca i32, i32 10 + call void @dummy_use(i32* %mem, i32 10) + ret void + } + + attributes #0 = { "split-stack" } +... +--- +name: test_basic +tracksRegLiveness: true +frameInfo: + stackSize: 48 + maxAlignment: 4 + adjustsStack: true + hasCalls: true +stack: + - { id: 0, name: mem, offset: -48, size: 40, alignment: 4 } + - { id: 1, type: spill-slot, offset: -4, size: 4, alignment: 4, + callee-saved-register: '%lr' } + - { id: 2, type: spill-slot, offset: -8, size: 4, alignment: 4, + callee-saved-register: '%r11' } +body: | + bb.0: + successors: %bb.2, %bb.1 + liveins: %r11, %lr + + %sp = STMDB_UPD %sp, 14, _, %r4, %r5 + CFI_INSTRUCTION .cfi_def_cfa_offset 8 + CFI_INSTRUCTION .cfi_offset %r5, -4 + CFI_INSTRUCTION .cfi_offset %r4, -8 + %r5 = MOVr %sp, 14, _, _ + %r4 = MRC 15, 0, 13, 0, 3, 14, _ + %r4 = LDRi12 %r4, 4, 14, _ + CMPrr %r4, %r5, 14, _, implicit-def %cpsr + Bcc %bb.2, 3, %cpsr + + bb.1: + successors: %bb.2 + liveins: %r11, %lr + + %r4 = MOVi 48, 14, _, _ + %r5 = MOVi 0, 14, _, _ + %sp = STMDB_UPD %sp, 14, _, %lr + CFI_INSTRUCTION .cfi_def_cfa_offset 12 + CFI_INSTRUCTION .cfi_offset %lr, -12 + BL $__morestack, implicit-def %lr, implicit %sp + %sp = LDMIA_UPD %sp, 14, _, %lr + %sp = LDMIA_UPD %sp, 14, _, %r4, %r5 + CFI_INSTRUCTION .cfi_def_cfa_offset 0 + BX_RET 14, _ + + bb.2: + liveins: %r11, %lr + + %sp = LDMIA_UPD %sp, 14, _, %r4, %r5 + CFI_INSTRUCTION .cfi_def_cfa_offset 0 + ; CHECK: CFI_INSTRUCTION .cfi_same_value %r4 + ; CHECK-NEXT: CFI_INSTRUCTION .cfi_same_value %r5 + CFI_INSTRUCTION .cfi_same_value %r4 + CFI_INSTRUCTION .cfi_same_value %r5 + %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r11, killed %lr + frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8 + frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4 + frame-setup CFI_INSTRUCTION .cfi_offset %r11, -8 + %sp = frame-setup SUBri killed %sp, 40, 14, _, _ + frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 48 + %r0 = MOVr %sp, 14, _, _ + %r1 = MOVi 10, 14, _, _ + BL @dummy_use, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit killed %r1, implicit-def %sp + %sp = ADDri killed %sp, 40, 14, _, _ + %sp = LDMIA_UPD %sp, 14, _, %r4, %r5 + MOVPCLR 14, _ +... diff --git a/test/CodeGen/MIR/ARM/expected-closing-brace.mir b/test/CodeGen/MIR/ARM/expected-closing-brace.mir new file mode 100644 index 000000000000..78d91aead247 --- /dev/null +++ b/test/CodeGen/MIR/ARM/expected-closing-brace.mir @@ -0,0 +1,50 @@ +# RUN: not llc -mtriple thumbv7-apple-ios -start-after block-placement -stop-after block-placement -o /dev/null %s 2>&1 | FileCheck %s + +--- | + @G = external global i32 + + define i32 @test1(i32 %a) { + entry: + br label %foo + + foo: + %cmp = icmp sgt i32 %a, -78 + %. = zext i1 %cmp to i32 + br i1 %cmp, label %if.then, label %if.else + + if.then: + ret i32 %. + + if.else: + %b = load i32, i32* @G + %c = add i32 %b, 1 + br label %foo + } +... +--- +name: test1 +tracksRegLiveness: true +liveins: + - { reg: '%r0' } +body: | + bb.0.entry: + successors: %bb.1.foo + liveins: %r0 + bb.1.foo: + successors: %bb.2.if.then, %bb.1.foo + liveins: %r0 + + t2CMNri %r0, 78, 14, _, implicit-def %cpsr + %r1 = t2MOVi 0, 14, _, _ + BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { + t2IT 12, 8, implicit-def %itstate + %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit killed %itstate + t2CMNri %r0, 77, 14, _, implicit-def %cpsr + t2Bcc %bb.1.foo, 11, killed %cpsr + ; CHECK: [[@LINE+1]]:3: expected '}' + bb.2.if.then: + liveins: %r1 + + %r0 = tMOVr killed %r1, 14, _ + tBX_RET 14, _, implicit killed %r0 +... diff --git a/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir b/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir new file mode 100644 index 000000000000..a069dd307936 --- /dev/null +++ b/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir @@ -0,0 +1,20 @@ +# RUN: not llc -mtriple thumbv7-apple-ios -start-after block-placement -stop-after block-placement -o /dev/null %s 2>&1 | FileCheck %s + +--- | + define i32 @test1(i32 %a) { + entry: + ret i32 %a + } +... +--- +name: test1 +tracksRegLiveness: true +liveins: + - { reg: '%r0' } +body: | + bb.0.entry: + liveins: %r0 + tBX_RET 14, _, implicit killed %r0 + ; CHECK: [[@LINE+1]]:5: extraneous closing brace ('}') + } +... diff --git a/test/CodeGen/MIR/ARM/lit.local.cfg b/test/CodeGen/MIR/ARM/lit.local.cfg new file mode 100644 index 000000000000..236e1d344166 --- /dev/null +++ b/test/CodeGen/MIR/ARM/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'ARM' in config.root.targets: + config.unsupported = True diff --git a/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir b/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir new file mode 100644 index 000000000000..b93697857e79 --- /dev/null +++ b/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir @@ -0,0 +1,30 @@ +# RUN: not llc -mtriple thumbv7-apple-ios -start-after block-placement -stop-after block-placement -o /dev/null %s 2>&1 | FileCheck %s + +--- | + define i32 @test1(i32 %a) { + entry: + %cmp = icmp sgt i32 %a, -78 + %. = zext i1 %cmp to i32 + ret i32 %. + } +... +--- +name: test1 +tracksRegLiveness: true +liveins: + - { reg: '%r0' } +body: | + bb.0.entry: + liveins: %r0 + %r1 = t2MOVi 0, 14, _, _ + t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr + BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { + t2IT 12, 8, implicit-def %itstate + %r1 = t2MOVi 1, 12, killed %cpsr, _ + ; CHECK: [[@LINE+1]]:14: nested instruction bundles are not allowed + BUNDLE { + } + } + %r0 = tMOVr killed %r1, 14, _ + tBX_RET 14, _, implicit killed %r0 +... diff --git a/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir new file mode 100644 index 000000000000..5b5750b8d1e8 --- /dev/null +++ b/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -0,0 +1,160 @@ +# RUN: llc -mtriple thumbv7 -start-after if-converter -print-before=post-RA-sched -print-after=post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s +--- | + ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' + target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv7" + + %struct.s = type opaque + + ; Function Attrs: nounwind + define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 { + entry: + tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !18, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !19, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !20, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28 + %cmp = icmp ult i32 %n, 4, !dbg !29 + br i1 %cmp, label %return, label %if.end, !dbg !31 + + if.end: ; preds = %entry + tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32 + br label %return, !dbg !33 + + return: ; preds = %if.end, %entry + %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] + ret i32 %retval.0, !dbg !34 + } + + ; NOTE: This is checking that the register in the DEBUG_VALUE node is not + ; accidentally being marked as KILL. The DBG_VALUE node gets introduced in + ; If-Conversion, and gets bundled into the IT block. The Post RA Scheduler + ; attempts to schedule the Machine Instr, and tries to tag the register in the + ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or + ; hopefully, triggering an assert). + + ; CHECK: BUNDLE %ITSTATE<imp-def,dead> + ; CHECK: * DBG_VALUE %R1, %noreg, !"u" + ; CHECK-NOT: * DBG_VALUE %R1<kill>, %noreg, !"u" + + declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 + + ; Function Attrs: nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 + + attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #2 = { nounwind readnone } + attributes #3 = { nounwind } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!22, !23, !24, !25} + !llvm.ident = !{!26} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm") + !2 = !{} + !3 = !{!4} + !4 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, variables: !17) + !5 = !DISubroutineType(types: !6) + !6 = !{!7, !8, !11, !12, !16} + !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 32, align: 32) + !9 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !1, line: 5, baseType: !10) + !10 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !1, line: 5, flags: DIFlagFwdDecl) + !11 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) + !12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 32, align: 32) + !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14) + !14 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !1, line: 2, baseType: !15) + !15 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) + !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !1, line: 3, baseType: !11) + !17 = !{!18, !19, !20, !21} + !18 = !DILocalVariable(name: "s", arg: 1, scope: !4, file: !1, line: 9, type: !8) + !19 = !DILocalVariable(name: "u", arg: 2, scope: !4, file: !1, line: 9, type: !11) + !20 = !DILocalVariable(name: "b", arg: 3, scope: !4, file: !1, line: 9, type: !12) + !21 = !DILocalVariable(name: "n", arg: 4, scope: !4, file: !1, line: 9, type: !16) + !22 = !{i32 2, !"Dwarf Version", i32 4} + !23 = !{i32 2, !"Debug Info Version", i32 3} + !24 = !{i32 1, !"wchar_size", i32 4} + !25 = !{i32 1, !"min_enum_size", i32 4} + !26 = !{!"clang version 3.7.0 (llvm/trunk 237059)"} + !27 = !DIExpression() + !28 = !DILocation(line: 9, scope: !4) + !29 = !DILocation(line: 10, scope: !30) + !30 = distinct !DILexicalBlock(scope: !4, file: !1, line: 10) + !31 = !DILocation(line: 10, scope: !4) + !32 = !DILocation(line: 13, scope: !4) + !33 = !DILocation(line: 14, scope: !4) + !34 = !DILocation(line: 15, scope: !4) + +... +--- +name: f +alignment: 1 +exposesReturnsTwice: false +hasInlineAsm: false +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: false +liveins: + - { reg: '%r0' } + - { reg: '%r2' } + - { reg: '%r3' } +calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', + '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', + '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', + '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', + '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', + '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', + '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', + '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', + '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', + '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', + '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', + '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', + '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', + '%d11_d12_d13_d14' ] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 8 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +stack: + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } + - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } +body: | + bb.0.entry: + liveins: %r0, %r2, %r3, %lr, %r7 + + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 + t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + %r0 = t2MOVi -1, 3, %cpsr, _, implicit undef %r0 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + tBX_RET 3, %cpsr, implicit %r0, debug-location !34 + %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr + frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8 + frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4 + frame-setup CFI_INSTRUCTION .cfi_offset %r7, -8 + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 + %r1 = tMOVr killed %r2, 14, _, debug-location !32 + %r2 = tMOVr killed %r3, 14, _, debug-location !32 + tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 + %r0 = t2MOVi 0, 14, _, _ + %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 + +... diff --git a/test/CodeGen/MIR/Generic/basic-blocks.mir b/test/CodeGen/MIR/Generic/basic-blocks.mir new file mode 100644 index 000000000000..22f8d28290db --- /dev/null +++ b/test/CodeGen/MIR/Generic/basic-blocks.mir @@ -0,0 +1,49 @@ +# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses machine functions correctly. + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + + define i32 @bar() { + start: + ret i32 0 + } + + define i32 @test() { + start: + ret i32 0 + } + +... +--- +# CHECK-LABEL: name: foo +# CHECK: body: +# CHECK-NEXT: bb.0.entry: +name: foo +body: | + bb.0.entry: +... +--- +# CHECK-LABEL: name: bar +# CHECK: body: +# CHECK-NEXT: bb.0.start (align 4): +# CHECK: bb.1 (address-taken): +name: bar +body: | + bb.0.start (align 4): + bb.1 (address-taken): +... +--- +# CHECK-LABEL: name: test +# CHECK: body: +# CHECK-NEXT: bb.0.start (address-taken, align 4): +# CHECK: bb.1 (address-taken, align 4): +name: test +body: | + bb.0.start (align 4, address-taken): + bb.1 (address-taken, align 4): +... diff --git a/test/CodeGen/MIR/machine-basic-block-redefinition-error.mir b/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir index deac3b0b69bf..892258666d10 100644 --- a/test/CodeGen/MIR/machine-basic-block-redefinition-error.mir +++ b/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir @@ -10,8 +10,7 @@ ... --- name: foo -body: - # CHECK: redefinition of machine basic block with id #0 - - id: 0 - - id: 0 +body: | + ; CHECK: [[@LINE+1]]:13: expected ':' + bb.0.entry ... diff --git a/test/CodeGen/MIR/expected-mbb-reference-for-successor-mbb.mir b/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir index ce9192901d7d..a5e04f86c6d1 100644 --- a/test/CodeGen/MIR/expected-mbb-reference-for-successor-mbb.mir +++ b/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir @@ -17,13 +17,12 @@ ... --- name: foo -body: - - id: 0 - name: entry - # CHECK: [[@LINE+1]]:35: expected a machine basic block reference - successors: [ '%bb.1.less', '2' ] - - id: 1 - name: less - - id: 2 - name: exit +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:29: expected a machine basic block reference + successors: %bb.1.less, 2 + + bb.1.less: + + bb.2.exit: ... diff --git a/test/CodeGen/MIR/frame-info.mir b/test/CodeGen/MIR/Generic/frame-info.mir index c5468f94f33a..6e4e3955cb17 100644 --- a/test/CodeGen/MIR/frame-info.mir +++ b/test/CodeGen/MIR/Generic/frame-info.mir @@ -44,9 +44,8 @@ tracksRegLiveness: true # CHECK: body frameInfo: maxAlignment: 4 -body: - - id: 0 - name: entry +body: | + bb.0.entry: ... --- name: test2 @@ -84,8 +83,7 @@ frameInfo: hasOpaqueSPAdjustment: true hasVAStart: true hasMustTailInVarArgFunc: true -body: - - id: 0 - name: entry +body: | + bb.0.entry: ... diff --git a/test/CodeGen/MIR/function-missing-machine-function.mir b/test/CodeGen/MIR/Generic/function-missing-machine-function.mir index 71b5b2845340..71b5b2845340 100644 --- a/test/CodeGen/MIR/function-missing-machine-function.mir +++ b/test/CodeGen/MIR/Generic/function-missing-machine-function.mir diff --git a/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir b/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir new file mode 100644 index 000000000000..576de4bd9dc7 --- /dev/null +++ b/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir @@ -0,0 +1,53 @@ +# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test_jumptable(i32 %in) { + entry: + switch i32 %in, label %def [ + i32 0, label %lbl1 + i32 1, label %lbl2 + i32 2, label %lbl3 + i32 3, label %lbl4 + ] + + def: + ret i32 0 + + lbl1: + ret i32 1 + + lbl2: + ret i32 2 + + lbl3: + ret i32 4 + + lbl4: + ret i32 8 + } + +... +--- +name: test_jumptable +jumpTable: + # CHECK: [[@LINE+1]]:18: unknown enumerated scalar + kind: switch + entries: + - id: 0 + blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +body: | + bb.0.entry: + + bb.1.entry: + + bb.2.def: + + bb.3.lbl1: + + bb.4.lbl2: + + bb.5.lbl3: + + bb.6.lbl4: +... diff --git a/test/CodeGen/MIR/Generic/lit.local.cfg b/test/CodeGen/MIR/Generic/lit.local.cfg new file mode 100644 index 000000000000..f3f03bd7047e --- /dev/null +++ b/test/CodeGen/MIR/Generic/lit.local.cfg @@ -0,0 +1,3 @@ +if 'native' not in config.available_features: + config.unsupported = True + diff --git a/test/CodeGen/MIR/llvm-ir-error-reported.mir b/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir index 3508c341c44d..3508c341c44d 100644 --- a/test/CodeGen/MIR/llvm-ir-error-reported.mir +++ b/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir diff --git a/test/CodeGen/MIR/llvmIR.mir b/test/CodeGen/MIR/Generic/llvmIR.mir index 3c084ad7d393..c7a220afa505 100644 --- a/test/CodeGen/MIR/llvmIR.mir +++ b/test/CodeGen/MIR/Generic/llvmIR.mir @@ -32,6 +32,6 @@ ... --- name: foo -body: - - id: 0 +body: | + bb.0: ... diff --git a/test/CodeGen/MIR/llvmIRMissing.mir b/test/CodeGen/MIR/Generic/llvmIRMissing.mir index 80cea5a6fdaa..afa96010f297 100644 --- a/test/CodeGen/MIR/llvmIRMissing.mir +++ b/test/CodeGen/MIR/Generic/llvmIRMissing.mir @@ -4,6 +4,6 @@ --- # CHECK: name: foo name: foo -body: - - id: 0 +body: | + bb.0: ... diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir b/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir new file mode 100644 index 000000000000..d6ecd5dc8514 --- /dev/null +++ b/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir @@ -0,0 +1,17 @@ +# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser preserves unnamed LLVM IR block +# references. + +--- | + + define i32 @foo() { + ret i32 0 + } + +... +--- +name: foo +body: | + ; CHECK: bb.0 (%ir-block.0): + bb.0 (%ir-block.0): +... diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir b/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir new file mode 100644 index 000000000000..41747535c351 --- /dev/null +++ b/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir @@ -0,0 +1,18 @@ +# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + +... +--- +name: foo +body: | + ; CHECK: [[@LINE+3]]:3: redefinition of machine basic block with id #0 + bb.0: + + bb.0: +... diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir b/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir new file mode 100644 index 000000000000..df559f852ec0 --- /dev/null +++ b/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir @@ -0,0 +1,15 @@ +# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo() { + ret i32 0 + } + +... +--- +name: foo +body: | + ; CHECK: [[@LINE+1]]:9: use of undefined IR block '%ir-block.10' + bb.0 (%ir-block.10): +... diff --git a/test/CodeGen/MIR/machine-basic-block-unknown-name.mir b/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir index df8eee9d2708..876947b868b0 100644 --- a/test/CodeGen/MIR/machine-basic-block-unknown-name.mir +++ b/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir @@ -12,8 +12,7 @@ ... --- name: foo -body: - # CHECK: [[@LINE+2]]:18: basic block 'entrie' is not defined in the function 'foo' - - id: 0 - name: entrie +body: | + ; CHECK: [[@LINE+1]]:3: basic block 'entrie' is not defined in the function 'foo' + bb.0.entrie: ... diff --git a/test/CodeGen/MIR/machine-function-missing-body-error.mir b/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir index 0dc7477f6275..0dc7477f6275 100644 --- a/test/CodeGen/MIR/machine-function-missing-body-error.mir +++ b/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir diff --git a/test/CodeGen/MIR/machine-function-missing-function.mir b/test/CodeGen/MIR/Generic/machine-function-missing-function.mir index 424c34aae847..6800f8724324 100644 --- a/test/CodeGen/MIR/machine-function-missing-function.mir +++ b/test/CodeGen/MIR/Generic/machine-function-missing-function.mir @@ -12,12 +12,12 @@ ... --- name: foo -body: - - id: 0 +body: | + bb.0: ... --- # CHECK: function 'faa' isn't defined in the provided LLVM IR name: faa -body: - - id: 0 +body: | + bb.0: ... diff --git a/test/CodeGen/MIR/machine-function-missing-name.mir b/test/CodeGen/MIR/Generic/machine-function-missing-name.mir index a868a65d35f2..f65b77880e97 100644 --- a/test/CodeGen/MIR/machine-function-missing-name.mir +++ b/test/CodeGen/MIR/Generic/machine-function-missing-name.mir @@ -16,11 +16,11 @@ --- # CHECK: [[@LINE+1]]:1: missing required key 'name' nme: foo -body: - - id: 0 +body: | + bb.0: ... --- name: bar -body: - - id: 0 +body: | + bb.0: ... diff --git a/test/CodeGen/MIR/machine-function-redefinition-error.mir b/test/CodeGen/MIR/Generic/machine-function-redefinition-error.mir index be84161b5630..be84161b5630 100644 --- a/test/CodeGen/MIR/machine-function-redefinition-error.mir +++ b/test/CodeGen/MIR/Generic/machine-function-redefinition-error.mir diff --git a/test/CodeGen/MIR/machine-function.mir b/test/CodeGen/MIR/Generic/machine-function.mir index afd10ab02c26..1c4ca3d07d2a 100644 --- a/test/CodeGen/MIR/machine-function.mir +++ b/test/CodeGen/MIR/Generic/machine-function.mir @@ -27,8 +27,8 @@ # CHECK-NEXT: hasInlineAsm: false # CHECK: ... name: foo -body: - - id: 0 +body: | + bb.0: ... --- # CHECK: name: bar @@ -37,8 +37,8 @@ body: # CHECK-NEXT: hasInlineAsm: false # CHECK: ... name: bar -body: - - id: 0 +body: | + bb.0: ... --- # CHECK: name: func @@ -48,8 +48,8 @@ body: # CHECK: ... name: func alignment: 8 -body: - - id: 0 +body: | + bb.0: ... --- # CHECK: name: func2 @@ -61,6 +61,6 @@ name: func2 alignment: 16 exposesReturnsTwice: true hasInlineAsm: true -body: - - id: 0 +body: | + bb.0: ... diff --git a/test/CodeGen/MIR/register-info.mir b/test/CodeGen/MIR/Generic/register-info.mir index 9585faa96223..229cf0f9130f 100644 --- a/test/CodeGen/MIR/register-info.mir +++ b/test/CodeGen/MIR/Generic/register-info.mir @@ -22,8 +22,8 @@ # CHECK-NEXT: tracksSubRegLiveness: false # CHECK: ... name: foo -body: - - id: 0 +body: | + bb.0: ... --- # CHECK: name: bar @@ -35,6 +35,6 @@ name: bar isSSA: false tracksRegLiveness: true tracksSubRegLiveness: true -body: - - id: 0 +body: | + bb.0: ... diff --git a/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir b/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir new file mode 100644 index 000000000000..ea94c9906557 --- /dev/null +++ b/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir @@ -0,0 +1,41 @@ +# RUN: not llc -march=mipsel -mattr=mips16 -relocation-model=pic -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +--- | + define i32 @test(i32 %a) { + entry: + %call = call i32 @foo(i32 %a) + ret i32 0 + } + + declare i32 @foo(i32) +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%a0' } +frameInfo: + stackSize: 24 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 16 +stack: + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, + callee-saved-register: '%ra' } +body: | + bb.0.entry: + liveins: %a0, %ra + + Save16 %ra, 24, implicit-def %sp, implicit %sp + %v0, %v1 = GotPrologue16 $_gp_disp, $_gp_disp + %v0 = SllX16 killed %v0, 16 + %v0 = AdduRxRyRz16 killed %v1, killed %v0 + ; CHECK: [[@LINE+1]]:67: expected a global value or an external symbol after 'call-entry' + %v1 = LwRxRyOffMemX16 %v0, @foo, 0 :: (load 4 from call-entry foo) + %t9 = COPY %v1 + %gp = COPY killed %v0 + JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit killed %t9, implicit %a0, implicit killed %gp, implicit-def %sp, implicit-def dead %v0 + %v0 = LiRxImmX16 0 + %ra = Restore16 24, implicit-def %sp, implicit %sp + RetRA16 implicit %v0 +... diff --git a/test/CodeGen/MIR/Mips/lit.local.cfg b/test/CodeGen/MIR/Mips/lit.local.cfg new file mode 100644 index 000000000000..7d12f7a9c564 --- /dev/null +++ b/test/CodeGen/MIR/Mips/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'Mips' in config.root.targets: + config.unsupported = True diff --git a/test/CodeGen/MIR/Mips/memory-operands.mir b/test/CodeGen/MIR/Mips/memory-operands.mir new file mode 100644 index 000000000000..d4206b067f7e --- /dev/null +++ b/test/CodeGen/MIR/Mips/memory-operands.mir @@ -0,0 +1,102 @@ +# RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the call entry pseudo source +# values in memory operands correctly. + +--- | + define i32 @test(i32 %a) { + entry: + %call = call i32 @foo(i32 %a) + ret i32 0 + } + + declare i32 @foo(i32) + + define float @test2() #0 { + entry: + %call = tail call float bitcast (float (...)* @g to float ()*)() + call void @__mips16_ret_sf(float %call) + ret float %call + } + + declare float @g(...) + + declare void @__mips16_ret_sf(float) #1 + + attributes #0 = { "saveS2" } + attributes #1 = { noinline readnone "__Mips16RetHelper" } +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%a0' } +frameInfo: + stackSize: 24 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 16 +stack: + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, + callee-saved-register: '%ra' } +body: | + bb.0.entry: + liveins: %a0, %ra + + Save16 %ra, 24, implicit-def %sp, implicit %sp + CFI_INSTRUCTION .cfi_def_cfa_offset 24 + CFI_INSTRUCTION .cfi_offset %ra_64, -4 + %v0, %v1 = GotPrologue16 $_gp_disp, $_gp_disp + %v0 = SllX16 killed %v0, 16 + %v0 = AdduRxRyRz16 killed %v1, killed %v0 + ; CHECK-LABEL: name: test + ; CHECK: %v1 = LwRxRyOffMemX16 %v0, @foo, 0 :: (load 4 from call-entry @foo) + %v1 = LwRxRyOffMemX16 %v0, @foo, 0 :: (load 4 from call-entry @foo) + %t9 = COPY %v1 + %gp = COPY killed %v0 + JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit killed %t9, implicit %a0, implicit killed %gp, implicit-def %sp, implicit-def dead %v0 + %v0 = LiRxImmX16 0 + %ra = Restore16 24, implicit-def %sp, implicit %sp + RetRA16 implicit %v0 +... +--- +name: test2 +tracksRegLiveness: true +frameInfo: + stackSize: 32 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 16 +stack: + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, + callee-saved-register: '%ra' } + - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, + callee-saved-register: '%s2' } + - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, + callee-saved-register: '%s0' } +body: | + bb.0.entry: + liveins: %ra, %s2, %s0, %ra, %s2, %s0 + + SaveX16 %s0, %ra, %s2, 32, implicit-def %sp, implicit %sp + CFI_INSTRUCTION .cfi_def_cfa_offset 32 + CFI_INSTRUCTION .cfi_offset %ra_64, -4 + CFI_INSTRUCTION .cfi_offset %s2_64, -8 + CFI_INSTRUCTION .cfi_offset %s0_64, -12 + %v0, %v1 = GotPrologue16 $_gp_disp, $_gp_disp + %v0 = SllX16 killed %v0, 16 + %s0 = AdduRxRyRz16 killed %v1, killed %v0 + %v0 = LwRxRyOffMemX16 %s0, @g, 0 :: (load 4 from call-entry @g) + ; CHECK-LABEL: test2 + ; CHECK: %v1 = LwRxRyOffMemX16 %s0, $__mips16_call_stub_sf_0, 0 :: (load 4 from call-entry $__mips16_call_stub_sf_0) + %v1 = LwRxRyOffMemX16 %s0, $__mips16_call_stub_sf_0, 0 :: (load 4 from call-entry $__mips16_call_stub_sf_0) + %gp = COPY %s0 + JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit %v0, implicit killed %gp, implicit-def %sp, implicit-def %v0 + %v1 = LwRxRyOffMemX16 %s0, @__mips16_ret_sf, 0 :: (load 4 from call-entry @__mips16_ret_sf) + %t9 = COPY %v1 + %gp = COPY killed %s0 + JumpLinkReg16 killed %v1, csr_mips16rethelper, implicit-def %ra, implicit killed %t9, implicit %v0, implicit killed %gp, implicit-def %sp + %s0, %ra, %s2 = RestoreX16 32, implicit-def %sp, implicit %sp + RetRA16 implicit %v0 +... diff --git a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir new file mode 100644 index 000000000000..28fb2a2cf5c9 --- /dev/null +++ b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=nvptx -mcpu=sm_20 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define float @test(float %k) { + entry: + %0 = fadd float %k, 3.250000e+00 + ret float %0 + } + +... +--- +name: test +registers: + - { id: 0, class: float32regs } + - { id: 1, class: float32regs } +body: | + bb.0.entry: + %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0 + ; CHECK: [[@LINE+1]]:33: expected a floating point literal + %1 = FADD_rnf32ri %0, float 3 + StoreRetvalF32 %1, 0 + Return +... diff --git a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir new file mode 100644 index 000000000000..18866d58a946 --- /dev/null +++ b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir @@ -0,0 +1,81 @@ +# RUN: llc -march=nvptx -mcpu=sm_20 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses floating point constant operands +# correctly. + +--- | + + define float @test(float %k, i32 %i) { + entry: + %0 = fpext float %k to double + %1 = fadd double %0, 3.250000e+00 + %2 = fptrunc double %1 to float + %3 = sitofp i32 %i to float + %4 = fadd float %3, 6.250000e+00 + %5 = fmul float %4, %2 + ret float %5 + } + + define float @test2(float %k, i32 %i) { + entry: + %0 = fpext float %k to double + %1 = fadd double %0, 0x7FF8000000000000 + %2 = fptrunc double %1 to float + %3 = sitofp i32 %i to float + %4 = fadd float %3, 0x7FF8000000000000 + %5 = fmul float %4, %2 + ret float %5 + } + +... +--- +name: test +registers: + - { id: 0, class: float32regs } + - { id: 1, class: float64regs } + - { id: 2, class: int32regs } + - { id: 3, class: float64regs } + - { id: 4, class: float32regs } + - { id: 5, class: float32regs } + - { id: 6, class: float32regs } + - { id: 7, class: float32regs } +body: | + bb.0.entry: + %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0 + %1 = CVT_f64_f32 %0, 0 + %2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1 + ; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00 + %3 = FADD_rnf64ri %1, double 3.250000e+00 + %4 = CVT_f32_f64 %3, 5 + %5 = CVT_f32_s32 %2, 5 + ; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00 + %6 = FADD_rnf32ri %5, float 6.250000e+00 + %7 = FMUL_rnf32rr %6, %4 + StoreRetvalF32 %7, 0 + Return +... +--- +name: test2 +registers: + - { id: 0, class: float32regs } + - { id: 1, class: float64regs } + - { id: 2, class: int32regs } + - { id: 3, class: float64regs } + - { id: 4, class: float32regs } + - { id: 5, class: float32regs } + - { id: 6, class: float32regs } + - { id: 7, class: float32regs } +body: | + bb.0.entry: + %0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0 + %1 = CVT_f64_f32 %0, 0 + %2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1 + ; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000 + %3 = FADD_rnf64ri %1, double 0x7FF8000000000000 + %4 = CVT_f32_f64 %3, 5 + %5 = CVT_f32_s32 %2, 5 + ; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000 + %6 = FADD_rnf32ri %5, float 0x7FF8000000000000 + %7 = FMUL_rnf32rr %6, %4 + StoreRetvalF32 %7, 0 + Return +... diff --git a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir new file mode 100644 index 000000000000..e4080f80ee52 --- /dev/null +++ b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=nvptx -mcpu=sm_20 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define float @test(float %k) { + entry: + %0 = fadd float %k, 3.250000e+00 + ret float %0 + } + +... +--- +name: test +registers: + - { id: 0, class: float32regs } + - { id: 1, class: float32regs } +body: | + bb.0.entry: + %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0 + ; CHECK: [[@LINE+1]]:33: floating point constant does not have type 'float' + %1 = FADD_rnf32ri %0, float 0xH3C00 + StoreRetvalF32 %1, 0 + Return +... diff --git a/test/CodeGen/MIR/NVPTX/lit.local.cfg b/test/CodeGen/MIR/NVPTX/lit.local.cfg new file mode 100644 index 000000000000..2cb98eb371b2 --- /dev/null +++ b/test/CodeGen/MIR/NVPTX/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'NVPTX' in config.root.targets: + config.unsupported = True diff --git a/test/CodeGen/MIR/PowerPC/lit.local.cfg b/test/CodeGen/MIR/PowerPC/lit.local.cfg new file mode 100644 index 000000000000..091332439b18 --- /dev/null +++ b/test/CodeGen/MIR/PowerPC/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'PowerPC' in config.root.targets: + config.unsupported = True diff --git a/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir b/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir new file mode 100644 index 000000000000..39d14e72ffee --- /dev/null +++ b/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir @@ -0,0 +1,45 @@ +# RUN: llc -mtriple=powerpc64-unknown-linux-gnu -start-after machine-combiner -stop-after machine-combiner -o /dev/null %s | FileCheck %s +# PR24724 + +--- | + define signext i32 @main(i32* %p) #0 { + entry: + %0 = load i32, i32* %p, align 4 + %or = or i32 0, %0 + store i32 %or, i32* %p, align 4 + %lnot.1 = icmp eq i32 undef, 0 + %lnot.ext.1 = zext i1 %lnot.1 to i32 + %shr.i.1 = lshr i32 2072, %lnot.ext.1 + %call.lobit.1 = lshr i32 %shr.i.1, 7 + %1 = and i32 %call.lobit.1, 1 + %or.1 = or i32 %1, %or + ret i32 %or.1 + } + + attributes #0 = { nounwind "target-cpu"="ppc64" } +... +--- +name: main +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0 } + - { id: 1, class: gprc } + - { id: 2, class: gprc } + - { id: 3, class: gprc } + - { id: 4, class: g8rc } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +body: | + bb.0.entry: + liveins: %x3 + + %0 = COPY %x3 + %1 = LWZ 0, %0 :: (load 4 from %ir.p) + %2 = LI 0 + %3 = RLWIMI %2, killed %1, 0, 0, 31 + %4 = EXTSW_32_64 killed %3 + %x3 = COPY %4 + ; CHECK: BLR8 implicit %lr8, implicit %rm, implicit %x3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 +... diff --git a/test/CodeGen/MIR/X86/basic-block-liveins.mir b/test/CodeGen/MIR/X86/basic-block-liveins.mir index d749a0524422..00732975495d 100644 --- a/test/CodeGen/MIR/X86/basic-block-liveins.mir +++ b/test/CodeGen/MIR/X86/basic-block-liveins.mir @@ -9,17 +9,54 @@ ret i32 %c } + define i32 @test2(i32 %a, i32 %b) { + body: + %c = add i32 %a, %b + ret i32 %c + } + + define i32 @test3() { + body: + ret i32 0 + } + ... --- name: test -body: - # CHECK: name: body - # CHECK: liveins: [ '%edi', '%esi' ] - # CHECK-NEXT: instructions: - - id: 0 - name: body - liveins: [ '%edi', '%esi' ] - instructions: - - '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _' - - 'RETQ %eax' +body: | + ; CHECK-LABEL: bb.0.body: + ; CHECK-NEXT: liveins: %edi, %esi + bb.0.body: + liveins: %edi, %esi + + %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _ + RETQ %eax +... +--- +name: test2 +body: | + ; CHECK-LABEL: name: test2 + ; Verify that we can have multiple lists of liveins that will be merged into + ; one. + ; CHECK: bb.0.body: + ; CHECK-NEXT: liveins: %edi, %esi + bb.0.body: + liveins: %edi + liveins: %esi + + %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _ + RETQ %eax +... +--- +name: test3 +body: | + ; Verify that we can have an empty list of liveins. + ; CHECK-LABEL: name: test3 + ; CHECK: bb.0.body: + ; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags + bb.0.body: + liveins: + + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax ... diff --git a/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir b/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir new file mode 100644 index 000000000000..b4b7dddea56c --- /dev/null +++ b/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir @@ -0,0 +1,41 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: ; preds = %entry + ret i32 0 + + exit: ; preds = %entry + ret i32 %a + } + +... +--- +name: foo +tracksRegLiveness: true +liveins: + - { reg: '%edi' } +body: | + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + liveins: %edi 44 + + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit killed %eflags + + ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line + less bb.1: + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + + bb.2.exit: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/block-address-operands.mir b/test/CodeGen/MIR/X86/block-address-operands.mir new file mode 100644 index 000000000000..3c2d2aefff20 --- /dev/null +++ b/test/CodeGen/MIR/X86/block-address-operands.mir @@ -0,0 +1,121 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the block address operands +# correctly. + +--- | + + @addr = global i8* null + + define void @test() { + entry: + store volatile i8* blockaddress(@test, %block), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %block] + + block: + ret void + } + + define void @test2() { + entry: + store volatile i8* blockaddress(@test2, %"quoted block"), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %"quoted block"] + + "quoted block": + ret void + } + + define void @slot_in_other_function(i8** %addr) { + entry: + store volatile i8* blockaddress(@test3, %0), i8** %addr + ret void + } + + define void @test3() { + entry: + store volatile i8* blockaddress(@test3, %0), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %0] + + ret void + } + + define void @test4() { + entry: + store volatile i8* blockaddress(@test4, %block), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %block] + + block: + ret void + } + +... +--- +name: test +body: | + bb.0.entry: + successors: %bb.1.block + ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _ + %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1.block (address-taken): + RETQ +... +--- +name: test2 +tracksRegLiveness: true +body: | + bb.0.entry: + successors: %bb.1 + ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ + %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1 (address-taken): + RETQ +... +--- +name: slot_in_other_function +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: %rdi + ; CHECK-LABEL: name: slot_in_other_function + ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ + %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ + MOV64mr killed %rdi, 1, _, 0, _, killed %rax + RETQ +... +--- +name: test3 +tracksRegLiveness: true +body: | + bb.0.entry: + successors: %bb.1 + ; CHECK-LABEL: name: test3 + ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ + %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1 (address-taken): + RETQ +... +--- +name: test4 +body: | + bb.0.entry: + successors: %bb.1.block + ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ + %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1.block (address-taken): + RETQ +... diff --git a/test/CodeGen/MIR/X86/callee-saved-info.mir b/test/CodeGen/MIR/X86/callee-saved-info.mir new file mode 100644 index 000000000000..17c7739951d9 --- /dev/null +++ b/test/CodeGen/MIR/X86/callee-saved-info.mir @@ -0,0 +1,95 @@ +# RUN: llc -march=x86-64 -start-after prologepilog -stop-after prologepilog -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses callee saved information in the +# stack objects correctly. + +--- | + + define i32 @compute(i32 %a) { + body: + ret i32 %a + } + + define i32 @func(i32 %a) { + entry: + %b = alloca i32 + store i32 %a, i32* %b + br label %check + + check: + %comp = icmp sle i32 %a, 10 + br i1 %comp, label %loop, label %exit + + loop: + %c = load i32, i32* %b + %d = call i32 @compute(i32 %c) + %e = sub i32 %d, 1 + store i32 %e, i32* %b + br label %check + + exit: + ret i32 0 + } + +... +--- +name: compute +tracksRegLiveness: true +body: | + bb.0.body: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... +--- +name: func +tracksRegLiveness: true +frameInfo: + stackSize: 24 + maxAlignment: 4 + adjustsStack: true + hasCalls: true +# CHECK: fixedStack: +# CHECK-NEXT: , callee-saved-register: '%rbx' } +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' } +# CHECK: stack: +# CHECK-NEXT: - { id: 0 +# CHECK-NEXT: , callee-saved-register: '%edi' } +stack: + - { id: 0, name: b, offset: -20, size: 4, alignment: 4 } + - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' } +body: | + bb.0.entry: + successors: %bb.1.check + liveins: %edi, %rbx + + frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags + %ebx = COPY %edi + MOV32mr %rsp, 1, _, 12, _, %ebx + + bb.1.check: + successors: %bb.2.loop, %bb.3.exit + liveins: %ebx + + CMP32ri8 %ebx, 10, implicit-def %eflags + JG_1 %bb.3.exit, implicit killed %eflags + JMP_1 %bb.2.loop + + bb.2.loop: + successors: %bb.1.check + liveins: %ebx + + %edi = MOV32rm %rsp, 1, _, 12, _ + CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + %eax = DEC32r killed %eax, implicit-def dead %eflags + MOV32mr %rsp, 1, _, 12, _, killed %eax + JMP_1 %bb.1.check + + bb.3.exit: + %eax = MOV32r0 implicit-def dead %eflags + %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir b/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir new file mode 100644 index 000000000000..47051a53e3f4 --- /dev/null +++ b/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir @@ -0,0 +1,29 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the .cfi_def_cfa_offset operands +# correctly. + +--- | + + define void @test() { + entry: + %tmp = alloca [4168 x i8], align 4 + ret void + } + +... +--- +name: test +tracksRegLiveness: true +frameInfo: + stackSize: 4040 +stack: + - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } +body: | + bb.0.entry: + %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags + ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048 + CFI_INSTRUCTION .cfi_def_cfa_offset 4048 + %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags + RETQ +... + diff --git a/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir b/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir new file mode 100644 index 000000000000..74a33b5c3437 --- /dev/null +++ b/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir @@ -0,0 +1,32 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the .cfi_def_cfa_register +# operands correctly. + +--- | + + define void @func() #0 { + entry: + unreachable + } + + attributes #0 = { "no-frame-pointer-elim"="true" } + +... +--- +name: func +tracksRegLiveness: true +frameInfo: + stackSize: 8 +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } +body: | + bb.0.entry: + liveins: %rbp + + PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp + CFI_INSTRUCTION .cfi_def_cfa_offset 16 + CFI_INSTRUCTION .cfi_offset %rbp, -16 + %rbp = MOV64rr %rsp + ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp + CFI_INSTRUCTION .cfi_def_cfa_register %rbp +... diff --git a/test/CodeGen/MIR/X86/cfi-offset.mir b/test/CodeGen/MIR/X86/cfi-offset.mir new file mode 100644 index 000000000000..fd9e605a036a --- /dev/null +++ b/test/CodeGen/MIR/X86/cfi-offset.mir @@ -0,0 +1,47 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the .cfi_offset operands +# correctly. + +--- | + + declare void @foo(i32) + + define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) { + entry: + %add = add nsw i32 %b, %a + %add1 = add nsw i32 %add, %c + %add2 = add nsw i32 %add1, %d + tail call void @foo(i32 %add2) + %add6 = add nsw i32 %add2, %add2 + ret i32 %add6 + } + +... +--- +name: test +tracksRegLiveness: true +frameInfo: + stackSize: 8 + adjustsStack: true + hasCalls: true +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } +body: | + bb.0.entry: + liveins: %ecx, %edi, %edx, %esi, %rbx + + PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + CFI_INSTRUCTION .cfi_def_cfa_offset 16 + ; CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16 + CFI_INSTRUCTION .cfi_offset %rbx, -16 + %ebx = COPY %edi, implicit-def %rbx + %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags + %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags + %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags + %edi = COPY %ebx + CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp + %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _ + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... + diff --git a/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir b/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir new file mode 100644 index 000000000000..2ddf5736b977 --- /dev/null +++ b/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define double @test(double %a, float %b) { + entry: + %c = fadd double %a, 3.250000e+00 + ret double %c + } + +... +--- +name: test +constants: + - id: 0 + value: 'double 3.250000e+00' +# CHECK: [[@LINE+1]]:18: redefinition of constant pool item '%const.0' + - id: 0 + value: 'double 3.250000e+00' +body: | + bb.0.entry: + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ + RETQ %xmm0 +... + diff --git a/test/CodeGen/MIR/X86/constant-pool.mir b/test/CodeGen/MIR/X86/constant-pool.mir new file mode 100644 index 000000000000..213e4e283485 --- /dev/null +++ b/test/CodeGen/MIR/X86/constant-pool.mir @@ -0,0 +1,139 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses constant pool constants and +# constant pool operands correctly. + +--- | + + define double @test(double %a, float %b) { + entry: + %c = fadd double %a, 3.250000e+00 + %d = fadd float %b, 6.250000e+00 + %e = fpext float %d to double + %f = fmul double %c, %e + ret double %f + } + + define double @test2(double %a, float %b) { + entry: + %c = fadd double %a, 3.250000e+00 + %d = fadd float %b, 6.250000e+00 + %e = fpext float %d to double + %f = fmul double %c, %e + ret double %f + } + + define double @test3(double %a, float %b) { + entry: + %c = fadd double %a, 3.250000e+00 + %d = fadd float %b, 6.250000e+00 + %e = fpext float %d to double + %f = fmul double %c, %e + ret double %f + } + + define double @test4(double %a, float %b) { + entry: + %c = fadd double %a, 3.250000e+00 + %d = fadd float %b, 6.250000e+00 + %e = fpext float %d to double + %f = fmul double %c, %e + ret double %f + } +... +--- +# CHECK: name: test +# CHECK: constants: +# CHECK-NEXT: - id: 0 +# CHECK-NEXT: value: 'double 3.250000e+00' +# CHECK-NEXT: alignment: 8 +# CHECK-NEXT: - id: 1 +# CHECK-NEXT: value: 'float 6.250000e+00' +# CHECK-NEXT: alignment: 4 +name: test +constants: + - id: 0 + value: 'double 3.250000e+00' + alignment: 8 + - id: 1 + value: 'float 6.250000e+00' + alignment: 4 +body: | + bb.0.entry: + ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ + ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ + %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ + %xmm1 = CVTSS2SDrr killed %xmm1 + %xmm0 = MULSDrr killed %xmm0, killed %xmm1 + RETQ %xmm0 +... +--- +# Verify that alignment can be inferred: +# CHECK: name: test2 +# CHECK: constants: +# CHECK-NEXT: - id: 0 +# CHECK-NEXT: value: 'double 3.250000e+00' +# CHECK-NEXT: alignment: 8 +# CHECK-NEXT: - id: 1 +# CHECK-NEXT: value: 'float 6.250000e+00' +# CHECK-NEXT: alignment: 4 +name: test2 +constants: + - id: 0 + value: 'double 3.250000e+00' + - id: 1 + value: 'float 6.250000e+00' +body: | + bb.0.entry: + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ + %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ + %xmm1 = CVTSS2SDrr killed %xmm1 + %xmm0 = MULSDrr killed %xmm0, killed %xmm1 + RETQ %xmm0 +... +--- +# Verify that the non-standard alignments are respected: +# CHECK: name: test3 +# CHECK: constants: +# CHECK-NEXT: - id: 0 +# CHECK-NEXT: value: 'double 3.250000e+00' +# CHECK-NEXT: alignment: 128 +# CHECK-NEXT: - id: 1 +# CHECK-NEXT: value: 'float 6.250000e+00' +# CHECK-NEXT: alignment: 1 +name: test3 +constants: + - id: 0 + value: 'double 3.250000e+00' + alignment: 128 + - id: 1 + value: 'float 6.250000e+00' + alignment: 1 +body: | + bb.0.entry: + ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ + ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ + %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ + %xmm1 = CVTSS2SDrr killed %xmm1 + %xmm0 = MULSDrr killed %xmm0, killed %xmm1 + RETQ %xmm0 +... +--- +# CHECK: name: test4 +name: test4 +constants: + - id: 0 + value: 'double 3.250000e+00' + - id: 1 + value: 'float 6.250000e+00' +body: | + bb.0.entry: + ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _ + ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _ + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _ + %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _ + %xmm1 = CVTSS2SDrr killed %xmm1 + %xmm0 = MULSDrr killed %xmm0, killed %xmm1 + RETQ %xmm0 +... diff --git a/test/CodeGen/MIR/X86/constant-value-error.mir b/test/CodeGen/MIR/X86/constant-value-error.mir new file mode 100644 index 000000000000..1e14d2282c5a --- /dev/null +++ b/test/CodeGen/MIR/X86/constant-value-error.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that the MIR parser reports an error when parsing an invalid +# constant value. + +--- | + + define double @test(double %a, float %b) { + entry: + %c = fadd double %a, 3.250000e+00 + ret double %c + } + +... +--- +name: test +constants: + - id: 0 + # CHECK: [[@LINE+1]]:19: expected type + value: 'dub 3.250000e+00' +body: | + bb.0.entry: + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ + RETQ %xmm0 +... + diff --git a/test/CodeGen/MIR/X86/dead-register-flag.mir b/test/CodeGen/MIR/X86/dead-register-flag.mir index 988b554659cb..309e776de46a 100644 --- a/test/CodeGen/MIR/X86/dead-register-flag.mir +++ b/test/CodeGen/MIR/X86/dead-register-flag.mir @@ -15,12 +15,10 @@ ... --- name: foo -body: - # CHECK: name: body - - id: 0 - name: body - instructions: - # CHECK: - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags' - - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags' - - 'RETQ %eax' +body: | + ; CHECK: bb.0.body: + bb.0.body: + ; CHECK: %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags + %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/def-register-already-tied-error.mir b/test/CodeGen/MIR/X86/def-register-already-tied-error.mir new file mode 100644 index 000000000000..69c816f59b9b --- /dev/null +++ b/test/CodeGen/MIR/X86/def-register-already-tied-error.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +--- | + define i64 @test(i64 %x) #0 { + entry: + %asm = tail call i64 asm sideeffect "$foo", "=r,0"(i64 %x) nounwind + ret i64 %asm + } + + attributes #0 = { nounwind } +... +--- +name: test +hasInlineAsm: true +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + + ; CHECK: [[@LINE+1]]:83: the tied-def operand #3 is already tied with another register operand + INLINEASM $"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 3), killed %rdi(tied-def 3) + %rax = COPY killed %rdi + RETQ killed %rax +... diff --git a/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir b/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir new file mode 100644 index 000000000000..7d01810c792b --- /dev/null +++ b/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir @@ -0,0 +1,27 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @volatile_inc(i32* %x) { + entry: + %0 = load volatile i32, i32* %x + %1 = add i32 %0, 1 + store volatile i32 %1, i32* %x + ret i32 %1 + } + +... +--- +name: volatile_inc +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag + %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x) + %eax = INC32r killed %eax, implicit-def dead %eflags + MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir b/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir new file mode 100644 index 000000000000..d80c6ed061de --- /dev/null +++ b/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir @@ -0,0 +1,35 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + +... +--- +name: foo +body: | + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + + CMP32ri8 %edi, 10, implicit-def %eflags + ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag + JG_1 %bb.2.exit, implicit implicit %eflags + + bb.1.less: + %eax = MOV32r0 implicit-def %eflags + RETQ %eax + + bb.2.exit: + %eax = COPY %edi + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir new file mode 100644 index 000000000000..4dc442e4fb94 --- /dev/null +++ b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir @@ -0,0 +1,45 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the 'early-clobber' register +# flags correctly. + +--- | + + declare void @foo(i32) + + define void @test(i32 %a, i32 %b) #0 { + entry: + %c = add i32 %a, %b + call void asm sideeffect "nop", "~{ax},~{di}"() + call void @foo(i32 %c) + ret void + } + + attributes #0 = { optsize } + +... +--- +name: test +hasInlineAsm: true +tracksRegLiveness: true +liveins: + - { reg: '%edi' } + - { reg: '%esi' } +frameInfo: + stackSize: 8 + adjustsStack: true + hasCalls: true +body: | + bb.0.entry: + liveins: %edi, %esi + + frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp + CFI_INSTRUCTION .cfi_def_cfa_offset 16 + %ecx = COPY %edi + %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags + ; CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di + INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di + %edi = COPY killed %ecx + CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp + %rax = POP64r implicit-def %rsp, implicit %rsp + RETQ +... diff --git a/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir new file mode 100644 index 000000000000..f2e349454c5d --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir @@ -0,0 +1,30 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define void @memory_alignment(<8 x float>* %vec) { + entry: + %v = load <8 x float>, <8 x float>* %vec + %v2 = insertelement <8 x float> %v, float 0.0, i32 4 + store <8 x float> %v2, <8 x float>* %vec + ret void + } + +... +--- +name: memory_alignment +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:65: expected 'align' + %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32) + %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + %xmm2 = FsFLD0SS + %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 + MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + RETQ +... diff --git a/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir new file mode 100644 index 000000000000..7ce377f8c5fb --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir @@ -0,0 +1,30 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define void @memory_alignment(<8 x float>* %vec) { + entry: + %v = load <8 x float>, <8 x float>* %vec + %v2 = insertelement <8 x float> %v, float 0.0, i32 4 + store <8 x float> %v2, <8 x float>* %vec + ret void + } + +... +--- +name: memory_alignment +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:70: expected an integer literal after 'align' + %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align) + %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + %xmm2 = FsFLD0SS + %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 + MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + RETQ +... diff --git a/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir b/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir new file mode 100644 index 000000000000..861baec4bcbc --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir @@ -0,0 +1,40 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: ; preds = %entry + ret i32 0 + + exit: ; preds = %entry + ret i32 %a + } + +... +--- +name: foo +tracksRegLiveness: true +liveins: + - { reg: '%edi' } +body: | + ; CHECK: [[@LINE+1]]:3: expected a basic block definition before instructions + successors: %bb.1.less, %bb.2.exit + liveins: %edi 44 + + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit killed %eflags + + bb.1.less: + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + + bb.2.exit: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir b/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir new file mode 100644 index 000000000000..ef7df4c8c20f --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir @@ -0,0 +1,30 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @addr = global i8* null + + define void @test() { + entry: + store volatile i8* blockaddress(@test, %block), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %block] + + block: + ret void + } + +... +--- +name: test +body: | + bb.0.entry: + successors: %bb.1.block + ; CHECK: [[@LINE+1]]:51: expected an IR block reference + %rax = LEA64r %rip, 1, _, blockaddress(@test, _), _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1.block (address-taken): + RETQ +... diff --git a/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir b/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir new file mode 100644 index 000000000000..ba7b2ab64c3e --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir @@ -0,0 +1,42 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + declare void @foo(i32) + + define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) { + entry: + %add = add nsw i32 %b, %a + %add1 = add nsw i32 %add, %c + %add2 = add nsw i32 %add1, %d + tail call void @foo(i32 %add2) + %add6 = add nsw i32 %add2, %add2 + ret i32 %add6 + } + +... +--- +name: test +tracksRegLiveness: true +frameInfo: + stackSize: 8 + adjustsStack: true + hasCalls: true +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } +body: | + bb.0.entry: + PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + CFI_INSTRUCTION .cfi_def_cfa_offset 16 + ; CHECK: [[@LINE+1]]:38: expected ',' + CFI_INSTRUCTION .cfi_offset %rbx -16 + %ebx = COPY %edi, implicit-def %rbx + %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags + %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags + %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags + %edi = COPY %ebx + CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp + %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _ + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir b/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir new file mode 100644 index 000000000000..dd5693952573 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define void @test(i32* %a) { + entry2: + %b = load i32, i32* %a + %c = add i32 %b, 1 + store i32 %c, i32* %a + ret void + } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry2: + liveins: %rdi + ; CHECK: [[@LINE+1]]:87: expected ',' before the next machine memory operand + INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a) + RETQ +... diff --git a/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir b/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir index c5f5aaca34e0..601551a7720a 100644 --- a/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir +++ b/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir @@ -19,20 +19,16 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - - 'CMP32ri8 %eax, 10, implicit-def %eflags' -# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags' - - 'JG_1 %bb.2.exit, implicit %eax' - - id: 1 - name: less - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 2 - name: exit - instructions: - - 'RETQ %eax' +body: | + bb.0.entry: + %eax = MOV32rm %rdi, 1, _, 0, _ + CMP32ri8 %eax, 10, implicit-def %eflags + ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit %eflags' + JG_1 %bb.2.exit, implicit %eax + + bb.1.less: + %eax = MOV32r0 implicit-def %eflags + + bb.2.exit: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir b/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir index ecf3a122bf66..6494960d3264 100644 --- a/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir +++ b/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir @@ -19,20 +19,16 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - - 'CMP32ri8 %eax, 10, implicit-def %eflags' -# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags' - - 'JG_1 %bb.2.exit, implicit-def %eflags' - - id: 1 - name: less - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 2 - name: exit - instructions: - - 'RETQ %eax' +body: | + bb.0.entry: + %eax = MOV32rm %rdi, 1, _, 0, _ + CMP32ri8 %eax, 10, implicit-def %eflags + ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit %eflags' + JG_1 %bb.2.exit, implicit-def %eflags + + bb.1.less: + %eax = MOV32r0 implicit-def %eflags + + bb.2.exit: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir new file mode 100644 index 000000000000..f9e9d0b22968 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32* %a) { + entry: + %b = load i32, i32* %a + ret i32 %b + } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:55: expected 'from' + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a) + RETQ %eax +... + diff --git a/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir b/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir new file mode 100644 index 000000000000..de6a745fd702 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir @@ -0,0 +1,30 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @addr = global i8* null + + define void @test() { + entry: + store volatile i8* blockaddress(@test, %block), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %block] + + block: + ret void + } + +... +--- +name: test +body: | + bb.0.entry: + successors: %bb.1.block + ; CHECK: [[@LINE+1]]:44: expected an IR function reference + %rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1.block (address-taken): + RETQ +... diff --git a/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir b/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir new file mode 100644 index 000000000000..f737c06c3e1e --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir @@ -0,0 +1,30 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @addr = global i8* null + + define void @test() { + entry: + store volatile i8* blockaddress(@test, %block), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %block] + + block: + ret void + } + +... +--- +name: test +body: | + bb.0.entry: + successors: %bb.1.block + ; CHECK: [[@LINE+1]]:44: expected a global value + %rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1.block (address-taken): + RETQ +... diff --git a/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir b/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir new file mode 100644 index 000000000000..e337292f17a2 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @G = external global i32 + + define i32 @inc() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + +... +--- +name: inc +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:37: expected an integer literal after '+' + %rax = MOV64rm %rip, 1, _, @G + , _ + %eax = MOV32rm %rax, 1, _, 0, _ + %eax = INC32r %eax, implicit-def %eflags + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir b/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir new file mode 100644 index 000000000000..580d2bc0a419 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +--- | + define i64 @test(i64 %x) #0 { + entry: + %asm = tail call i64 asm sideeffect "$foo", "=r,0"(i64 %x) nounwind + ret i64 %asm + } + + attributes #0 = { nounwind } +... +--- +name: test +hasInlineAsm: true +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + + ; CHECK: [[@LINE+1]]:78: expected an integer literal after 'tied-def' + INLINEASM $"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def) + %rax = COPY killed %rdi + RETQ killed %rax +... diff --git a/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir b/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir new file mode 100644 index 000000000000..83874eb67476 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir @@ -0,0 +1,38 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + +... +--- +name: foo +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:29: expected an integer literal after '(' + successors: %bb.1.less (_), %bb.2.exit(32) + liveins: %edi + + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit killed %eflags + + bb.1.less: + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + + bb.2.exit: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir new file mode 100644 index 000000000000..8fcd622a18e6 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir @@ -0,0 +1,23 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32* %a) { + entry: + %b = load i32, i32* %a + ret i32 %b + } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a) + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-machine-operand.mir b/test/CodeGen/MIR/X86/expected-machine-operand.mir index 3725c93cd3ea..3ba5126b9982 100644 --- a/test/CodeGen/MIR/X86/expected-machine-operand.mir +++ b/test/CodeGen/MIR/X86/expected-machine-operand.mir @@ -10,12 +10,10 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:24: expected a machine operand - - '%eax = XOR32rr =' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:20: expected a machine operand + %eax = XOR32rr = + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir b/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir new file mode 100644 index 000000000000..620bb5d961ee --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir @@ -0,0 +1,59 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %x) #0 !dbg !4 { + entry: + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !12, metadata !13), !dbg !14 + %0 = load i32, i32* %x.addr, align 4, !dbg !15 + ret i32 %0, !dbg !15 + } + + declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + + attributes #0 = { nounwind "no-frame-pointer-elim"="false" } + attributes #1 = { nounwind readnone } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!9, !10} + !llvm.ident = !{!11} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !1 = !DIFile(filename: "test.ll", directory: "") + !2 = !{} + !3 = !{!4} + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !5 = !DIFile(filename: "test.c", directory: "") + !6 = !DISubroutineType(types: !7) + !7 = !{!8, !8} + !8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !9 = !{i32 2, !"Dwarf Version", i32 4} + !10 = !{i32 2, !"Debug Info Version", i32 3} + !11 = !{!"clang version 3.7.0"} + !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8) + !13 = !DIExpression() + !14 = !DILocation(line: 4, scope: !4) + !15 = !DILocation(line: 8, scope: !4) + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, name: x.addr, size: 4, alignment: 4 } +body: | + bb.0.entry: + %0 = COPY %edi + ; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location' + DBG_VALUE _, 0, !12, !13, debug-location 14 + MOV32mr %stack.x.addr, 1, _, 0, _, %0 + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir b/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir new file mode 100644 index 000000000000..6497f5db2026 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir @@ -0,0 +1,59 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %x) #0 !dbg !4 { + entry: + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !12, metadata !13), !dbg !14 + %0 = load i32, i32* %x.addr, align 4, !dbg !15 + ret i32 %0, !dbg !15 + } + + declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + + attributes #0 = { nounwind "no-frame-pointer-elim"="false" } + attributes #1 = { nounwind readnone } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!9, !10} + !llvm.ident = !{!11} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !1 = !DIFile(filename: "test.ll", directory: "") + !2 = !{} + !3 = !{!4} + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !5 = !DIFile(filename: "test.c", directory: "") + !6 = !DISubroutineType(types: !7) + !7 = !{!8, !8} + !8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !9 = !{i32 2, !"Dwarf Version", i32 4} + !10 = !{i32 2, !"Debug Info Version", i32 3} + !11 = !{!"clang version 3.7.0"} + !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8) + !13 = !DIExpression() + !14 = !DILocation(line: 4, scope: !4) + !15 = !DILocation(line: 8, scope: !4) + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, name: x.addr, size: 4, alignment: 4 } +body: | + bb.0.entry: + %0 = COPY %edi + ; CHECK: [[@LINE+1]]:28: expected metadata id after '!' + DBG_VALUE _, 0, !12, ! _ + MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir b/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir new file mode 100644 index 000000000000..9a4696779fb5 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +--- | + define i32 @test(i32 %x) { + entry: + %xa = alloca i32, align 4 + store i32 %x, i32* %xa, align 4 + %0 = load i32, i32* %xa, align 4 + ret i32 %0 + } +... +--- +name: test +liveins: + - { reg: '%edi' } +stack: +# CHECK: [[@LINE+1]]:74: expected a metadata node + - { id: 0, name: xa, offset: -12, size: 4, alignment: 4, di-variable: '0' } +body: | + bb.0.entry: + liveins: %edi + + MOV32mr %rsp, 1, _, -4, _, %edi :: (store 4 into %ir.xa) + %eax = COPY killed %edi + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir new file mode 100644 index 000000000000..04568f6dde57 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir @@ -0,0 +1,29 @@ +# RUN: not llc -march=x86-64 -start-after machine-scheduler -stop-after machine-scheduler -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %a, i32 %b) { + body: + %c = mul i32 %a, %b + ret i32 %c + } + +... +--- +name: test +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + # CHECK: [[@LINE+1]]:48: expected a named register + - { id: 1, class: gr32, preferred-register: '%0' } + - { id: 2, class: gr32, preferred-register: '%edi' } +body: | + bb.0.body: + liveins: %edi, %esi + + %1 = COPY %esi + %2 = COPY %edi + %2 = IMUL32rr %2, %1, implicit-def dead %eflags + %eax = COPY %2 + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir b/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir new file mode 100644 index 000000000000..be57734ecf33 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir @@ -0,0 +1,88 @@ +# RUN: not llc -march=x86-64 -start-after prologepilog -stop-after prologepilog -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @compute(i32 %a) { + body: + ret i32 %a + } + + define i32 @func(i32 %a) { + entry: + %b = alloca i32 + store i32 %a, i32* %b + br label %check + + check: + %comp = icmp sle i32 %a, 10 + br i1 %comp, label %loop, label %exit + + loop: + %c = load i32, i32* %b + %d = call i32 @compute(i32 %c) + %e = sub i32 %d, 1 + store i32 %e, i32* %b + br label %check + + exit: + ret i32 0 + } + +... +--- +name: compute +tracksRegLiveness: true +body: | + bb.0.body: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... +--- +name: func +tracksRegLiveness: true +frameInfo: + stackSize: 24 + maxAlignment: 4 + adjustsStack: true + hasCalls: true +fixedStack: + # CHECK: [[@LINE+1]]:93: expected a named register + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%0' } +stack: + - { id: 0, name: b, offset: -20, size: 4, alignment: 4 } +body: | + bb.0.entry: + successors: %bb.1.check + liveins: %edi, %rbx + + frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags + %ebx = COPY %edi + MOV32mr %rsp, 1, _, 12, _, %ebx + + bb.1.check: + successors: %bb.2.loop, %bb.3.exit + liveins: %ebx + + CMP32ri8 %ebx, 10, implicit-def %eflags + JG_1 %bb.3.exit, implicit killed %eflags + JMP_1 %bb.2.loop + + bb.2.loop: + successors: %bb.1.check + liveins: %ebx + + %edi = MOV32rm %rsp, 1, _, 12, _ + CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + %eax = DEC32r killed %eax, implicit-def dead %eflags + MOV32mr %rsp, 1, _, 12, _, killed %eax + JMP_1 %bb.1.check + + bb.3.exit: + %eax = MOV32r0 implicit-def dead %eflags + %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir b/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir new file mode 100644 index 000000000000..ae9f776ad769 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir @@ -0,0 +1,27 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %a) { + body: + ret i32 %a + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +liveins: + # CHECK: [[@LINE+1]]:13: expected a named register + - { reg: '%0' } +body: | + bb.0.body: + liveins: %edi + + %0 = COPY %edi + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-named-register-livein.mir b/test/CodeGen/MIR/X86/expected-named-register-livein.mir index 1fbe881c8c70..41e6a4a6cc88 100644 --- a/test/CodeGen/MIR/X86/expected-named-register-livein.mir +++ b/test/CodeGen/MIR/X86/expected-named-register-livein.mir @@ -10,12 +10,11 @@ ... --- name: test -body: - - id: 0 - name: body - # CHECK: [[@LINE+1]]:21: expected a named register - liveins: [ '%0' ] - instructions: - - '%eax = COPY %edi' - - 'RETQ %eax' +body: | + bb.0.body: + ; CHECK: [[@LINE+1]]:14: expected a named register + liveins: %0 + + %eax = COPY %edi + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir b/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir new file mode 100644 index 000000000000..1f0439d126f4 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir @@ -0,0 +1,41 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: ; preds = %entry + ret i32 0 + + exit: ; preds = %entry + ret i32 %a + } + +... +--- +name: foo +tracksRegLiveness: true +liveins: + - { reg: '%edi' } +body: | + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + ; CHECK: [[@LINE+1]]:19: expected line break at the end of a list + liveins: %edi 44 + + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit killed %eflags + + bb.1.less: + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + + bb.2.exit: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/expected-number-after-bb.mir b/test/CodeGen/MIR/X86/expected-number-after-bb.mir index 5343a847fbb9..a239cf176f5f 100644 --- a/test/CodeGen/MIR/X86/expected-number-after-bb.mir +++ b/test/CodeGen/MIR/X86/expected-number-after-bb.mir @@ -18,20 +18,16 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - - 'CMP32ri8 %eax, 10, implicit-def %eflags' - # CHECK: [[@LINE+1]]:18: expected a number after '%bb.' - - 'JG_1 %bb.nah, implicit %eflags' - - id: 1 - name: yes - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 2 - name: nah - instructions: - - 'RETQ %eax' +body: | + bb.0.entry: + %eax = MOV32rm %rdi, 1, _, 0, _ + CMP32ri8 %eax, 10, implicit-def %eflags + ; CHECK: [[@LINE+1]]:14: expected a number after '%bb.' + JG_1 %bb.nah, implicit %eflags + + bb.1.true: + %eax = MOV32r0 implicit-def %eflags + + bb.2.nah: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir b/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir new file mode 100644 index 000000000000..aefeed9ce05e --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir @@ -0,0 +1,27 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define void @test() { + entry: + %tmp = alloca [4168 x i8], align 4 + ret void + } + +... +--- +name: test +tracksRegLiveness: true +frameInfo: + stackSize: 4040 +stack: + - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } +body: | + bb.0.entry: + %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags + ; CHECK: [[@LINE+1]]:41: expected a cfi offset + CFI_INSTRUCTION .cfi_def_cfa_offset _ + %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags + RETQ +... + diff --git a/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir new file mode 100644 index 000000000000..fca078c3497c --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32* %a) { + entry: + %b = load i32, i32* %a + ret i32 %b + } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:60: expected a pointer IR value + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b) + RETQ %eax +... + diff --git a/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir b/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir new file mode 100644 index 000000000000..31b4c5be1251 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir @@ -0,0 +1,30 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define void @memory_alignment(<8 x float>* %vec) { + entry: + %v = load <8 x float>, <8 x float>* %vec + %v2 = insertelement <8 x float> %v, float 0.0, i32 4 + store <8 x float> %v2, <8 x float>* %vec + ret void + } + +... +--- +name: memory_alignment +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:71: expected an integer literal after 'align' + %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32) + %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + %xmm2 = FsFLD0SS + %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 + MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + RETQ +... diff --git a/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir b/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir new file mode 100644 index 000000000000..3280fca6d551 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir @@ -0,0 +1,42 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + declare void @foo(i32) + + define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) { + entry: + %add = add nsw i32 %b, %a + %add1 = add nsw i32 %add, %c + %add2 = add nsw i32 %add1, %d + tail call void @foo(i32 %add2) + %add6 = add nsw i32 %add2, %add2 + ret i32 %add6 + } + +... +--- +name: test +tracksRegLiveness: true +frameInfo: + stackSize: 8 + adjustsStack: true + hasCalls: true +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } +body: | + bb.0.entry: + PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + CFI_INSTRUCTION .cfi_def_cfa_offset 16 + ; CHECK: [[@LINE+1]]:33: expected a cfi register + CFI_INSTRUCTION .cfi_offset %0, -16 + %ebx = COPY %edi, implicit-def %rbx + %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags + %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags + %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags + %edi = COPY %ebx + CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp + %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _ + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-register-after-flags.mir b/test/CodeGen/MIR/X86/expected-register-after-flags.mir index 111f5496a378..68f1060ad873 100644 --- a/test/CodeGen/MIR/X86/expected-register-after-flags.mir +++ b/test/CodeGen/MIR/X86/expected-register-after-flags.mir @@ -12,11 +12,9 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:37: expected a register after register flags - - '%eax = MOV32r0 implicit-def 2' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:33: expected a register after register flags + %eax = MOV32r0 implicit-def 2 + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir b/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir new file mode 100644 index 000000000000..71ff15bd9c52 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32* %a) { + entry: + %b = load i32, i32* %a + ret i32 %b + } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:53: expected the size integer literal after memory operation + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a) + RETQ %eax +... + diff --git a/test/CodeGen/MIR/X86/expected-stack-object.mir b/test/CodeGen/MIR/X86/expected-stack-object.mir new file mode 100644 index 000000000000..ff0c10d59e33 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-stack-object.mir @@ -0,0 +1,67 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + + +--- | + @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 + @__stack_chk_guard = external global i8* + + define i32 @test() #0 { + entry: + %StackGuardSlot = alloca i8* + %StackGuard = load i8*, i8** @__stack_chk_guard + call void @llvm.stackprotector(i8* %StackGuard, i8** %StackGuardSlot) + %test = alloca i8*, align 8 + %a = alloca i8, i64 5 + store i8* %a, i8** %test, align 8 + %b = load i8*, i8** %test, align 8 + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %b) + call void @llvm.stackprotectorcheck(i8** @__stack_chk_guard) + ret i32 %call + } + + declare i32 @printf(i8*, ...) + + declare void @llvm.stackprotector(i8*, i8**) #1 + + declare void @llvm.stackprotectorcheck(i8**) #2 + + attributes #0 = { ssp "stack-protector-buffer-size"="5" } + attributes #1 = { nounwind } + attributes #2 = { nounwind argmemonly } +... +--- +name: test +alignment: 4 +tracksRegLiveness: true +frameInfo: + stackSize: 40 + maxAlignment: 8 + adjustsStack: true + hasCalls: true +# CHECK: [[@LINE+1]]:21: expected a stack object + stackProtector: '0' +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, + callee-saved-register: '%rbx' } +stack: + - { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 } + - { id: 1, name: test, offset: -40, size: 8, alignment: 8 } + - { id: 2, name: a, offset: -29, size: 5, alignment: 1 } +body: | + bb.0.entry: + liveins: %rbx, %rbx + + frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + %rsp = frame-setup SUB64ri8 %rsp, 32, implicit-def dead %eflags + %rbx = LOAD_STACK_GUARD :: (invariant load 8 from %ir.__stack_chk_guard) + MOV64mr %rsp, 1, _, 24, _, %rbx + %rsi = LEA64r %rsp, 1, _, 19, _ + MOV64mr %rsp, 1, _, 8, _, %rsi + %rdi = LEA64r %rip, 1, _, @.str, _ + dead %eax = MOV32r0 implicit-def dead %eflags, implicit-def %al + CALL64pcrel32 @printf, csr_64, implicit %rsp, implicit %rdi, implicit %rsi, implicit %al, implicit-def %rsp, implicit-def %eax + CMP64rm killed %rbx, %rsp, 1, _, 24, _, implicit-def %eflags + %rsp = ADD64ri8 %rsp, 32, implicit-def dead %eflags + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir index c891a115a180..6283427c10b3 100644 --- a/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir +++ b/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir @@ -16,14 +16,12 @@ registers: - { id: 0, class: gr32 } - { id: 1, class: gr8 } - { id: 2, class: gr8 } -body: - - name: entry - id: 0 - instructions: - - '%0 = COPY %edi' - # CHECK: [[@LINE+1]]:25: expected a subregister index after ':' - - '%1 = COPY %0 : 42' - - '%2 = AND8ri %1, 1, implicit-def %eflags' - - '%al = COPY %2' - - 'RETQ %al' +body: | + bb.0.entry: + %0 = COPY %edi + ; CHECK: [[@LINE+1]]:20: expected a subregister index after ':' + %1 = COPY %0 : 42 + %2 = AND8ri %1, 1, implicit-def %eflags + %al = COPY %2 + RETQ %al ... diff --git a/test/CodeGen/MIR/X86/expected-target-flag-name.mir b/test/CodeGen/MIR/X86/expected-target-flag-name.mir new file mode 100644 index 000000000000..3d094a11e9f3 --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-target-flag-name.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @G = external global i32 + + define i32 @inc() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + +... +--- +name: inc +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:46: expected the name of the target flag + %rax = MOV64rm %rip, 1, _, target-flags( ) @G, _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + %eax = INC32r killed %eax, implicit-def dead %eflags + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir b/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir new file mode 100644 index 000000000000..e8d6afd5333e --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +--- | + define i64 @test(i64 %x) #0 { + entry: + %asm = tail call i64 asm sideeffect "$foo", "=r,0"(i64 %x) nounwind + ret i64 %asm + } + + attributes #0 = { nounwind } +... +--- +name: test +hasInlineAsm: true +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + + ; CHECK: [[@LINE+1]]:70: expected 'tied-def' after '(' + INLINEASM $"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(3) + %rax = COPY killed %rdi + RETQ killed %rax +... diff --git a/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir new file mode 100644 index 000000000000..f99443f1726d --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32* %a) { + entry: + %b = load i32, i32* %a + ret i32 %b + } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:60: expected an IR value reference + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a) + RETQ %eax +... + diff --git a/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir b/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir new file mode 100644 index 000000000000..da0d1e166a1c --- /dev/null +++ b/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir @@ -0,0 +1,27 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %a) { + body: + ret i32 %a + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +liveins: + # CHECK: [[@LINE+1]]:34: expected a virtual register + - { reg: '%edi', virtual-reg: '%edi' } +body: | + bb.0.body: + liveins: %edi + + %0 = COPY %edi + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/external-symbol-operands.mir b/test/CodeGen/MIR/X86/external-symbol-operands.mir new file mode 100644 index 000000000000..7e85d946b75a --- /dev/null +++ b/test/CodeGen/MIR/X86/external-symbol-operands.mir @@ -0,0 +1,64 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the external symbol machine +# operands correctly. + +--- | + @__stack_chk_guard = external global i8* + + define i32 @test(i32 %n) #0 { + entry: + %StackGuardSlot = alloca i8* + %StackGuard = load i8*, i8** @__stack_chk_guard + call void @llvm.stackprotector(i8* %StackGuard, i8** %StackGuardSlot) + %a = alloca [128 x i32], align 16 + %idxprom = sext i32 %n to i64 + %arrayidx = getelementptr inbounds [128 x i32], [128 x i32]* %a, i64 0, i64 %idxprom + %0 = load i32, i32* %arrayidx, align 4 + call void @llvm.stackprotectorcheck(i8** @__stack_chk_guard) + ret i32 %0 + } + + declare void @llvm.stackprotector(i8*, i8**) #1 + + declare void @llvm.stackprotectorcheck(i8**) #1 + + attributes #0 = { ssp "stack-protector-buffer-size"="8" } + attributes #1 = { nounwind } + +... +--- +name: test +tracksRegLiveness: true +body: | + bb.0.entry: + successors: %bb.1.entry, %bb.2.entry + liveins: %edi + + %rsp = SUB64ri32 %rsp, 520, implicit-def %eflags + %rcx = LOAD_STACK_GUARD + MOV64mr %rsp, 1, _, 512, _, %rcx + %rax = MOVSX64rr32 %edi + %eax = MOV32rm %rsp, 4, %rax, 0, _ + CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags + JNE_1 %bb.2.entry, implicit %eflags + + bb.1.entry: + liveins: %eax + + %rsp = ADD64ri32 %rsp, 520, implicit-def %eflags + RETQ %eax + + bb.2.entry: + ; CHECK: CALL64pcrel32 $__stack_chk_fail, + ; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_, + ; CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$", + ; CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ", + ; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2, + ; CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20, + CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp + CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp + CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp + CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp + CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp + CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp +... diff --git a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir new file mode 100644 index 000000000000..75d0f8a39c1c --- /dev/null +++ b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir @@ -0,0 +1,39 @@ +# RUN: llc -march=x86 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses fixed stack memory operands +# correctly. + +--- | + + define i32 @test(i32 %a) #0 { + entry: + %b = alloca i32 + store i32 %a, i32* %b + %c = load i32, i32* %b + ret i32 %c + } + + attributes #0 = { "no-frame-pointer-elim"="false" } + +... +--- +name: test +alignment: 4 +tracksRegLiveness: true +frameInfo: + stackSize: 4 + maxAlignment: 4 +fixedStack: + - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true } +stack: + - { id: 0, name: b, offset: -8, size: 4, alignment: 4 } +body: | + bb.0.entry: + frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp + CFI_INSTRUCTION .cfi_def_cfa_offset 8 + ; CHECK: name: test + ; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16) + %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16) + MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b) + %edx = POP32r implicit-def %esp, implicit %esp + RETL %eax +... diff --git a/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir b/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir new file mode 100644 index 000000000000..c4c57a1d2443 --- /dev/null +++ b/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir @@ -0,0 +1,28 @@ +# RUN: not llc -march=x86 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %a, i32 %b) #0 { + entry: + %c = add i32 %a, %b + ret i32 %c + } + + attributes #0 = { "no-frame-pointer-elim"="false" } + +... +--- +name: test +tracksRegLiveness: true +frameInfo: + maxAlignment: 4 +fixedStack: + - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } +# CHECK: [[@LINE+1]]:11: redefinition of fixed stack object '%fixed-stack.0' + - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +body: | + bb.0.entry: + %eax = MOV32rm %esp, 1, _, 4, _ + %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags + RETL %eax +... diff --git a/test/CodeGen/MIR/X86/fixed-stack-objects.mir b/test/CodeGen/MIR/X86/fixed-stack-objects.mir index dcbe6f73a6d0..70e5a7428359 100644 --- a/test/CodeGen/MIR/X86/fixed-stack-objects.mir +++ b/test/CodeGen/MIR/X86/fixed-stack-objects.mir @@ -25,11 +25,9 @@ fixedStack: - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false } stack: - { id: 0, offset: -8, size: 4, alignment: 4 } -body: - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %esp, 1, _, 8, _' - - 'MOV32mr %esp, 1, _, 0, _, %eax' - - 'RETL %eax' +body: | + bb.0.entry: + %eax = MOV32rm %esp, 1, _, 8, _ + MOV32mr %esp, 1, _, 0, _, %eax + RETL %eax ... diff --git a/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir b/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir new file mode 100644 index 000000000000..54fa8ad0b616 --- /dev/null +++ b/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir @@ -0,0 +1,73 @@ +# RUN: llc -march=x86-64 -enable-shrink-wrap=true -start-after shrink-wrap -stop-after shrink-wrap -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the save and restore points in +# the machine frame info correctly. + +--- | + + define i32 @foo(i32 %a, i32 %b) { + entry: + %tmp = alloca i32, align 4 + %tmp2 = icmp slt i32 %a, %b + br i1 %tmp2, label %true, label %false + + true: + store i32 %a, i32* %tmp, align 4 + %tmp4 = call i32 @doSomething(i32 0, i32* %tmp) + br label %false + + false: + %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %entry ] + ret i32 %tmp.0 + } + + declare i32 @doSomething(i32, i32*) + +... +--- +name: foo +tracksRegLiveness: true +liveins: + - { reg: '%edi' } + - { reg: '%esi' } +# CHECK: frameInfo: +# CHECK: savePoint: '%bb.2.true' +# CHECK-NEXT: restorePoint: '%bb.2.true' +# CHECK: stack +frameInfo: + maxAlignment: 4 + hasCalls: true + savePoint: '%bb.2.true' + restorePoint: '%bb.2.true' +stack: + - { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 } +body: | + bb.0: + successors: %bb.2.true, %bb.1 + liveins: %edi, %esi + + %eax = COPY %edi + CMP32rr %eax, killed %esi, implicit-def %eflags + JL_1 %bb.2.true, implicit killed %eflags + + bb.1: + successors: %bb.3.false + liveins: %eax + + JMP_1 %bb.3.false + + bb.2.true: + successors: %bb.3.false + liveins: %eax + + MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax + ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp + %rsi = LEA64r %stack.0.tmp, 1, _, 0, _ + %edi = MOV32r0 implicit-def dead %eflags + CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax + ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp + + bb.3.false: + liveins: %eax + + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/frame-info-stack-references.mir b/test/CodeGen/MIR/X86/frame-info-stack-references.mir new file mode 100644 index 000000000000..c8fa3bbe226f --- /dev/null +++ b/test/CodeGen/MIR/X86/frame-info-stack-references.mir @@ -0,0 +1,79 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the stack protector stack +# object reference in the machine frame info correctly. + +--- | + @.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 + @__stack_chk_guard = external global i8* + + define i32 @test() #0 { + entry: + %StackGuardSlot = alloca i8* + %StackGuard = load i8*, i8** @__stack_chk_guard + call void @llvm.stackprotector(i8* %StackGuard, i8** %StackGuardSlot) + %test = alloca i8*, align 8 + %a = alloca i8, i64 5 + store i8* %a, i8** %test, align 8 + %b = load i8*, i8** %test, align 8 + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %b) + call void @llvm.stackprotectorcheck(i8** @__stack_chk_guard) + ret i32 %call + } + + declare i32 @printf(i8*, ...) + + declare void @llvm.stackprotector(i8*, i8**) #1 + + declare void @llvm.stackprotectorcheck(i8**) #2 + + attributes #0 = { ssp "stack-protector-buffer-size"="5" } + attributes #1 = { nounwind } + attributes #2 = { nounwind argmemonly } +... +--- +name: test +alignment: 4 +tracksRegLiveness: true +frameInfo: + stackSize: 40 + maxAlignment: 8 + adjustsStack: true + hasCalls: true +# CHECK-LABEL: name: test +# CHECK: frameInfo +# CHECK: stackProtector: '%stack.0.StackGuardSlot' + stackProtector: '%stack.0.StackGuardSlot' +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, + callee-saved-register: '%rbx' } +stack: + - { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 } + - { id: 1, name: test, offset: -40, size: 8, alignment: 8 } + - { id: 2, name: a, offset: -29, size: 5, alignment: 1 } +body: | + bb.0.entry: + successors: %bb.1.entry, %bb.2.entry + liveins: %rbx, %rbx + + frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + %rsp = frame-setup SUB64ri8 %rsp, 32, implicit-def dead %eflags + %rbx = LOAD_STACK_GUARD :: (invariant load 8 from @__stack_chk_guard) + MOV64mr %rsp, 1, _, 24, _, %rbx + %rsi = LEA64r %rsp, 1, _, 19, _ + MOV64mr %rsp, 1, _, 8, _, %rsi + %rdi = LEA64r %rip, 1, _, @.str, _ + dead %eax = MOV32r0 implicit-def dead %eflags, implicit-def %al + CALL64pcrel32 @printf, csr_64, implicit %rsp, implicit %rdi, implicit %rsi, implicit %al, implicit-def %rsp, implicit-def %eax + CMP64rm killed %rbx, %rsp, 1, _, 24, _, implicit-def %eflags + JNE_1 %bb.2.entry, implicit %eflags + + bb.1.entry: + liveins: %eax + + %rsp = ADD64ri8 %rsp, 32, implicit-def dead %eflags + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax + + bb.2.entry: + CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp +... diff --git a/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir b/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir new file mode 100644 index 000000000000..87c1fc68046e --- /dev/null +++ b/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir @@ -0,0 +1,35 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the frame setup instruction flag. + +--- | + + define i32 @compute(i32 %a) { + body: + %c = mul i32 %a, 11 + ret i32 %c + } + + define i32 @foo(i32 %a) { + entry: + %b = call i32 @compute(i32 %a) + ret i32 %b + } + +... +--- +name: compute +body: | + bb.0.body: + %eax = IMUL32rri8 %edi, 11, implicit-def %eflags + RETQ %eax +... +--- +name: foo +body: | + bb.0.entry: + ; CHECK: frame-setup PUSH64r %rax + frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp + CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + %rdx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/function-liveins.mir b/test/CodeGen/MIR/X86/function-liveins.mir new file mode 100644 index 000000000000..95f8786b47a8 --- /dev/null +++ b/test/CodeGen/MIR/X86/function-liveins.mir @@ -0,0 +1,37 @@ +# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses machine function's liveins +# correctly. + +--- | + + define i32 @test(i32 %a, i32 %b) { + body: + %c = add i32 %a, %b + ret i32 %c + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr32 } + - { id: 2, class: gr32 } +# CHECK: liveins: +# CHECK-NEXT: - { reg: '%edi', virtual-reg: '%0' } +# CHECK-NEXT: - { reg: '%esi', virtual-reg: '%1' } +liveins: + - { reg: '%edi', virtual-reg: '%0' } + - { reg: '%esi', virtual-reg: '%1' } +body: | + bb.0.body: + liveins: %edi, %esi + + %1 = COPY %esi + %0 = COPY %edi + %2 = ADD32rr %0, %1, implicit-def dead %eflags + %eax = COPY %2 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/global-value-operands.mir b/test/CodeGen/MIR/X86/global-value-operands.mir index 3ea729b00554..394aa397aef4 100644 --- a/test/CodeGen/MIR/X86/global-value-operands.mir +++ b/test/CodeGen/MIR/X86/global-value-operands.mir @@ -20,30 +20,121 @@ ret i32 %b } + @.$0 = external global i32 + @-_- = external global i32 + @_-_a = external global i32 + @$.-B = external global i32 + + define i32 @test() { + entry: + %a = load i32, i32* @.$0 + store i32 %a, i32* @-_- + %b = load i32, i32* @_-_a + store i32 %b, i32* @$.-B + ret i32 %b + } + + @"\01Hello@$%09 \\ World," = external global i32 + + define i32 @test2() { + entry: + %a = load i32, i32* @"\01Hello@$%09 \\ World," + ret i32 %a + } + + define i32 @test3() { + entry: + %a = load i32, i32* @.$0 + store i32 %a, i32* @-_- + %b = load i32, i32* @_-_a + store i32 %b, i32* @$.-B + ret i32 %b + } + + define i32 @tf() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + ... --- # CHECK: name: inc name: inc -body: - - id: 0 - name: entry - instructions: - # CHECK: - '%rax = MOV64rm %rip, 1, _, @G, _' - - '%rax = MOV64rm %rip, 1, _, @G, _' - - '%eax = MOV32rm %rax, 1, _, 0, _' - - '%eax = INC32r %eax, implicit-def %eflags' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ + %rax = MOV64rm %rip, 1, _, @G, _ + %eax = MOV32rm %rax, 1, _, 0, _ + %eax = INC32r %eax, implicit-def %eflags + RETQ %eax ... --- # CHECK: name: inc2 name: inc2 -body: - - id: 0 - name: entry - instructions: - # CHECK: - '%rax = MOV64rm %rip, 1, _, @0, _' - - '%rax = MOV64rm %rip, 1, _, @0, _' - - '%eax = MOV32rm %rax, 1, _, 0, _' - - '%eax = INC32r %eax, implicit-def %eflags' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: %rax = MOV64rm %rip, 1, _, @0, _ + %rax = MOV64rm %rip, 1, _, @0, _ + %eax = MOV32rm %rax, 1, _, 0, _ + %eax = INC32r %eax, implicit-def %eflags + RETQ %eax +... +--- +name: test +body: | + bb.0.entry: + ; CHECK: , @".$0", + ; CHECK: , @-_-, + ; CHECK: , @_-_a, + ; CHECK: , @"$.-B", + %rax = MOV64rm %rip, 1, _, @.$0, _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + %rcx = MOV64rm %rip, 1, _, @-_-, _ + MOV32mr killed %rcx, 1, _, 0, _, killed %eax + %rax = MOV64rm %rip, 1, _, @_-_a, _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + %rcx = MOV64rm %rip, 1, _, @$.-B, _ + MOV32mr killed %rcx, 1, _, 0, _, %eax + RETQ %eax +... +--- +name: test2 +body: | + bb.0.entry: + ; CHECK: , @"\01Hello@$%09 \5C World,", + %rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + RETQ %eax +... +--- +# CHECK: name: test3 +name: test3 +body: | + bb.0.entry: + ; CHECK: , @".$0", + ; CHECK: , @-_-, + ; CHECK: , @_-_a + 4, + ; CHECK: , @"$.-B" - 8, + %rax = MOV64rm %rip, 1, _, @.$0 + 0, _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + %rcx = MOV64rm %rip, 1, _, @-_- - 0, _ + MOV32mr killed %rcx, 1, _, 0, _, killed %eax + %rax = MOV64rm %rip, 1, _, @_-_a + 4, _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + %rcx = MOV64rm %rip, 1, _, @$.-B - 8, _ + MOV32mr killed %rcx, 1, _, 0, _, %eax + RETQ %eax +... +--- +# CHECK: name: tf +name: tf +body: | + bb.0.entry: + ; CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _ + %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _ + %eax = MOV32rm %rax, 1, _, 0, _ + %eax = INC32r %eax, implicit-def %eflags + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/immediate-operands.mir b/test/CodeGen/MIR/X86/immediate-operands.mir index 5d4956f539dd..34bd0fa14904 100644 --- a/test/CodeGen/MIR/X86/immediate-operands.mir +++ b/test/CodeGen/MIR/X86/immediate-operands.mir @@ -17,24 +17,20 @@ --- # CHECK: name: foo name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: - '%eax = MOV32ri 42' - # CHECK-NEXT: - 'RETQ %eax' - - '%eax = MOV32ri 42' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: %eax = MOV32ri 42 + ; CHECK-NEXT: RETQ %eax + %eax = MOV32ri 42 + RETQ %eax ... --- # CHECK: name: bar name: bar -body: - - id: 0 - name: entry - instructions: - # CHECK: - '%eax = MOV32ri -11' - # CHECK-NEXT: - 'RETQ %eax' - - '%eax = MOV32ri -11' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: %eax = MOV32ri -11 + ; CHECK-NEXT: RETQ %eax + %eax = MOV32ri -11 + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/implicit-register-flag.mir b/test/CodeGen/MIR/X86/implicit-register-flag.mir index 9c6882d27bdc..b0a15ed93a8f 100644 --- a/test/CodeGen/MIR/X86/implicit-register-flag.mir +++ b/test/CodeGen/MIR/X86/implicit-register-flag.mir @@ -16,26 +16,53 @@ ret i32 %a } + define i1 @implicit_subregister1() { + entry: + ret i1 false + } + + define i16 @implicit_subregister2() { + entry: + ret i16 0 + } + ... --- name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: - 'CMP32ri8 %edi, 10, implicit-def %eflags' - # CHECK-NEXT: - 'JG_1 %bb.2.exit, implicit %eflags' - - 'CMP32ri8 %edi, 10, implicit-def %eflags' - - 'JG_1 %bb.2.exit, implicit %eflags' - - id: 1 - name: less - instructions: - # CHECK: - '%eax = MOV32r0 implicit-def %eflags' - - '%eax = MOV32r0 implicit-def %eflags' - - 'RETQ %eax' - - id: 2 - name: exit - instructions: - - '%eax = COPY %edi' - - 'RETQ %eax' +body: | + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + ; CHECK: CMP32ri8 %edi, 10, implicit-def %eflags + ; CHECK-NEXT: JG_1 %bb.2.exit, implicit %eflags + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit %eflags + + bb.1.less: + ; CHECK: %eax = MOV32r0 implicit-def %eflags + %eax = MOV32r0 implicit-def %eflags + RETQ %eax + + bb.2.exit: + %eax = COPY %edi + RETQ %eax +... +--- +name: implicit_subregister1 +body: | + bb.0.entry: + ; Verify that the implicit register verifier won't report an error on implicit + ; subregisters. + ; CHECK-LABEL: name: implicit_subregister1 + ; CHECK: dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al + dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al + RETQ killed %al +... +--- +name: implicit_subregister2 +body: | + bb.0.entry: + ; CHECK-LABEL: name: implicit_subregister2 + ; CHECK: dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w + dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w + RETQ killed %r15w ... diff --git a/test/CodeGen/MIR/X86/inline-asm-registers.mir b/test/CodeGen/MIR/X86/inline-asm-registers.mir new file mode 100644 index 000000000000..3fd565891091 --- /dev/null +++ b/test/CodeGen/MIR/X86/inline-asm-registers.mir @@ -0,0 +1,54 @@ +# RUN: llc -march=x86-64 -start-after block-placement -stop-after block-placement -o /dev/null %s | FileCheck %s + +--- | + define i64 @test(i64 %x, i64 %y) #0 { + entry: + %x0 = call { i64, i64 } asm "foo", "=r,=r,1,0,~{dirflag},~{fpsr},~{flags}"(i64 %x, i64 %y) #0 + %x1 = extractvalue { i64, i64 } %x0, 0 + ret i64 %x1 + } + + define i64 @test2(i64 %x, i64 %y) #0 { + entry: + %x0 = call { i64, i64 } asm "foo", "=r,=r,1,0,~{dirflag},~{fpsr},~{flags}"(i64 %x, i64 %y) #0 + %x1 = extractvalue { i64, i64 } %x0, 0 + ret i64 %x1 + } + + attributes #0 = { nounwind } +... +--- +name: test +hasInlineAsm: true +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + liveins: %rdi, %rsi + + ; CHECK-LABEL: name: test + ; CHECK: INLINEASM $foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, + INLINEASM $foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi, 2147483657, killed %rsi, 12, implicit-def dead early-clobber %eflags + %rax = MOV64rr killed %rsi + RETQ killed %rax +... +--- +name: test2 +hasInlineAsm: true +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + liveins: %rdi, %rsi + + ; Verify that the register ties are preserved. + ; CHECK-LABEL: name: test2 + ; CHECK: INLINEASM $foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi(tied-def 5), 2147483657, killed %rsi(tied-def 3), 12, implicit-def dead early-clobber %eflags + INLINEASM $foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi(tied-def 5), 2147483657, killed %rsi(tied-def 3), 12, implicit-def dead early-clobber %eflags + %rax = MOV64rr killed %rsi + RETQ killed %rax +... diff --git a/test/CodeGen/MIR/X86/instructions-debug-location.mir b/test/CodeGen/MIR/X86/instructions-debug-location.mir new file mode 100644 index 000000000000..ea2cdbf7cb2f --- /dev/null +++ b/test/CodeGen/MIR/X86/instructions-debug-location.mir @@ -0,0 +1,98 @@ +# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the machine instruction's +# debug location metadata correctly. + +--- | + + define i32 @test(i32 %x) #0 !dbg !4 { + entry: + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !12, metadata !13), !dbg !14 + %0 = load i32, i32* %x.addr, align 4, !dbg !15 + ret i32 %0, !dbg !15 + } + + define i32 @test_typed_immediates(i32 %x) #0 { + entry: + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !12, metadata !13), !dbg !14 + %0 = load i32, i32* %x.addr, align 4, !dbg !15 + ret i32 %0, !dbg !15 + } + + declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + + attributes #0 = { nounwind "no-frame-pointer-elim"="false" } + attributes #1 = { nounwind readnone } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!9, !10} + !llvm.ident = !{!11} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !1 = !DIFile(filename: "test.ll", directory: "") + !2 = !{} + !3 = !{!4} + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !5 = !DIFile(filename: "test.c", directory: "") + !6 = !DISubroutineType(types: !7) + !7 = !{!8, !8} + !8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !9 = !{i32 2, !"Dwarf Version", i32 4} + !10 = !{i32 2, !"Debug Info Version", i32 3} + !11 = !{!"clang version 3.7.0"} + !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8) + !13 = !DIExpression() + !14 = !DILocation(line: 4, scope: !4) + !15 = !DILocation(line: 8, scope: !4) + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, name: x.addr, size: 4, alignment: 4 } +body: | + bb.0.entry: + liveins: %edi + ; CHECK: DBG_VALUE debug-use _, 0, !12, !13, debug-location !14 + ; CHECK: %eax = COPY %0, debug-location !15 + ; CHECK: RETQ %eax, debug-location !15 + %0 = COPY %edi + DBG_VALUE debug-use _, 0, !12, !13, debug-location !14 + MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 + %eax = COPY %0, debug-location !15 + RETQ %eax, debug-location !15 +... +--- +name: test_typed_immediates +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, name: x.addr, size: 4, alignment: 4 } +body: | + bb.0.entry: + liveins: %edi + + %0 = COPY %edi + ; CHECK: DBG_VALUE _, i32 0, !12, !13 + ; CHECK-NEXT: DBG_VALUE _, i64 -22, !12, !13 + ; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13 + DBG_VALUE _, i32 0, !12, !13 + DBG_VALUE _, i64 -22, !12, !13 + DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13 + MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir b/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir new file mode 100644 index 000000000000..afd6c78546ce --- /dev/null +++ b/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that the MIR parser reports an error when parsing an invalid +# constant pool item operand. + +--- | + + define double @test(double %a, float %b) { + entry: + %c = fadd double %a, 3.250000e+00 + ret double %c + } + +... +--- +name: test +constants: + - id: 0 + value: 'double 3.250000e+00' +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:47: use of undefined constant '%const.10' + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _ + RETQ %xmm0 +... + diff --git a/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir b/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir new file mode 100644 index 000000000000..a6c2e509da0c --- /dev/null +++ b/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir @@ -0,0 +1,53 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +--- | + declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 + + define void @foo() #1 { + entry: + %x.i = alloca i8, align 1 + %y.i = alloca [256 x i8], align 16 + %0 = bitcast [256 x i8]* %y.i to i8* + br label %for.body + + for.body: + %1 = bitcast [256 x i8]* %y.i to i8* + call void @llvm.dbg.declare(metadata i8* %0, metadata !4, metadata !7) #3, !dbg !8 + br label %for.body + } + + attributes #0 = { nounwind readnone } + attributes #1 = { nounwind ssp uwtable } + attributes #3 = { nounwind } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!3} + + !0 = distinct !DICompileUnit(language: DW_LANG_C89, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: 0, enums: !2, retainedTypes: !2) + !1 = !DIFile(filename: "t.c", directory: "") + !2 = !{} + !3 = !{i32 1, !"Debug Info Version", i32 3} + !4 = !DILocalVariable(name: "x", scope: !5, file: !1, line: 16, type: !6) + !5 = distinct !DISubprogram(scope: null, isLocal: false, isDefinition: true, isOptimized: false) + !6 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) + !7 = !DIExpression() + !8 = !DILocation(line: 0, scope: !5) +... +--- +name: foo +isSSA: true +tracksRegLiveness: true +frameInfo: + maxAlignment: 16 +stack: +# CHECK: [[@LINE+1]]:75: expected a reference to a 'DILocalVariable' metadata node + - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!8', + di-expression: '!7', di-location: '!8' } +body: | + bb.0.entry: + successors: %bb.1.for.body + bb.1.for.body: + successors: %bb.1.for.body + + DBG_VALUE %stack.0.y.i, 0, !4, !7, debug-location !8 + JMP_1 %bb.1.for.body +... diff --git a/test/CodeGen/MIR/X86/invalid-target-flag-name.mir b/test/CodeGen/MIR/X86/invalid-target-flag-name.mir new file mode 100644 index 000000000000..313c5bdafed8 --- /dev/null +++ b/test/CodeGen/MIR/X86/invalid-target-flag-name.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @G = external global i32 + + define i32 @inc() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + +... +--- +name: inc +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:45: use of undefined target flag 'x86-test' + %rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + %eax = INC32r killed %eax, implicit-def dead %eflags + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir b/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir new file mode 100644 index 000000000000..00436adca484 --- /dev/null +++ b/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +--- | + define i64 @test(i64 %x) #0 { + entry: + %asm = tail call i64 asm sideeffect "$foo", "=r,0"(i64 %x) nounwind + ret i64 %asm + } + + attributes #0 = { nounwind } +... +--- +name: test +hasInlineAsm: true +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + + ; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '300'; instruction has only 6 operands + INLINEASM $"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 300) + %rax = COPY killed %rdi + RETQ killed %rax +... diff --git a/test/CodeGen/MIR/X86/jump-table-info.mir b/test/CodeGen/MIR/X86/jump-table-info.mir new file mode 100644 index 000000000000..a4e6f6a1728c --- /dev/null +++ b/test/CodeGen/MIR/X86/jump-table-info.mir @@ -0,0 +1,150 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the jump table info and jump +# table operands correctly. + +--- | + + define i32 @test_jumptable(i32 %in) { + entry: + switch i32 %in, label %def [ + i32 0, label %lbl1 + i32 1, label %lbl2 + i32 2, label %lbl3 + i32 3, label %lbl4 + ] + + def: + ret i32 0 + + lbl1: + ret i32 1 + + lbl2: + ret i32 2 + + lbl3: + ret i32 4 + + lbl4: + ret i32 8 + } + + define i32 @test_jumptable2(i32 %in) { + entry: + switch i32 %in, label %def [ + i32 0, label %lbl1 + i32 1, label %lbl2 + i32 2, label %lbl3 + i32 3, label %lbl4 + ] + + def: + ret i32 0 + + lbl1: + ret i32 1 + + lbl2: + ret i32 2 + + lbl3: + ret i32 4 + + lbl4: + ret i32 8 + } + +... +--- +name: test_jumptable +# CHECK: jumpTable: +# CHECK-NEXT: kind: label-difference32 +# CHECK-NEXT: entries: +# CHECK-NEXT: - id: 0 +# CHECK-NEXT: blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +# CHECK_NEXT: body: +jumpTable: + kind: label-difference32 + entries: + - id: 0 + blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +body: | + bb.0.entry: + successors: %bb.2.def, %bb.1.entry + + %eax = MOV32rr %edi, implicit-def %rax + CMP32ri8 %edi, 3, implicit-def %eflags + JA_1 %bb.2.def, implicit %eflags + + bb.1.entry: + successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 + ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _ + %rcx = LEA64r %rip, 1, _, %jump-table.0, _ + %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ + %rax = ADD64rr %rax, %rcx, implicit-def %eflags + JMP64r %rax + + bb.2.def: + %eax = MOV32r0 implicit-def %eflags + RETQ %eax + + bb.3.lbl1: + %eax = MOV32ri 1 + RETQ %eax + + bb.4.lbl2: + %eax = MOV32ri 2 + RETQ %eax + + bb.5.lbl3: + %eax = MOV32ri 4 + RETQ %eax + + bb.6.lbl4: + %eax = MOV32ri 8 + RETQ %eax +... +--- +name: test_jumptable2 +jumpTable: + kind: label-difference32 + entries: + - id: 1 + blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +body: | + bb.0.entry: + successors: %bb.2.def, %bb.1.entry + + %eax = MOV32rr %edi, implicit-def %rax + CMP32ri8 %edi, 3, implicit-def %eflags + JA_1 %bb.2.def, implicit %eflags + + bb.1.entry: + successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 + ; Verify that the printer will use an id of 0 for this jump table: + ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _ + %rcx = LEA64r %rip, 1, _, %jump-table.1, _ + %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ + %rax = ADD64rr %rax, %rcx, implicit-def %eflags + JMP64r %rax + + bb.2.def: + %eax = MOV32r0 implicit-def %eflags + RETQ %eax + + bb.3.lbl1: + %eax = MOV32ri 1 + RETQ %eax + + bb.4.lbl2: + %eax = MOV32ri 2 + RETQ %eax + + bb.5.lbl3: + %eax = MOV32ri 4 + RETQ %eax + + bb.6.lbl4: + %eax = MOV32ri 8 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir b/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir new file mode 100644 index 000000000000..d4ab11f40787 --- /dev/null +++ b/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir @@ -0,0 +1,76 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test_jumptable(i32 %in) { + entry: + switch i32 %in, label %def [ + i32 0, label %lbl1 + i32 1, label %lbl2 + i32 2, label %lbl3 + i32 3, label %lbl4 + ] + + def: + ret i32 0 + + lbl1: + ret i32 1 + + lbl2: + ret i32 2 + + lbl3: + ret i32 4 + + lbl4: + ret i32 8 + } + +... +--- +name: test_jumptable +jumpTable: + kind: label-difference32 + entries: + - id: 0 + blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +# CHECK: [[@LINE+1]]:18: redefinition of jump table entry '%jump-table.0' + - id: 0 + blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +body: | + bb.0.entry: + successors: %bb.2.def, %bb.1.entry + + %eax = MOV32rr %edi, implicit-def %rax + CMP32ri8 %edi, 3, implicit-def %eflags + JA_1 %bb.2.def, implicit %eflags + + bb.1.entry: + successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 + + %rcx = LEA64r %rip, 1, _, %jump-table.0, _ + %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ + %rax = ADD64rr %rax, %rcx, implicit-def %eflags + JMP64r %rax + + bb.2.def: + %eax = MOV32r0 implicit-def %eflags + RETQ %eax + + bb.3.lbl1: + %eax = MOV32ri 1 + RETQ %eax + + bb.4.lbl2: + %eax = MOV32ri 2 + RETQ %eax + + bb.5.lbl3: + %eax = MOV32ri 4 + RETQ %eax + + bb.6.lbl4: + %eax = MOV32ri 8 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/killed-register-flag.mir b/test/CodeGen/MIR/X86/killed-register-flag.mir index d654a9d2fa56..9e8f3ba3b368 100644 --- a/test/CodeGen/MIR/X86/killed-register-flag.mir +++ b/test/CodeGen/MIR/X86/killed-register-flag.mir @@ -19,24 +19,22 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - - 'CMP32ri8 %edi, 10, implicit-def %eflags' - - 'JG_1 %bb.2.exit, implicit %eflags' - - id: 1 - name: less - instructions: - # CHECK: - '%eax = MOV32r0 - # CHECK-NEXT: - 'RETQ killed %eax - - '%eax = MOV32r0 implicit-def %eflags' - - 'RETQ killed %eax' - - id: 2 - name: exit - instructions: - # CHECK: - '%eax = COPY killed %edi - # CHECK-NEXT: - 'RETQ killed %eax - - '%eax = COPY killed %edi' - - 'RETQ killed %eax' +body: | + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit %eflags + + bb.1.less: + ; CHECK: %eax = MOV32r0 + ; CHECK-NEXT: RETQ killed %eax + %eax = MOV32r0 implicit-def %eflags + RETQ killed %eax + + bb.2.exit: + ; CHECK: %eax = COPY killed %edi + ; CHECK-NEXT: RETQ killed %eax + %eax = COPY killed %edi + RETQ killed %eax ... diff --git a/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir b/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir new file mode 100644 index 000000000000..93ce30abec7c --- /dev/null +++ b/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir @@ -0,0 +1,27 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define void @test() { + entry: + %tmp = alloca [4168 x i8], align 4 + ret void + } + +... +--- +name: test +tracksRegLiveness: true +frameInfo: + stackSize: 4040 +stack: + - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 } +body: | + bb.0.entry: + %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags + ; CHECK: [[@LINE+1]]:41: expected a 32 bit integer (the cfi offset is too large) + CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456 + %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags + RETQ +... + diff --git a/test/CodeGen/MIR/X86/large-immediate-operand-error.mir b/test/CodeGen/MIR/X86/large-immediate-operand-error.mir new file mode 100644 index 000000000000..f815c63e18e9 --- /dev/null +++ b/test/CodeGen/MIR/X86/large-immediate-operand-error.mir @@ -0,0 +1,18 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @foo() { + entry: + ret i32 42 + } + +... +--- +name: foo +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:20: integer literal is too large to be an immediate operand + %eax = MOV32ri 12346127502983478823754212949184914 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/large-index-number-error.mir b/test/CodeGen/MIR/X86/large-index-number-error.mir index fdb25c907f52..272cd685b381 100644 --- a/test/CodeGen/MIR/X86/large-index-number-error.mir +++ b/test/CodeGen/MIR/X86/large-index-number-error.mir @@ -18,18 +18,16 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - - 'CMP32ri8 %eax, 10, implicit-def %eflags' - # CHECK: [[@LINE+1]]:14: expected 32-bit integer (too large) - - 'JG_1 %bb.123456789123456, implicit %eflags' - - id: 1 - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 2 - instructions: - - 'RETQ %eax' +body: | + bb.0.entry: + %eax = MOV32rm %rdi, 1, _, 0, _ + CMP32ri8 %eax, 10, implicit-def %eflags + ; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large) + JG_1 %bb.123456789123456, implicit %eflags + + bb.1: + %eax = MOV32r0 implicit-def %eflags + + bb.2: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/large-offset-number-error.mir b/test/CodeGen/MIR/X86/large-offset-number-error.mir new file mode 100644 index 000000000000..5463cdbce444 --- /dev/null +++ b/test/CodeGen/MIR/X86/large-offset-number-error.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @G = external global i32 + + define i32 @inc() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + +... +--- +name: inc +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:37: expected 64-bit integer (too large) + %rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _ + %eax = MOV32rm %rax, 1, _, 0, _ + %eax = INC32r %eax implicit-def %eflags + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir b/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir new file mode 100644 index 000000000000..c570f0992a3f --- /dev/null +++ b/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32* %a) { + entry: + %b = load i32, i32* %a + ret i32 %b + } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:53: expected 64-bit integer (too large) + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a) + RETQ %eax +... + diff --git a/test/CodeGen/MIR/X86/liveout-register-mask.mir b/test/CodeGen/MIR/X86/liveout-register-mask.mir new file mode 100644 index 000000000000..7ded7287060e --- /dev/null +++ b/test/CodeGen/MIR/X86/liveout-register-mask.mir @@ -0,0 +1,42 @@ +# RUN: llc -march=x86-64 -start-after stackmap-liveness -stop-after stackmap-liveness -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the liveout register mask +# machine operands correctly. + +--- | + + define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { + entry: + %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2) + ret void + } + + declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) + +... +--- +name: small_patchpoint_codegen +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +frameInfo: + hasPatchPoint: true + stackSize: 8 + adjustsStack: true + hasCalls: true +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 } +body: | + bb.0.entry: + liveins: %rdi, %rsi, %rbp + + frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp + CFI_INSTRUCTION .cfi_def_cfa_offset 16 + CFI_INSTRUCTION .cfi_offset %rbp, -16 + %rbp = frame-setup MOV64rr %rsp + CFI_INSTRUCTION .cfi_def_cfa_register %rbp + ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), + PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax + %rbp = POP64r implicit-def %rsp, implicit %rsp + RETQ +... diff --git a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir index 607acb5f273e..0d7a9f8ef34c 100644 --- a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir +++ b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir @@ -33,43 +33,41 @@ --- # CHECK: name: foo name: foo -body: - # CHECK: name: entry - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - # CHECK: - 'CMP32ri8 %eax, 10 - # CHECK-NEXT: - 'JG_1 %bb.2.exit - - 'CMP32ri8 %eax, 10, implicit-def %eflags' - - 'JG_1 %bb.2.exit, implicit %eflags' - # CHECK: name: less - - id: 1 - name: less - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 2 - name: exit - instructions: - - 'RETQ %eax' +body: | + ; CHECK: bb.0.entry + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + + %eax = MOV32rm %rdi, 1, _, 0, _ + ; CHECK: CMP32ri8 %eax, 10 + ; CHECK-NEXT: JG_1 %bb.2.exit + CMP32ri8 %eax, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit %eflags + ; CHECK: bb.1.less: + + bb.1.less: + %eax = MOV32r0 implicit-def %eflags + + bb.2.exit: + RETQ %eax ... --- # CHECK: name: bar name: bar -body: - # CHECK: name: entry - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - # CHECK: - 'CMP32ri8 %eax, 10 - # CHECK-NEXT: - 'JG_1 %bb.2 - - 'CMP32ri8 %eax, 10, implicit-def %eflags' - - 'JG_1 %bb.3, implicit %eflags' - - id: 1 - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 3 - instructions: - - 'RETQ %eax' +body: | + ; CHECK: bb.0.entry: + bb.0.entry: + successors: %bb.1, %bb.3 + + %eax = MOV32rm %rdi, 1, _, 0, _ + ; CHECK: CMP32ri8 %eax, 10 + ; CHECK-NEXT: JG_1 %bb.2 + CMP32ri8 %eax, 10, implicit-def %eflags + JG_1 %bb.3, implicit %eflags + + bb.1: + %eax = MOV32r0 implicit-def %eflags + + bb.3: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/machine-instructions.mir b/test/CodeGen/MIR/X86/machine-instructions.mir index 08f3d76486b1..0e46d01e0bd1 100644 --- a/test/CodeGen/MIR/X86/machine-instructions.mir +++ b/test/CodeGen/MIR/X86/machine-instructions.mir @@ -14,12 +14,10 @@ --- # CHECK: name: inc name: inc -body: - - id: 0 - name: entry - instructions: - # CHECK: - MOV32rr - # CHECK-NEXT: - RETQ - - MOV32rr - - ' RETQ ' +body: | + bb.0.entry: + ; CHECK: MOV32rr + ; CHECK-NEXT: RETQ + %eax = MOV32rr %eax + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/machine-verifier.mir b/test/CodeGen/MIR/X86/machine-verifier.mir new file mode 100644 index 000000000000..a7413d4d03bc --- /dev/null +++ b/test/CodeGen/MIR/X86/machine-verifier.mir @@ -0,0 +1,22 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that the MIR parser runs the machine verifier after parsing. + +--- | + + define i32 @inc(i32 %a) { + entry: + ret i32 %a + } + +... +--- +name: inc +body: | + bb.0.entry: + liveins: %edi + ; CHECK: *** Bad machine code: Too few operands *** + ; CHECK: instruction: COPY + ; CHECK: 2 operands expected, but 0 given. + COPY + RETQ +... diff --git a/test/CodeGen/MIR/X86/memory-operands.mir b/test/CodeGen/MIR/X86/memory-operands.mir new file mode 100644 index 000000000000..3c9463d2f313 --- /dev/null +++ b/test/CodeGen/MIR/X86/memory-operands.mir @@ -0,0 +1,508 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the machine memory operands +# correctly. + +--- | + + define i32 @test(i32* %a) { + entry: + %b = load i32, i32* %a + store i32 42, i32* %a + ret i32 %b + } + + define void @test2(i32* %"a value") { + entry2: + %b = load i32, i32* %"a value" + %c = add i32 %b, 1 + store i32 %c, i32* %"a value" + ret void + } + + define void @test3(i32*) { + entry3: + %1 = alloca i32 + %b = load i32, i32* %0 + %c = add i32 %b, 1 + store i32 %c, i32* %1 + ret void + } + + define i32 @volatile_inc(i32* %x) { + entry: + %0 = load volatile i32, i32* %x + %1 = add i32 %0, 1 + store volatile i32 %1, i32* %x + ret i32 %1 + } + + define void @non_temporal_store(i32* %a, i32 %b) { + entry: + store i32 %b, i32* %a, align 16, !nontemporal !0 + ret void + } + + !0 = !{i32 1} + + define i32 @invariant_load(i32* %x) { + entry: + %v = load i32, i32* %x, !invariant.load !1 + ret i32 %v + } + + !1 = !{} + + define void @memory_offset(<8 x float>* %vec) { + entry: + %v = load <8 x float>, <8 x float>* %vec + %v2 = insertelement <8 x float> %v, float 0.0, i32 4 + store <8 x float> %v2, <8 x float>* %vec + ret void + } + + define void @memory_alignment(<8 x float>* %vec) { + entry: + %v = load <8 x float>, <8 x float>* %vec + %v2 = insertelement <8 x float> %v, float 0.0, i32 4 + store <8 x float> %v2, <8 x float>* %vec + ret void + } + + define double @constant_pool_psv(double %a) { + entry: + %b = fadd double %a, 3.250000e+00 + ret double %b + } + + declare x86_fp80 @cosl(x86_fp80) #0 + + define x86_fp80 @stack_psv(x86_fp80 %x) { + entry: + %y = call x86_fp80 @cosl(x86_fp80 %x) #0 + ret x86_fp80 %y + } + + attributes #0 = { readonly } + + @G = external global i32 + + define i32 @got_psv() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + + @0 = external global i32 + + define i32 @global_value() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + %c = load i32, i32* @0 + %d = add i32 %b, %c + ret i32 %d + } + + define i32 @jumptable_psv(i32 %in) { + entry: + switch i32 %in, label %def [ + i32 0, label %lbl1 + i32 1, label %lbl2 + i32 2, label %lbl3 + i32 3, label %lbl4 + ] + def: + ret i32 0 + lbl1: + ret i32 1 + lbl2: + ret i32 2 + lbl3: + ret i32 4 + lbl4: + ret i32 8 + } + + %struct.XXH_state64_t = type { i32, i32, i64, i64, i64 } + + @a = common global i32 0, align 4 + + define i32 @tbaa_metadata() { + entry: + %0 = load i32, i32* @a, align 4, !tbaa !2 + %1 = inttoptr i32 %0 to %struct.XXH_state64_t* + %total_len2 = bitcast %struct.XXH_state64_t* %1 to i32* + %2 = load i32, i32* %total_len2, align 4, !tbaa !6 + ret i32 %2 + } + + !2 = !{!3, !3, i64 0} + !3 = !{!"int", !4, i64 0} + !4 = !{!"omnipotent char", !5, i64 0} + !5 = !{!"Simple C/C++ TBAA"} + !6 = !{!7, !3, i64 0} + !7 = !{!"XXH_state64_t", !3, i64 0, !3, i64 4, !8, i64 8, !8, i64 16, !8, i64 24} + !8 = !{!"long long", !4, i64 0} + + define void @aa_scope(float* nocapture %a, float* nocapture readonly %c) #1 { + entry: + %0 = load float, float* %c, align 4, !alias.scope !9 + %arrayidx.i = getelementptr inbounds float, float* %a, i64 5 + store float %0, float* %arrayidx.i, align 4, !noalias !9 + %1 = load float, float* %c, align 4 + %arrayidx = getelementptr inbounds float, float* %a, i64 7 + store float %1, float* %arrayidx, align 4 + ret void + } + + attributes #1 = { nounwind uwtable } + + !9 = distinct !{!9, !10, !"some scope"} + !10 = distinct !{!10, !"some domain"} + + define zeroext i1 @range_metadata(i8* %x) { + entry: + %0 = load i8, i8* %x, align 1, !range !11 + %tobool = trunc i8 %0 to i1 + ret i1 %tobool + } + + !11 = !{i8 0, i8 2} + + %st = type { i32, i32 } + + @values = common global [50 x %st] zeroinitializer, align 16 + + define void @gep_value(i64 %d) { + entry: + %conv = trunc i64 %d to i32 + store i32 %conv, i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0), align 16 + ret void + } + + define i8* @undef_value() { + entry: + %0 = load i8*, i8** undef, align 8 + ret i8* %0 + } +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a) + ; CHECK-NEXT: MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a) + %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a) + MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a) + RETQ %eax +... +--- +name: test2 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry2: + liveins: %rdi + ; CHECK: INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") + INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") + RETQ +... +--- +name: test3 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, offset: -12, size: 4, alignment: 4 } +body: | + bb.0.entry3: + liveins: %rdi + ; Verify that the unnamed local values can be serialized. + ; CHECK-LABEL: name: test3 + ; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0) + ; CHECK: MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1) + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0) + %eax = INC32r killed %eax, implicit-def dead %eflags + MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1) + RETQ +... +--- +name: volatile_inc +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: name: volatile_inc + ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x) + ; CHECK: MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) + %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x) + %eax = INC32r killed %eax, implicit-def dead %eflags + MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) + RETQ %eax +... +--- +name: non_temporal_store +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%esi' } +body: | + bb.0.entry: + liveins: %esi, %rdi + ; CHECK: name: non_temporal_store + ; CHECK: MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a) + MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a) + RETQ +... +--- +name: invariant_load +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: name: invariant_load + ; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x) + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x) + RETQ %eax +... +--- +name: memory_offset +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: name: memory_offset + ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec) + ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16) + ; CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec) + ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16) + %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec) + %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16) + %xmm2 = FsFLD0SS + %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 + MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec) + MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16) + RETQ +... +--- +name: memory_alignment +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: name: memory_alignment + ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32) + ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + ; CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) + ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32) + %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + %xmm2 = FsFLD0SS + %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 + MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + RETQ +... +--- +name: constant_pool_psv +tracksRegLiveness: true +liveins: + - { reg: '%xmm0' } +constants: + - id: 0 + value: 'double 3.250000e+00' +body: | + bb.0.entry: + liveins: %xmm0 + ; CHECK: name: constant_pool_psv + ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool) + ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8) + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool) + %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8) + RETQ %xmm0 +... +--- +name: stack_psv +tracksRegLiveness: true +frameInfo: + stackSize: 24 + maxAlignment: 16 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 16 +fixedStack: + - { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false } +body: | + bb.0.entry: + %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags + CFI_INSTRUCTION .cfi_def_cfa_offset 32 + LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw + ; CHECK: name: stack_psv + ; CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16) + ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16) + CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0 + %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags + RETQ +... +--- +name: got_psv +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK: name: got_psv + ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got) + %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got) + %eax = MOV32rm killed %rax, 1, _, 0, _ + %eax = INC32r killed %eax, implicit-def dead %eflags + RETQ %eax +... +--- +name: global_value +tracksRegLiveness: true +body: | + bb.0.entry: + %rax = MOV64rm %rip, 1, _, @G, _ + ; CHECK-LABEL: name: global_value + ; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G) + ; CHECK: %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0) + %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G) + %rcx = MOV64rm %rip, 1, _, @0, _ + %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0) + %eax = LEA64_32r killed %rax, 1, killed %rcx, 1, _ + RETQ %eax +... +--- +name: jumptable_psv +tracksRegLiveness: true +liveins: + - { reg: '%edi' } +jumpTable: + kind: label-difference32 + entries: + - id: 0 + blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +body: | + bb.0.entry: + successors: %bb.2.def, %bb.1.entry + liveins: %edi + + %eax = MOV32rr %edi, implicit-def %rax + CMP32ri8 killed %edi, 3, implicit-def %eflags + JA_1 %bb.2.def, implicit killed %eflags + + bb.1.entry: + successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 + liveins: %rax + + %rcx = LEA64r %rip, 1, _, %jump-table.0, _ + ; CHECK: name: jumptable_psv + ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8) + %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8) + %rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags + JMP64r killed %rax + + bb.2.def: + %eax = MOV32r0 implicit-def dead %eflags + RETQ %eax + + bb.3.lbl1: + %eax = MOV32ri 1 + RETQ %eax + + bb.4.lbl2: + %eax = MOV32ri 2 + RETQ %eax + + bb.5.lbl3: + %eax = MOV32ri 4 + RETQ %eax + + bb.6.lbl4: + %eax = MOV32ri 8 + RETQ %eax +... +--- +name: tbaa_metadata +tracksRegLiveness: true +body: | + bb.0.entry: + %rax = MOV64rm %rip, 1, _, @a, _ :: (load 8 from got) + ; CHECK-LABEL: name: tbaa_metadata + ; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2) + ; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6) + %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2) + %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6) + RETQ %eax +... +--- +name: aa_scope +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + liveins: %rdi, %rsi + ; CHECK-LABEL: name: aa_scope + ; CHECK: %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9) + %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9) + ; CHECK-NEXT: MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) + MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) + %xmm0 = MOVSSrm killed %rsi, 1, _, 0, _ :: (load 4 from %ir.c) + MOVSSmr killed %rdi, 1, _, 28, _, killed %xmm0 :: (store 4 into %ir.arrayidx) + RETQ +... +--- +name: range_metadata +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK-LABEL: name: range_metadata + ; CHECK: %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11) + %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11) + RETQ %al +... +--- +name: gep_value +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + + %rax = MOV64rm %rip, 1, _, @values, _ :: (load 8 from got) + ; CHECK-LABEL: gep_value + ; CHECK: MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) + MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) + RETQ +... +--- +name: undef_value +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: undef_value + ; CHECK: %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`) + %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`) + RETQ %rax +... diff --git a/test/CodeGen/MIR/X86/metadata-operands.mir b/test/CodeGen/MIR/X86/metadata-operands.mir new file mode 100644 index 000000000000..89a1e6fcb815 --- /dev/null +++ b/test/CodeGen/MIR/X86/metadata-operands.mir @@ -0,0 +1,63 @@ +# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the metadata machine operands +# correctly. + +--- | + + define i32 @test(i32 %x) #0 !dbg !4 { + entry: + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !12, metadata !13), !dbg !14 + %0 = load i32, i32* %x.addr, align 4, !dbg !15 + ret i32 %0, !dbg !15 + } + + declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + + attributes #0 = { nounwind "no-frame-pointer-elim"="false" } + attributes #1 = { nounwind readnone } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!9, !10} + !llvm.ident = !{!11} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !1 = !DIFile(filename: "test.ll", directory: "") + !2 = !{} + !3 = !{!4} + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !5 = !DIFile(filename: "test.c", directory: "") + !6 = !DISubroutineType(types: !7) + !7 = !{!8, !8} + !8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !9 = !{i32 2, !"Dwarf Version", i32 4} + !10 = !{i32 2, !"Debug Info Version", i32 3} + !11 = !{!"clang version 3.7.0"} + !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8) + !13 = !DIExpression() + !14 = !DILocation(line: 4, scope: !4) + !15 = !DILocation(line: 8, scope: !4) + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, name: x.addr, size: 4, alignment: 4 } +body: | + bb.0.entry: + liveins: %edi + ; CHECK: %0 = COPY %edi + ; CHECK-NEXT: DBG_VALUE _, 0, !12, !13 + %0 = COPY %edi + DBG_VALUE _, 0, !12, ! 13 + MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/missing-closing-quote.mir b/test/CodeGen/MIR/X86/missing-closing-quote.mir new file mode 100644 index 000000000000..9f4b369a3df4 --- /dev/null +++ b/test/CodeGen/MIR/X86/missing-closing-quote.mir @@ -0,0 +1,22 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @"quoted name" = external global i32 + + define i32 @test() { + entry: + %a = load i32, i32* @"quoted name" + ret i32 %a + } + +... +--- +name: test +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:48: end of machine instruction reached before the closing '"' + %rax = MOV64rm %rip, 1, _, @"quoted name, _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/missing-comma.mir b/test/CodeGen/MIR/X86/missing-comma.mir index 54c67ac6c911..092995e59c70 100644 --- a/test/CodeGen/MIR/X86/missing-comma.mir +++ b/test/CodeGen/MIR/X86/missing-comma.mir @@ -10,12 +10,10 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:29: expected ',' before the next machine operand - - '%eax = XOR32rr %eax %eflags' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:25: expected ',' before the next machine operand + %eax = XOR32rr %eax %eflags + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/missing-implicit-operand.mir b/test/CodeGen/MIR/X86/missing-implicit-operand.mir index 4d2cd03f4a3d..0135c756e138 100644 --- a/test/CodeGen/MIR/X86/missing-implicit-operand.mir +++ b/test/CodeGen/MIR/X86/missing-implicit-operand.mir @@ -21,20 +21,18 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - - 'CMP32ri8 %eax, 10, implicit-def %eflags' -# CHECK: [[@LINE+1]]:24: missing implicit register operand 'implicit %eflags' - - 'JG_1 %bb.2.exit' - - id: 1 - name: less - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 2 - name: exit - instructions: - - 'RETQ %eax' +body: | + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + + %eax = MOV32rm %rdi, 1, _, 0, _ + CMP32ri8 %eax, 10, implicit-def %eflags + ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit %eflags' + JG_1 %bb.2.exit + + bb.1.less: + %eax = MOV32r0 implicit-def %eflags + + bb.2.exit: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/missing-instruction.mir b/test/CodeGen/MIR/X86/missing-instruction.mir deleted file mode 100644 index 8d11ab5eaabe..000000000000 --- a/test/CodeGen/MIR/X86/missing-instruction.mir +++ /dev/null @@ -1,19 +0,0 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s - ---- | - - define void @foo() { - entry: - ret void - } - -... ---- -name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:9: expected a machine instruction - - '' -... diff --git a/test/CodeGen/MIR/X86/named-registers.mir b/test/CodeGen/MIR/X86/named-registers.mir index 91ed48568678..e547c326563e 100644 --- a/test/CodeGen/MIR/X86/named-registers.mir +++ b/test/CodeGen/MIR/X86/named-registers.mir @@ -12,12 +12,10 @@ --- # CHECK: name: foo name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: - '%eax = MOV32r0 - # CHECK-NEXT: - 'RETQ %eax - - '%eax = MOV32r0 implicit-def %eflags' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: %eax = MOV32r0 + ; CHECK-NEXT: RETQ %eax + %eax = MOV32r0 implicit-def %eflags + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/newline-handling.mir b/test/CodeGen/MIR/X86/newline-handling.mir new file mode 100644 index 000000000000..bce06d540114 --- /dev/null +++ b/test/CodeGen/MIR/X86/newline-handling.mir @@ -0,0 +1,109 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + + define i32 @bar(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + +... +--- +name: foo +tracksRegLiveness: true +liveins: + - { reg: '%edi' } +# CHECK-LABEL: name: foo +# CHECK: body: | +# CHECK-NEXT: bb.0.entry: +# CHECK-NEXT: successors: %bb.1.less(0x40000000 / 0x80000000 = 50.00%), %bb.2.exit(0x40000000 / 0x80000000 = 50.00%) +# CHECK-NEXT: liveins: %edi +# CHECK: CMP32ri8 %edi, 10, implicit-def %eflags +# CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags + +# CHECK: bb.1.less: +# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags +# CHECK-NEXT: RETQ killed %eax + +# CHECK: bb.2.exit: +# CHECK-NEXT: liveins: %edi +# CHECK: %eax = COPY killed %edi +# CHECK-NEXT: RETQ killed %eax +body: | + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + + liveins: %edi + + CMP32ri8 %edi, 10, implicit-def %eflags + + JG_1 %bb.2.exit, implicit killed %eflags + + bb.1.less: + + + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + bb.2.exit: + + + liveins: %edi + %eax = COPY killed %edi + RETQ killed %eax + +... +--- +name: bar +tracksRegLiveness: true +liveins: + - { reg: '%edi' } +# CHECK-LABEL: name: bar +# CHECK: body: | +# CHECK-NEXT: bb.0.entry: +# CHECK-NEXT: successors: %bb.1.less(0x40000000 / 0x80000000 = 50.00%), %bb.2.exit(0x40000000 / 0x80000000 = 50.00%) +# CHECK-NEXT: liveins: %edi +# CHECK: CMP32ri8 %edi, 10, implicit-def %eflags +# CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags + +# CHECK: bb.1.less: +# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags +# CHECK-NEXT: RETQ killed %eax + +# CHECK: bb.2.exit: +# CHECK-NEXT: liveins: %edi +# CHECK: %eax = COPY killed %edi +# CHECK-NEXT: RETQ killed %eax +body: | + + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + liveins: %edi + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit killed %eflags + bb.1.less: %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + + bb.2.exit: liveins: %edi + %eax = COPY killed %edi + RETQ killed %eax + +... diff --git a/test/CodeGen/MIR/X86/null-register-operands.mir b/test/CodeGen/MIR/X86/null-register-operands.mir index 55c0ceb3a60a..5563ef8e8f75 100644 --- a/test/CodeGen/MIR/X86/null-register-operands.mir +++ b/test/CodeGen/MIR/X86/null-register-operands.mir @@ -13,12 +13,10 @@ --- # CHECK: name: deref name: deref -body: - - id: 0 - name: entry - instructions: - # CHECK: - '%eax = MOV32rm %rdi, 1, _, 0, _' - # CHECK-NEXT: - 'RETQ %eax' - - '%eax = MOV32rm %rdi, 1, _, 0, %noreg' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ + ; CHECK-NEXT: RETQ %eax + %eax = MOV32rm %rdi, 1, _, 0, %noreg + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/register-mask-operands.mir b/test/CodeGen/MIR/X86/register-mask-operands.mir index f4136598ff5c..9fa4e6e3994e 100644 --- a/test/CodeGen/MIR/X86/register-mask-operands.mir +++ b/test/CodeGen/MIR/X86/register-mask-operands.mir @@ -20,24 +20,20 @@ ... --- name: compute -body: - - id: 0 - name: body - instructions: - - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags' - - 'RETQ %eax' +body: | + bb.0.body: + %eax = IMUL32rri8 %edi, 11, implicit-def %eflags + RETQ %eax ... --- # CHECK: name: foo name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: - 'PUSH64r %rax - # CHECK-NEXT: - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax' - - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp' - - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax' - - '%rdx = POP64r implicit-def %rsp, implicit %rsp' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: PUSH64r %rax + ; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + PUSH64r %rax, implicit-def %rsp, implicit %rsp + CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + %rdx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir b/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir new file mode 100644 index 000000000000..64d46d20db74 --- /dev/null +++ b/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @G = external global i32 + + define i32 @inc() { + entry: + %a = load i32, i32* @G + %b = add i32 %a, 1 + ret i32 %b + } + +... +--- +name: inc +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:42: register operands can't have target flags + %rax = MOV64rm target-flags(x86-got) %rip, 1, _, @G, _ + %eax = MOV32rm killed %rax, 1, _, 0, _ + %eax = INC32r killed %eax, implicit-def dead %eflags + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir new file mode 100644 index 000000000000..d7e76329be73 --- /dev/null +++ b/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir @@ -0,0 +1,34 @@ +# RUN: llc -march=x86-64 -start-after machine-scheduler -stop-after machine-scheduler -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses simple register allocation hints +# correctly. + +--- | + + define i32 @test(i32 %a, i32 %b) { + body: + %c = mul i32 %a, %b + ret i32 %c + } + +... +--- +name: test +tracksRegLiveness: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gr32 } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '%esi' } +# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '%edi' } +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr32, preferred-register: '%esi' } + - { id: 2, class: gr32, preferred-register: '%edi' } +body: | + bb.0.body: + liveins: %edi, %esi + + %1 = COPY %esi + %2 = COPY %edi + %2 = IMUL32rr %2, %1, implicit-def dead %eflags + %eax = COPY %2 + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir index 67f4bd21cd05..b62cd755fec1 100644 --- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir +++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir @@ -22,11 +22,9 @@ fixedStack: - { id: 0, type: spill-slot, offset: 0, size: 4, isAliased: true } stack: - { id: 0, offset: -12, size: 4, alignment: 4 } -body: - - id: 0 - name: entry - instructions: - - 'MOV32mr %rsp, 1, _, -4, _, %edi' - - '%eax = COPY %edi' - - 'RETQ %eax' +body: | + bb.0.entry: + MOV32mr %rsp, 1, _, -4, _, %edi + %eax = COPY %edi + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir index 1e1b0fdcc8dc..c89216bea67a 100644 --- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir +++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir @@ -22,11 +22,9 @@ fixedStack: - { id: 0, type: spill-slot, offset: 0, size: 4, isImmutable: true } stack: - { id: 0, offset: -12, size: 4, alignment: 4 } -body: - - id: 0 - name: entry - instructions: - - 'MOV32mr %rsp, 1, _, -4, _, %edi' - - '%eax = COPY %edi' - - 'RETQ %eax' +body: | + bb.0.entry: + MOV32mr %rsp, 1, _, -4, _, %edi + %eax = COPY %edi + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir index f771f796ec34..7e13a26f0b68 100644 --- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir +++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir @@ -24,11 +24,9 @@ fixedStack: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 } stack: - { id: 0, offset: -12, size: 4, alignment: 4 } -body: - - id: 0 - name: entry - instructions: - - 'MOV32mr %rsp, 1, _, -4, _, %edi' - - '%eax = COPY %edi' - - 'RETQ %eax' +body: | + bb.0.entry: + MOV32mr %rsp, 1, _, -4, _, %edi + %eax = COPY %edi + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/stack-object-debug-info.mir b/test/CodeGen/MIR/X86/stack-object-debug-info.mir new file mode 100644 index 000000000000..509b196416fd --- /dev/null +++ b/test/CodeGen/MIR/X86/stack-object-debug-info.mir @@ -0,0 +1,65 @@ +# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the stack object's debug info +# correctly. +--- | + declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 + + define void @foo() #1 { + entry: + %x.i = alloca i8, align 1 + %y.i = alloca [256 x i8], align 16 + %0 = bitcast [256 x i8]* %y.i to i8* + br label %for.body + + for.body: + %1 = bitcast [256 x i8]* %y.i to i8* + call void @llvm.lifetime.end(i64 -1, i8* %1) #3 + call void @llvm.lifetime.start(i64 -1, i8* %0) #3 + call void @llvm.dbg.declare(metadata i8* %0, metadata !4, metadata !7) #3, !dbg !8 + br label %for.body + } + + declare void @llvm.lifetime.start(i64, i8* nocapture) #2 + + declare void @llvm.lifetime.end(i64, i8* nocapture) #2 + + attributes #0 = { nounwind readnone } + attributes #1 = { nounwind ssp uwtable } + attributes #2 = { nounwind argmemonly } + attributes #3 = { nounwind } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!3} + + !0 = distinct !DICompileUnit(language: DW_LANG_C89, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: 0, enums: !2, retainedTypes: !2) + !1 = !DIFile(filename: "t.c", directory: "") + !2 = !{} + !3 = !{i32 1, !"Debug Info Version", i32 3} + !4 = !DILocalVariable(name: "x", scope: !5, file: !1, line: 16, type: !6) + !5 = distinct !DISubprogram(scope: null, isLocal: false, isDefinition: true, isOptimized: false) + !6 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) + !7 = !DIExpression() + !8 = !DILocation(line: 0, scope: !5) +... +--- +name: foo +isSSA: true +tracksRegLiveness: true +frameInfo: + maxAlignment: 16 +# CHECK-LABEL: foo +# CHECK: stack: +# CHECK: - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4', +# CHECK-NEXT: di-expression: '!7', di-location: '!8' } +stack: + - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4', + di-expression: '!7', di-location: '!8' } +body: | + bb.0.entry: + successors: %bb.1.for.body + bb.1.for.body: + successors: %bb.1.for.body + + DBG_VALUE %stack.0.y.i, 0, !4, !7, debug-location !8 + JMP_1 %bb.1.for.body +... diff --git a/test/CodeGen/MIR/X86/stack-object-invalid-name.mir b/test/CodeGen/MIR/X86/stack-object-invalid-name.mir new file mode 100644 index 000000000000..e42e1e59f1e7 --- /dev/null +++ b/test/CodeGen/MIR/X86/stack-object-invalid-name.mir @@ -0,0 +1,28 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that the MIR parser reports an error when it encounters a +# stack object with a name that can't be associated with an alloca instruction. + +--- | + + define i32 @test(i32 %a) { + entry: + %b = alloca i32 + store i32 %a, i32* %b + %c = load i32, i32* %b + ret i32 %c + } + +... +--- +name: test +frameInfo: + maxAlignment: 4 +stack: + # CHECK: [[@LINE+1]]:20: alloca instruction named 'x' isn't defined in the function 'test' + - { id: 0, name: x, offset: -12, size: 4, alignment: 4 } +body: | + bb.0.entry: + MOV32mr %rsp, 1, _, -4, _, %edi + %eax = MOV32rm %rsp, 1, _, -4, _ + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir b/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir new file mode 100644 index 000000000000..46661d95e727 --- /dev/null +++ b/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir @@ -0,0 +1,33 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an stack object reference +# uses a different name then the stack object definition. + +--- | + + define i32 @test(i32 %a) { + entry: + %b = alloca i32 + store i32 %a, i32* %b + %c = load i32, i32* %b + ret i32 %c + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, name: b, size: 4, alignment: 4 } +body: | + bb.0.entry: + %0 = COPY %edi + ; CHECK: [[@LINE+1]]:13: the name of the stack object '%stack.0' isn't 'x' + MOV32mr %stack.0.x, 1, _, 0, _, %0 + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/stack-object-operands.mir b/test/CodeGen/MIR/X86/stack-object-operands.mir new file mode 100644 index 000000000000..fce5bf717d1a --- /dev/null +++ b/test/CodeGen/MIR/X86/stack-object-operands.mir @@ -0,0 +1,45 @@ +# RUN: llc -march=x86 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses stack object machine operands +# correctly. + +--- | + + define i32 @test(i32 %a) { + entry: + %b = alloca i32 + %0 = alloca i32 + store i32 %a, i32* %b + store i32 2, i32* %0 + %c = load i32, i32* %b + ret i32 %c + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr32 } +frameInfo: + maxAlignment: 4 +fixedStack: + - { id: 0, offset: 0, size: 4, isImmutable: true, isAliased: false } +stack: + - { id: 0, name: b, size: 4, alignment: 4 } + - { id: 1, size: 4, alignment: 4 } +body: | + ; CHECK: bb.0.entry: + ; CHECK-NEXT: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ + ; CHECK-NEXT: MOV32mr %stack.0.b, 1, _, 0, _, %0 + ; CHECK-NEXT: MOV32mi %stack.1, 1, _, 0, _, 2 + ; CHECK-NEXT: %1 = MOV32rm %stack.0.b, 1, _, 0, _ + bb.0.entry: + %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ + MOV32mr %stack.0.b, 1, _, 0, _, %0 + MOV32mi %stack.1, 1, _, 0, _, 2 + %1 = MOV32rm %stack.0, 1, _, 0, _ + %eax = COPY %1 + RETL %eax +... diff --git a/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir b/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir new file mode 100644 index 000000000000..b84863ebca67 --- /dev/null +++ b/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir @@ -0,0 +1,37 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %a) #0 { + entry: + %b = alloca i32 + %x = alloca i64 + store i32 %a, i32* %b + store i64 2, i64* %x + %c = load i32, i32* %b + ret i32 %c + } + + attributes #0 = { "no-frame-pointer-elim"="false" } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%edi' } +frameInfo: + maxAlignment: 8 +stack: + - { id: 0, name: b, offset: -12, size: 4, alignment: 4 } +# CHECK: [[@LINE+1]]:11: redefinition of stack object '%stack.0' + - { id: 0, name: x, offset: -24, size: 8, alignment: 8 } +body: | + bb.0.entry: + liveins: %edi + + MOV32mr %rsp, 1, _, -4, _, killed %edi + MOV64mi32 %rsp, 1, _, -16, _, 2 + %eax = MOV32rm %rsp, 1, _, -4, _ + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/stack-objects.mir b/test/CodeGen/MIR/X86/stack-objects.mir index 14ed4b74f96f..bdd911075da0 100644 --- a/test/CodeGen/MIR/X86/stack-objects.mir +++ b/test/CodeGen/MIR/X86/stack-objects.mir @@ -21,19 +21,17 @@ name: test frameInfo: maxAlignment: 8 # CHECK: stack: -# CHECK-NEXT: - { id: 0, offset: -12, size: 4, alignment: 4 } -# CHECK-NEXT: - { id: 1, offset: -24, size: 8, alignment: 8 } +# CHECK-NEXT: - { id: 0, name: b, offset: -12, size: 4, alignment: 4 } +# CHECK-NEXT: - { id: 1, name: x, offset: -24, size: 8, alignment: 8 } # CHECK-NEXT: - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 } stack: - - { id: 0, offset: -12, size: 4, alignment: 4 } - - { id: 1, offset: -24, size: 8, alignment: 8 } + - { id: 0, name: b, offset: -12, size: 4, alignment: 4 } + - { id: 1, name: x, offset: -24, size: 8, alignment: 8 } - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 } -body: - - id: 0 - name: entry - instructions: - - 'MOV32mr %rsp, 1, _, -4, _, %edi' - - 'MOV64mi32 %rsp, 1, _, -16, _, 2' - - '%eax = MOV32rm %rsp, 1, _, -4, _' - - 'RETQ %eax' +body: | + bb.0.entry: + MOV32mr %rsp, 1, _, -4, _, %edi + MOV64mi32 %rsp, 1, _, -16, _, 2 + %eax = MOV32rm %rsp, 1, _, -4, _ + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/standalone-register-error.mir b/test/CodeGen/MIR/X86/standalone-register-error.mir new file mode 100644 index 000000000000..f17451bfc89c --- /dev/null +++ b/test/CodeGen/MIR/X86/standalone-register-error.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +--- | + define i32 @test(i32 %a) { + body: + ret i32 %a + } +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +liveins: +# CHECK: [[@LINE+1]]:13: unknown register name 'register' + - { reg: '%register', virtual-reg: '%0' } +body: | + bb.0.body: + liveins: %edi + + %0 = COPY %edi + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/subregister-operands.mir b/test/CodeGen/MIR/X86/subregister-operands.mir index 5e46fab4b058..8a3fcf69aca6 100644 --- a/test/CodeGen/MIR/X86/subregister-operands.mir +++ b/test/CodeGen/MIR/X86/subregister-operands.mir @@ -18,16 +18,15 @@ registers: - { id: 0, class: gr32 } - { id: 1, class: gr8 } - { id: 2, class: gr8 } -body: - - name: entry - id: 0 - instructions: - # CHECK: %0 = COPY %edi - # CHECK-NEXT: %1 = COPY %0:sub_8bit - - '%0 = COPY %edi' - - '%1 = COPY %0:sub_8bit' - - '%2 = AND8ri %1, 1, implicit-def %eflags' - - '%al = COPY %2' - - 'RETQ %al' +body: | + bb.0.entry: + liveins: %edi + ; CHECK: %0 = COPY %edi + ; CHECK-NEXT: %1 = COPY %0:sub_8bit + %0 = COPY %edi + %1 = COPY %0:sub_8bit + %2 = AND8ri %1, 1, implicit-def %eflags + %al = COPY %2 + RETQ %al ... diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir new file mode 100644 index 000000000000..64af6121189a --- /dev/null +++ b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir @@ -0,0 +1,42 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses basic block successors and +# probabilities correctly. + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + +... +--- +name: foo +body: | + ; CHECK-LABEL: bb.0.entry: + ; CHECK: successors: %bb.1.less({{[0-9a-fx/= ]+}}33.00%), %bb.2.exit({{[0-9a-fx/= ]+}}67.00%) + ; CHECK-LABEL: bb.1.less: + bb.0.entry: + successors: %bb.1.less (33), %bb.2.exit(67) + liveins: %edi + + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit killed %eflags + + bb.1.less: + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + + bb.2.exit: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks.mir b/test/CodeGen/MIR/X86/successor-basic-blocks.mir new file mode 100644 index 000000000000..a6c14f70bc7c --- /dev/null +++ b/test/CodeGen/MIR/X86/successor-basic-blocks.mir @@ -0,0 +1,83 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses basic block successors correctly. + +--- | + + define i32 @foo(i32 %a) { + entry: + %0 = icmp sle i32 %a, 10 + br i1 %0, label %less, label %exit + + less: + ret i32 0 + + exit: + ret i32 %a + } + + define i32 @bar(i32 %a) { + entry: + %b = icmp sle i32 %a, 10 + br i1 %b, label %0, label %1 + + ; <label>:0 + ret i32 0 + + ; <label>:1 + ret i32 %a + } + +... +--- +name: foo +body: | + ; CHECK-LABEL: bb.0.entry: + ; CHECK: successors: %bb.1.less(0x40000000 / 0x80000000 = 50.00%), %bb.2.exit(0x40000000 / 0x80000000 = 50.00%) + ; CHECK-LABEL: bb.1.less: + bb.0.entry: + successors: %bb.1.less, %bb.2.exit + liveins: %edi + + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit killed %eflags + + bb.1.less: + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + + bb.2.exit: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... +--- +name: bar +body: | + ; CHECK-LABEL: name: bar + ; Verify that we can have multiple lists of successors that will be merged + ; into one. + ; CHECK-LABEL: bb.0.entry: + ; CHECK: successors: %bb.1(0x80000000 / 0x80000000 = 100.00%), %bb.2(0x00000000 / 0x80000000 = 0.00%) + bb.0.entry: + liveins: %edi + successors: %bb.1 + successors: %bb.2 + + CMP32ri8 %edi, 10, implicit-def %eflags + JG_1 %bb.2, implicit killed %eflags + + ; Verify that we can have an empty list of successors. + ; CHECK-LABEL: bb.1: + ; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags + bb.1: + successors: + %eax = MOV32r0 implicit-def dead %eflags + RETQ killed %eax + + bb.2: + liveins: %edi + + %eax = COPY killed %edi + RETQ killed %eax +... diff --git a/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir b/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir new file mode 100644 index 000000000000..fe5263df355f --- /dev/null +++ b/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +--- | + define i64 @test(i64 %x) #0 { + entry: + %asm = tail call i64 asm sideeffect "$foo", "=r,0"(i64 %x) nounwind + ret i64 %asm + } + + attributes #0 = { nounwind } +... +--- +name: test +hasInlineAsm: true +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + + ; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '0'; the operand #0 isn't a defined register + INLINEASM $"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 0) + %rax = COPY killed %rdi + RETQ killed %rax +... diff --git a/test/CodeGen/MIR/X86/undef-register-flag.mir b/test/CodeGen/MIR/X86/undef-register-flag.mir index 83b9e10a80d1..0b26c528aee1 100644 --- a/test/CodeGen/MIR/X86/undef-register-flag.mir +++ b/test/CodeGen/MIR/X86/undef-register-flag.mir @@ -21,22 +21,18 @@ ... --- name: compute -body: - - id: 0 - name: body - instructions: - - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags' - - 'RETQ %eax' +body: | + bb.0.body: + %eax = IMUL32rri8 %edi, 11, implicit-def %eflags + RETQ %eax ... --- name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: - 'PUSH64r undef %rax - - 'PUSH64r undef %rax, implicit-def %rsp, implicit %rsp' - - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax' - - '%rdx = POP64r implicit-def %rsp, implicit %rsp' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: PUSH64r undef %rax + PUSH64r undef %rax, implicit-def %rsp, implicit %rsp + CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + %rdx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir b/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir new file mode 100644 index 000000000000..8d8f8614f32b --- /dev/null +++ b/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir @@ -0,0 +1,38 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +--- | + + define i32 @test(i32 %a) { + entry: + %b = alloca i32 + %0 = alloca i32 + store i32 %a, i32* %b + store i32 2, i32* %0 + %c = load i32, i32* %b + ret i32 %c + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr32 } +frameInfo: + maxAlignment: 4 +fixedStack: + - { id: 0, offset: 0, size: 4, isImmutable: true, isAliased: false } +stack: + - { id: 0, name: b, size: 4, alignment: 4 } + - { id: 1, size: 4, alignment: 4 } +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:18: use of undefined fixed stack object '%fixed-stack.11' + %0 = MOV32rm %fixed-stack.11, 1, _, 0, _ + MOV32mr %stack.0, 1, _, 0, _, %0 + MOV32mi %stack.1, 1, _, 0, _, 2 + %1 = MOV32rm %stack.0, 1, _, 0, _ + %eax = COPY %1 + RETL %eax +... diff --git a/test/CodeGen/MIR/X86/undefined-global-value.mir b/test/CodeGen/MIR/X86/undefined-global-value.mir index e41dc0454d2c..f82c626397a9 100644 --- a/test/CodeGen/MIR/X86/undefined-global-value.mir +++ b/test/CodeGen/MIR/X86/undefined-global-value.mir @@ -16,13 +16,11 @@ ... --- name: inc -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:37: use of undefined global value '@2' - - '%rax = MOV64rm %rip, 1, _, @2, _' - - '%eax = MOV32rm %rax, 1, _, 0, _' - - '%eax = INC32r %eax' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:32: use of undefined global value '@2' + %rax = MOV64rm %rip, 1, _, @2, _ + %eax = MOV32rm %rax, 1, _, 0, _ + %eax = INC32r %eax + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir b/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir new file mode 100644 index 000000000000..f6b10e3123ca --- /dev/null +++ b/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir @@ -0,0 +1,30 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @addr = global i8* null + + define void @test() { + entry: + store volatile i8* blockaddress(@test, %block), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %block] + + block: + ret void + } + +... +--- +name: test +body: | + bb.0.entry: + successors: %bb.1.block + ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block."block "' + %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block."block "), _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1.block (address-taken): + RETQ +... diff --git a/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir b/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir new file mode 100644 index 000000000000..0b3c0093dc62 --- /dev/null +++ b/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir @@ -0,0 +1,29 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + @addr = global i8* null + + define void @test() { + entry: + store volatile i8* blockaddress(@test, %0), i8** @addr + %val = load volatile i8*, i8** @addr + indirectbr i8* %val, [label %0] + + ret void + } + +... +--- +name: test +body: | + bb.0.entry: + successors: %bb.1 + ; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block.1' + %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.1), _ + MOV64mr %rip, 1, _, @addr, _, killed %rax + JMP64m %rip, 1, _, @addr, _ + + bb.1 (address-taken): + RETQ +... diff --git a/test/CodeGen/MIR/X86/undefined-jump-table-id.mir b/test/CodeGen/MIR/X86/undefined-jump-table-id.mir new file mode 100644 index 000000000000..b463dc4bd9f4 --- /dev/null +++ b/test/CodeGen/MIR/X86/undefined-jump-table-id.mir @@ -0,0 +1,73 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test_jumptable(i32 %in) { + entry: + switch i32 %in, label %def [ + i32 0, label %lbl1 + i32 1, label %lbl2 + i32 2, label %lbl3 + i32 3, label %lbl4 + ] + + def: + ret i32 0 + + lbl1: + ret i32 1 + + lbl2: + ret i32 2 + + lbl3: + ret i32 4 + + lbl4: + ret i32 8 + } + +... +--- +name: test_jumptable +jumpTable: + kind: label-difference32 + entries: + - id: 0 + blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +body: | + bb.0.entry: + successors: %bb.2.def, %bb.1.entry + + %eax = MOV32rr %edi, implicit-def %rax + CMP32ri8 %edi, 3, implicit-def %eflags + JA_1 %bb.2.def, implicit %eflags + + bb.1.entry: + successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 + ; CHECK: [[@LINE+1]]:31: use of undefined jump table '%jump-table.2' + %rcx = LEA64r %rip, 1, _, %jump-table.2, _ + %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ + %rax = ADD64rr %rax, %rcx, implicit-def %eflags + JMP64r %rax + + bb.2.def: + %eax = MOV32r0 implicit-def %eflags + RETQ %eax + + bb.3.lbl1: + %eax = MOV32ri 1 + RETQ %eax + + bb.4.lbl2: + %eax = MOV32ri 2 + RETQ %eax + + bb.5.lbl3: + %eax = MOV32ri 4 + RETQ %eax + + bb.6.lbl4: + %eax = MOV32ri 8 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/undefined-named-global-value.mir b/test/CodeGen/MIR/X86/undefined-named-global-value.mir index b40c2ce43b5f..a1ada4b42e46 100644 --- a/test/CodeGen/MIR/X86/undefined-named-global-value.mir +++ b/test/CodeGen/MIR/X86/undefined-named-global-value.mir @@ -16,13 +16,11 @@ ... --- name: inc -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:37: use of undefined global value '@GG' - - '%rax = MOV64rm %rip, 1, _, @GG, _' - - '%eax = MOV32rm %rax, 1, _, 0, _' - - '%eax = INC32r %eax' - - 'RETQ %eax' +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:32: use of undefined global value '@GG' + %rax = MOV64rm %rip, 1, _, @GG, _ + %eax = MOV32rm %rax, 1, _, 0, _ + %eax = INC32r %eax + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/undefined-register-class.mir b/test/CodeGen/MIR/X86/undefined-register-class.mir index a14d2303a7d8..348f6af5c44f 100644 --- a/test/CodeGen/MIR/X86/undefined-register-class.mir +++ b/test/CodeGen/MIR/X86/undefined-register-class.mir @@ -17,10 +17,8 @@ tracksRegLiveness: true registers: # CHECK: [[@LINE+1]]:20: use of undefined register class 'gr3200' - {id: 0, class: 'gr3200'} -body: - - id: 0 - name: entry - instructions: - - 'RETQ %eax' +body: | + bb.0.entry: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/undefined-stack-object.mir b/test/CodeGen/MIR/X86/undefined-stack-object.mir new file mode 100644 index 000000000000..416e6789ba0f --- /dev/null +++ b/test/CodeGen/MIR/X86/undefined-stack-object.mir @@ -0,0 +1,30 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +--- | + + define i32 @test(i32 %a) { + entry: + %b = alloca i32 + store i32 %a, i32* %b + %c = load i32, i32* %b + ret i32 %c + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, name: b, size: 4, alignment: 4 } +body: | + bb.0.entry: + %0 = COPY %edi + ; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2' + MOV32mr %stack.2, 1, _, 0, _, %0 + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir new file mode 100644 index 000000000000..a3907d7a3a4a --- /dev/null +++ b/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir @@ -0,0 +1,24 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32* %a) { + entry: + %b = load i32, i32* %a + ret i32 %b + } + +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:60: use of undefined IR value '%ir.c' + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.c) + RETQ %eax +... + diff --git a/test/CodeGen/MIR/X86/undefined-virtual-register.mir b/test/CodeGen/MIR/X86/undefined-virtual-register.mir index 12370c80caf9..2f9a304ffe5c 100644 --- a/test/CodeGen/MIR/X86/undefined-virtual-register.mir +++ b/test/CodeGen/MIR/X86/undefined-virtual-register.mir @@ -16,13 +16,11 @@ isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } -body: - - id: 0 - name: entry - instructions: - - '%0 = COPY %edi' - # CHECK: [[@LINE+1]]:22: use of undefined virtual register '%10' - - '%eax = COPY %10' - - 'RETQ %eax' +body: | + bb.0.entry: + %0 = COPY %edi + ; CHECK: [[@LINE+1]]:17: use of undefined virtual register '%10' + %eax = COPY %10 + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/unknown-instruction.mir b/test/CodeGen/MIR/X86/unknown-instruction.mir index 4e58ca6bad40..cec354948832 100644 --- a/test/CodeGen/MIR/X86/unknown-instruction.mir +++ b/test/CodeGen/MIR/X86/unknown-instruction.mir @@ -12,10 +12,8 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:8: unknown machine instruction name 'retJust0' - - retJust0 +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:5: unknown machine instruction name 'retJust0' + retJust0 ... diff --git a/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir b/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir index a82e9a780f54..a512d9aa08e6 100644 --- a/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir +++ b/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir @@ -21,18 +21,16 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - - 'CMP32ri8 %eax, 10, implicit-def %eflags' - # CHECK: [[@LINE+1]]:14: use of undefined machine basic block #4 - - 'JG_1 %bb.4, implicit %eflags' - - id: 1 - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 2 - instructions: - - 'RETQ %eax' +body: | + bb.0.entry: + %eax = MOV32rm %rdi, 1, _, 0, _ + CMP32ri8 %eax, 10, implicit-def %eflags + ; CHECK: [[@LINE+1]]:10: use of undefined machine basic block #4 + JG_1 %bb.4, implicit %eflags + + bb.1: + %eax = MOV32r0 implicit-def %eflags + + bb.2: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir b/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir new file mode 100644 index 000000000000..c58c38ab1322 --- /dev/null +++ b/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir @@ -0,0 +1,25 @@ +# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s + +--- | + define i32 @inc(i32* %x) { + entry: + %0 = load i32, i32* %x + %1 = add i32 %0, 1 + store i32 %1, i32* %x + ret i32 %1 + } +... +--- +name: inc +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:60: use of unknown metadata keyword '!tba' + %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.x, !tba !0) + %eax = INC32r killed %eax, implicit-def dead %eflags + MOV32mr killed %rdi, 1, _, 0, _, %eax :: (store 4 into %ir.x) + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/unknown-metadata-node.mir b/test/CodeGen/MIR/X86/unknown-metadata-node.mir new file mode 100644 index 000000000000..958a30678be1 --- /dev/null +++ b/test/CodeGen/MIR/X86/unknown-metadata-node.mir @@ -0,0 +1,59 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %x) #0 !dbg !4 { + entry: + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !12, metadata !13), !dbg !14 + %0 = load i32, i32* %x.addr, align 4, !dbg !15 + ret i32 %0, !dbg !15 + } + + declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + + attributes #0 = { nounwind "no-frame-pointer-elim"="false" } + attributes #1 = { nounwind readnone } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!9, !10} + !llvm.ident = !{!11} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !1 = !DIFile(filename: "test.ll", directory: "") + !2 = !{} + !3 = !{!4} + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !5 = !DIFile(filename: "test.c", directory: "") + !6 = !DISubroutineType(types: !7) + !7 = !{!8, !8} + !8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !9 = !{i32 2, !"Dwarf Version", i32 4} + !10 = !{i32 2, !"Debug Info Version", i32 3} + !11 = !{!"clang version 3.7.0"} + !12 = !DILocalVariable(name: "x", arg: 1, scope: !4, file: !5, line: 4, type: !8) + !13 = !DIExpression() + !14 = !DILocation(line: 4, scope: !4) + !15 = !DILocation(line: 8, scope: !4) + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, name: x.addr, size: 4, alignment: 4 } +body: | + bb.0.entry: + %0 = COPY %edi + ; CHECK: [[@LINE+1]]:21: use of undefined metadata '!42' + DBG_VALUE _, 0, !42, !13 + MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 + %eax = COPY %0 + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir b/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir index f304113f40b9..6627273d4470 100644 --- a/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir +++ b/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir @@ -20,20 +20,16 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - - '%eax = MOV32rm %rdi, 1, _, 0, _' - - 'CMP32ri8 %eax, 10, implicit-def %eflags' - # CHECK: [[@LINE+1]]:14: the name of machine basic block #2 isn't 'hit' - - 'JG_1 %bb.2.hit, implicit %eflags' - - id: 1 - name: less - instructions: - - '%eax = MOV32r0 implicit-def %eflags' - - id: 2 - name: exit - instructions: - - 'RETQ %eax' +body: | + bb.0.entry: + %eax = MOV32rm %rdi, 1, _, 0, _ + CMP32ri8 %eax, 10, implicit-def %eflags + ; CHECK: [[@LINE+1]]:10: the name of machine basic block #2 isn't 'hit' + JG_1 %bb.2.hit, implicit %eflags + + bb.1.less: + %eax = MOV32r0 implicit-def %eflags + + bb.2.exit: + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/unknown-register.mir b/test/CodeGen/MIR/X86/unknown-register.mir index ce40ee809bf3..da0798ca1b52 100644 --- a/test/CodeGen/MIR/X86/unknown-register.mir +++ b/test/CodeGen/MIR/X86/unknown-register.mir @@ -12,11 +12,9 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:9: unknown register name 'xax' - - '%xax = MOV32r0' - - 'RETQ %xax' +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:5: unknown register name 'xax' + %xax = MOV32r0 + RETQ %xax ... diff --git a/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/test/CodeGen/MIR/X86/unknown-subregister-index.mir index 50461232b623..5dde34561236 100644 --- a/test/CodeGen/MIR/X86/unknown-subregister-index.mir +++ b/test/CodeGen/MIR/X86/unknown-subregister-index.mir @@ -18,14 +18,12 @@ registers: - { id: 0, class: gr32 } - { id: 1, class: gr8 } - { id: 2, class: gr8 } -body: - - name: entry - id: 0 - instructions: - - '%0 = COPY %edi' - # CHECK: [[@LINE+1]]:23: use of unknown subregister index 'bit8' - - '%1 = COPY %0:bit8' - - '%2 = AND8ri %1, 1, implicit-def %eflags' - - '%al = COPY %2' - - 'RETQ %al' +body: | + bb.0.entry: + %0 = COPY %edi + ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8' + %1 = COPY %0:bit8 + %2 = AND8ri %1, 1, implicit-def %eflags + %al = COPY %2 + RETQ %al ... diff --git a/test/CodeGen/MIR/X86/unrecognized-character.mir b/test/CodeGen/MIR/X86/unrecognized-character.mir index 3b4fb1a9fc6e..cf99028677fa 100644 --- a/test/CodeGen/MIR/X86/unrecognized-character.mir +++ b/test/CodeGen/MIR/X86/unrecognized-character.mir @@ -10,10 +10,8 @@ ... --- name: foo -body: - - id: 0 - name: entry - instructions: - # CHECK: [[@LINE+1]]:9: unexpected character '`' - - '` RETQ' +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:5: unexpected character '\' + \ RETQ ... diff --git a/test/CodeGen/MIR/X86/used-physical-register-info.mir b/test/CodeGen/MIR/X86/used-physical-register-info.mir new file mode 100644 index 000000000000..9a81578703e0 --- /dev/null +++ b/test/CodeGen/MIR/X86/used-physical-register-info.mir @@ -0,0 +1,109 @@ +# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses the callee saved register mask +# correctly and that the MIR parser can infer it as well. + +--- | + + define i32 @compute(i32 %a) #0 { + body: + %c = mul i32 %a, 11 + ret i32 %c + } + + define i32 @foo(i32 %a) #0 { + entry: + %b = call i32 @compute(i32 %a) + ret i32 %b + } + + define i32 @bar(i32 %a) #0 { + entry: + %b = call i32 @compute(i32 %a) + ret i32 %b + } + + define i32 @empty(i32 %a) #0 { + entry: + %b = call i32 @compute(i32 %a) + ret i32 %b + } + + attributes #0 = { "no-frame-pointer-elim"="false" } + +... +--- +# CHECK: name: compute +# CHECK: liveins: +# CHECK-NEXT: - { reg: '%edi' } +# CHECK-NEXT: frameInfo: +name: compute +liveins: + - { reg: '%edi' } +frameInfo: + stackSize: 8 +body: | + bb.0.body: + liveins: %edi + + %eax = IMUL32rri8 %edi, 11, implicit-def %eflags + RETQ %eax +... +--- +name: foo +liveins: + - { reg: '%edi' } +# CHECK: name: foo +# CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', +# CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', +# CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', +# CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] +calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', + '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', + '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', + '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] +body: | + bb.0.entry: + liveins: %edi + + PUSH64r %rax, implicit-def %rsp, implicit %rsp + CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + %rdx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... +--- +name: bar +liveins: + - { reg: '%edi' } +# Verify that the callee saved register can be inferred from register mask +# machine operands: +# CHECK: name: bar +# CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', +# CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', +# CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', +# CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] +body: | + bb.0.entry: + liveins: %edi + + PUSH64r %rax, implicit-def %rsp, implicit %rsp + CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + %rdx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... +--- +name: empty +liveins: + - { reg: '%edi' } +# Verify that the callee saved register can be empty. +# CHECK: name: empty +# CHECK: calleeSavedRegisters: [ ] +calleeSavedRegisters: [ ] +body: | + bb.0.entry: + liveins: %edi + + PUSH64r %rax, implicit-def %rsp, implicit %rsp + CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax + %rdx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax +... diff --git a/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir b/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir index 8e50c52f5e18..e6a9ef8d4c88 100644 --- a/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir +++ b/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir @@ -25,12 +25,10 @@ stack: - { id: 1, offset: -32, size: 8, alignment: 8 } # CHECK: [[@LINE+1]]:55: unknown key 'size' - { id: 2, type: variable-sized, offset: -32, size: 42, alignment: 1 } -body: - - id: 0 - name: entry - instructions: - - 'MOV32mr %rsp, 1, _, -4, _, %edi' - - 'MOV64mi32 %rsp, 1, _, -16, _, 2' - - '%eax = MOV32rm %rsp, 1, _, -4, _' - - 'RETQ %eax' +body: | + bb.0.entry: + MOV32mr %rsp, 1, _, -4, _, %edi + MOV64mi32 %rsp, 1, _, -16, _, 2 + %eax = MOV32rm %rsp, 1, _, -4, _ + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir b/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir index 4c45742b25a4..a58be69ae046 100644 --- a/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir +++ b/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir @@ -26,17 +26,15 @@ frameInfo: # CHECK: stack: # CHECK-NEXT: - { id: 0, offset: -20, size: 4, alignment: 4 } # CHECK-NEXT: - { id: 1, offset: -32, size: 8, alignment: 8 } -# CHECK-NEXT: - { id: 2, type: variable-sized, offset: -32, alignment: 1 } +# CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 } stack: - { id: 0, offset: -20, size: 4, alignment: 4 } - { id: 1, offset: -32, size: 8, alignment: 8 } - - { id: 2, type: variable-sized, offset: -32, alignment: 1 } -body: - - id: 0 - name: entry - instructions: - - 'MOV32mr %rsp, 1, _, -4, _, %edi' - - 'MOV64mi32 %rsp, 1, _, -16, _, 2' - - '%eax = MOV32rm %rsp, 1, _, -4, _' - - 'RETQ %eax' + - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 } +body: | + bb.0.entry: + MOV32mr %rsp, 1, _, -4, _, %edi + MOV64mi32 %rsp, 1, _, -16, _, 2 + %eax = MOV32rm %rsp, 1, _, -4, _ + RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir new file mode 100644 index 000000000000..5dae6e666c83 --- /dev/null +++ b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir @@ -0,0 +1,27 @@ +# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s + +--- | + + define i32 @test(i32 %a) { + body: + ret i32 %a + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +# CHECK: [[@LINE+1]]:11: redefinition of virtual register '%0' + - { id: 0, class: gr32 } +body: | + bb.0.body: + liveins: %edi + + %0 = COPY %edi + %eax = COPY %0 + RETQ %eax +... + diff --git a/test/CodeGen/MIR/X86/virtual-registers.mir b/test/CodeGen/MIR/X86/virtual-registers.mir index c6d76e6a18c5..93c2fea6fd95 100644 --- a/test/CodeGen/MIR/X86/virtual-registers.mir +++ b/test/CodeGen/MIR/X86/virtual-registers.mir @@ -41,29 +41,27 @@ registers: - { id: 0, class: gr32 } - { id: 1, class: gr32 } - { id: 2, class: gr32 } -body: - - id: 0 - name: entry - # CHECK: %0 = COPY %edi - # CHECK-NEXT: %1 = SUB32ri8 %0, 10 - instructions: - - '%0 = COPY %edi' - - '%1 = SUB32ri8 %0, 10, implicit-def %eflags' - - 'JG_1 %bb.2.exit, implicit %eflags' - - 'JMP_1 %bb.1.less' - - id: 1 - name: less - # CHECK: %2 = MOV32r0 - # CHECK-NEXT: %eax = COPY %2 - instructions: - - '%2 = MOV32r0 implicit-def %eflags' - - '%eax = COPY %2' - - 'RETQ %eax' - - id: 2 - name: exit - instructions: - - '%eax = COPY %0' - - 'RETQ %eax' +body: | + bb.0.entry: + successors: %bb.2.exit, %bb.1.less + liveins: %edi + ; CHECK: %0 = COPY %edi + ; CHECK-NEXT: %1 = SUB32ri8 %0, 10 + %0 = COPY %edi + %1 = SUB32ri8 %0, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit %eflags + JMP_1 %bb.1.less + + bb.1.less: + ; CHECK: %2 = MOV32r0 + ; CHECK-NEXT: %eax = COPY %2 + %2 = MOV32r0 implicit-def %eflags + %eax = COPY %2 + RETQ %eax + + bb.2.exit: + %eax = COPY %0 + RETQ %eax ... --- name: foo @@ -78,28 +76,26 @@ registers: - { id: 2, class: gr32 } - { id: 0, class: gr32 } - { id: 10, class: gr32 } -body: - - id: 0 - name: entry - # CHECK: %0 = COPY %edi - # CHECK-NEXT: %1 = SUB32ri8 %0, 10 - instructions: - - '%2 = COPY %edi' - - '%0 = SUB32ri8 %2, 10, implicit-def %eflags' - - 'JG_1 %bb.2.exit, implicit %eflags' - - 'JMP_1 %bb.1.less' - - id: 1 - name: less - # CHECK: %2 = MOV32r0 - # CHECK-NEXT: %eax = COPY %2 - instructions: - - '%10 = MOV32r0 implicit-def %eflags' - - '%eax = COPY %10' - - 'RETQ %eax' - - id: 2 - name: exit - # CHECK: %eax = COPY %0 - instructions: - - '%eax = COPY %2' - - 'RETQ %eax' +body: | + bb.0.entry: + successors: %bb.2.exit, %bb.1.less + liveins: %edi + ; CHECK: %0 = COPY %edi + ; CHECK-NEXT: %1 = SUB32ri8 %0, 10 + %2 = COPY %edi + %0 = SUB32ri8 %2, 10, implicit-def %eflags + JG_1 %bb.2.exit, implicit %eflags + JMP_1 %bb.1.less + + bb.1.less: + ; CHECK: %2 = MOV32r0 + ; CHECK-NEXT: %eax = COPY %2 + %10 = MOV32r0 implicit-def %eflags + %eax = COPY %10 + RETQ %eax + + bb.2.exit: + ; CHECK: %eax = COPY %0 + %eax = COPY %2 + RETQ %eax ... diff --git a/test/CodeGen/MIR/basic-blocks.mir b/test/CodeGen/MIR/basic-blocks.mir deleted file mode 100644 index 17313047576b..000000000000 --- a/test/CodeGen/MIR/basic-blocks.mir +++ /dev/null @@ -1,49 +0,0 @@ -# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s -# This test ensures that the MIR parser parses machine functions correctly. - ---- | - - define i32 @foo() { - entry: - ret i32 0 - } - - define i32 @bar() { - start: - ret i32 0 - } - -... ---- -# CHECK: name: foo -# CHECK: body: -# CHECK-NEXT: - id: 0 -# CHECK-NEXT: name: entry -# CHECK-NEXT: alignment: 0 -# CHECK-NEXT: isLandingPad: false -# CHECK-NEXT: addressTaken: false -name: foo -body: - - id: 0 - name: entry -... ---- -# CHECK: name: bar -# CHECK: body: -# CHECK-NEXT: - id: 0 -# CHECK-NEXT: name: start -# CHECK-NEXT: alignment: 4 -# CHECK-NEXT: isLandingPad: false -# CHECK-NEXT: addressTaken: false -# CHECK-NEXT: - id: 1 -# CHECK-NEXT: alignment: 0 -# CHECK-NEXT: isLandingPad: false -# CHECK-NEXT: addressTaken: true -name: bar -body: - - id: 0 - name: start - alignment: 4 - - id: 1 - addressTaken: true -... diff --git a/test/CodeGen/MIR/expected-eof-after-successor-mbb.mir b/test/CodeGen/MIR/expected-eof-after-successor-mbb.mir deleted file mode 100644 index 25ae51192971..000000000000 --- a/test/CodeGen/MIR/expected-eof-after-successor-mbb.mir +++ /dev/null @@ -1,29 +0,0 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s - ---- | - - define i32 @foo(i32 %a) { - entry: - %0 = icmp sle i32 %a, 10 - br i1 %0, label %less, label %exit - - less: - ret i32 0 - - exit: - ret i32 %a - } - -... ---- -name: foo -body: - - id: 0 - name: entry - # CHECK: [[@LINE+1]]:46: expected end of string after the machine basic block reference - successors: [ '%bb.1.less', '%bb.2.exit 2' ] - - id: 1 - name: less - - id: 2 - name: exit -... diff --git a/test/CodeGen/MIR/successor-basic-blocks.mir b/test/CodeGen/MIR/successor-basic-blocks.mir deleted file mode 100644 index 3fe01e3ad438..000000000000 --- a/test/CodeGen/MIR/successor-basic-blocks.mir +++ /dev/null @@ -1,58 +0,0 @@ -# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s -# This test ensures that the MIR parser parses basic block successors correctly. - ---- | - - define i32 @foo(i32 %a) { - entry: - %0 = icmp sle i32 %a, 10 - br i1 %0, label %less, label %exit - - less: - ret i32 0 - - exit: - ret i32 %a - } - - define i32 @bar(i32 %a) { - entry: - %b = icmp sle i32 %a, 10 - br i1 %b, label %0, label %1 - - ; <label>:0 - ret i32 0 - - ; <label>:1 - ret i32 %a - } - -... ---- -name: foo -body: - # CHECK: name: entry - # CHECK: successors: [ '%bb.1.less', '%bb.2.exit' ] - # CHECK: name: less - - id: 0 - name: entry - successors: [ '%bb.1.less', '%bb.2.exit' ] - - id: 1 - name: less - - id: 2 - name: exit -... ---- -name: bar -body: - # CHECK: name: bar - # CHECK: name: entry - # CHECK: successors: [ '%bb.1', '%bb.2' ] - # CHECK: id: 1 - # CHECK: id: 2 - - id: 0 - name: entry - successors: [ '%bb.1', '%bb.2' ] - - id: 1 - - id: 2 -... |