1 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/MSP430/fp.ll b/test/CodeGen/MSP430/fp.ll
index 018090566f18..2559e23ae1f5 100644
--- a/test/CodeGen/MSP430/fp.ll
+++ b/test/CodeGen/MSP430/fp.ll
@@ -15,3 +15,15 @@ entry:
 ; CHECK: pop.w r4
   ret void
 }
+
+; Due to FPB not being marked as reserved, the register allocator used to select
+; r4 as the register for the "r" constraint below. This test verifies that this
+; does not happen anymore. Note that the only reason an ISR is used here is that
+; the register allocator selects r4 first instead of fifth in a normal function.
+define msp430_intrcc void @fpb_alloced() #0 {
+; CHECK-LABEL: fpb_alloced:
+; CHECK-NOT: mov.b #0, r4
+; CHECK: nop
+  call void asm sideeffect "nop", "r"(i8 0)
+  ret void
+}