diff options
Diffstat (limited to 'test/CodeGen/Mips')
68 files changed, 1316 insertions, 588 deletions
diff --git a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll index c0229c626a0e..d3cc03ffc8e3 100644 --- a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll +++ b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll @@ -17,7 +17,7 @@ entry: ; STATIC-N32: lwc1 $f0, %lo(.LCPI0_0)($[[R0]]) ; PIC-N64: ld $[[R0:[0-9]+]], %got_page(.LCPI0_0) ; PIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]]) -; STATIC-N64: ld $[[R0:[0-9]+]], %got_page(.LCPI0_0) -; STATIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]]) +; STATIC-N64: lui $[[R0:[0-9]+]], %highest(.LCPI0_0) +; STATIC-N64: lwc1 $f0, %lo(.LCPI0_0)($[[R0]]) ret float 0x400B333340000000 } diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll index 5f0a0a5a4929..087a34f3c1bc 100644 --- a/test/CodeGen/Mips/2010-07-20-Switch.ll +++ b/test/CodeGen/Mips/2010-07-20-Switch.ll @@ -3,13 +3,13 @@ ; RUN: llc < %s -march=mips -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefix=PIC-O32 ; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips4 | \ -; RUN: FileCheck %s -check-prefix=N64 +; RUN: FileCheck %s -check-prefix=PIC-N64 ; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips4 | \ -; RUN: FileCheck %s -check-prefix=N64 +; RUN: FileCheck %s -check-prefix=STATIC-N64 ; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 | \ -; RUN: FileCheck %s -check-prefix=N64 +; RUN: FileCheck %s -check-prefix=PIC-N64 ; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips64 | \ -; RUN: FileCheck %s -check-prefix=N64 +; RUN: FileCheck %s -check-prefix=STATIC-N64 define i32 @main() nounwind readnone { entry: @@ -20,18 +20,29 @@ entry: ; STATIC-O32: lui $[[R1:[0-9]+]], %hi($JTI0_0) ; STATIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]]) + ; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2 ; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0) ; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]]) ; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]] ; PIC-O32: jr $[[R5]] -; N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3 -; N64: ld $[[R1:[0-9]+]], %got_page(.LJTI0_0) -; N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]] -; N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]]) -; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]] -; N64: jr $[[R5]] + +; STATIC-N64: mflo $[[R0:[0-9]]] +; STATIC-N64: lui $[[R1:[0-9]]], %highest(.LJTI0_0) +; STATIC-N64: daddiu $[[R2:[0-9]]], $[[R1]], %higher(.LJTI0_0) +; STATIC-N64: dsll $[[R3:[0-9]]], $[[R2]], 16 +; STATIC-N64: daddiu $[[R4:[0-9]]], $[[R3]], %hi(.LJTI0_0) +; STATIC-N64: dsll $[[R5:[0-9]]], $[[R4]], 16 +; STATIC-N64: daddu $[[R6:[0-9]]], $[[R0]], $[[R4]] +; STATIC-N64: ld ${{[0-9]+}}, %lo(.LJTI0_0)($[[R6]]) + +; PIC-N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 32 +; PIC-N64: ld $[[R1:[0-9]+]], %got_page(.LJTI0_0) +; PIC-N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]] +; PIC-N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]]) +; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]] +; PIC-N64: jr $[[R5]] switch i32 %0, label %bb4 [ i32 0, label %bb5 i32 1, label %bb1 @@ -65,12 +76,18 @@ bb5: ; preds = %entry ; PIC-O32: $JTI0_0: ; PIC-O32: .gpword ; PIC-O32: .gpword -; PIC-O32: .gpword -; PIC-O32: .gpword -; N64: .p2align 3 -; N64: .LJTI0_0: -; N64: .gpdword -; N64: .gpdword -; N64: .gpdword -; N64: .gpdword +; PIC-O32: .gpword +; PIC-O32: .gpword +; STATIC-N64: .p2align 3 +; STATIC-N64: LJTI0_0: +; STATIC-N64: .8byte +; STATIC-N64: .8byte +; STATIC-N64: .8byte +; STATIC-N64: .8byte +;; PIC-N64: .p2align 3 +; PIC-N64: .LJTI0_0: +; PIC-N64: .gpdword +; PIC-N64: .gpdword +; PIC-N64: .gpdword +; PIC-N64: .gpdword diff --git a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll index 5594de8177d4..b8973efda179 100644 --- a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll +++ b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll @@ -1,40 +1,40 @@ ; Targets where we should not enable FastISel. ; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mattr=mips16 -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; Valid targets for FastISel. ; RUN: llc -march=mips -mcpu=mips32r0 -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -check-prefix=FISEL +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL ; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -check-prefix=FISEL +; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL ; The CHECK prefix is being used by those targets that do not support FastISel. ; By checking that we don't emit the "FastISel missed terminator..." message, diff --git a/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll b/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll index d9ce8b3964a4..0aec8d506f77 100644 --- a/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll +++ b/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-verbose 2>&1 | FileCheck %s +; RUN: -pass-remarks-missed=isel 2>&1 | FileCheck %s ; CHECK: FastISel missed call: ; CHECK-SAME: %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b) diff --git a/test/CodeGen/Mips/abicalls.ll b/test/CodeGen/Mips/abicalls.ll index 26bbab40b3b3..2de539776879 100644 --- a/test/CodeGen/Mips/abicalls.ll +++ b/test/CodeGen/Mips/abicalls.ll @@ -1,7 +1,12 @@ ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,STATIC %s ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=pic %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s -; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips4 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s -; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips4 -relocation-model=static %s -o - | FileCheck -check-prefixes=N64-STATIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefixes=N64-STATIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips4 -relocation-model=static -mattr=+sym32 %s -o - | FileCheck -check-prefixes=ABICALLS,STATIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=static -mattr=+sym32 %s -o - | FileCheck -check-prefixes=ABICALLS,STATIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips4 -relocation-model=pic %s -o - | FileCheck -check-prefixes=ABICALLS %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=pic %s -o - | FileCheck -check-prefixes=ABICALLS %s + ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr noabicalls -relocation-model=static %s -o - | FileCheck -implicit-check-not='.abicalls' -implicit-check-not='pic0' %s @@ -9,3 +14,6 @@ ; STATIC: pic0 ; PIC-NOT: pic0 + +; N64-STATIC-NOT: .abicalls +; N64-STATIC-NOT: .pic0 diff --git a/test/CodeGen/Mips/blockaddr.ll b/test/CodeGen/Mips/blockaddr.ll index 9bc9a305a204..80b24bcdeb16 100644 --- a/test/CodeGen/Mips/blockaddr.ll +++ b/test/CodeGen/Mips/blockaddr.ll @@ -34,10 +34,14 @@ entry: ; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst(.Ltmp[[T0]]) ; PIC-N64: ld $[[R1:[0-9]+]], %got_page(.Ltmp[[T1:[0-9]+]]) ; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst(.Ltmp[[T1]]) -; STATIC-N64: ld $[[R2:[0-9]+]], %got_page(.Ltmp[[T2:[0-9]+]]) -; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst(.Ltmp[[T2]]) -; STATIC-N64: ld $[[R3:[0-9]+]], %got_page(.Ltmp[[T3:[0-9]+]]) -; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst(.Ltmp[[T3]]) + +; STATIC-N64: lui $[[R0:[0-9]]], %highest(.Ltmp[[L0:[0-9]]]) +; STATIC-N64: daddiu $[[R1:[0-9]]], $[[R0]], %higher(.Ltmp[[L0]]) +; STATIC-N64: dsll $[[R2:[0-9]]], $[[R1]], 16 +; STATIC-N64: daddiu $[[R3:[0-9]]], $[[R2]], %hi(.Ltmp[[L0]]) +; STATIC-N64: dsll $[[R4:[0-9]]], $[[R3]], 16 +; STATIC-N64: daddiu $[[R5:[0-9]]], $[[R4]], %lo(.Ltmp[[L0]]) + ; STATIC-MIPS16-1: .ent f ; STATIC-MIPS16-2: .ent f ; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]]) diff --git a/test/CodeGen/Mips/brconnez.ll b/test/CodeGen/Mips/brconnez.ll index 27cf9e8cacb8..eafddccdd4c7 100644 --- a/test/CodeGen/Mips/brconnez.ll +++ b/test/CodeGen/Mips/brconnez.ll @@ -7,7 +7,7 @@ define void @test() nounwind { entry: %0 = load i32, i32* @j, align 4 %cmp = icmp eq i32 %0, 0 - br i1 %cmp, label %if.then, label %if.end + br i1 %cmp, label %if.then, label %if.end, !prof !1 ; 16: bnez ${{[0-9]+}}, $[[LABEL:[0-9A-Ba-b_]+]] ; 16: lw ${{[0-9]+}}, %got(result)(${{[0-9]+}}) @@ -21,4 +21,4 @@ if.end: ; preds = %if.then, %entry ret void } - +!1 = !{!"branch_weights", i32 2, i32 1} diff --git a/test/CodeGen/Mips/cconv/arguments-float.ll b/test/CodeGen/Mips/cconv/arguments-float.ll index a76cf6226dc0..004f6d94749d 100644 --- a/test/CodeGen/Mips/cconv/arguments-float.ll +++ b/test/CodeGen/Mips/cconv/arguments-float.ll @@ -49,7 +49,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)( +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles) ; The first four arguments are the same in O32/N32/N64. ; The first argument is floating point but soft-float is enabled so floating @@ -63,39 +63,39 @@ entry: ; NEW-DAG: sd $5, 16([[R2]]) ; O32 has run out of argument registers and starts using the stack -; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp) -; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 16($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 20($sp) ; O32-DAG: sw [[R3]], 24([[R2]]) ; O32-DAG: sw [[R4]], 28([[R2]]) ; NEW-DAG: sd $6, 24([[R2]]) -; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp) -; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp) ; O32-DAG: sw [[R3]], 32([[R2]]) ; O32-DAG: sw [[R4]], 36([[R2]]) ; NEW-DAG: sd $7, 32([[R2]]) -; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp) -; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp) ; O32-DAG: sw [[R3]], 40([[R2]]) ; O32-DAG: sw [[R4]], 44([[R2]]) ; NEW-DAG: sd $8, 40([[R2]]) -; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp) -; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp) ; O32-DAG: sw [[R3]], 48([[R2]]) ; O32-DAG: sw [[R4]], 52([[R2]]) ; NEW-DAG: sd $9, 48([[R2]]) -; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 56($sp) -; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 60($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp) ; O32-DAG: sw [[R3]], 56([[R2]]) ; O32-DAG: sw [[R4]], 60([[R2]]) ; NEW-DAG: sd $10, 56([[R2]]) ; N32/N64 have run out of registers and starts using the stack too -; O32-DAG: lw [[R3:\$[0-9]+]], 64($sp) -; O32-DAG: lw [[R4:\$[0-9]+]], 68($sp) +; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp) +; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp) ; O32-DAG: sw [[R3]], 64([[R2]]) ; O32-DAG: sw [[R4]], 68([[R2]]) ; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp) @@ -132,7 +132,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(floats)( +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats) ; The first four arguments are the same in O32/N32/N64. ; The first argument is floating point but soft-float is enabled so floating @@ -180,10 +180,10 @@ entry: ; ALL-LABEL: double_arg2: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. -; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) -; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)( -; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)( +; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) +; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes) +; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles) +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles) ; The first four arguments are the same in O32/N32/N64. ; The first argument isn't floating point so floating point registers are not @@ -207,10 +207,11 @@ entry: ; ALL-LABEL: float_arg2: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. -; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) -; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)( -; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(floats)( +; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) +; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes) +; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats) +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats) + ; The first four arguments are the same in O32/N32/N64. ; The first argument isn't floating point so floating point registers are not diff --git a/test/CodeGen/Mips/cconv/arguments-fp128.ll b/test/CodeGen/Mips/cconv/arguments-fp128.ll index 70df97608aa9..086ba9bce27a 100644 --- a/test/CodeGen/Mips/cconv/arguments-fp128.ll +++ b/test/CodeGen/Mips/cconv/arguments-fp128.ll @@ -30,7 +30,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(ldoubles) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(ldoubles)( +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(ldoubles) ; The first four arguments are the same in N32/N64. ; The first argument is floating point but soft-float is enabled so floating diff --git a/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll b/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll index 5f7a86534bdf..c59ec02fa2d4 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll @@ -42,7 +42,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)( +; SYM64-DAG: daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles) ; O32 forbids using floating point registers for the non-variable portion. ; N32/N64 allow it. @@ -107,7 +107,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(floats)( +; SYM64-DAG: daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats) ; The first four arguments are the same in O32/N32/N64. ; The non-variable portion should be unaffected. diff --git a/test/CodeGen/Mips/cconv/arguments-hard-float.ll b/test/CodeGen/Mips/cconv/arguments-hard-float.ll index 2e753d0f07cb..24bb95c7c68f 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-float.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-float.ll @@ -49,7 +49,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)( +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles) ; The first argument is floating point so floating point registers are used. ; The first argument is the same for O32/N32/N64 but the second argument differs @@ -111,8 +111,8 @@ entry: ; ALL-LABEL: float_args: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. -; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(floats) -; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(floats)( +; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(floats) +; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(floats) ; The first argument is floating point so floating point registers are used. ; The first argument is the same for O32/N32/N64 but the second argument differs @@ -164,9 +164,9 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) -; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)( +; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes) ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(doubles)( +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles) ; The first argument is the same in O32/N32/N64. ; ALL-DAG: sb $4, 1([[R1]]) @@ -195,9 +195,9 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) -; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)( +; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes) ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(floats)( +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats) ; The first argument is the same in O32/N32/N64. ; ALL-DAG: sb $4, 1([[R1]]) diff --git a/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll b/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll index 1a3b664d9159..6c601e96ed8d 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll @@ -30,7 +30,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(ldoubles) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(ldoubles)( +; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(ldoubles) ; The first four arguments are the same in N32/N64. ; ALL-DAG: sdc1 $f12, 16([[R2]]) diff --git a/test/CodeGen/Mips/cconv/arguments-struct.ll b/test/CodeGen/Mips/cconv/arguments-struct.ll index 44ea7c0f8337..6288b5d52fd9 100644 --- a/test/CodeGen/Mips/cconv/arguments-struct.ll +++ b/test/CodeGen/Mips/cconv/arguments-struct.ll @@ -28,7 +28,7 @@ entry: ; SYM32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(bytes) ; SYM32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(bytes) -; SYM64-DAG: ld [[PTR:\$[0-9]+]], %got_disp(bytes)( +; SYM64-DAG: addiu [[PTR:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) ; O32-BE-DAG: srl [[ARG:\$[0-9]+]], $4, 24 ; O32-BE-DAG: sb [[ARG]], 1([[PTR]]) diff --git a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll index ba3aeb598f50..b41b5b7597cb 100644 --- a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll +++ b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll @@ -259,7 +259,9 @@ entry: call void (i8*, ...) @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i32 0, i32 0), i64 inreg %3) ret void ; CHECK-LABEL: smallStruct_8b: + ; Check that the structure is not shifted before the pointer to str is loaded. ; CHECK-NOT: dsll + ; CHECK: lui } define void @smallStruct_9b(%struct.SmallStruct_9b* %ss) #0 { diff --git a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll index 74d3d859ed75..8a20f5e43f1c 100644 --- a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll +++ b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll @@ -96,6 +96,7 @@ entry: ret void ; CHECK-LABEL: smallStruct_1b1i: ; CHECK-NOT: dsll + ; CHECK: lui } define void @smallStruct_1b1s1b(%struct.SmallStruct_1b1s1b* %ss) #0 { @@ -129,6 +130,7 @@ entry: ret void ; CHECK-LABEL: smallStruct_1s1i: ; CHECK-NOT: dsll + ; CHECK: lui } define void @smallStruct_3b1s(%struct.SmallStruct_3b1s* %ss) #0 { diff --git a/test/CodeGen/Mips/cconv/arguments-varargs.ll b/test/CodeGen/Mips/cconv/arguments-varargs.ll index 9c20b882dcb6..d662128945f8 100644 --- a/test/CodeGen/Mips/cconv/arguments-varargs.ll +++ b/test/CodeGen/Mips/cconv/arguments-varargs.ll @@ -85,7 +85,7 @@ entry: ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; ALL-DAG: sh [[ARG1]], 2([[GV]]) @@ -203,7 +203,7 @@ entry: ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; ALL-DAG: sw [[ARG1]], 4([[GV]]) @@ -315,16 +315,15 @@ entry: ; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte ; order. ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) -; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) +; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA_TMP2]]) ; O32-DAG: sw [[ARG1]], 8([[GV]]) -; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) -; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 -; O32-DAG: sw [[VA2]], 0([[SP]]) -; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) +; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4 +; O32-DAG: sw [[VA3]], 0([[SP]]) +; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]]) ; O32-DAG: sw [[ARG1]], 12([[GV]]) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]]) @@ -349,10 +348,9 @@ entry: ; Load the second argument from the variable portion and copy it to the global. ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]]) ; O32-DAG: sw [[ARG2]], 16([[GV]]) -; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) -; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 -; O32-DAG: sw [[VA2]], 0([[SP]]) -; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]]) +; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4 +; O32-DAG: sw [[VA3]], 0([[SP]]) +; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]]) ; O32-DAG: sw [[ARG2]], 20([[GV]]) ; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]]) @@ -448,7 +446,7 @@ entry: ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; ALL-DAG: sh [[ARG1]], 2([[GV]]) @@ -566,7 +564,7 @@ entry: ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; ALL-DAG: sw [[ARG1]], 4([[GV]]) @@ -678,16 +676,15 @@ entry: ; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte ; order. ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) -; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) +; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA_TMP2]]) ; O32-DAG: sw [[ARG1]], 8([[GV]]) -; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) -; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 -; O32-DAG: sw [[VA2]], 0([[SP]]) -; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) +; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4 +; O32-DAG: sw [[VA3]], 0([[SP]]) +; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]]) ; O32-DAG: sw [[ARG1]], 12([[GV]]) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]]) @@ -712,10 +709,9 @@ entry: ; Load the second argument from the variable portion and copy it to the global. ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]]) ; O32-DAG: sw [[ARG2]], 16([[GV]]) -; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) -; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 +; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4 ; O32-DAG: sw [[VA2]], 0([[SP]]) -; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]]) +; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]]) ; O32-DAG: sw [[ARG2]], 20([[GV]]) ; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]]) @@ -810,7 +806,7 @@ entry: ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(hwords)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(hwords) ; ALL-DAG: sh [[ARG1]], 2([[GV]]) @@ -927,7 +923,7 @@ entry: ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(words)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(words) ; ALL-DAG: sw [[ARG1]], 4([[GV]]) @@ -1040,14 +1036,13 @@ entry: ; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) ; O32-DAG: sw [[ARG1]], 8([[GV]]) -; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) -; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 -; O32-DAG: sw [[VA2]], 0([[SP]]) -; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]]) +; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4 +; O32-DAG: sw [[VA3]], 0([[SP]]) +; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]]) ; O32-DAG: sw [[ARG1]], 12([[GV]]) ; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) -; N64-DAG: ld [[GV:\$[0-9]+]], %got_disp(dwords)( +; N64-DAG: daddiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]]) @@ -1072,10 +1067,9 @@ entry: ; Load the second argument from the variable portion and copy it to the global. ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]]) ; O32-DAG: sw [[ARG2]], 16([[GV]]) -; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) -; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4 -; O32-DAG: sw [[VA2]], 0([[SP]]) -; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]]) +; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4 +; O32-DAG: sw [[VA3]], 0([[SP]]) +; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]]) ; O32-DAG: sw [[ARG2]], 20([[GV]]) ; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]]) diff --git a/test/CodeGen/Mips/cconv/arguments.ll b/test/CodeGen/Mips/cconv/arguments.ll index 7af4e5517d51..2466d59045bb 100644 --- a/test/CodeGen/Mips/cconv/arguments.ll +++ b/test/CodeGen/Mips/cconv/arguments.ll @@ -55,7 +55,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) -; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)( +; SYM64-DAG: daddiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) ; The first four arguments are the same in O32/N32/N64 ; ALL-DAG: sb $4, 1([[R1]]) @@ -120,9 +120,9 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) -; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)( +; SYM64-DAG: daddiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) -; SYM64-DAG: ld [[R2:\$[0-9]+]], %got_disp(dwords)( +; SYM64-DAG: daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; The first argument is the same in O32/N32/N64. ; ALL-DAG: sb $4, 1([[R1]]) diff --git a/test/CodeGen/Mips/cconv/return-float.ll b/test/CodeGen/Mips/cconv/return-float.ll index b9a6d6c5bc0d..dd457fc18cd8 100644 --- a/test/CodeGen/Mips/cconv/return-float.ll +++ b/test/CodeGen/Mips/cconv/return-float.ll @@ -30,8 +30,7 @@ entry: ; O32-DAG: lw $2, %lo(float)([[R1]]) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float) ; N32-DAG: lw $2, %lo(float)([[R1]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)( -; N64-DAG: lw $2, 0([[R1]]) +; N64-DAG: lw $2, %lo(float)([[R1:\$[0-9+]]]) define double @retdouble() nounwind { entry: @@ -44,5 +43,4 @@ entry: ; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(double) ; O32-DAG: lw $3, 4([[R2]]) ; N32-DAG: ld $2, %lo(double)([[R1:\$[0-9]+]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)( -; N64-DAG: ld $2, 0([[R1]]) +; N64-DAG: ld $2, %lo(double)([[R1:\$[0-9]+]]) diff --git a/test/CodeGen/Mips/cconv/return-hard-float.ll b/test/CodeGen/Mips/cconv/return-hard-float.ll index 768cb6a9f2c6..44ef65ee2581 100644 --- a/test/CodeGen/Mips/cconv/return-hard-float.ll +++ b/test/CodeGen/Mips/cconv/return-hard-float.ll @@ -33,8 +33,7 @@ entry: ; O32-DAG: lwc1 $f0, %lo(float)([[R1]]) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float) ; N32-DAG: lwc1 $f0, %lo(float)([[R1]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)( -; N64-DAG: lwc1 $f0, 0([[R1]]) +; N64-DAG: lwc1 $f0, %lo(float)([[R1:\$[0-9+]]]) define double @retdouble() nounwind { entry: @@ -45,8 +44,7 @@ entry: ; ALL-LABEL: retdouble: ; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]]) ; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)( -; N64-DAG: ldc1 $f0, 0([[R1]]) +; N64-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]]) define { double, double } @retComplexDouble() #0 { %retval = alloca { double, double }, align 8 diff --git a/test/CodeGen/Mips/cconv/return-hard-fp128.ll b/test/CodeGen/Mips/cconv/return-hard-fp128.ll index bdbfb80bd4aa..e527866eb97b 100644 --- a/test/CodeGen/Mips/cconv/return-hard-fp128.ll +++ b/test/CodeGen/Mips/cconv/return-hard-fp128.ll @@ -24,8 +24,8 @@ entry: ; N32-DAG: dmtc1 [[R2]], $f0 ; N32-DAG: dmtc1 [[R4]], $f2 -; N64-DAG: ld [[R2:\$[0-9]+]], %got_disp(fp128)([[R1:\$[0-9]+]]) -; N64-DAG: ld [[R3:\$[0-9]+]], 0([[R2]]) +; N64-DAG: lui [[R2:\$[0-9]+]], %highest(fp128) +; N64-DAG: ld [[R3:\$[0-9]+]], %lo(fp128)([[R2]]) ; N64-DAG: ld [[R4:\$[0-9]+]], 8([[R2]]) ; N64-DAG: dmtc1 [[R3]], $f0 ; N64-DAG: dmtc1 [[R4]], $f2 diff --git a/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll b/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll index 9b178e4380d1..492db7689500 100644 --- a/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll +++ b/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll @@ -29,8 +29,8 @@ entry: ; N32-DAG: ld [[R4:\$[0-9]+]], 8([[R3]]) ; N32-DAG: dmtc1 [[R4]], $f1 -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(struct_fp128)($1) -; N64-DAG: ld [[R2:\$[0-9]+]], 0([[R1]]) +; N64-DAG: lui [[R1:\$[0-9]+]], %highest(struct_fp128) +; N64-DAG: ld [[R2:\$[0-9]+]], %lo(struct_fp128)([[R1]]) ; N64-DAG: dmtc1 [[R2]], $f0 ; N64-DAG: ld [[R4:\$[0-9]+]], 8([[R1]]) ; N64-DAG: dmtc1 [[R4]], $f1 diff --git a/test/CodeGen/Mips/cconv/return-struct.ll b/test/CodeGen/Mips/cconv/return-struct.ll index da20919ffd42..0997cfbd98a1 100644 --- a/test/CodeGen/Mips/cconv/return-struct.ll +++ b/test/CodeGen/Mips/cconv/return-struct.ll @@ -37,12 +37,10 @@ entry: ; N32-BE-DAG: lb [[R2:\$[0-9]+]], %lo(struct_byte)([[R1]]) ; N32-BE-DAG: dsll $2, [[R2]], 56 -; N64-LE-DAG: ld [[R1:\$[0-9]+]], %got_disp(struct_byte)($1) -; N64-LE-DAG: lb $2, 0([[R1]]) +; N64-LE-DAG: lb $2, %lo(struct_byte)(${{[0-9]+}}) -; N64-BE-DAG: ld [[R1:\$[0-9]+]], %got_disp(struct_byte)($1) -; N64-BE-DAG: lb [[R2:\$[0-9]+]], 0([[R1]]) -; N64-BE-DAG: dsll $2, [[R2]], 56 +; N64-BE-DAG: lb [[R1:\$[0-9]+]], %lo(struct_byte)(${{[0-9]+}}) +; N64-BE-DAG: dsll $2, [[R1]], 56 ; This test is based on the way clang currently lowers {i8,i8} to {i16}. ; FIXME: It should probably work for without any lowering too but this doesn't @@ -75,13 +73,15 @@ entry: ; N32-BE-DAG: lh [[R3:\$[0-9]+]], 8([[SP:\$sp]]) ; N32-BE-DAG: dsll $2, [[R3]], 48 -; N64-LE-DAG: ld [[R1:\$[0-9]+]], %got_disp(struct_2byte)($1) -; N64-LE-DAG: lhu [[R2:\$[0-9]+]], 0([[R1]]) +; N64-LE-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %hi(struct_2byte) +; N64-LE-DAG: dsll [[R1:\$[0-9]]], $[[R0]], 16 +; N64-LE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]]) ; N64-LE-DAG: sh [[R2]], 8([[SP:\$sp]]) ; N64-LE-DAG: lh $2, 8([[SP:\$sp]]) -; N64-BE-DAG: ld [[R1:\$[0-9]+]], %got_disp(struct_2byte)($1) -; N64-BE-DAG: lhu [[R2:\$[0-9]+]], 0([[R1]]) +; N64-BE-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %hi(struct_2byte) +; N64-BE-DAG: dsll $[[R1:[0-9]]], $[[R0]], 16 +; N64-BE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)($[[R1]]) ; N64-BE-DAG: sh [[R2]], 8([[SP:\$sp]]) ; N64-BE-DAG: lh [[R3:\$[0-9]+]], 8([[SP:\$sp]]) ; N64-BE-DAG: dsll $2, [[R3]], 48 @@ -126,14 +126,14 @@ entry: ; N32-BE-DAG: or [[R4:\$[0-9]+]], [[R3]], [[R2]] ; N32-BE-DAG: dsll $2, [[R4]], 16 -; N64-LE-DAG: ld [[PTR:\$[0-9]+]], %got_disp(struct_3xi16)($1) +; N64-LE-DAG: daddiu [[PTR:\$[0-9]+]], [[R0:\$[0-9]+]], %lo(struct_3xi16) ; N64-LE-DAG: lh [[R1:\$[0-9]+]], 4([[PTR]]) -; N64-LE-DAG: lwu [[R2:\$[0-9]+]], 0([[PTR]]) +; N64-LE-DAG: lwu [[R2:\$[0-9]+]], %lo(struct_3xi16)([[R0]]) ; N64-LE-DAG: dsll [[R3:\$[0-9]+]], [[R1]], 32 ; N64-LE-DAG: or $2, [[R2]], [[R3]] -; N64-BE-DAG: ld [[PTR:\$[0-9]+]], %got_disp(struct_3xi16)($1) -; N64-BE-DAG: lw [[R1:\$[0-9]+]], 0([[PTR]]) +; N64-BE-DAG: daddiu [[PTR:\$[0-9]+]], [[R0:\$[0-9]+]], %lo(struct_3xi16) +; N64-BE-DAG: lw [[R1:\$[0-9]+]], %lo(struct_3xi16)([[R0]]) ; N64-BE-DAG: dsll [[R2:\$[0-9]+]], [[R1]], 16 ; N64-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR]]) ; N64-BE-DAG: or [[R4:\$[0-9]+]], [[R3]], [[R2]] @@ -161,9 +161,8 @@ entry: ; N32: jal memcpy ; sret pointer is already in $4 -; N64-DAG: ld $5, %got_disp(struct_128xi16)( -; N64-DAG: ld $25, %call16(memcpy)( -; N64: jalr $25 +; N64-DAG: lui ${{[0-9]}}, %highest(struct_128xi16) +; N64: jal memcpy ; Ensure that large structures (>128-bit) are returned indirectly. ; This will generate inlined memcpy's anyway so pick the smallest large @@ -214,13 +213,14 @@ entry: ; N32-DAG: sw [[T5]], 20([[RET_PTR]]) ; sret pointer is already in $4 -; N64-DAG: ld [[PTR:\$[0-9]+]], %got_disp(struct_6xi32)( -; N64-DAG: lw [[T0:\$[0-9]+]], 0([[PTR]]) +; N64-DAG: lui [[PTR_HI:\$[0-9]+]], %highest(struct_6xi32) +; N64-DAG: daddiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_6xi32) ; N64-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]]) ; N64-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]]) ; N64-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]]) ; N64-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]]) ; N64-DAG: lw [[T5:\$[0-9]+]], 20([[PTR]]) +; N64-DAG: lw [[T0:\$[0-9]+]], %lo(struct_6xi32)([[PTR_HI]]) ; N64-DAG: sw [[T0]], 0($4) ; N64-DAG: sw [[T1]], 4($4) ; N64-DAG: sw [[T2]], 8($4) diff --git a/test/CodeGen/Mips/cconv/return.ll b/test/CodeGen/Mips/cconv/return.ll index 561c94cb5783..c2bbe77e54bb 100644 --- a/test/CodeGen/Mips/cconv/return.ll +++ b/test/CodeGen/Mips/cconv/return.ll @@ -33,8 +33,8 @@ entry: ; O32-DAG: lbu $2, %lo(byte)([[R1]]) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(byte) ; N32-DAG: lbu $2, %lo(byte)([[R1]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)( -; N64-DAG: lbu $2, 0([[R1]]) +; N64-DAG: lui [[R1:\$[0-9]+]], %highest(byte) +; N64-DAG: lbu $2, %lo(byte)([[R1]]) define i32 @reti32() nounwind { entry: @@ -47,8 +47,8 @@ entry: ; O32-DAG: lw $2, %lo(word)([[R1]]) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(word) ; N32-DAG: lw $2, %lo(word)([[R1]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)( -; N64-DAG: lw $2, 0([[R1]]) +; N64-DAG: lui [[R1:\$[0-9]+]], %highest(word) +; N64-DAG: lw $2, %lo(word)([[R1]]) define i64 @reti64() nounwind { entry: @@ -62,5 +62,5 @@ entry: ; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(dword) ; O32-DAG: lw $3, 4([[R2]]) ; N32-DAG: ld $2, %lo(dword)([[R1:\$[0-9]+]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(dword)([[R1:\$[0-9]+]]) -; N64-DAG: ld $2, 0([[R1]]) +; N64-DAG: lui [[R1:\$[0-9]+]], %highest(dword) +; N64-DAG: ld $2, %lo(dword)([[R1]]) diff --git a/test/CodeGen/Mips/cconv/roundl-call.ll b/test/CodeGen/Mips/cconv/roundl-call.ll index 8e4d6597784c..0861197290ae 100644 --- a/test/CodeGen/Mips/cconv/roundl-call.ll +++ b/test/CodeGen/Mips/cconv/roundl-call.ll @@ -5,8 +5,8 @@ ; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \ ; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \ -; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \ +; RUN: < %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT @@ -14,9 +14,11 @@ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \ -; RUN: | FileCheck %s -check-prefixes=ALL,N64,SOFT-FLOAT +; RUN: -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,N64,SOFT-FLOAT ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \ -; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,SOFT-FLOAT +; RUN: %s -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,N64,SOFT-FLOAT @fp128 = global fp128 zeroinitializer diff --git a/test/CodeGen/Mips/cins.ll b/test/CodeGen/Mips/cins.ll new file mode 100644 index 000000000000..4fe25564d1c1 --- /dev/null +++ b/test/CodeGen/Mips/cins.ll @@ -0,0 +1,92 @@ +; RUN: llc -march=mips64 -mcpu=octeon -target-abi=n64 < %s -o - | FileCheck %s + +define i64 @cins_zext(i32 signext %n) { +entry: + %shl = shl i32 %n, 5 + %conv = zext i32 %shl to i64 + ret i64 %conv + +; CHECK-LABEL: cins_zext: +; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 26 + +} + +define i64 @cins_and_shl(i64 zeroext %n) { +entry: + %and = shl i64 %n, 8 + %shl = and i64 %and, 16776960 + ret i64 %shl + +; CHECK-LABEL: cins_and_shl: +; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 15 + +} + +define i64 @cins_and_shl32(i64 zeroext %n) { +entry: + %and = shl i64 %n, 38 + %shl = and i64 %and, 18014123631575040 + ret i64 %shl + +; CHECK-LABEL: cins_and_shl32: +; CHECK: cins32 $[[R0:[0-9]+]], $[[R1:[0-9]+]], 6, 15 + +} + +define zeroext i16 @cins_and_shl_16(i16 zeroext %n) { +entry: + %0 = shl i16 %n, 2 + %1 = and i16 %0, 60 + ret i16 %1 + +; CHECK-LABEL: cins_and_shl_16: +; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 3 + +} + +define zeroext i8 @cins_and_shl_8(i8 zeroext %n) { +entry: + %0 = shl i8 %n, 2 + %1 = and i8 %0, 12 + ret i8 %1 + +; CHECK-LABEL: cins_and_shl_8: +; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 1 + +} + +define i32 @cins_i32(i32 signext %a) { +entry: + %and = shl i32 %a, 17 + %shl = and i32 %and, 536739840 + ret i32 %shl + +; CHECK-LABEL: cins_i32: +; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 17, 11 + +} + +define i64 @cins_shl_and(i32 signext %n) { +entry: + %and = and i32 %n, 65535 + %conv = zext i32 %and to i64 + %shl = shl nuw nsw i64 %conv, 31 + ret i64 %shl + +; CHECK-LABEL: cins_shl_and: +; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 31, 15 + +} + + +define i64 @cins_shl_and32(i32 signext %n) { +entry: + %and = and i32 %n, 65535 + %conv = zext i32 %and to i64 + %shl = shl nuw nsw i64 %conv, 47 + ret i64 %shl + +; CHECK-LABEL: cins_shl_and32: +; CHECK: cins32 $[[R0:[0-9]+]], $[[R1:[0-9]+]], 15, 15 + +} diff --git a/test/CodeGen/Mips/compactbranches/compact-branches-64.ll b/test/CodeGen/Mips/compactbranches/compact-branches-64.ll index cda42a33ccf6..1290acd29d96 100644 --- a/test/CodeGen/Mips/compactbranches/compact-branches-64.ll +++ b/test/CodeGen/Mips/compactbranches/compact-branches-64.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s +; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips64r6 \ +; RUN: -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s ; Function Attrs: nounwind define void @l() { diff --git a/test/CodeGen/Mips/compactbranches/compact-branches.ll b/test/CodeGen/Mips/compactbranches/compact-branches.ll index 75ff8a0bbcbb..ebbeea592354 100644 --- a/test/CodeGen/Mips/compactbranches/compact-branches.ll +++ b/test/CodeGen/Mips/compactbranches/compact-branches.ll @@ -1,5 +1,7 @@ -; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32 -; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static \ +; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32 +; RUN: llc -march=mipsel -mcpu=mips64r6 -relocation-model=pic -target-abi n64 \ +; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC ; Function Attrs: nounwind define void @l() { @@ -38,7 +40,7 @@ entry: ; PIC: jalrc $25 %call1 = tail call i32 @i() %cmp = icmp eq i32 %call, %call1 -; CHECK beqc +; CHECK: beqc br i1 %cmp, label %if.end, label %if.then if.then: ; preds = %entry: @@ -61,7 +63,7 @@ entry: ; PIC: jalrc $25 %call = tail call i32 @k() %cmp = icmp slt i32 %call, 0 -; CHECK : bgez +; CHECK: bgez br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry: diff --git a/test/CodeGen/Mips/compactbranches/empty-block.mir b/test/CodeGen/Mips/compactbranches/empty-block.mir new file mode 100644 index 000000000000..7831e51e3157 --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/empty-block.mir @@ -0,0 +1,92 @@ +# RUN: llc -march=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s + +# Check that empty blocks in the cfg don't cause the mips hazard scheduler to +# crash and that the nop is inserted correctly. + +# CHECK: blezc +# CHECK: nop +# CHECK: # BB#1: +# CHECK: .insn +# CHECK: # BB#2: +# CHECK: .insn +# CHECK: # BB#3: +# CHECK: jal + +--- | + ; ModuleID = '<stdin>' + source_filename = "<stdin>" + target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" + + declare i32 @k() + + declare void @f(i32) + + define void @l5() { + entry: + %call = tail call i32 @k() + %cmp = icmp sgt i32 %call, 0 + br i1 %cmp, label %if.then, label %if.end + + if.then: ; preds = %entry + tail call void @f(i32 signext 2) + br label %if.end + + if.end: ; preds = %if.then, %entry + ret void + } + +--- +name: l5 +alignment: 2 +exposesReturnsTwice: false +noVRegs: true +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 24 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 16 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +stack: + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%ra' } +body: | + bb.0.entry: + successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000) + liveins: %ra + + %sp = ADDiu %sp, -24 + CFI_INSTRUCTION def_cfa_offset 24 + SW killed %ra, %sp, 20 :: (store 4 into %stack.0) + CFI_INSTRUCTION offset %ra_64, -4 + JAL @k, csr_o32_fp64, implicit-def dead %ra, implicit-def %sp, implicit-def %v0 + BLEZ %v0, %bb.4.if.end, implicit-def %at + + bb.1.if.then: + successors: %bb.2.if.then(0x80000000) + + bb.2.if.then: + successors: %bb.3.if.then(0x80000000) + + bb.3.if.then: + successors: %bb.4.if.end(0x80000000) + + %a0 = ADDiu %zero, 2 + JAL @f, csr_o32_fp64, implicit-def dead %ra, implicit killed %a0, implicit-def %sp + + bb.4.if.end: + %ra = LW %sp, 20 :: (load 4 from %stack.0) + %sp = ADDiu %sp, 24 + PseudoReturn undef %ra + +... diff --git a/test/CodeGen/Mips/cstmaterialization/stack.ll b/test/CodeGen/Mips/cstmaterialization/stack.ll index 7266d00069cc..41b5bf638107 100644 --- a/test/CodeGen/Mips/cstmaterialization/stack.ll +++ b/test/CodeGen/Mips/cstmaterialization/stack.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32 -; RUN: llc -march=mips64el -mcpu=mips64 < %s | \ +; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-MIPS64 ; RUN: llc -march=mipsel -mcpu=mips64 -target-abi n32 < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-MIPSN32 diff --git a/test/CodeGen/Mips/dext.ll b/test/CodeGen/Mips/dext.ll new file mode 100644 index 000000000000..1794f16b2cd7 --- /dev/null +++ b/test/CodeGen/Mips/dext.ll @@ -0,0 +1,105 @@ +; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s + +define i64 @dext_add_zext(i32 signext %n) { +entry: + %add = add i32 %n, 1 + %res = zext i32 %add to i64 + ret i64 %res + +; CHECK-LABEL: dext_add_zext: +; CHECK: dext $[[R0:[0-9]+]], $[[R0:[0-9]+]], 0, 32 + +} + +define i32 @ext_and24(i32 signext %a) { +entry: + %and = and i32 %a, 16777215 + ret i32 %and + +; CHECK-LABEL: ext_and24: +; CHECK: ext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 24 + +} + +define i64 @dext_and32(i64 zeroext %a) { +entry: + %and = and i64 %a, 4294967295 + ret i64 %and + +; CHECK-LABEL: dext_and32: +; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32 + +} + +define i64 @dext_and35(i64 zeroext %a) { +entry: + %and = and i64 %a, 34359738367 + ret i64 %and + +; CHECK-LABEL: dext_and35: +; CHECK: dextm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 35 + +} + +define i64 @dext_and20(i64 zeroext %a) { +entry: + %and = and i64 %a, 1048575 + ret i64 %and + +; CHECK-LABEL: dext_and20: +; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 20 + +} + +define i64 @dext_and16(i64 zeroext %a) { +entry: + %and = and i64 %a, 65535 + ret i64 %and + +; CHECK-LABEL: dext_and16: +; CHECK: andi $[[R0:[0-9]+]], $[[R1:[0-9]+]], 65535 + +} + +define i64 @dext_lsr_and20(i64 zeroext %a) { +entry: + %shr = lshr i64 %a, 5 + %and = and i64 %shr, 1048575 + ret i64 %and + +; CHECK-LABEL: dext_lsr_and20: +; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 20 + +} + +define i64 @dext_lsr_and8(i64 zeroext %a) { +entry: + %shr = lshr i64 %a, 40 + %and = and i64 %shr, 255 + ret i64 %and + +; CHECK-LABEL: dext_lsr_and8: +; CHECK: dextu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 40, 8 + +} + +define i64 @dext_zext(i32 signext %a) { +entry: + %conv = zext i32 %a to i64 + ret i64 %conv + +; CHECK-LABEL: dext_zext: +; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32 + +} + +define i64 @dext_and_lsr(i64 zeroext %n) { +entry: + %and = lshr i64 %n, 8 + %shr = and i64 %and, 4095 + ret i64 %shr + +; CHECK-LABEL: dext_and_lsr: +; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 12 + +} diff --git a/test/CodeGen/Mips/elf_eflags.ll b/test/CodeGen/Mips/elf_eflags.ll index 40910d8987d2..80b9c48f5bee 100644 --- a/test/CodeGen/Mips/elf_eflags.ll +++ b/test/CodeGen/Mips/elf_eflags.ll @@ -14,7 +14,6 @@ ; EF_MIPS_ARCH_64R2 (0x80000000) ; Note that EF_MIPS_CPIC is set by -mabicalls which is the default on Linux -; TODO need to support -mno-abicalls ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE32 %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | FileCheck -check-prefix=CHECK-LE32_PIC %s @@ -24,12 +23,12 @@ ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips %s -o - | FileCheck -check-prefix=CHECK-LE32R2-MICROMIPS_PIC %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -target-abi n64 -relocation-model=pic %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n64 -relocation-model=pic %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64R2 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64R2_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n64 -relocation-model=pic %s -o - | FileCheck -check-prefix=CHECK-LE64R2_PIC %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mips16 -relocation-model=pic %s -o - | FileCheck -check-prefix=CHECK-LE32R2-MIPS16 %s @@ -61,7 +60,6 @@ ; CHECK-LE32R2-MICROMIPS_PIC: .set micromips ; ; 64(R1) bit with NO_REORDER and static -; CHECK-LE64: .abicalls ; CHECK-LE64: .set noreorder ; ; 64(R1) bit with NO_REORDER and PIC @@ -69,7 +67,6 @@ ; CHECK-LE64_PIC: .set noreorder ; ; 64R2 bit with NO_REORDER and static -; CHECK-LE64R2: .abicalls ; CHECK-LE64R2: .set noreorder ; ; 64R2 bit with NO_REORDER and PIC diff --git a/test/CodeGen/Mips/fastcc.ll b/test/CodeGen/Mips/fastcc.ll index 13abc20eb3e8..fb1bc4d9a8ab 100644 --- a/test/CodeGen/Mips/fastcc.ll +++ b/test/CodeGen/Mips/fastcc.ll @@ -132,20 +132,19 @@ entry: define internal fastcc void @callee0(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15, i32 %a16) nounwind noinline { entry: ; CHECK: callee0 -; CHECK: sw $4 -; CHECK: sw $5 -; CHECK: sw $6 -; CHECK: sw $7 -; CHECK: sw $8 -; CHECK: sw $9 -; CHECK: sw $10 -; CHECK: sw $11 -; CHECK: sw $12 -; CHECK: sw $13 -; CHECK: sw $14 -; CHECK: sw $15 -; CHECK: sw $24 -; CHECK: sw $3 +; CHECK-DAG: sw $4 +; CHECK-DAG: sw $5 +; CHECK-DAG: sw $7 +; CHECK-DAG: sw $8 +; CHECK-DAG: sw $9 +; CHECK-DAG: sw $10 +; CHECK-DAG: sw $11 +; CHECK-DAG: sw $12 +; CHECK-DAG: sw $13 +; CHECK-DAG: sw $14 +; CHECK-DAG: sw $15 +; CHECK-DAG: sw $24 +; CHECK-DAG: sw $3 ; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc. ; CHECK-NACL-NOT: sw $14 @@ -223,27 +222,27 @@ entry: define internal fastcc void @callee1(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15, float %a16, float %a17, float %a18, float %a19, float %a20) nounwind noinline { entry: -; CHECK: callee1 -; CHECK: swc1 $f0 -; CHECK: swc1 $f1 -; CHECK: swc1 $f2 -; CHECK: swc1 $f3 -; CHECK: swc1 $f4 -; CHECK: swc1 $f5 -; CHECK: swc1 $f6 -; CHECK: swc1 $f7 -; CHECK: swc1 $f8 -; CHECK: swc1 $f9 -; CHECK: swc1 $f10 -; CHECK: swc1 $f11 -; CHECK: swc1 $f12 -; CHECK: swc1 $f13 -; CHECK: swc1 $f14 -; CHECK: swc1 $f15 -; CHECK: swc1 $f16 -; CHECK: swc1 $f17 -; CHECK: swc1 $f18 -; CHECK: swc1 $f19 +; CHECK-LABEL: callee1: +; CHECK-DAG: swc1 $f0 +; CHECK-DAG: swc1 $f1 +; CHECK-DAG: swc1 $f2 +; CHECK-DAG: swc1 $f3 +; CHECK-DAG: swc1 $f4 +; CHECK-DAG: swc1 $f5 +; CHECK-DAG: swc1 $f6 +; CHECK-DAG: swc1 $f7 +; CHECK-DAG: swc1 $f8 +; CHECK-DAG: swc1 $f9 +; CHECK-DAG: swc1 $f10 +; CHECK-DAG: swc1 $f11 +; CHECK-DAG: swc1 $f12 +; CHECK-DAG: swc1 $f13 +; CHECK-DAG: swc1 $f14 +; CHECK-DAG: swc1 $f15 +; CHECK-DAG: swc1 $f16 +; CHECK-DAG: swc1 $f17 +; CHECK-DAG: swc1 $f18 +; CHECK-DAG: swc1 $f19 store float %a0, float* @gf0, align 4 store float %a1, float* @gf1, align 4 @@ -316,8 +315,6 @@ entry: ; NOODDSPREG-LABEL: callee2: -; NOODDSPREG: addiu $sp, $sp, -[[OFFSET:[0-9]+]] - ; Check that first 10 arguments are received in even float registers ; f0, f2, ... , f18. Check that 11th argument is received on stack. @@ -333,7 +330,7 @@ entry: ; NOODDSPREG-DAG: swc1 $f16, 32($[[R0]]) ; NOODDSPREG-DAG: swc1 $f18, 36($[[R0]]) -; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp) +; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*[02468]]], 0($sp) ; NOODDSPREG-DAG: swc1 $[[F0]], 40($[[R0]]) store float %a0, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 0), align 4 @@ -397,7 +394,6 @@ entry: ; FP64-NOODDSPREG-LABEL: callee3: -; FP64-NOODDSPREG: addiu $sp, $sp, -[[OFFSET:[0-9]+]] ; Check that first 10 arguments are received in even float registers ; f0, f2, ... , f18. Check that 11th argument is received on stack. @@ -414,7 +410,7 @@ entry: ; FP64-NOODDSPREG-DAG: sdc1 $f16, 64($[[R0]]) ; FP64-NOODDSPREG-DAG: sdc1 $f18, 72($[[R0]]) -; FP64-NOODDSPREG-DAG: ldc1 $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp) +; FP64-NOODDSPREG-DAG: ldc1 $[[F0:f[0-9]*[02468]]], 0($sp) ; FP64-NOODDSPREG-DAG: sdc1 $[[F0]], 80($[[R0]]) store double %a0, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 0), align 8 diff --git a/test/CodeGen/Mips/fcmp.ll b/test/CodeGen/Mips/fcmp.ll index e22b12a5d534..eb6c06db4eff 100644 --- a/test/CodeGen/Mips/fcmp.ll +++ b/test/CodeGen/Mips/fcmp.ll @@ -1076,12 +1076,12 @@ entry: ; 32-CMP-DAG: bnezc $[[T4]], ; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 -; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)( +; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %lo(.LCPI32_0)( ; 64-C-DAG: c.ole.s $[[T0]], $[[T1]] ; 64-C-DAG: bc1t ; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 -; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)( +; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo(.LCPI32_0)( ; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]] ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. @@ -1102,16 +1102,17 @@ entry: ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 ; MM32R6-DAG: bnez $[[T5]], -; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32))) -; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 -; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32))) -; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12 -; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page(.LCPI32_0)($[[T2]]) -; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst(.LCPI32_0)($[[T4]]) -; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]] -; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] -; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 -; MM64R6-DAG: bnez $[[T8]], +; MM64R6-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 +; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI32_0) +; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI32_0) +; MM64R6-DAG: dsll $[[T3:[0-9]+]], $[[T2]], 16 +; MM64R6-DAG: daddiu $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI32_0) +; MM64R6-DAG: dsll $[[T5:[0-9]+]], $[[T4]], 16 +; MM64R6-DAG: lwc1 $[[T6:f[0-9]+]], %lo(.LCPI32_0)($[[T5]]) +; MM64R6-DAG: cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]] +; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]] +; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1 +; MM64R6-DAG: bnez $[[T9]], %add = fadd fast float %at, %angle %cmp = fcmp ogt float %add, 1.000000e+00 @@ -1145,12 +1146,12 @@ entry: ; 32-CMP-DAG: bnezc $[[T4]], ; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 -; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)( +; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %lo(.LCPI33_0)( ; 64-C-DAG: c.ole.d $[[T0]], $[[T1]] ; 64-C-DAG: bc1t ; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 -; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)( +; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo(.LCPI33_0)( ; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]] ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. @@ -1171,16 +1172,17 @@ entry: ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 ; MM32R6-DAG: bnez $[[T5]], -; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64))) -; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 -; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64))) -; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12 -; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page(.LCPI33_0)($[[T2]]) -; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst(.LCPI33_0)($[[T4]]) -; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]] -; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] -; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 -; MM64R6-DAG: bnez $[[T8]], +; MM64R6-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 +; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI33_0) +; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI33_0) +; MM64R6-DAG: dsll $[[T3:[0-9]+]], $[[T2]], 16 +; MM64R6-DAG: daddiu $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI33_0) +; MM64R6-DAG: dsll $[[T5:[0-9]+]], $[[T4]], 16 +; MM64R6-DAG: ldc1 $[[T6:f[0-9]+]], %lo(.LCPI33_0)($[[T5]]) +; MM64R6-DAG: cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]] +; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]] +; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1 +; MM64R6-DAG: bnez $[[T9]], %add = fadd fast double %at, %angle %cmp = fcmp ogt double %add, 1.000000e+00 diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll index a3ea22feca25..e0229d14c526 100644 --- a/test/CodeGen/Mips/fcopysign-f32-f64.ll +++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -36,12 +36,12 @@ define double @func3(double %d, float %f) nounwind readnone { entry: ; ALL-LABEL: func3: -; 64: dmfc1 $[[R0:[0-9]+]], ${{.*}} +; 64: mfc1 $[[MFC:[0-9]+]], $f13 ; 64: daddiu $[[R1:[0-9]+]], $zero, 1 +; 64: dmfc1 $[[R0:[0-9]+]], ${{.*}} ; 64: dsll $[[R2:[0-9]+]], $[[R1]], 63 ; 64: daddiu $[[R3:[0-9]+]], $[[R2]], -1 ; 64: and $[[AND0:[0-9]+]], $[[R0]], $[[R3]] -; 64: mfc1 $[[MFC:[0-9]+]], $f13 ; 64: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] diff --git a/test/CodeGen/Mips/global-address.ll b/test/CodeGen/Mips/global-address.ll index ecf5e563a577..ed79de920e85 100644 --- a/test/CodeGen/Mips/global-address.ll +++ b/test/CodeGen/Mips/global-address.ll @@ -29,9 +29,15 @@ entry: ; PIC-N64: ld $[[R0:[0-9]+]], %got_page(s1) ; PIC-N64: lw ${{[0-9]+}}, %got_ofst(s1)($[[R0]]) ; PIC-N64: ld ${{[0-9]+}}, %got_disp(g1) -; STATIC-N64: ld $[[R1:[0-9]+]], %got_page(s1) -; STATIC-N64: lw ${{[0-9]+}}, %got_ofst(s1)($[[R1]]) -; STATIC-N64: ld ${{[0-9]+}}, %got_disp(g1) +; STATIC-N64: lui $[[R1:[0-9]+]], %highest(s1) +; STATIC-N64: daddiu ${{[0-9]+}}, ${{[0-9]+}}, %higher(s1) +; STATIC-N64: daddiu ${{[0-9]+}}, ${{[0-9]+}}, %hi(s1) +; STATIC-N64: dsll $[[R2:[0-9]+]], $[[R1]], 16 +; STATIC-N64: lw ${{[0-9]+}}, %lo(s1)($[[R2]]) +; STATIC-N64: lui $[[R3:[0-9]+]], %highest(g1) +; STATIC-N64: daddiu $[[R3]], $[[R3]], %higher(g1) +; STATIC-N64: daddiu $[[R3]], $[[R3]], %hi(g1) +; STATIC-N64: lw ${{[0-9]+}}, %lo(g1)($[[R3]]) %0 = load i32, i32* @s1, align 4 tail call void @foo1(i32 %0) nounwind diff --git a/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll b/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll index a99cb976eaa9..2a0904c54c9a 100644 --- a/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll +++ b/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll @@ -1,7 +1,9 @@ ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6 -; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck %s --check-prefixes=ALL,R6 +; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic \ +; RUN: < %s | FileCheck %s --check-prefixes=ALL,R6 ; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6 -; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s --check-prefixes=ALL,PRER6 +; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 -relocation-model=pic \ +; RUN: < %s | FileCheck %s --check-prefixes=ALL,PRER6 %struct.anon = type { [63 x i32], i32, i32 } diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll index c8d0e76f94e2..f9fb91be0906 100644 --- a/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -83,20 +83,23 @@ entry: ; M2: srav $[[T0:[0-9]+]], $4, $7 ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] ; M2: move $3, $[[T0]] + ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: nop + ; M2: $[[EXIT:BB[0-9_]+]]: + ; M2: jr $ra + ; M2: nop + ; M2: $[[BB0]]: ; M2: srlv $[[T2:[0-9]+]], $5, $7 ; M2: not $[[T3:[0-9]+]], $7 ; M2: sll $[[T4:[0-9]+]], $4, 1 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; M2: beqz $[[T1]], $[[EXIT]] ; M2: or $3, $[[T3]], $[[T2]] - ; M2: $[[BB0]]: - ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] - ; M2: nop - ; M2: sra $2, $4, 31 ; M2: $[[BB1]]: ; M2: jr $ra - ; M2: nop + ; M2: sra $2, $4, 31 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 ; 32R1-R5: not $[[T1:[0-9]+]], $7 @@ -169,20 +172,23 @@ entry: ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsrav $[[T1:[0-9]+]], $4, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: bnez $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]] + ; M3: beqz $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]] ; M3: move $3, $[[T1]] + ; M3: bnez $[[T3]], [[BB1:.LBB[0-9_]+]] + ; M3: nop + ; M3: [[EXIT:.LBB[0-9_]+]]: + ; M3: jr $ra + ; M3: nop + ; M3: [[BB0]]: ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; M3: beqz $[[T3]], [[EXIT]] ; M3: or $3, $[[T7]], $[[T4]] - ; M3: [[BB0]]: - ; M3: beqz $[[T3]], [[BB1:.LBB[0-9_]+]] - ; M3: nop - ; M3: dsra $2, $4, 63 ; M3: [[BB1]]: ; M3: jr $ra - ; M3: nop + ; M3: dsra $2, $4, 63 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index 9af3e8d8cd23..a036fafbe969 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -6,24 +6,24 @@ ; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C -; RUN: llc -march=mips64 -mcpu=mips4 -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64 -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r2 -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r3 -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r5 -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,R6C ; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C ; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C ; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C ; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C -; RUN: llc -march=mips64 -mcpu=mips4 -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64 -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r2 -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r3 -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r5 -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C +; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C declare void @extern_void_void() declare i32 @extern_i32_void() diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll index 09617edc9406..926f3e4c8d79 100644 --- a/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -81,20 +81,24 @@ entry: ; M2: srlv $[[T0:[0-9]+]], $4, $7 ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] ; M2: move $3, $[[T0]] + ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: addiu $2, $zero, 0 + ; M2: $[[EXIT:BB[0-9_]+]]: + ; M2: jr $ra + ; M2: nop + ; M2: $[[BB0]]: ; M2: srlv $[[T2:[0-9]+]], $5, $7 ; M2: not $[[T3:[0-9]+]], $7 ; M2: sll $[[T4:[0-9]+]], $4, 1 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] ; M2: or $3, $[[T3]], $[[T2]] - ; M2: $[[BB0]]: - ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: bnez $[[T1]], $[[EXIT:BB[0-9_]+]] ; M2: addiu $2, $zero, 0 - ; M2: move $2, $[[T0]] ; M2: $[[BB1]]: ; M2: jr $ra - ; M2: nop + ; M2: move $2, $[[T0]] ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 ; 32R1-R5: not $[[T1:[0-9]+]], $7 @@ -160,20 +164,24 @@ entry: ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsrlv $[[T1:[0-9]+]], $4, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: bnez $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] + ; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] ; M3: move $3, $[[T1]] + ; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]] + ; M3: daddiu $2, $zero, 0 + ; M3: [[EXIT:\.LBB[0-9_]+]]: + ; M3: jr $ra + ; M3: nop + ; M3: [[BB0]]: ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: or $3, $[[T7]], $[[T4]] - ; M3: [[BB0]]: - ; M3: bnez $[[T3]], [[BB1:\.LBB[0-9_]+]] + ; M3: bnez $[[T3]], [[EXIT]] ; M3: daddiu $2, $zero, 0 - ; M3: move $2, $[[T1]] ; M3: [[BB1]]: ; M3: jr $ra - ; M3: nop + ; M3: move $2, $[[T1]] ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll index ce3b91373f7f..13545907e21e 100644 --- a/test/CodeGen/Mips/llvm-ir/shl.ll +++ b/test/CodeGen/Mips/llvm-ir/shl.ll @@ -97,20 +97,24 @@ entry: ; M2: sllv $[[T0:[0-9]+]], $5, $7 ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] ; M2: move $2, $[[T0]] + ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: addiu $3, $zero, 0 + ; M2: $[[EXIT:BB[0-9_]+]]: + ; M2: jr $ra + ; M2: nop + ; M2: $[[BB0]]: ; M2: sllv $[[T2:[0-9]+]], $4, $7 ; M2: not $[[T3:[0-9]+]], $7 ; M2: srl $[[T4:[0-9]+]], $5, 1 ; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]] ; M2: or $2, $[[T2]], $[[T3]] - ; M2: $[[BB0]]: - ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: bnez $[[T1]], $[[EXIT]] ; M2: addiu $3, $zero, 0 - ; M2: move $3, $[[T0]] ; M2: $[[BB1]]: ; M2: jr $ra - ; M2: nop + ; M2: move $3, $[[T0]] ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7 ; 32R1-R5: not $[[T1:[0-9]+]], $7 @@ -176,20 +180,24 @@ entry: ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsllv $[[T1:[0-9]+]], $5, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: bnez $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] + ; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] ; M3: move $2, $[[T1]] + ; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]] + ; M3: daddiu $3, $zero, 0 + ; M3: [[EXIT:\.LBB[0-9_]+]]: + ; M3: jr $ra + ; M3: nop + ; M3: [[BB0]]: ; M3: dsllv $[[T4:[0-9]+]], $4, $7 ; M3: dsrl $[[T5:[0-9]+]], $5, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: or $2, $[[T4]], $[[T7]] - ; M3: [[BB0]]: - ; M3: bnez $[[T3]], [[BB1:\.LBB[0-9_]+]] + ; M3: bnez $[[T3]], [[EXIT]] ; M3: daddiu $3, $zero, 0 - ; M3: move $3, $[[T1]] ; M3: [[BB1]]: ; M3: jr $ra - ; M3: nop + ; M3: move $3, $[[T1]] ; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7 ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1 diff --git a/test/CodeGen/Mips/load-store-left-right.ll b/test/CodeGen/Mips/load-store-left-right.ll index 3bd924a81200..b998772d367c 100644 --- a/test/CodeGen/Mips/load-store-left-right.ll +++ b/test/CodeGen/Mips/load-store-left-right.ll @@ -8,8 +8,8 @@ ; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s ; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s ; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s -; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s +; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EL %s +; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EB %s ; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EL %s ; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EB %s @@ -37,9 +37,15 @@ entry: ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) ; MIPS64-EL: lwr $[[R0]], 0($[[R1]]) +; MIPS64R2-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; MIPS64R2-EL: lwr $[[R0]], 0($[[R1]]) + ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) ; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) +; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]]) + ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( ; MIPS64R6: lw $2, 0($[[PTR]]) @@ -63,9 +69,15 @@ entry: ; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) ; MIPS64-EL: swr $[[R0]], 0($[[R1]]) +; MIPS64R2-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; MIPS64R2-EL: swr $[[R0]], 0($[[R1]]) + ; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) ; MIPS64-EB: swr $[[R0]], 3($[[R1]]) +; MIPS64R2-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; MIPS64R2-EB: swr $[[R0]], 3($[[R1]]) + ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( ; MIPS64R6: sw $4, 0($[[PTR]]) @@ -94,9 +106,15 @@ entry: ; MIPS64-EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) ; MIPS64-EL: ldr $[[R0]], 0($[[R1]]) +; MIPS64R2-EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) +; MIPS64R2-EL: ldr $[[R0]], 0($[[R1]]) + ; MIPS64-EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) ; MIPS64-EB: ldr $[[R0]], 7($[[R1]]) +; MIPS64R2-EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; MIPS64R2-EB: ldr $[[R0]], 7($[[R1]]) + ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sll)( ; MIPS64R6: ld $2, 0($[[PTR]]) @@ -123,9 +141,15 @@ entry: ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) ; MIPS64-EL: lwr $[[R0]], 0($[[R1]]) +; MIPS64R2-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; MIPS64R2-EL: lwr $[[R0]], 0($[[R1]]) + ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) ; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) +; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]]) + ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( ; MIPS64R6: lw $2, 0($[[PTR]]) @@ -159,9 +183,17 @@ entry: ; MIPS64-EL-DAG: daddiu $[[R4:[0-9]+]], $[[R3]], -1 ; MIPS64-EL-DAG: and ${{[0-9]+}}, $[[R0]], $[[R4]] +; MIPS64R2-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; MIPS64R2-EL-DAG: lwr $[[R0]], 0($[[R1]]) +; MIPS64R2-EL-DAG: dext $[[R0]], $[[R0]], 0, 32 + ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) ; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) +; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]]) +; MIPS64R2-EB: dext $[[R0]], $[[R0]], 0, 32 + ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sui)( ; MIPS64R6: lwu $2, 0($[[PTR]]) @@ -191,9 +223,15 @@ entry: ; MIPS64-EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) ; MIPS64-EL: sdr $[[R0]], 0($[[R1]]) +; MIPS64R2-EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) +; MIPS64R2-EL: sdr $[[R0]], 0($[[R1]]) + ; MIPS64-EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) ; MIPS64-EB: sdr $[[R0]], 7($[[R1]]) +; MIPS64R2-EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; MIPS64R2-EB: sdr $[[R0]], 7($[[R1]]) + ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sll)( ; MIPS64R6: sd $4, 0($[[PTR]]) @@ -217,9 +255,15 @@ entry: ; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) ; MIPS64-EL: swr $[[R0]], 0($[[R1]]) +; MIPS64R2-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) +; MIPS64R2-EL: swr $[[R0]], 0($[[R1]]) + ; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) ; MIPS64-EB: swr $[[R0]], 3($[[R1]]) +; MIPS64R2-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) +; MIPS64R2-EB: swr $[[R0]], 3($[[R1]]) + ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( ; MIPS64R6: sw $4, 0($[[PTR]]) @@ -247,15 +291,23 @@ entry: ; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s0)( ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s0)( ; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( +; MIPS64R2-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( ; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( +; MIPS64R2-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( -; FIXME: We should be able to do better than this on MIPS32r6/MIPS64r6 since -; we have unaligned halfword load/store available -; ALL-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) -; ALL-DAG: sb $[[R1]], 2($[[PTR]]) -; ALL-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) -; ALL-DAG: sb $[[R1]], 3($[[PTR]]) +; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS32-DAG: sb $[[R1]], 2($[[PTR]]) +; MIPS32-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]]) +; MIPS32-DAG: sb $[[R2]], 3($[[PTR]]) + +; MIPS32R6: lhu $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS32R6: sh $[[R1]], 2($[[PTR]]) + +; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64-DAG: sb $[[R1]], 2($[[PTR]]) +; MIPS64-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]]) +; MIPS64-DAG: sb $[[R2]], 3($[[PTR]]) %0 = load %struct.S0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 0), align 1 store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 1), align 1 @@ -268,37 +320,65 @@ entry: ; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s1)( ; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s1)( -; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) -; MIPS32-DAG: sb $[[R1]], 4($[[PTR]]) -; MIPS32-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) -; MIPS32-DAG: sb $[[R1]], 5($[[PTR]]) -; MIPS32-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) -; MIPS32-DAG: sb $[[R1]], 6($[[PTR]]) -; MIPS32-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) -; MIPS32-DAG: sb $[[R1]], 7($[[PTR]]) +; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) +; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]]) +; MIPS32-EL-DAG: swl $[[R1]], 7($[[PTR]]) +; MIPS32-EL-DAG: swr $[[R1]], 4($[[PTR]]) +; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]]) +; MIPS32-EB-DAG: swl $[[R1]], 4($[[PTR]]) +; MIPS32-EB-DAG: swr $[[R1]], 7($[[PTR]]) + +; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 4($[[PTR]]) +; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) +; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 5($[[PTR]]) +; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) +; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 6($[[PTR]]) +; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) +; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 7($[[PTR]]) ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s1)( -; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]]) -; MIPS32R6-DAG: sh $[[R1]], 4($[[PTR]]) -; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]]) -; MIPS32R6-DAG: sh $[[R1]], 6($[[PTR]]) +; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS32R6-DAG: sw $[[R1]], 4($[[PTR]]) ; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( +; MIPS64R2-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( ; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( -; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) -; MIPS64-DAG: sb $[[R1]], 4($[[PTR]]) -; MIPS64-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) -; MIPS64-DAG: sb $[[R1]], 5($[[PTR]]) -; MIPS64-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) -; MIPS64-DAG: sb $[[R1]], 6($[[PTR]]) -; MIPS64-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) -; MIPS64-DAG: sb $[[R1]], 7($[[PTR]]) +; MIPS64R2-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( + +; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) +; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]]) +; MIPS64-EL-DAG: swl $[[R1]], 7($[[PTR]]) +; MIPS64-EL-DAG: swr $[[R1]], 4($[[PTR]]) + +; MIPS64R2-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) +; MIPS64R2-EL-DAG: lwr $[[R1]], 0($[[PTR]]) +; MIPS64R2-EL-DAG: swl $[[R1]], 7($[[PTR]]) +; MIPS64R2-EL-DAG: swr $[[R1]], 4($[[PTR]]) + +; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]]) +; MIPS64-EB-DAG: swl $[[R1]], 4($[[PTR]]) +; MIPS64-EB-DAG: swr $[[R1]], 7($[[PTR]]) + +; MIPS64R2-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64R2-EB-DAG: lwr $[[R1]], 3($[[PTR]]) +; MIPS64R2-EB-DAG: swl $[[R1]], 4($[[PTR]]) +; MIPS64R2-EB-DAG: swr $[[R1]], 7($[[PTR]]) + +; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 4($[[PTR]]) +; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) +; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 5($[[PTR]]) +; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) +; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 6($[[PTR]]) +; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) +; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 7($[[PTR]]) ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( -; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]]) -; MIPS64R6-DAG: sh $[[R1]], 4($[[PTR]]) -; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]]) -; MIPS64R6-DAG: sh $[[R1]], 6($[[PTR]]) +; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64R6-DAG: sw $[[R1]], 4($[[PTR]]) %0 = load %struct.S1, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 0), align 1 store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 1), align 1 @@ -336,30 +416,34 @@ entry: ; MIPS32R6-DAG: sw $[[R1]], 12($[[PTR]]) ; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( -; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) -; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]]) -; MIPS64-EL-DAG: swl $[[R1]], 11($[[PTR]]) -; MIPS64-EL-DAG: swr $[[R1]], 8($[[PTR]]) -; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 7($[[PTR]]) -; MIPS64-EL-DAG: lwr $[[R1]], 4($[[PTR]]) -; MIPS64-EL-DAG: swl $[[R1]], 15($[[PTR]]) -; MIPS64-EL-DAG: swr $[[R1]], 12($[[PTR]]) + +; MIPS64-EL-DAG: ldl $[[R1:[0-9]+]], 7($[[PTR]]) +; MIPS64-EL-DAG: ldr $[[R1]], 0($[[PTR]]) +; MIPS64-EL-DAG: sdl $[[R1]], 15($[[PTR]]) +; MIPS64-EL-DAG: sdr $[[R1]], 8($[[PTR]]) + +; MIPS64R2-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( + +; MIPS64R2-EL-DAG: ldl $[[R1:[0-9]+]], 7($[[PTR]]) +; MIPS64R2-EL-DAG: ldr $[[R1]], 0($[[PTR]]) +; MIPS64R2-EL-DAG: sdl $[[R1]], 15($[[PTR]]) +; MIPS64R2-EL-DAG: sdr $[[R1]], 8($[[PTR]]) ; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( -; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) -; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]]) -; MIPS64-EB-DAG: swl $[[R1]], 8($[[PTR]]) -; MIPS64-EB-DAG: swr $[[R1]], 11($[[PTR]]) -; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]]) -; MIPS64-EB-DAG: lwr $[[R1]], 7($[[PTR]]) -; MIPS64-EB-DAG: swl $[[R1]], 12($[[PTR]]) -; MIPS64-EB-DAG: swr $[[R1]], 15($[[PTR]]) +; MIPS64-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64-EB-DAG: ldr $[[R1]], 7($[[PTR]]) +; MIPS64-EB-DAG: sdl $[[R1]], 8($[[PTR]]) +; MIPS64-EB-DAG: sdr $[[R1]], 15($[[PTR]]) + +; MIPS64R2-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( +; MIPS64R2-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64R2-EB-DAG: ldr $[[R1]], 7($[[PTR]]) +; MIPS64R2-EB-DAG: sdl $[[R1]], 8($[[PTR]]) +; MIPS64R2-EB-DAG: sdr $[[R1]], 15($[[PTR]]) ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( -; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]]) -; MIPS64R6-DAG: sw $[[R1]], 8($[[PTR]]) -; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 4($[[PTR]]) -; MIPS64R6-DAG: sw $[[R1]], 12($[[PTR]]) +; MIPS64R6-DAG: ld $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64R6-DAG: sd $[[R1]], 8($[[PTR]]) %0 = load %struct.S2, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 0), align 1 store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 1), align 1 @@ -416,20 +500,39 @@ entry: ; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) ; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]]) -; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)( -; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) -; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]]) -; MIPS64-EB-DAG: dsll $[[R1]], $[[R1]], 32 +; MIPS64R2-EL: ld $[[SPTR:[0-9]+]], %got_disp(arr)( +; MIPS64R2-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) +; MIPS64R2-EL-DAG: lwr $[[R1]], 0($[[PTR]]) + +; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)( ; MIPS64-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]]) ; MIPS64-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]]) ; MIPS64-EB-DAG: dsll $[[T0:[0-9]+]], $[[R3]], 8 ; MIPS64-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]] -; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16 -; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R1]], $[[T1]] ; MIPS64-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) +; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16 +; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) +; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]]) +; MIPS64-EB-DAG: dsll $[[R5:[0-9]+]], $[[R1]], 32 +; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R5]], $[[T1]] ; MIPS64-EB-DAG: dsll $[[T4:[0-9]+]], $[[R4]], 8 ; MIPS64-EB-DAG: or $4, $[[T3]], $[[T4]] +; MIPS64R2-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)( +; MIPS64R2-EB-DAG: lbu $[[R1:[0-9]+]], 5($[[PTR]]) +; MIPS64R2-EB-DAG: lbu $[[R2:[0-9]+]], 4($[[PTR]]) +; MIPS64R2-EB-DAG: dsll $[[T0:[0-9]+]], $[[R2]], 8 +; MIPS64R2-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R1]] +; MIPS64R2-EB-DAG: dsll $[[T1]], $[[T1]], 16 +; MIPS64R2-EB-DAG: lwl $[[R3:[0-9]+]], 0($[[PTR]]) +; MIPS64R2-EB-DAG: lwr $[[R3]], 3($[[PTR]]) +; MIPS64R2-EB-DAG: dext $[[R3]], $[[R3]], 0, 32 +; MIPS64R2-EB-DAG: dsll $[[R3]], $[[R3]], 32 +; MIPS64R2-EB-DAG: or $[[T2:[0-9]+]], $[[R3]], $[[T1]] +; MIPS64R2-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) +; MIPS64R2-EB-DAG: dsll $[[T3:[0-9]+]], $[[R4]], 8 +; MIPS64R2-EB-DAG: or $4, $[[T2]], $[[T3]] + ; MIPS64R6: ld $[[SPTR:[0-9]+]], %got_disp(arr)( tail call void @extern_func([7 x i8]* byval @arr) nounwind diff --git a/test/CodeGen/Mips/mature-mc-support.ll b/test/CodeGen/Mips/mature-mc-support.ll index 6e5998d8a7cb..9c93e96a376b 100644 --- a/test/CodeGen/Mips/mature-mc-support.ll +++ b/test/CodeGen/Mips/mature-mc-support.ll @@ -29,4 +29,4 @@ module asm " .this_directive_is_very_unlikely_to_exist" -; CHECK: LLVM ERROR: Error parsing inline asm +; CHECK: error: unknown directive diff --git a/test/CodeGen/Mips/micromips-compact-branches.ll b/test/CodeGen/Mips/micromips-compact-branches.ll index c689944d386b..332cd8cd105c 100644 --- a/test/CodeGen/Mips/micromips-compact-branches.ll +++ b/test/CodeGen/Mips/micromips-compact-branches.ll @@ -6,7 +6,7 @@ entry: %x = alloca i32, align 4 %0 = load i32, i32* %x, align 4 %cmp = icmp eq i32 %0, 0 - br i1 %cmp, label %if.then, label %if.end + br i1 %cmp, label %if.then, label %if.end, !prof !1 if.then: store i32 10, i32* %x, align 4 @@ -17,3 +17,4 @@ if.end: } ; CHECK: bnezc +!1 = !{!"branch_weights", i32 2, i32 1} diff --git a/test/CodeGen/Mips/micromips-li.ll b/test/CodeGen/Mips/micromips-li.ll index ac315f938251..997f4e9196af 100644 --- a/test/CodeGen/Mips/micromips-li.ll +++ b/test/CodeGen/Mips/micromips-li.ll @@ -13,6 +13,6 @@ entry: ret i32 0 } -; CHECK: li16 ${{[2-7]|16|17}}, 1 ; CHECK: addiu ${{[0-9]+}}, $zero, 2148 +; CHECK: li16 ${{[2-7]|16|17}}, 1 ; CHECK: ori ${{[0-9]+}}, $zero, 33332 diff --git a/test/CodeGen/Mips/mips64-f128-call.ll b/test/CodeGen/Mips/mips64-f128-call.ll index 9a093e6f9825..19fa8fc75245 100644 --- a/test/CodeGen/Mips/mips64-f128-call.ll +++ b/test/CodeGen/Mips/mips64-f128-call.ll @@ -4,8 +4,8 @@ @gld1 = external global fp128 ; CHECK: foo0 -; CHECK: sdc1 $f13, 8(${{[0-9]+}}) -; CHECK: sdc1 $f12, 0(${{[0-9]+}}) +; CHECK-DAG: sdc1 $f12, %lo(gld0)(${{[0-9]+}}) +; CHECK-DAG: sdc1 $f13, 8(${{[0-9]+}}) define void @foo0(fp128 %a0) { entry: @@ -14,8 +14,8 @@ entry: } ; CHECK: foo1 -; CHECK: ldc1 $f13, 8(${{[0-9]+}}) -; CHECK: ldc1 $f12, 0(${{[0-9]+}}) +; CHECK-DAG: ldc1 $f12, %lo(gld0)(${{[0-9]+}}) +; CHECK-DAG: ldc1 $f13, 8(${{[0-9]+}}) define void @foo1() { entry: @@ -26,13 +26,18 @@ entry: declare void @foo2(fp128) -; CHECK: foo3 -; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld0) -; CHECK: sdc1 $f2, 8($[[R0]]) -; CHECK: sdc1 $f0, 0($[[R0]]) -; CHECK: ld $[[R1:[0-9]+]], %got_disp(gld1) -; CHECK: ldc1 $f0, 0($[[R1]]) -; CHECK: ldc1 $f2, 8($[[R1]]) + +; CHECK: foo3: + +; CHECK: daddiu $[[R2:[0-9]+]], $[[R1:[0-9]+]], %lo(gld0) +; CHECK: sdc1 $f0, %lo(gld0)($[[R1]]) +; CHECK: sdc1 $f2, 8($[[R2]]) +; CHECK: daddiu $[[R3:[0-9]+]], ${{[0-9]+}}, %hi(gld1) +; CHECK: dsll $[[R4:[0-9]+]], $[[R3]], 16 +; CHECK: ldc1 $f0, %lo(gld1)($[[R4]]) +; CHECK: daddiu $[[R5:[0-9]]], $[[R4]], %lo(gld1) +; CHECK: ldc1 $f2, 8($[[R5]]) + define fp128 @foo3() { entry: diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll index 2b1c154f095b..a6dafb1abfd6 100644 --- a/test/CodeGen/Mips/mips64-f128.ll +++ b/test/CodeGen/Mips/mips64-f128.ll @@ -1,11 +1,15 @@ ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -mattr=+soft-float -O1 \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6 +; RUN: -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck \ +; RUN: %s -check-prefixes=ALL,C_CC_FMT,PRER6,NOT-R2R6 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -mattr=+soft-float -O1 \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6 -; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float -O1 \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6 -; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float -O1 \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,CMP_CC_FMT,R6 +; RUN: -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck \ +; RUN: %s -check-prefixes=ALL,C_CC_FMT,PRER6,NOT-R2R6 +; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float \ +; RUN: -O1 -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck \ +; RUN: %s -check-prefixes=ALL,C_CC_FMT,PRER6,R2R6 +; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float \ +; RUN: -O1 -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck \ +; RUN: %s -check-prefixes=ALL,CMP_CC_FMT,R6,R2R6 @gld0 = external global fp128 @gld1 = external global fp128 @@ -238,12 +242,16 @@ entry: } ; ALL-LABEL: libcall1_fabsl: -; ALL-DAG: ld $[[R0:[0-9]+]], 8($[[R4:[0-9]+]]) -; ALL-DAG: daddiu $[[R1:[0-9]+]], $zero, 1 -; ALL-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63 -; ALL-DAG: daddiu $[[R3:[0-9]+]], $[[R2]], -1 -; ALL-DAG: and $4, $[[R0]], $[[R3]] -; ALL-DAG: ld $2, 0($[[R4]]) +; NOT-R2R6-DAG: ld $[[R0:[0-9]+]], 8($[[R4:[0-9]+]]) +; NOT-R2R6-DAG: daddiu $[[R1:[0-9]+]], $zero, 1 +; NOT-R2R6-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63 +; NOT-R2R6-DAG: daddiu $[[R3:[0-9]+]], $[[R2]], -1 +; NOT-R2R6-DAG: and $4, $[[R0]], $[[R3]] +; NOT-R2R6-DAG: ld $2, 0($[[R4]]) + +; R2R6-DAG: ld $[[R0:[0-9]+]], 0($[[R3:[0-9]+]]) +; R2R6-DAG: ld $[[R1:[0-9]+]], 8($[[R3]]) +; R2R6-DAG: dextm $[[R2:[0-9]+]], $[[R1]], 0, 63 define fp128 @libcall1_fabsl() { entry: @@ -410,17 +418,19 @@ entry: declare fp128 @llvm.powi.f128(fp128, i32) #3 ; ALL-LABEL: libcall2_copysignl: -; ALL-DAG: daddiu $[[R2:[0-9]+]], $zero, 1 -; ALL-DAG: dsll $[[R3:[0-9]+]], $[[R2]], 63 -; ALL-DAG: ld $[[R0:[0-9]+]], %got_disp(gld1) -; ALL-DAG: ld $[[R1:[0-9]+]], 8($[[R0]]) -; ALL-DAG: and $[[R4:[0-9]+]], $[[R1]], $[[R3]] -; ALL-DAG: ld $[[R5:[0-9]+]], %got_disp(gld0) -; ALL-DAG: ld $[[R6:[0-9]+]], 8($[[R5]]) -; ALL-DAG: daddiu $[[R7:[0-9]+]], $[[R3]], -1 -; ALL-DAG: and $[[R8:[0-9]+]], $[[R6]], $[[R7]] -; ALL-DAG: or $4, $[[R8]], $[[R4]] -; ALL-DAG: ld $2, 0($[[R5]]) +; ALL-DAG: daddiu $[[R2:[0-9]+]], $zero, 1 +; ALL-DAG: dsll $[[R3:[0-9]+]], $[[R2]], 63 +; ALL-DAG: ld $[[R0:[0-9]+]], %got_disp(gld1) +; ALL-DAG: ld $[[R1:[0-9]+]], 8($[[R0]]) +; ALL-DAG: and $[[R4:[0-9]+]], $[[R1]], $[[R3]] +; ALL-DAG: ld $[[R5:[0-9]+]], %got_disp(gld0) +; ALL-DAG: ld $[[R6:[0-9]+]], 8($[[R5]]) +; NOT-R2R6-DAG: daddiu $[[R7:[0-9]+]], $[[R3]], -1 +; NOT-R2R6-DAG: and $[[R8:[0-9]+]], $[[R6]], $[[R7]] +; NOT-R2R6-DAG: or $4, $[[R8]], $[[R4]] +; R2R6-DAG: dextm $[[R7:[0-9]+]], $[[R6]], 0, 63 +; R2R6-DAG: or $4, $[[R7]], $[[R4]] +; ALL-DAG: ld $2, 0($[[R5]]) define fp128 @libcall2_copysignl() { entry: @@ -573,10 +583,10 @@ entry: ; ALL-LABEL: store_LD_LD: ; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1) -; ALL: ld $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: ld $[[R2:[0-9]+]], 8($[[R0]]) ; ALL: ld $[[R3:[0-9]+]], %got_disp(gld0) ; ALL: sd $[[R2]], 8($[[R3]]) +; ALL: ld $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: sd $[[R1]], 0($[[R3]]) define void @store_LD_LD() { diff --git a/test/CodeGen/Mips/mips64-libcall.ll b/test/CodeGen/Mips/mips64-libcall.ll index 8512e9fcb72e..7c0e5b2bbfdc 100644 --- a/test/CodeGen/Mips/mips64-libcall.ll +++ b/test/CodeGen/Mips/mips64-libcall.ll @@ -20,7 +20,7 @@ declare double @floor(double) nounwind readnone ; Check call16. ; ; SOFT-LABEL: f64add: -; SOFT: ld $25, %call16(__adddf3) +; SOFT: jal __adddf3 define double @f64add(double %a, double %b) { entry: diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll index 8f124c89db4b..c08c1b73d740 100644 --- a/test/CodeGen/Mips/mips64instrs.ll +++ b/test/CodeGen/Mips/mips64instrs.ll @@ -111,10 +111,8 @@ entry: define i64 @f14(i64 %a, i64 %b) nounwind readnone { entry: ; ALL-LABEL: f14: -; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)( -; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)( -; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]]) -; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]]) +; ALL-DAG: ld $[[T0:[0-9]+]], %lo(gll0)(${{[0-9]+}}) +; ALL-DAG: ld $[[T1:[0-9]+]], %lo(gll1)(${{[0-9]+}}) ; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]] ; ACCMULDIV: teq $[[T1]], $zero, 7 @@ -132,10 +130,8 @@ entry: define i64 @f15() nounwind readnone { entry: ; ALL-LABEL: f15: -; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)( -; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)( -; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]]) -; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]]) +; ALL-DAG: ld $[[T0:[0-9]+]], %lo(gll0)(${{[0-9]+}}) +; ALL-DAG: ld $[[T1:[0-9]+]], %lo(gll1)(${{[0-9]+}}) ; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]] ; ACCMULDIV: teq $[[T1]], $zero, 7 diff --git a/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/test/CodeGen/Mips/mno-ldc1-sdc1.ll index 9663138d4c81..0260afaa1860 100644 --- a/test/CodeGen/Mips/mno-ldc1-sdc1.ll +++ b/test/CodeGen/Mips/mno-ldc1-sdc1.ll @@ -130,12 +130,12 @@ ; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) ; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25 ; MM-MNO-PIC: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) -; MM-MNO-PIC: lw16 $[[R4:[0-9]+]], 0($[[R3]]) -; MM-MNO-PIC: lw16 $[[R5:[0-9]+]], 4($[[R3]]) -; MM-MNO-LE-PIC: mtc1 $[[R4]], $f0 -; MM-MNO-LE-PIC: mthc1 $[[R5]], $f0 -; MM-MNO-BE-PIC: mtc1 $[[R5]], $f0 -; MM-MNO-BE-PIC: mthc1 $[[R4]], $f0 +; MM-MNO-PIC-DAG: lw16 $[[R4:[0-9]+]], 0($[[R3]]) +; MM-MNO-PIC-DAG: lw16 $[[R5:[0-9]+]], 4($[[R3]]) +; MM-MNO-LE-PIC-DAG: mtc1 $[[R4]], $f0 +; MM-MNO-LE-PIC-DAG: mthc1 $[[R5]], $f0 +; MM-MNO-BE-PIC-DAG: mtc1 $[[R5]], $f0 +; MM-MNO-BE-PIC-DAG: mthc1 $[[R4]], $f0 ; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0) ; MM-STATIC-PIC: ldc1 $f0, %lo(g0)($[[R0]]) @@ -214,13 +214,13 @@ entry: ; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp) ; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) ; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25 -; MM-MNO-LE-PIC: mfc1 $[[R3:[0-9]+]], $f12 -; MM-MNO-BE-PIC: mfhc1 $[[R3:[0-9]+]], $f12 -; MM-MNO-PIC: lw $[[R4:[0-9]+]], %got(g0)($[[R2]]) -; MM-MNO-PIC: sw16 $[[R3]], 0($[[R4]]) -; MM-MNO-LE-PIC: mfhc1 $[[R5:[0-9]+]], $f12 -; MM-MNO-BE-PIC: mfc1 $[[R5:[0-9]+]], $f12 -; MM-MNO-PIC: sw16 $[[R5]], 4($[[R4]]) +; MM-MNO-LE-PIC-DAG: mfc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-BE-PIC-DAG: mfhc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-PIC-DAG: lw $[[R4:[0-9]+]], %got(g0)($[[R2]]) +; MM-MNO-PIC-DAG: sw16 $[[R3]], 0($[[R4]]) +; MM-MNO-LE-PIC-DAG: mfhc1 $[[R5:[0-9]+]], $f12 +; MM-MNO-BE-PIC-DAG: mfc1 $[[R5:[0-9]+]], $f12 +; MM-MNO-PIC-DAG: sw16 $[[R5]], 4($[[R4]]) ; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0) ; MM-STATIC-PIC: sdc1 $f12, %lo(g0)($[[R0]]) @@ -267,8 +267,8 @@ entry: ; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3 ; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]] -; MM-MNO-PIC: lw16 $[[R2:[0-9]+]], 0($[[R1]]) -; MM-MNO-PIC: lw16 $[[R3:[0-9]+]], 4($[[R1]]) +; MM-MNO-PIC-DAG: lw16 $[[R2:[0-9]+]], 0($[[R1]]) +; MM-MNO-PIC-DAG: lw16 $[[R3:[0-9]+]], 4($[[R1]]) ; MM-MNO-LE-PIC: mtc1 $[[R2]], $f0 ; MM-MNO-LE-PIC: mthc1 $[[R3]], $f0 ; MM-MNO-BE-PIC: mtc1 $[[R3]], $f0 @@ -313,14 +313,14 @@ entry: ; MM: addu16 $[[R1:[0-9]+]], $6, $[[R0]] ; MM: sdc1 $f12, 0($[[R1]]) -; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3 -; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] -; MM-MNO-LE-PIC: mfc1 $[[R2:[0-9]+]], $f12 -; MM-MNO-BE-PIC: mfhc1 $[[R2:[0-9]+]], $f12 -; MM-MNO-PIC: sw16 $[[R2]], 0($[[R1]]) -; MM-MNO-LE-PIC: mfhc1 $[[R3:[0-9]+]], $f12 -; MM-MNO-BE-PIC: mfc1 $[[R3:[0-9]+]], $f12 -; MM-MNO-PIC: sw16 $[[R3]], 4($[[R1]]) +; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3 +; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] +; MM-MNO-LE-PIC-DAG: mfc1 $[[R2:[0-9]+]], $f12 +; MM-MNO-BE-PIC-DAG: mfhc1 $[[R2:[0-9]+]], $f12 +; MM-MNO-PIC-DAG: sw16 $[[R2]], 0($[[R1]]) +; MM-MNO-LE-PIC-DAG: mfhc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-BE-PIC-DAG: mfc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-PIC-DAG: sw16 $[[R3]], 4($[[R1]]) ; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3 ; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] diff --git a/test/CodeGen/Mips/msa/3r_4r_widen.ll b/test/CodeGen/Mips/msa/3r_4r_widen.ll index fe248eeb566b..467cff5a1a3c 100644 --- a/test/CodeGen/Mips/msa/3r_4r_widen.ll +++ b/test/CodeGen/Mips/msa/3r_4r_widen.ll @@ -5,18 +5,16 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s -@llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 @llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16 @llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16 @llvm_mips_dpadd_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 define void @llvm_mips_dpadd_s_h_test() nounwind { entry: - %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_s_h_ARG1 - %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_s_h_ARG2 - %2 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_s_h_ARG3 - %3 = tail call <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2) - store <8 x i16> %3, <8 x i16>* @llvm_mips_dpadd_s_h_RES + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_s_h_ARG2 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_s_h_ARG3 + %2 = tail call <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>, <16 x i8> %0, <16 x i8> %1) + store <8 x i16> %2, <8 x i16>* @llvm_mips_dpadd_s_h_RES ret void } @@ -25,23 +23,21 @@ declare <8 x i16> @llvm.mips.dpadd.s.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_dpadd_s_h_test: ; CHECK: ld.b ; CHECK: ld.b -; CHECK: ld.h -; CHECK: dpadd_s.h +; CHECK: ldi.h [[R1:\$w[0-9]+]], +; CHECK: dpadd_s.h [[R1]], ; CHECK: st.h ; CHECK: .size llvm_mips_dpadd_s_h_test ; -@llvm_mips_dpadd_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 @llvm_mips_dpadd_s_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16 @llvm_mips_dpadd_s_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16 @llvm_mips_dpadd_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 define void @llvm_mips_dpadd_s_w_test() nounwind { entry: - %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_s_w_ARG1 - %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_s_w_ARG2 - %2 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_s_w_ARG3 - %3 = tail call <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2) - store <4 x i32> %3, <4 x i32>* @llvm_mips_dpadd_s_w_RES + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_s_w_ARG2 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_s_w_ARG3 + %2 = tail call <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32> <i32 4, i32 4, i32 4, i32 4>, <8 x i16> %0, <8 x i16> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_dpadd_s_w_RES ret void } @@ -50,48 +46,44 @@ declare <4 x i32> @llvm.mips.dpadd.s.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_dpadd_s_w_test: ; CHECK: ld.h ; CHECK: ld.h -; CHECK: ld.w -; CHECK: dpadd_s.w +; CHECK: ldi.w [[R1:\$w[0-9]+]], +; CHECK: dpadd_s.w [[R1]], ; CHECK: st.w ; CHECK: .size llvm_mips_dpadd_s_w_test ; -@llvm_mips_dpadd_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 @llvm_mips_dpadd_s_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16 @llvm_mips_dpadd_s_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16 @llvm_mips_dpadd_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 define void @llvm_mips_dpadd_s_d_test() nounwind { entry: - %0 = load <2 x i64>, <2 x i64>* @llvm_mips_dpadd_s_d_ARG1 - %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_s_d_ARG2 - %2 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_s_d_ARG3 - %3 = tail call <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2) - store <2 x i64> %3, <2 x i64>* @llvm_mips_dpadd_s_d_RES + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_s_d_ARG2 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_s_d_ARG3 + %2 = tail call <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64> <i64 4, i64 4>, <4 x i32> %0, <4 x i32> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_dpadd_s_d_RES ret void } declare <2 x i64> @llvm.mips.dpadd.s.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_dpadd_s_d_test: +; CHECK: ldi.d [[R1:\$w[0-9]+]], ; CHECK: ld.w ; CHECK: ld.w -; CHECK: ld.d -; CHECK: dpadd_s.d +; CHECK: dpadd_s.d [[R1]], ; CHECK: st.d ; CHECK: .size llvm_mips_dpadd_s_d_test ; -@llvm_mips_dpadd_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 @llvm_mips_dpadd_u_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16 @llvm_mips_dpadd_u_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16 @llvm_mips_dpadd_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 define void @llvm_mips_dpadd_u_h_test() nounwind { entry: - %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_u_h_ARG1 - %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_u_h_ARG2 - %2 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_u_h_ARG3 - %3 = tail call <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16> %0, <16 x i8> %1, <16 x i8> %2) - store <8 x i16> %3, <8 x i16>* @llvm_mips_dpadd_u_h_RES + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_u_h_ARG2 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_dpadd_u_h_ARG3 + %2 = tail call <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>, <16 x i8> %0, <16 x i8> %1) + store <8 x i16> %2, <8 x i16>* @llvm_mips_dpadd_u_h_RES ret void } @@ -100,23 +92,21 @@ declare <8 x i16> @llvm.mips.dpadd.u.h(<8 x i16>, <16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_dpadd_u_h_test: ; CHECK: ld.b ; CHECK: ld.b -; CHECK: ld.h -; CHECK: dpadd_u.h +; CHECK: ldi.h [[R1:\$w[0-9]+]], +; CHECK: dpadd_u.h [[R1]], ; CHECK: st.h ; CHECK: .size llvm_mips_dpadd_u_h_test ; -@llvm_mips_dpadd_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 @llvm_mips_dpadd_u_w_ARG2 = global <8 x i16> <i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11>, align 16 @llvm_mips_dpadd_u_w_ARG3 = global <8 x i16> <i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19>, align 16 @llvm_mips_dpadd_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 define void @llvm_mips_dpadd_u_w_test() nounwind { entry: - %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_u_w_ARG1 - %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_u_w_ARG2 - %2 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_u_w_ARG3 - %3 = tail call <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32> %0, <8 x i16> %1, <8 x i16> %2) - store <4 x i32> %3, <4 x i32>* @llvm_mips_dpadd_u_w_RES + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_u_w_ARG2 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_dpadd_u_w_ARG3 + %2 = tail call <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32> <i32 4, i32 4, i32 4, i32 4>, <8 x i16> %0, <8 x i16> %1) + store <4 x i32> %2, <4 x i32>* @llvm_mips_dpadd_u_w_RES ret void } @@ -125,33 +115,31 @@ declare <4 x i32> @llvm.mips.dpadd.u.w(<4 x i32>, <8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_dpadd_u_w_test: ; CHECK: ld.h ; CHECK: ld.h -; CHECK: ld.w -; CHECK: dpadd_u.w +; CHECK: ldi.w [[R1:\$w[0-9]+]], +; CHECK: dpadd_u.w [[R1]], ; CHECK: st.w ; CHECK: .size llvm_mips_dpadd_u_w_test ; -@llvm_mips_dpadd_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 @llvm_mips_dpadd_u_d_ARG2 = global <4 x i32> <i32 2, i32 3, i32 4, i32 5>, align 16 @llvm_mips_dpadd_u_d_ARG3 = global <4 x i32> <i32 6, i32 7, i32 8, i32 9>, align 16 @llvm_mips_dpadd_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 define void @llvm_mips_dpadd_u_d_test() nounwind { entry: - %0 = load <2 x i64>, <2 x i64>* @llvm_mips_dpadd_u_d_ARG1 - %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_u_d_ARG2 - %2 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_u_d_ARG3 - %3 = tail call <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64> %0, <4 x i32> %1, <4 x i32> %2) - store <2 x i64> %3, <2 x i64>* @llvm_mips_dpadd_u_d_RES + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_u_d_ARG2 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_dpadd_u_d_ARG3 + %2 = tail call <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64> <i64 4, i64 4>, <4 x i32> %0, <4 x i32> %1) + store <2 x i64> %2, <2 x i64>* @llvm_mips_dpadd_u_d_RES ret void } declare <2 x i64> @llvm.mips.dpadd.u.d(<2 x i64>, <4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_dpadd_u_d_test: +; CHECK: ldi.d [[R1:\$w[0-9]+]], ; CHECK: ld.w ; CHECK: ld.w -; CHECK: ld.d -; CHECK: dpadd_u.d +; CHECK: dpadd_u.d [[R1]], ; CHECK: st.d ; CHECK: .size llvm_mips_dpadd_u_d_test ; diff --git a/test/CodeGen/Mips/msa/basic_operations.ll b/test/CodeGen/Mips/msa/basic_operations.ll index d7a05800a273..c14221937f4d 100644 --- a/test/CodeGen/Mips/msa/basic_operations.ll +++ b/test/CodeGen/Mips/msa/basic_operations.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s | \ -; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-BE %s +; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-BE,O32-BE %s ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s | \ -; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-LE %s +; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-LE,O32-LE %s ; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 \ ; RUN: -relocation-model=pic -verify-machineinstrs < %s | \ ; RUN: FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-BE %s @@ -58,10 +58,19 @@ define void @const_v16i8() nounwind { ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8 - ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L - ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL-BE-DAG: lui [[R3:\$[0-9]+]], 1286 + ; ALL-LE-DAG: lui [[R3:\$[0-9]+]], 2055 + ; ALL-BE-DAG: ori [[R4:\$[0-9]+]], [[R3]], 1800 + ; ALL-LE-DAG: ori [[R4:\$[0-9]+]], [[R3]], 1541 + ; O32-BE: fill.w [[R1:\$w[0-9]+]], [[R4]] + + ; O32: insert.w [[R1]][1], [[R2]] + ; O32: splati.d $w{{.*}}, [[R1]][0] + + ; MIPS64-BE: dinsu [[R4]], [[R2]], 32, 32 + ; MIPS64-LE: dinsu [[R2]], [[R4]], 32, 32 + ; MIPS64-BE: fill.d $w{{.*}}, [[R4]] + ; MIPS64-LE: fill.d $w{{.*}}, [[R2]] ret void } @@ -92,10 +101,19 @@ define void @const_v8i16() nounwind { ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16 - ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L - ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; ALL-BE-DAG: lui [[R3:\$[0-9]+]], 3 + ; ALL-LE-DAG: lui [[R3:\$[0-9]+]], 4 + ; ALL-BE-DAG: ori [[R4:\$[0-9]+]], [[R3]], 4 + ; ALL-LE-DAG: ori [[R4:\$[0-9]+]], [[R3]], 3 + + ; O32-BE: fill.w [[R1:\$w[0-9]+]], [[R4]] + ; O32: insert.w [[R1]][1], [[R2]] + ; O32: splati.d $w{{.*}}, [[R1]][0] + + ; MIPS64-BE: dinsu [[R4]], [[R2]], 32, 32 + ; MIPS64-LE: dinsu [[R2]], [[R4]], 32, 32 + ; MIPS64-BE: fill.d $w{{.*}}, [[R4]] + ; MIPS64-LE: fill.d $w{{.*}}, [[R2]] ret void } @@ -122,10 +140,23 @@ define void @const_v4i32() nounwind { ; ALL: ldi.h [[R1:\$w[0-9]+]], 1 store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32 - ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L - ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) + ; -BE-DAG: ori [[R2:\$[0-9]+]], $zero, 1 + ; O32-BE-DAG: ori [[R3:\$[0-9]+]], $zero, 1 + ; O32-BE-DAG: ori [[R4:\$[0-9]+]], $zero, 2 + ; O32-LE-DAG: ori [[R3:\$[0-9]+]], $zero, 2 + ; O32-LE-DAG: ori [[R4:\$[0-9]+]], $zero, 1 + ; O32: fill.w [[W0:\$w[0-9]+]], [[R4]] + ; O32: insert.w [[W0]][1], [[R3]] + ; O32: splati.d [[W1:\$w[0-9]+]], [[W0]] + + ; MIPS64-DAG: ori [[R5:\$[0-9]+]], $zero, 2 + ; MIPS64-DAG: ori [[R6:\$[0-9]+]], $zero, 1 + + ; MIPS64-BE: dinsu [[R5]], [[R6]], 32, 32 + ; MIPS64-LE: dinsu [[R6]], [[R5]], 32, 32 + ; MIPS64-BE: fill.d $w{{.*}}, [[R4]] + ; MIPS64-LE: fill.d $w{{.*}}, [[R2]] + store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ diff --git a/test/CodeGen/Mips/msa/bitwise.ll b/test/CodeGen/Mips/msa/bitwise.ll index 2a260b2c5733..63fce5283ba0 100644 --- a/test/CodeGen/Mips/msa/bitwise.ll +++ b/test/CodeGen/Mips/msa/bitwise.ll @@ -1099,7 +1099,7 @@ define void @binsl_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind i8 63, i8 63, i8 63, i8 63, i8 63, i8 63, i8 63, i8 63> %5 = or <16 x i8> %3, %4 - ; CHECK-DAG: binsli.b [[R2]], [[R1]], 2 + ; CHECK-DAG: binsli.b [[R2]], [[R1]], 1 store <16 x i8> %5, <16 x i8>* %c ; CHECK-DAG: st.b [[R2]], 0($4) @@ -1119,7 +1119,7 @@ define void @binsl_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind %4 = and <8 x i16> %2, <i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383> %5 = or <8 x i16> %3, %4 - ; CHECK-DAG: binsli.h [[R2]], [[R1]], 2 + ; CHECK-DAG: binsli.h [[R2]], [[R1]], 1 store <8 x i16> %5, <8 x i16>* %c ; CHECK-DAG: st.h [[R2]], 0($4) @@ -1137,7 +1137,7 @@ define void @binsl_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind %3 = and <4 x i32> %1, <i32 3221225472, i32 3221225472, i32 3221225472, i32 3221225472> %4 = and <4 x i32> %2, <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823> %5 = or <4 x i32> %3, %4 - ; CHECK-DAG: binsli.w [[R2]], [[R1]], 2 + ; CHECK-DAG: binsli.w [[R2]], [[R1]], 1 store <4 x i32> %5, <4 x i32>* %c ; CHECK-DAG: st.w [[R2]], 0($4) @@ -1159,7 +1159,7 @@ define void @binsl_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind ; issue. If the mask doesn't fit within a 10-bit immediate, it gets ; legalized into a constant pool. We should add a test to cover the ; other cases once they correctly select binsli.d. - ; CHECK-DAG: binsli.d [[R2]], [[R1]], 61 + ; CHECK-DAG: binsli.d [[R2]], [[R1]], 60 store <2 x i64> %5, <2 x i64>* %c ; CHECK-DAG: st.d [[R2]], 0($4) @@ -1181,7 +1181,7 @@ define void @binsr_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252> %5 = or <16 x i8> %3, %4 - ; CHECK-DAG: binsri.b [[R2]], [[R1]], 2 + ; CHECK-DAG: binsri.b [[R2]], [[R1]], 1 store <16 x i8> %5, <16 x i8>* %c ; CHECK-DAG: st.b [[R2]], 0($4) @@ -1201,7 +1201,7 @@ define void @binsr_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind %4 = and <8 x i16> %2, <i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532> %5 = or <8 x i16> %3, %4 - ; CHECK-DAG: binsri.h [[R2]], [[R1]], 2 + ; CHECK-DAG: binsri.h [[R2]], [[R1]], 1 store <8 x i16> %5, <8 x i16>* %c ; CHECK-DAG: st.h [[R2]], 0($4) @@ -1219,7 +1219,7 @@ define void @binsr_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind %3 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3> %4 = and <4 x i32> %2, <i32 4294967292, i32 4294967292, i32 4294967292, i32 4294967292> %5 = or <4 x i32> %3, %4 - ; CHECK-DAG: binsri.w [[R2]], [[R1]], 2 + ; CHECK-DAG: binsri.w [[R2]], [[R1]], 1 store <4 x i32> %5, <4 x i32>* %c ; CHECK-DAG: st.w [[R2]], 0($4) @@ -1237,7 +1237,7 @@ define void @binsr_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind %3 = and <2 x i64> %1, <i64 3, i64 3> %4 = and <2 x i64> %2, <i64 18446744073709551612, i64 18446744073709551612> %5 = or <2 x i64> %3, %4 - ; CHECK-DAG: binsri.d [[R2]], [[R1]], 2 + ; CHECK-DAG: binsri.d [[R2]], [[R1]], 1 store <2 x i64> %5, <2 x i64>* %c ; CHECK-DAG: st.d [[R2]], 0($4) diff --git a/test/CodeGen/Mips/msa/bmzi_bmnzi.ll b/test/CodeGen/Mips/msa/bmzi_bmnzi.ll new file mode 100644 index 000000000000..d1cb3c348c73 --- /dev/null +++ b/test/CodeGen/Mips/msa/bmzi_bmnzi.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s + +@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, align 16 +@llvm_mips_bmnzi_b_ARG2 = global <16 x i8> zeroinitializer, align 16 +@llvm_mips_bmnzi_b_RES = global <16 x i8> zeroinitializer, align 16 + +define void @llvm_mips_bmnzi_b_test() nounwind { +entry: + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG2 + %2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 240) + store <16 x i8> %2, <16 x i8>* @llvm_mips_bmnzi_b_RES + %3 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 15) + store <16 x i8> %3, <16 x i8>* @llvm_mips_bmnzi_b_RES + %4 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 170) + store <16 x i8> %4, <16 x i8>* @llvm_mips_bmnzi_b_RES + ret void +} +; CHECK-LABEL: llvm_mips_bmnzi_b_test: +; CHECK: lw [[R0:\$[0-9]+]], %got(llvm_mips_bmnzi_b_RES)( +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)( +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)( +; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]]) +; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]] +; CHECK: binsli.b [[R5]], [[R3]], 3 +; CHECK: binsri.b [[R5]], [[R3]], 3 +; CHECK: bmnzi.b [[R4]], [[R3]], 170 + +define void @llvm_mips_bmzi_b_test() nounwind { +entry: + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG2 + %2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 240) + store <16 x i8> %2, <16 x i8>* @llvm_mips_bmnzi_b_RES + %3 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 15) + store <16 x i8> %3, <16 x i8>* @llvm_mips_bmnzi_b_RES + %4 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 170) + store <16 x i8> %4, <16 x i8>* @llvm_mips_bmnzi_b_RES + ret void +} +; CHECK-LABEL: llvm_mips_bmzi_b_test: +; CHECK: lw [[R0:\$[0-9]+]], %got(llvm_mips_bmnzi_b_RES)( +; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)( +; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)( +; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]]) +; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]]) +; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]] +; CHECK: binsli.b [[R5]], [[R3]], 3 +; CHECK: binsri.b [[R5]], [[R3]], 3 +; bmnzi.b is the same as bmzi.b with ws and wd_in swapped +; CHECK: bmnzi.b [[R4]], [[R3]], 170 + +declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind +declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind diff --git a/test/CodeGen/Mips/msa/f16-llvm-ir.ll b/test/CodeGen/Mips/msa/f16-llvm-ir.ll index 9957d5be26ed..ac69dc913c18 100644 --- a/test/CodeGen/Mips/msa/f16-llvm-ir.ll +++ b/test/CodeGen/Mips/msa/f16-llvm-ir.ll @@ -234,15 +234,15 @@ entry: ; MIPS32: insert.w $w[[W0]][1], $[[R1]] ; MIPS32: insert.w $w[[W0]][3], $[[R1]] -; MIPS64-N64: ld $[[R3:[0-9]+]], %got_disp(h) -; MIPS64-N32: lw $[[R3:[0-9]+]], %got_disp(h) -; MIPS64: dmfc1 $[[R1:[0-9]+]], $f[[F2]] -; MIPS64: fill.d $w[[W0:[0-9]+]], $[[R1]] +; MIPS64-N64-DAG: ld $[[R3:[0-9]+]], %got_disp(h) +; MIPS64-N32-DAG: lw $[[R3:[0-9]+]], %got_disp(h) +; MIPS64-DAG: dmfc1 $[[R1:[0-9]+]], $f[[F2]] +; MIPS64-DAG: fill.d $w[[W0:[0-9]+]], $[[R1]] -; ALL: fexdo.w $w[[W1:[0-9]+]], $w[[W0]], $w[[W0]] -; ALL: fexdo.h $w[[W2:[0-9]+]], $w[[W1]], $w[[W1]] +; ALL-DAG: fexdo.w $w[[W1:[0-9]+]], $w[[W0]], $w[[W0]] +; ALL-DAG: fexdo.h $w[[W2:[0-9]+]], $w[[W1]], $w[[W1]] -; MIPS32: lw $[[R3:[0-9]+]], %got(h) +; MIPS32-DAG: lw $[[R3:[0-9]+]], %got(h) ; ALL: copy_u.h $[[R2:[0-9]+]], $w[[W2]] ; ALL: sh $[[R2]], 0($[[R3]]) diff --git a/test/CodeGen/Mips/msa/i5-b.ll b/test/CodeGen/Mips/msa/i5-b.ll index c588c8b2407e..5afd3cd48dd5 100644 --- a/test/CodeGen/Mips/msa/i5-b.ll +++ b/test/CodeGen/Mips/msa/i5-b.ll @@ -89,7 +89,7 @@ define void @llvm_mips_binsli_b_test() nounwind { entry: %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsli_b_ARG1 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsli_b_ARG2 - %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 7) + %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 6) store <16 x i8> %2, <16 x i8>* @llvm_mips_binsli_b_RES ret void } @@ -101,7 +101,7 @@ declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32) nounwind ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG2)( ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: binsli.b [[R3]], [[R4]], 7 +; CHECK-DAG: binsli.b [[R3]], [[R4]], 6 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_b_RES)( ; CHECK-DAG: st.b [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsli_b_test @@ -193,7 +193,7 @@ define void @llvm_mips_binsri_b_test() nounwind { entry: %0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsri_b_ARG1 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsri_b_ARG2 - %2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 7) + %2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 6) store <16 x i8> %2, <16 x i8>* @llvm_mips_binsri_b_RES ret void } @@ -205,7 +205,7 @@ declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32) nounwind ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG2)( ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) -; CHECK-DAG: binsri.b [[R3]], [[R4]], 7 +; CHECK-DAG: binsri.b [[R3]], [[R4]], 6 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_b_RES)( ; CHECK-DAG: st.b [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsri_b_test diff --git a/test/CodeGen/Mips/msa/i5_ld_st.ll b/test/CodeGen/Mips/msa/i5_ld_st.ll index c644d242a003..812c400d46e4 100644 --- a/test/CodeGen/Mips/msa/i5_ld_st.ll +++ b/test/CodeGen/Mips/msa/i5_ld_st.ll @@ -336,8 +336,8 @@ entry: ; CHECK: llvm_mips_st_b_valid_range_tests: ; CHECK: ld.b -; CHECK: st.b [[R1:\$w[0-9]+]], -512( -; CHECK: st.b [[R1:\$w[0-9]+]], 511( +; CHECK-DAG: st.b [[R1:\$w[0-9]+]], -512( +; CHECK-DAG: st.b [[R1:\$w[0-9]+]], 511( ; CHECK: .size llvm_mips_st_b_valid_range_tests ; @@ -351,10 +351,10 @@ entry: } ; CHECK: llvm_mips_st_b_invalid_range_tests: -; CHECK: addiu $2, $1, -513 +; CHECK: addiu $2, $1, 512 ; CHECK: ld.b ; CHECK: st.b [[R1:\$w[0-9]+]], 0( -; CHECK: addiu $1, $1, 512 +; CHECK: addiu $1, $1, -513 ; CHECK: st.b [[R1:\$w[0-9]+]], 0( ; CHECK: .size llvm_mips_st_b_invalid_range_tests ; @@ -404,8 +404,8 @@ entry: ; CHECK: llvm_mips_st_h_valid_range_tests: ; CHECK: ld.h -; CHECK: st.h [[R1:\$w[0-9]+]], -1024( -; CHECK: st.h [[R1:\$w[0-9]+]], 1022( +; CHECK-DAG: st.h [[R1:\$w[0-9]+]], -1024( +; CHECK-DAG: st.h [[R1:\$w[0-9]+]], 1022( ; CHECK: .size llvm_mips_st_h_valid_range_tests ; @@ -419,10 +419,10 @@ entry: } ; CHECK: llvm_mips_st_h_invalid_range_tests: -; CHECK: addiu $2, $1, -1026 +; CHECK: addiu $2, $1, 1024 ; CHECK: ld.h ; CHECK: st.h [[R1:\$w[0-9]+]], 0( -; CHECK: addiu $1, $1, 1024 +; CHECK: addiu $1, $1, -1026 ; CHECK: st.h [[R1:\$w[0-9]+]], 0( ; CHECK: .size llvm_mips_st_h_invalid_range_tests ; @@ -472,8 +472,8 @@ entry: ; CHECK: llvm_mips_st_w_valid_range_tests: ; CHECK: ld.w -; CHECK: st.w [[R1:\$w[0-9]+]], -2048( -; CHECK: st.w [[R1:\$w[0-9]+]], 2044( +; CHECK-DAG: st.w [[R1:\$w[0-9]+]], -2048( +; CHECK-DAG: st.w [[R1:\$w[0-9]+]], 2044( ; CHECK: .size llvm_mips_st_w_valid_range_tests ; @@ -487,10 +487,10 @@ entry: } ; CHECK: llvm_mips_st_w_invalid_range_tests: -; CHECK: addiu $2, $1, -2052 +; CHECK: addiu $2, $1, 2048 ; CHECK: ld.w ; CHECK: st.w [[R1:\$w[0-9]+]], 0( -; CHECK: addiu $1, $1, 2048 +; CHECK: addiu $1, $1, -2052 ; CHECK: st.w [[R1:\$w[0-9]+]], 0( ; CHECK: .size llvm_mips_st_w_invalid_range_tests ; @@ -540,8 +540,8 @@ entry: ; CHECK: llvm_mips_st_d_valid_range_tests: ; CHECK: ld.d -; CHECK: st.d [[R1:\$w[0-9]+]], -4096( -; CHECK: st.d [[R1:\$w[0-9]+]], 4088( +; CHECK-DAG: st.d [[R1:\$w[0-9]+]], -4096( +; CHECK-DAG: st.d [[R1:\$w[0-9]+]], 4088( ; CHECK: .size llvm_mips_st_d_valid_range_tests ; @@ -555,10 +555,10 @@ entry: } ; CHECK: llvm_mips_st_d_invalid_range_tests: -; CHECK: addiu $2, $1, -4104 +; CHECK: addiu $2, $1, 4096 ; CHECK: ld.d ; CHECK: st.d [[R1:\$w[0-9]+]], 0( -; CHECK: addiu $1, $1, 4096 +; CHECK: addiu $1, $1, -4104 ; CHECK: st.d [[R1:\$w[0-9]+]], 0( ; CHECK: .size llvm_mips_st_d_invalid_range_tests ; diff --git a/test/CodeGen/Mips/msa/immediates.ll b/test/CodeGen/Mips/msa/immediates.ll index b561ace30a8a..0e9fb4c7adfc 100644 --- a/test/CodeGen/Mips/msa/immediates.ll +++ b/test/CodeGen/Mips/msa/immediates.ll @@ -616,7 +616,7 @@ entry: ; CHECK: binsri.h %a = load <8 x i16>, <8 x i16> * %ptr, align 16 %b = load <8 x i16>, <8 x i16> * %ptr2, align 16 - %r = call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %a, <8 x i16> %b, i32 15) + %r = call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %a, <8 x i16> %b, i32 14) store <8 x i16> %r, <8 x i16> * %ptr, align 16 ret void } @@ -920,7 +920,7 @@ entry: define void @bclri_d(<2 x i64> * %ptr) { entry: ; CHECK-LABEL: bclri_d: -; CHECK: and.v +; CHECK: bclri.d %a = load <2 x i64>, <2 x i64> * %ptr, align 16 %r = call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %a, i32 16) store <2 x i64> %r, <2 x i64> * %ptr, align 16 @@ -930,7 +930,7 @@ entry: define void @binsli_d(<2 x i64> * %ptr, <2 x i64> * %ptr2) { entry: ; CHECK-LABEL: binsli_d: -; CHECK: bsel.v +; CHECK: binsli.d %a = load <2 x i64>, <2 x i64> * %ptr, align 16 %b = load <2 x i64>, <2 x i64> * %ptr2, align 16 %r = call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %a, <2 x i64> %b, i32 4) @@ -952,7 +952,7 @@ entry: define void @bnegi_d(<2 x i64> * %ptr) { entry: ; CHECK-LABEL: bnegi_d: -; CHECK: xor.v +; CHECK: bnegi.d %a = load <2 x i64>, <2 x i64> * %ptr, align 16 %r = call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %a, i32 9) store <2 x i64> %r, <2 x i64> * %ptr, align 16 @@ -962,7 +962,7 @@ entry: define void @bseti_d(<2 x i64> * %ptr) { entry: ; CHECK-LABEL: bseti_d: -; CHECK: or.v +; CHECK: bseti.d %a = load <2 x i64>, <2 x i64> * %ptr, align 16 %r = call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %a, i32 25) store <2 x i64> %r, <2 x i64> * %ptr, align 16 diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index 33431dba43c4..eadf4abfc759 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -45,20 +45,18 @@ declare void @callee3(float, %struct.S3* byval, %struct.S1* byval) define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { entry: ; CHECK: addiu $sp, $sp, -48 -; CHECK: sw $7, 60($sp) -; CHECK: sw $6, 56($sp) -; CHECK: lw $4, 80($sp) -; CHECK: ldc1 $f[[F0:[0-9]+]], 72($sp) -; CHECK: lw $[[R3:[0-9]+]], 64($sp) -; CHECK: lw $[[R4:[0-9]+]], 68($sp) -; CHECK: lw $[[R2:[0-9]+]], 60($sp) -; CHECK: lh $[[R1:[0-9]+]], 58($sp) -; CHECK: lb $[[R0:[0-9]+]], 56($sp) -; CHECK: sw $[[R0]], 32($sp) -; CHECK: sw $[[R1]], 28($sp) -; CHECK: sw $[[R2]], 24($sp) -; CHECK: sw $[[R4]], 20($sp) -; CHECK: sw $[[R3]], 16($sp) +; CHECK-DAG: sw $7, 60($sp) +; CHECK-DAG: sw $6, 56($sp) +; CHECK-DAG: ldc1 $f[[F0:[0-9]+]], 72($sp) +; CHECK-DAG: lw $[[R3:[0-9]+]], 64($sp) +; CHECK-DAG: lw $[[R4:[0-9]+]], 68($sp) +; CHECK-DAG: lh $[[R1:[0-9]+]], 58($sp) +; CHECK-DAG: lb $[[R0:[0-9]+]], 56($sp) +; CHECK-DAG: sw $[[R0]], 32($sp) +; CHECK-DAG: sw $[[R1]], 28($sp) +; CHECK-DAG: sw $[[R4]], 20($sp) +; CHECK-DAG: sw $[[R3]], 16($sp) +; CHECK-DAG: sw $7, 24($sp) ; CHECK: mfc1 $6, $f[[F0]] %i2 = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 5 @@ -82,13 +80,11 @@ declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float) define void @f3(%struct.S2* nocapture byval %s2) nounwind { entry: ; CHECK: addiu $sp, $sp, -48 -; CHECK: sw $7, 60($sp) -; CHECK: sw $6, 56($sp) -; CHECK: sw $5, 52($sp) -; CHECK: sw $4, 48($sp) -; CHECK: lw $4, 48($sp) -; CHECK: lw $[[R0:[0-9]+]], 60($sp) -; CHECK: sw $[[R0]], 24($sp) +; CHECK-DAG: sw $7, 60($sp) +; CHECK-DAG: sw $6, 56($sp) +; CHECK-DAG: sw $5, 52($sp) +; CHECK-DAG: sw $4, 48($sp) +; CHECK-DAG: sw $7, 24($sp) %arrayidx = getelementptr inbounds %struct.S2, %struct.S2* %s2, i32 0, i32 0, i32 0 %tmp = load i32, i32* %arrayidx, align 4 @@ -101,14 +97,14 @@ entry: define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { entry: ; CHECK: addiu $sp, $sp, -48 -; CHECK: sw $7, 60($sp) -; CHECK: sw $6, 56($sp) -; CHECK: sw $5, 52($sp) -; CHECK: lw $4, 60($sp) -; CHECK: lw $[[R1:[0-9]+]], 80($sp) -; CHECK: lb $[[R0:[0-9]+]], 52($sp) -; CHECK: sw $[[R0]], 32($sp) -; CHECK: sw $[[R1]], 24($sp) +; CHECK-DAG: sw $7, 60($sp) +; CHECK-DAG: sw $6, 56($sp) +; CHECK-DAG: sw $5, 52($sp) +; CHECK-DAG: lw $[[R1:[0-9]+]], 80($sp) +; CHECK-DAG: lb $[[R0:[0-9]+]], 52($sp) +; CHECK-DAG: sw $[[R0]], 32($sp) +; CHECK-DAG: sw $[[R1]], 24($sp) +; CHECK: move $4, $7 %i = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 2 %tmp = load i32, i32* %i, align 4 diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll index b4597a3214e2..73aad48b73e6 100644 --- a/test/CodeGen/Mips/o32_cc_vararg.ll +++ b/test/CodeGen/Mips/o32_cc_vararg.ll @@ -29,9 +29,9 @@ entry: ; CHECK-LABEL: va1: ; CHECK: addiu $sp, $sp, -16 +; CHECK: sw $5, 20($sp) ; CHECK: sw $7, 28($sp) ; CHECK: sw $6, 24($sp) -; CHECK: sw $5, 20($sp) ; CHECK: lw $2, 20($sp) } @@ -83,8 +83,8 @@ entry: ; CHECK-LABEL: va3: ; CHECK: addiu $sp, $sp, -16 -; CHECK: sw $7, 28($sp) ; CHECK: sw $6, 24($sp) +; CHECK: sw $7, 28($sp) ; CHECK: lw $2, 24($sp) } @@ -236,8 +236,8 @@ entry: ret i32 %tmp ; CHECK-LABEL: va9: -; CHECK: addiu $sp, $sp, -32 -; CHECK: lw $2, 52($sp) +; CHECK: addiu $sp, $sp, -24 +; CHECK: lw $2, 44($sp) } ; double diff --git a/test/CodeGen/Mips/return_address.ll b/test/CodeGen/Mips/return_address.ll index 34b72baa6d25..54a106f4b349 100644 --- a/test/CodeGen/Mips/return_address.ll +++ b/test/CodeGen/Mips/return_address.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -verify-machineinstrs < %s | FileCheck %s define i8* @f1() nounwind { entry: diff --git a/test/CodeGen/Mips/stackcoloring.ll b/test/CodeGen/Mips/stackcoloring.ll index 817caee2f275..680b3128cc1b 100644 --- a/test/CodeGen/Mips/stackcoloring.ll +++ b/test/CodeGen/Mips/stackcoloring.ll @@ -11,7 +11,7 @@ define i32 @foo1() { entry: %b = alloca [16 x i32], align 4 %0 = bitcast [16 x i32]* %b to i8* - call void @llvm.lifetime.start(i64 64, i8* %0) + call void @llvm.lifetime.start.p0i8(i64 64, i8* %0) %arraydecay = getelementptr inbounds [16 x i32], [16 x i32]* %b, i32 0, i32 0 br label %for.body @@ -28,12 +28,12 @@ for.body: ; preds = %for.body, %entry br i1 %exitcond, label %for.end, label %for.body for.end: ; preds = %for.body - call void @llvm.lifetime.end(i64 64, i8* %0) + call void @llvm.lifetime.end.p0i8(i64 64, i8* %0) ret i32 %add } -declare void @llvm.lifetime.start(i64, i8* nocapture) +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) declare i32 @foo2(i32, i32*) -declare void @llvm.lifetime.end(i64, i8* nocapture) +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) diff --git a/test/CodeGen/Mips/start-asm-file.ll b/test/CodeGen/Mips/start-asm-file.ll index 6d0a5425230a..bcea5da59e75 100644 --- a/test/CodeGen/Mips/start-asm-file.ll +++ b/test/CodeGen/Mips/start-asm-file.ll @@ -75,7 +75,7 @@ ; CHECK-PIC-N32-NLEGACY: .nan legacy ; CHECK-PIC-N32-N2008: .nan 2008 -; CHECK-STATIC-N64: .abicalls +; CHECK-STATIC-N64-NOT: .abicalls ; CHECK-STATIC-N64-NOT: .option pic0 ; CHECK-STATIC-N64: .section .mdebug.abi64 ; CHECK-STATIC-N64-NLEGACY: .nan legacy diff --git a/test/CodeGen/Mips/stchar.ll b/test/CodeGen/Mips/stchar.ll index 34493e9ae338..a6021be8e808 100644 --- a/test/CodeGen/Mips/stchar.ll +++ b/test/CodeGen/Mips/stchar.ll @@ -34,7 +34,7 @@ entry: ; 16_h: lh ${{[0-9]+}}, [[offset2]](${{[0-9]+}}) } -declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind -declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll b/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll index 6b09b693a8e9..25a5e5b8fff5 100644 --- a/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll +++ b/test/CodeGen/Mips/tailcall/tailcall-wrong-isa.ll @@ -4,8 +4,11 @@ ; RUN: llc -filetype=obj -march=mipsel -relocation-model=static -verify-machineinstrs -mips-tail-calls=1 < %s -o - \ ; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=STATIC32 -; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -o - \ -; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=N64 +; RUN: llc -filetype=obj -march=mips64el -relocation-model=pic -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -o - \ +; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=PIC64 + +; RUN: llc -filetype=obj -march=mips64el -relocation-model=static -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -o - \ +; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=STATIC64 ; RUN: llc -filetype=obj -march=mipsel -relocation-model=pic -mattr=+micromips -mips-tail-calls=1 < %s -o - \ ; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=PIC32MM @@ -18,8 +21,11 @@ ; RUN: llc -filetype=obj -march=mipsel -relocation-model=static -mcpu=mips32r6 -mips-tail-calls=1 < %s -o - \ ; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=STATIC32R6 -; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64r6 -mips-tail-calls=1 < %s -o - \ -; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=N64R6 +; RUN: llc -filetype=obj -march=mips64el -relocation-model=pic -mcpu=mips64r6 -mips-tail-calls=1 < %s -o - \ +; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=PIC64R6 +; RUN: llc -filetype=obj -march=mips64el -relocation-model=static -mcpu=mips64r6 -mips-tail-calls=1 < %s -o - \ +; RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=STATIC64R6 + define internal i8 @f2(i8) { ret i8 4 @@ -34,7 +40,8 @@ define i8 @f1(i8 signext %i) nounwind { ; PIC32: {{[0-9a-z]}}: 08 00 20 03 jr $25 ; STATIC32: {{[0-9a-z]}}: 00 00 00 08 j 0 -; N64: {{[0-9a-z]+}}: 08 00 20 03 jr $25 +; PIC64: {{[0-9a-z]+}}: 08 00 20 03 jr $25 +; STATIC64: {{[0-9]}}: 00 00 00 08 j 0 ; PIC32MM: {{[0-9a-z]+}}: b9 45 jrc $25 ; STATIC32MM: {{[0-9a-z]}}: 00 d4 00 00 j 0 @@ -42,5 +49,5 @@ define i8 @f1(i8 signext %i) nounwind { ; PIC32R6: {{[0-9a-z]}}: 00 00 19 d8 jrc $25 ; STATIC32R6: {{[0-9a-z]}}: 00 00 00 08 j 0 -; N64R6: {{[0-9a-z]+}}: 00 00 19 d8 jrc $25 - +; PIC64R6: {{[0-9a-z]+}}: 00 00 19 d8 jrc $25 +; STATIC64R6: {{[0-9]}}: 00 00 00 08 j 0 diff --git a/test/CodeGen/Mips/tailcall/tailcall.ll b/test/CodeGen/Mips/tailcall/tailcall.ll index b0ac28d819cf..3f04e1cf3053 100644 --- a/test/CodeGen/Mips/tailcall/tailcall.ll +++ b/test/CodeGen/Mips/tailcall/tailcall.ll @@ -2,8 +2,10 @@ ; RUN: -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32 ; RUN: llc -march=mipsel -relocation-model=static \ ; RUN: -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32 -; RUN: llc -march=mips64el -mcpu=mips64r2 \ -; RUN: -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -relocation-model=pic \ +; RUN: -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -relocation-model=static \ +; RUN: -verify-machineinstrs -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC64 ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic \ ; RUN: -verify-machineinstrs -mips-tail-calls=1 < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,PIC16 @@ -15,17 +17,21 @@ ; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mips-tail-calls=1 < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,PIC32R6 -; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \ +; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r2 \ ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32 -; RUN: llc -march=mips64el -mcpu=mips64r6 \ -; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64R6 +; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r2 \ +; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64 +; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \ +; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64 ; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \ ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \ ; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32 -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+micromips -mips-tail-calls=1 < %s \ -; RUN: | FileCheck %s -check-prefixes=ALL,N64 +; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \ +; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM +; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \ +; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64 @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 @@ -96,7 +102,8 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal -; N64: jalr $25 +; PIC64: jalr $25 +; STATIC64: jal ; N64R6: jalr $25 ; PIC16: jalrc @@ -113,8 +120,8 @@ entry: ; PIC32R6: jr $25 ; PIC32MM: jr ; STATIC32: j -; N64: jr $25 -; N64R6: jr $25 +; PIC64: jr $25 +; STATIC64: j ; PIC16: jalrc %0 = load i32, i32* @g0, align 4 @@ -154,8 +161,10 @@ entry: ; PIC32R6: jrc $25 ; PIC32MM: jrc ; STATIC32: j -; N64: jr $25 -; N64R6: jrc $25 +; PIC64: jr $25 +; PIC64R6: jrc $25 +; PIC64R6MM: jr $25 +; STATIC64: j ; PIC16: jalrc %call = tail call fastcc i32 @caller8_1() @@ -169,8 +178,8 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal -; N64: jalr $25 -; N64R6: jalr $25 +; PIC64: jalr $25 +; STATIC64: jal ; PIC16: jalrc %call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind @@ -190,8 +199,9 @@ entry: ; PIC32R6: jrc $25 ; PIC32MM: jrc ; STATIC32: j -; N64: jr $25 -; N64R6: jrc $25 +; PIC64: jr $25 +; STATIC64: j +; PIC64R6: jrc $25 ; PIC16: jalrc %call = tail call fastcc i32 @caller9_1() ret i32 %call @@ -204,8 +214,9 @@ entry: ; PIC32R6: jalrc $25 ; PIC32MM: jalr $25 ; STATIC32: jal -; N64: jalr $25 -; N64R6: jalrc $25 +; STATIC64: jal +; PIC64: jalr $25 +; PIC64R6: jalrc $25 ; PIC16: jalrc %call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind @@ -221,8 +232,9 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal -; N64: jalr $25 -; N64R6: jalr $25 +; STATIC64: jal +; PIC64: jalr $25 +; PIC64R6: jalr $25 ; PIC16: jalrc %call = tail call i32 @callee10(i32 %a8, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind @@ -238,8 +250,9 @@ entry: ; PIC32R6: jalrc $25 ; PIC32MM: jalr $25 ; STATIC32: jal -; N64: jalr $25 -; N64R6: jalrc $25 +; STATIC64: jal +; PIC64: jalr $25 +; PIC64R6: jalrc $25 ; PIC16: jalrc %call = tail call i32 @callee11(%struct.S* byval @gs1) nounwind @@ -257,8 +270,9 @@ entry: ; PIC32R6: jalrc $25 ; PIC32MM: jalr $25 ; STATIC32: jal -; N64: jalr $25 -; N64R6: jalrc $25 +; STATIC64: jal +; PIC64: jalr $25 +; PIC64R6: jalrc $25 ; PIC16: jalrc %0 = bitcast %struct.S* %a0 to i8* @@ -271,13 +285,14 @@ declare i32 @callee13(i32, ...) define i32 @caller13() nounwind { entry: -; ALL-LABEL: caller13 +; ALL-LABEL: caller13: ; PIC32: jalr $25 ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal -; N64: jalr $25 -; N64R6: jalr $25 +; STATIC64: jal +; PIC64R6: jalr $25 +; PIC64: jalr $25 ; PIC16: jalrc %call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind diff --git a/test/CodeGen/Mips/tnaked.ll b/test/CodeGen/Mips/tnaked.ll index 08f1ab5be86e..7dff19c5d000 100644 --- a/test/CodeGen/Mips/tnaked.ll +++ b/test/CodeGen/Mips/tnaked.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel < %s -verify-machineinstrs | FileCheck %s define void @tnaked() #0 { diff --git a/test/CodeGen/Mips/xray-mips-attribute-instrumentation.ll b/test/CodeGen/Mips/xray-mips-attribute-instrumentation.ll new file mode 100644 index 000000000000..a7c859a1815f --- /dev/null +++ b/test/CodeGen/Mips/xray-mips-attribute-instrumentation.ll @@ -0,0 +1,147 @@ +; RUN: llc -filetype=asm -o - -mtriple=mips-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-MIPS32 %s +; RUN: llc -filetype=asm -o - -mtriple=mipsel-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-MIPS32 %s +; RUN: llc -filetype=asm -o - -mtriple=mips64-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-MIPS64 %s +; RUN: llc -filetype=asm -o - -mtriple=mips64el-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-MIPS64 %s + +define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" { +; CHECK: .p2align 2 +; CHECK-MIPS64-LABEL: .Lxray_sled_0: +; CHECK-MIPS32-LABEL: $xray_sled_0: +; CHECK-MIPS64: b .Ltmp0 +; CHECK-MIPS32: b $tmp0 +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64-LABEL: .Ltmp0: +; CHECK-MIPS32-LABEL: $tmp0: +; CHECK-MIPS32: addiu $25, $25, 52 + ret i32 0 +; CHECK: .p2align 2 +; CHECK-MIPS64-LABEL: .Lxray_sled_1: +; CHECK-MIPS32-LABEL: $xray_sled_1: +; CHECK-MIPS64: b .Ltmp1 +; CHECK-MIPS32: b $tmp1 +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64-LABEL: .Ltmp1: +; CHECK-MIPS32-LABEL: $tmp1: +; CHECK-MIPS32: addiu $25, $25, 52 +} +; CHECK: .section xray_instr_map,{{.*}} +; CHECK-MIPS64: .8byte .Lxray_sled_0 +; CHECK-MIPS64: .8byte .Lxray_sled_1 +; CHECK-MIPS32: .4byte ($xray_sled_0) +; CHECK-MIPS32: .4byte ($xray_sled_1) + +; We test multiple returns in a single function to make sure we're getting all +; of them with XRay instrumentation. +define i32 @bar(i32 %i) nounwind noinline uwtable "function-instrument"="xray-always" { +; CHECK: .p2align 2 +; CHECK-MIPS64-LABEL: .Lxray_sled_2: +; CHECK-MIPS32-LABEL: $xray_sled_2: +; CHECK-MIPS64: b .Ltmp2 +; CHECK-MIPS32: b $tmp2 +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64-LABEL: .Ltmp2: +; CHECK-MIPS32-LABEL: $tmp2: +; CHECK-MIPS32: addiu $25, $25, 52 +Test: + %cond = icmp eq i32 %i, 0 + br i1 %cond, label %IsEqual, label %NotEqual +IsEqual: + ret i32 0 +; CHECK: .p2align 2 +; CHECK-MIPS64-LABEL: .Lxray_sled_3: +; CHECK-MIPS32-LABEL: $xray_sled_3: +; CHECK-MIPS64: b .Ltmp3 +; CHECK-MIPS32: b $tmp3 +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64-LABEL: .Ltmp3: +; CHECK-MIPS32-LABEL: $tmp3: +; CHECK-MIPS32: addiu $25, $25, 52 +NotEqual: + ret i32 1 +; CHECK: .p2align 2 +; CHECK-MIPS64-LABEL: .Lxray_sled_4: +; CHECK-MIPS32-LABEL: $xray_sled_4: +; CHECK-MIPS64: b .Ltmp4 +; CHECK-MIPS32: b $tmp4 +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64: nop +; CHECK-MIPS64-LABEL: .Ltmp4: +; CHECK-MIPS32-LABEL: $tmp4: +; CHECK-MIPS32: addiu $25, $25, 52 +} +; CHECK: .section xray_instr_map,{{.*}} +; CHECK-MIPS64: .8byte .Lxray_sled_2 +; CHECK-MIPS64: .8byte .Lxray_sled_3 +; CHECK-MIPS64: .8byte .Lxray_sled_4 +; CHECK-MIPS32: .4byte ($xray_sled_2) +; CHECK-MIPS32: .4byte ($xray_sled_3) +; CHECK-MIPS32: .4byte ($xray_sled_4) diff --git a/test/CodeGen/Mips/xray-section-group.ll b/test/CodeGen/Mips/xray-section-group.ll new file mode 100644 index 000000000000..d87f178ec4be --- /dev/null +++ b/test/CodeGen/Mips/xray-section-group.ll @@ -0,0 +1,31 @@ +; RUN: llc -filetype=asm -o - -mtriple=mips-unknown-linux-gnu -function-sections < %s | FileCheck %s +; RUN: llc -filetype=asm -o - -mtriple=mipsel-unknown-linux-gnu -function-sections < %s | FileCheck %s +; RUN: llc -filetype=obj -o %t -mtriple=mips-unknown-linux-gnu -function-sections < %s +; RUN: llvm-readobj -sections %t | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc -filetype=obj -o %t -mtriple=mipsel-unknown-linux-gnu -function-sections < %s +; RUN: llvm-readobj -sections %t | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc -filetype=asm -o - -mtriple=mips64-unknown-linux-gnu -function-sections < %s | FileCheck %s +; RUN: llc -filetype=asm -o - -mtriple=mips64el-unknown-linux-gnu -function-sections < %s | FileCheck %s +; RUN: llc -filetype=obj -o %t -mtriple=mips64-unknown-linux-gnu -function-sections < %s +; RUN: llvm-readobj -sections %t | FileCheck %s --check-prefix=CHECK-OBJ +; RUN: llc -filetype=obj -o %t -mtriple=mips64el-unknown-linux-gnu -function-sections < %s +; RUN: llvm-readobj -sections %t | FileCheck %s --check-prefix=CHECK-OBJ + +define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" { +; CHECK: .section .text.foo,"ax",@progbits + ret i32 0 +; CHECK: .section xray_instr_map,"a",@progbits +} + +; CHECK-OBJ: Section { +; CHECK-OBJ: Name: xray_instr_map + +$bar = comdat any +define i32 @bar() nounwind noinline uwtable "function-instrument"="xray-always" comdat($bar) { +; CHECK: .section .text.bar,"axG",@progbits,bar,comdat + ret i32 1 +; CHECK: .section xray_instr_map,"aG",@progbits,bar,comdat +} + +; CHECK-OBJ: Section { +; CHECK-OBJ: Name: xray_instr_map |