diff options
Diffstat (limited to 'test/CodeGen/Mips')
25 files changed, 2866 insertions, 224 deletions
diff --git a/test/CodeGen/Mips/adjust-callstack-sp.ll b/test/CodeGen/Mips/adjust-callstack-sp.ll new file mode 100644 index 000000000000..8c61a650a962 --- /dev/null +++ b/test/CodeGen/Mips/adjust-callstack-sp.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=mips -mcpu=mips16 | FileCheck %s -check-prefix=M16 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips3 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips64r6 | FileCheck %s -check-prefix=GP64 + +declare void @bar(i32*) + +define void @foo(i32 %sz) { + ; ALL-LABEL: foo: + + ; M16-NOT: addiu $sp, 0 # 16 bit inst + ; GP32-NOT: addiu $sp, $sp, 0 + ; GP64-NOT: daddiu $sp, $sp, 0 + %a = alloca i32, i32 %sz + call void @bar(i32* %a) + ret void +} diff --git a/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll b/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll new file mode 100644 index 000000000000..d17290e552e0 --- /dev/null +++ b/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll @@ -0,0 +1,80 @@ +; RUN: llc < %s -march=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEB +; RUN: llc < %s -march=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEL +; RUN: llc < %s -march=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEB +; RUN: llc < %s -march=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEL + +; #include <stdio.h> +; +; struct S1 { +; char x1; +; short x2; +; char x3; +; }; +; +; struct S2 { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; }; +; +; void fS1(struct S1 s); +; void fS2(struct S2 s); +; +; void f1() { +; struct S1 s1_1; +; fS1(s1_1); +; } +; +; void f2() { +; struct S2 s2_1; +; fS2(s2_1); +; } +; +; int main() { +; f1(); +; f2(); +; } + +%struct.S1 = type { i8, i16, i8 } +%struct.S2 = type { i8, i8, i8, i8, i8 } + +declare void @fS1(i48 inreg) #1 +declare void @fS2(i40 inreg) #1 + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2 + +define void @f1() #0 { +entry: + %s1_1 = alloca %struct.S1, align 2 + %s1_1.coerce = alloca { i48 } + %0 = bitcast { i48 }* %s1_1.coerce to i8* + %1 = bitcast %struct.S1* %s1_1 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 6, i32 0, i1 false) + %2 = getelementptr { i48 }* %s1_1.coerce, i32 0, i32 0 + %3 = load i48* %2, align 1 + call void @fS1(i48 inreg %3) + ret void + ; ALL-LABEL: f1: + + ; MIPSEB: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 16 + ; MIPSEL-NOT: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 16 +} + +define void @f2() #0 { +entry: + %s2_1 = alloca %struct.S2, align 1 + %s2_1.coerce = alloca { i40 } + %0 = bitcast { i40 }* %s2_1.coerce to i8* + %1 = bitcast %struct.S2* %s2_1 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 5, i32 0, i1 false) + %2 = getelementptr { i40 }* %s2_1.coerce, i32 0, i32 0 + %3 = load i40* %2, align 1 + call void @fS2(i40 inreg %3) + ret void + ; ALL-LABEL: f2: + + ; MIPSEB: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 24 + ; MIPSEL-NOT: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 24 +} diff --git a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll new file mode 100644 index 000000000000..458b124c9927 --- /dev/null +++ b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll @@ -0,0 +1,282 @@ +; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s + +; Generated from the C program: +; +; #include <stdio.h> +; #include <string.h> +; +; struct SmallStruct_1b { +; char x1; +; }; +; +; struct SmallStruct_2b { +; char x1; +; char x2; +; }; +; +; struct SmallStruct_3b { +; char x1; +; char x2; +; char x3; +; }; +; +; struct SmallStruct_4b { +; char x1; +; char x2; +; char x3; +; char x4; +; }; +; +; struct SmallStruct_5b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; }; +; +; struct SmallStruct_6b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; char x6; +; }; +; +; struct SmallStruct_7b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; char x6; +; char x7; +; }; +; +; struct SmallStruct_8b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; char x6; +; char x7; +; char x8; +; }; +; +; struct SmallStruct_9b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; char x6; +; char x7; +; char x8; +; char x9; +; }; +; +; void varArgF_SmallStruct(char* c, ...); +; +; void smallStruct_1b(struct SmallStruct_1b* ss) { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_2b(struct SmallStruct_2b* ss) { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_3b(struct SmallStruct_3b* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_4b(struct SmallStruct_4b* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_5b(struct SmallStruct_5b* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_6b(struct SmallStruct_6b* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_7b(struct SmallStruct_7b* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_8b(struct SmallStruct_8b* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_9b(struct SmallStruct_9b* ss) +; { +; varArgF_SmallStruct("", *ss); +; } + +%struct.SmallStruct_1b = type { i8 } +%struct.SmallStruct_2b = type { i8, i8 } +%struct.SmallStruct_3b = type { i8, i8, i8 } +%struct.SmallStruct_4b = type { i8, i8, i8, i8 } +%struct.SmallStruct_5b = type { i8, i8, i8, i8, i8 } +%struct.SmallStruct_6b = type { i8, i8, i8, i8, i8, i8 } +%struct.SmallStruct_7b = type { i8, i8, i8, i8, i8, i8, i8 } +%struct.SmallStruct_8b = type { i8, i8, i8, i8, i8, i8, i8, i8 } +%struct.SmallStruct_9b = type { i8, i8, i8, i8, i8, i8, i8, i8, i8 } + +@.str = private unnamed_addr constant [3 x i8] c"01\00", align 1 + +declare void @varArgF_SmallStruct(i8* %c, ...) + +define void @smallStruct_1b(%struct.SmallStruct_1b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_1b*, align 8 + store %struct.SmallStruct_1b* %ss, %struct.SmallStruct_1b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_1b** %ss.addr, align 8 + %1 = bitcast %struct.SmallStruct_1b* %0 to { i8 }* + %2 = getelementptr { i8 }* %1, i32 0, i32 0 + %3 = load i8* %2, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i8 inreg %3) + ret void + ; CHECK-LABEL: smallStruct_1b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 +} + +define void @smallStruct_2b(%struct.SmallStruct_2b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_2b*, align 8 + store %struct.SmallStruct_2b* %ss, %struct.SmallStruct_2b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_2b** %ss.addr, align 8 + %1 = bitcast %struct.SmallStruct_2b* %0 to { i16 }* + %2 = getelementptr { i16 }* %1, i32 0, i32 0 + %3 = load i16* %2, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i16 inreg %3) + ret void + ; CHECK-LABEL: smallStruct_2b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 48 +} + +define void @smallStruct_3b(%struct.SmallStruct_3b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_3b*, align 8 + %.coerce = alloca { i24 } + store %struct.SmallStruct_3b* %ss, %struct.SmallStruct_3b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_3b** %ss.addr, align 8 + %1 = bitcast { i24 }* %.coerce to i8* + %2 = bitcast %struct.SmallStruct_3b* %0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 3, i32 0, i1 false) + %3 = getelementptr { i24 }* %.coerce, i32 0, i32 0 + %4 = load i24* %3, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i24 inreg %4) + ret void + ; CHECK-LABEL: smallStruct_3b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 40 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1 + +define void @smallStruct_4b(%struct.SmallStruct_4b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_4b*, align 8 + store %struct.SmallStruct_4b* %ss, %struct.SmallStruct_4b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_4b** %ss.addr, align 8 + %1 = bitcast %struct.SmallStruct_4b* %0 to { i32 }* + %2 = getelementptr { i32 }* %1, i32 0, i32 0 + %3 = load i32* %2, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 inreg %3) + ret void + ; CHECK-LABEL: smallStruct_4b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 32 +} + +define void @smallStruct_5b(%struct.SmallStruct_5b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_5b*, align 8 + %.coerce = alloca { i40 } + store %struct.SmallStruct_5b* %ss, %struct.SmallStruct_5b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_5b** %ss.addr, align 8 + %1 = bitcast { i40 }* %.coerce to i8* + %2 = bitcast %struct.SmallStruct_5b* %0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 5, i32 0, i1 false) + %3 = getelementptr { i40 }* %.coerce, i32 0, i32 0 + %4 = load i40* %3, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i40 inreg %4) + ret void + ; CHECK-LABEL: smallStruct_5b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 24 +} + +define void @smallStruct_6b(%struct.SmallStruct_6b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_6b*, align 8 + %.coerce = alloca { i48 } + store %struct.SmallStruct_6b* %ss, %struct.SmallStruct_6b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_6b** %ss.addr, align 8 + %1 = bitcast { i48 }* %.coerce to i8* + %2 = bitcast %struct.SmallStruct_6b* %0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 6, i32 0, i1 false) + %3 = getelementptr { i48 }* %.coerce, i32 0, i32 0 + %4 = load i48* %3, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i48 inreg %4) + ret void + ; CHECK-LABEL: smallStruct_6b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 16 +} + +define void @smallStruct_7b(%struct.SmallStruct_7b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_7b*, align 8 + %.coerce = alloca { i56 } + store %struct.SmallStruct_7b* %ss, %struct.SmallStruct_7b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_7b** %ss.addr, align 8 + %1 = bitcast { i56 }* %.coerce to i8* + %2 = bitcast %struct.SmallStruct_7b* %0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 7, i32 0, i1 false) + %3 = getelementptr { i56 }* %.coerce, i32 0, i32 0 + %4 = load i56* %3, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i56 inreg %4) + ret void + ; CHECK-LABEL: smallStruct_7b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 8 +} + +define void @smallStruct_8b(%struct.SmallStruct_8b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_8b*, align 8 + store %struct.SmallStruct_8b* %ss, %struct.SmallStruct_8b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_8b** %ss.addr, align 8 + %1 = bitcast %struct.SmallStruct_8b* %0 to { i64 }* + %2 = getelementptr { i64 }* %1, i32 0, i32 0 + %3 = load i64* %2, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 inreg %3) + ret void + ; CHECK-LABEL: smallStruct_8b: + ; CHECK-NOT: dsll +} + +define void @smallStruct_9b(%struct.SmallStruct_9b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_9b*, align 8 + %.coerce = alloca { i64, i8 } + store %struct.SmallStruct_9b* %ss, %struct.SmallStruct_9b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_9b** %ss.addr, align 8 + %1 = bitcast { i64, i8 }* %.coerce to i8* + %2 = bitcast %struct.SmallStruct_9b* %0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 9, i32 0, i1 false) + %3 = getelementptr { i64, i8 }* %.coerce, i32 0, i32 0 + %4 = load i64* %3, align 1 + %5 = getelementptr { i64, i8 }* %.coerce, i32 0, i32 1 + %6 = load i8* %5, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 inreg %4, i8 inreg %6) + ret void + ; CHECK-LABEL: smallStruct_9b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 +} diff --git a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll new file mode 100644 index 000000000000..899a3e8ff0a1 --- /dev/null +++ b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll @@ -0,0 +1,149 @@ +; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s + +; Generated from the C program: +; +; #include <stdio.h> +; #include <string.h> +; +; struct SmallStruct_1b1s { +; char x1; +; short x2; +; }; +; +; struct SmallStruct_1b1i { +; char x1; +; int x2; +; }; +; +; struct SmallStruct_1b1s1b { +; char x1; +; short x2; +; char x3; +; }; +; +; struct SmallStruct_1s1i { +; short x1; +; int x2; +; }; +; +; struct SmallStruct_3b1s { +; char x1; +; char x2; +; char x3; +; short x4; +; }; +; +; void varArgF_SmallStruct(char* c, ...); +; +; void smallStruct_1b1s(struct SmallStruct_1b1s* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_1b1i(struct SmallStruct_1b1i* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_1b1s1b(struct SmallStruct_1b1s1b* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_1s1i(struct SmallStruct_1s1i* ss) +; { +; varArgF_SmallStruct("", *ss); +; } +; +; void smallStruct_3b1s(struct SmallStruct_3b1s* ss) +; { +; varArgF_SmallStruct("", *ss); +; } + +%struct.SmallStruct_1b1s = type { i8, i16 } +%struct.SmallStruct_1b1i = type { i8, i32 } +%struct.SmallStruct_1b1s1b = type { i8, i16, i8 } +%struct.SmallStruct_1s1i = type { i16, i32 } +%struct.SmallStruct_3b1s = type { i8, i8, i8, i16 } + +@.str = private unnamed_addr constant [3 x i8] c"01\00", align 1 + +declare void @varArgF_SmallStruct(i8* %c, ...) + +define void @smallStruct_1b1s(%struct.SmallStruct_1b1s* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_1b1s*, align 8 + store %struct.SmallStruct_1b1s* %ss, %struct.SmallStruct_1b1s** %ss.addr, align 8 + %0 = load %struct.SmallStruct_1b1s** %ss.addr, align 8 + %1 = bitcast %struct.SmallStruct_1b1s* %0 to { i32 }* + %2 = getelementptr { i32 }* %1, i32 0, i32 0 + %3 = load i32* %2, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 inreg %3) + ret void + ; CHECK-LABEL: smallStruct_1b1s: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 32 +} + +define void @smallStruct_1b1i(%struct.SmallStruct_1b1i* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_1b1i*, align 8 + store %struct.SmallStruct_1b1i* %ss, %struct.SmallStruct_1b1i** %ss.addr, align 8 + %0 = load %struct.SmallStruct_1b1i** %ss.addr, align 8 + %1 = bitcast %struct.SmallStruct_1b1i* %0 to { i64 }* + %2 = getelementptr { i64 }* %1, i32 0, i32 0 + %3 = load i64* %2, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 inreg %3) + ret void + ; CHECK-LABEL: smallStruct_1b1i: + ; CHECK-NOT: dsll +} + +define void @smallStruct_1b1s1b(%struct.SmallStruct_1b1s1b* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_1b1s1b*, align 8 + %.coerce = alloca { i48 } + store %struct.SmallStruct_1b1s1b* %ss, %struct.SmallStruct_1b1s1b** %ss.addr, align 8 + %0 = load %struct.SmallStruct_1b1s1b** %ss.addr, align 8 + %1 = bitcast { i48 }* %.coerce to i8* + %2 = bitcast %struct.SmallStruct_1b1s1b* %0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 6, i32 0, i1 false) + %3 = getelementptr { i48 }* %.coerce, i32 0, i32 0 + %4 = load i48* %3, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i48 inreg %4) + ret void + ; CHECK-LABEL: smallStruct_1b1s1b: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 16 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1 + +define void @smallStruct_1s1i(%struct.SmallStruct_1s1i* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_1s1i*, align 8 + store %struct.SmallStruct_1s1i* %ss, %struct.SmallStruct_1s1i** %ss.addr, align 8 + %0 = load %struct.SmallStruct_1s1i** %ss.addr, align 8 + %1 = bitcast %struct.SmallStruct_1s1i* %0 to { i64 }* + %2 = getelementptr { i64 }* %1, i32 0, i32 0 + %3 = load i64* %2, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 inreg %3) + ret void + ; CHECK-LABEL: smallStruct_1s1i: + ; CHECK-NOT: dsll +} + +define void @smallStruct_3b1s(%struct.SmallStruct_3b1s* %ss) #0 { +entry: + %ss.addr = alloca %struct.SmallStruct_3b1s*, align 8 + %.coerce = alloca { i48 } + store %struct.SmallStruct_3b1s* %ss, %struct.SmallStruct_3b1s** %ss.addr, align 8 + %0 = load %struct.SmallStruct_3b1s** %ss.addr, align 8 + %1 = bitcast { i48 }* %.coerce to i8* + %2 = bitcast %struct.SmallStruct_3b1s* %0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* %2, i64 6, i32 0, i1 false) + %3 = getelementptr { i48 }* %.coerce, i32 0, i32 0 + %4 = load i48* %3, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i48 inreg %4) + ret void + ; CHECK-LABEL: smallStruct_3b1s: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 16 +} diff --git a/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll new file mode 100644 index 000000000000..1f7362523346 --- /dev/null +++ b/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll @@ -0,0 +1,161 @@ +; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s + +; Generated from the C program: +; +; #include <stdio.h> +; #include <string.h> +; +; struct SmallStruct_1b { +; char x1; +; }; +; +; struct SmallStruct_2b { +; char x1; +; char x2; +; }; +; +; struct SmallStruct_3b { +; char x1; +; char x2; +; char x3; +; }; +; +; struct SmallStruct_4b { +; char x1; +; char x2; +; char x3; +; char x4; +; }; +; +; struct SmallStruct_5b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; }; +; +; struct SmallStruct_6b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; char x6; +; }; +; +; struct SmallStruct_7b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; char x6; +; char x7; +; }; +; +; struct SmallStruct_8b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; char x6; +; char x7; +; char x8; +; }; +; +; struct SmallStruct_9b { +; char x1; +; char x2; +; char x3; +; char x4; +; char x5; +; char x6; +; char x7; +; char x8; +; char x9; +; }; +; +; void varArgF_SmallStruct(char* c, ...); +; +; void smallStruct_1b_x9(struct SmallStruct_1b* ss1, struct SmallStruct_1b* ss2, struct SmallStruct_1b* ss3, struct SmallStruct_1b* ss4, struct SmallStruct_1b* ss5, struct SmallStruct_1b* ss6, struct SmallStruct_1b* ss7, struct SmallStruct_1b* ss8, struct SmallStruct_1b* ss9) +; { +; varArgF_SmallStruct("", *ss1, *ss2, *ss3, *ss4, *ss5, *ss6, *ss7, *ss8, *ss9); +; } + +%struct.SmallStruct_1b = type { i8 } + +@.str = private unnamed_addr constant [3 x i8] c"01\00", align 1 + +declare void @varArgF_SmallStruct(i8* %c, ...) + +define void @smallStruct_1b_x9(%struct.SmallStruct_1b* %ss1, %struct.SmallStruct_1b* %ss2, %struct.SmallStruct_1b* %ss3, %struct.SmallStruct_1b* %ss4, %struct.SmallStruct_1b* %ss5, %struct.SmallStruct_1b* %ss6, %struct.SmallStruct_1b* %ss7, %struct.SmallStruct_1b* %ss8, %struct.SmallStruct_1b* %ss9) #0 { +entry: + %ss1.addr = alloca %struct.SmallStruct_1b*, align 8 + %ss2.addr = alloca %struct.SmallStruct_1b*, align 8 + %ss3.addr = alloca %struct.SmallStruct_1b*, align 8 + %ss4.addr = alloca %struct.SmallStruct_1b*, align 8 + %ss5.addr = alloca %struct.SmallStruct_1b*, align 8 + %ss6.addr = alloca %struct.SmallStruct_1b*, align 8 + %ss7.addr = alloca %struct.SmallStruct_1b*, align 8 + %ss8.addr = alloca %struct.SmallStruct_1b*, align 8 + %ss9.addr = alloca %struct.SmallStruct_1b*, align 8 + store %struct.SmallStruct_1b* %ss1, %struct.SmallStruct_1b** %ss1.addr, align 8 + store %struct.SmallStruct_1b* %ss2, %struct.SmallStruct_1b** %ss2.addr, align 8 + store %struct.SmallStruct_1b* %ss3, %struct.SmallStruct_1b** %ss3.addr, align 8 + store %struct.SmallStruct_1b* %ss4, %struct.SmallStruct_1b** %ss4.addr, align 8 + store %struct.SmallStruct_1b* %ss5, %struct.SmallStruct_1b** %ss5.addr, align 8 + store %struct.SmallStruct_1b* %ss6, %struct.SmallStruct_1b** %ss6.addr, align 8 + store %struct.SmallStruct_1b* %ss7, %struct.SmallStruct_1b** %ss7.addr, align 8 + store %struct.SmallStruct_1b* %ss8, %struct.SmallStruct_1b** %ss8.addr, align 8 + store %struct.SmallStruct_1b* %ss9, %struct.SmallStruct_1b** %ss9.addr, align 8 + %0 = load %struct.SmallStruct_1b** %ss1.addr, align 8 + %1 = load %struct.SmallStruct_1b** %ss2.addr, align 8 + %2 = load %struct.SmallStruct_1b** %ss3.addr, align 8 + %3 = load %struct.SmallStruct_1b** %ss4.addr, align 8 + %4 = load %struct.SmallStruct_1b** %ss5.addr, align 8 + %5 = load %struct.SmallStruct_1b** %ss6.addr, align 8 + %6 = load %struct.SmallStruct_1b** %ss7.addr, align 8 + %7 = load %struct.SmallStruct_1b** %ss8.addr, align 8 + %8 = load %struct.SmallStruct_1b** %ss9.addr, align 8 + %9 = bitcast %struct.SmallStruct_1b* %0 to { i8 }* + %10 = getelementptr { i8 }* %9, i32 0, i32 0 + %11 = load i8* %10, align 1 + %12 = bitcast %struct.SmallStruct_1b* %1 to { i8 }* + %13 = getelementptr { i8 }* %12, i32 0, i32 0 + %14 = load i8* %13, align 1 + %15 = bitcast %struct.SmallStruct_1b* %2 to { i8 }* + %16 = getelementptr { i8 }* %15, i32 0, i32 0 + %17 = load i8* %16, align 1 + %18 = bitcast %struct.SmallStruct_1b* %3 to { i8 }* + %19 = getelementptr { i8 }* %18, i32 0, i32 0 + %20 = load i8* %19, align 1 + %21 = bitcast %struct.SmallStruct_1b* %4 to { i8 }* + %22 = getelementptr { i8 }* %21, i32 0, i32 0 + %23 = load i8* %22, align 1 + %24 = bitcast %struct.SmallStruct_1b* %5 to { i8 }* + %25 = getelementptr { i8 }* %24, i32 0, i32 0 + %26 = load i8* %25, align 1 + %27 = bitcast %struct.SmallStruct_1b* %6 to { i8 }* + %28 = getelementptr { i8 }* %27, i32 0, i32 0 + %29 = load i8* %28, align 1 + %30 = bitcast %struct.SmallStruct_1b* %7 to { i8 }* + %31 = getelementptr { i8 }* %30, i32 0, i32 0 + %32 = load i8* %31, align 1 + %33 = bitcast %struct.SmallStruct_1b* %8 to { i8 }* + %34 = getelementptr { i8 }* %33, i32 0, i32 0 + %35 = load i8* %34, align 1 + call void (i8*, ...)* @varArgF_SmallStruct(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i8 inreg %11, i8 inreg %14, i8 inreg %17, i8 inreg %20, i8 inreg %23, i8 inreg %26, i8 inreg %29, i8 inreg %32, i8 inreg %35) + ret void + ; CHECK-LABEL: smallStruct_1b_x9: + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 + ; CHECK: dsll $[[R1:[0-9]+]], $[[R2:[0-9]+]], 56 +} diff --git a/test/CodeGen/Mips/check-adde-redundant-moves.ll b/test/CodeGen/Mips/check-adde-redundant-moves.ll new file mode 100644 index 000000000000..527c21770263 --- /dev/null +++ b/test/CodeGen/Mips/check-adde-redundant-moves.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL + +define i64 @add_i64(i64 %a) { + ; GP32-LABEL: add_i64 + + ; GP32-NOT: move $[[T0:[0-9]+]], $[[T0]] + %r = add i64 5, %a + ret i64 %r +} + +define i128 @add_i128(i128 %a) { + ; ALL-LABEL: add_i128 + + ; ALL-NOT: move $[[T0:[0-9]+]], $[[T0]] + %r = add i128 5, %a + ret i128 %r +} diff --git a/test/CodeGen/Mips/fcmp.ll b/test/CodeGen/Mips/fcmp.ll index 8e83b0064ed9..aa1f09bf7aba 100644 --- a/test/CodeGen/Mips/fcmp.ll +++ b/test/CodeGen/Mips/fcmp.ll @@ -1,10 +1,17 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-C -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-C -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP -; RUN: llc < %s -march=mips64el -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-C -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-C -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-C -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP +; RUN: llc < %s -march=mips -mcpu=mips32 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C +; RUN: llc < %s -march=mips -mcpu=mips32r2 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C +; RUN: llc < %s -march=mips -mcpu=mips32r6 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMP +; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP define i32 @false_f32(float %a, float %b) nounwind { ; ALL-LABEL: false_f32: @@ -18,15 +25,13 @@ define i32 @false_f32(float %a, float %b) nounwind { define i32 @oeq_f32(float %a, float %b) nounwind { ; ALL-LABEL: oeq_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.eq.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.eq.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -44,15 +49,13 @@ define i32 @oeq_f32(float %a, float %b) nounwind { define i32 @ogt_f32(float %a, float %b) nounwind { ; ALL-LABEL: ogt_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ule.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ule.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -70,15 +73,13 @@ define i32 @ogt_f32(float %a, float %b) nounwind { define i32 @oge_f32(float %a, float %b) nounwind { ; ALL-LABEL: oge_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ult.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ult.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -96,15 +97,13 @@ define i32 @oge_f32(float %a, float %b) nounwind { define i32 @olt_f32(float %a, float %b) nounwind { ; ALL-LABEL: olt_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.olt.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.olt.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -122,15 +121,13 @@ define i32 @olt_f32(float %a, float %b) nounwind { define i32 @ole_f32(float %a, float %b) nounwind { ; ALL-LABEL: ole_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ole.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ole.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -148,15 +145,13 @@ define i32 @ole_f32(float %a, float %b) nounwind { define i32 @one_f32(float %a, float %b) nounwind { ; ALL-LABEL: one_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ueq.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ueq.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -176,15 +171,13 @@ define i32 @one_f32(float %a, float %b) nounwind { define i32 @ord_f32(float %a, float %b) nounwind { ; ALL-LABEL: ord_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.un.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.un.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -204,15 +197,13 @@ define i32 @ord_f32(float %a, float %b) nounwind { define i32 @ueq_f32(float %a, float %b) nounwind { ; ALL-LABEL: ueq_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ueq.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ueq.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -230,15 +221,13 @@ define i32 @ueq_f32(float %a, float %b) nounwind { define i32 @ugt_f32(float %a, float %b) nounwind { ; ALL-LABEL: ugt_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ole.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ole.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -256,15 +245,13 @@ define i32 @ugt_f32(float %a, float %b) nounwind { define i32 @uge_f32(float %a, float %b) nounwind { ; ALL-LABEL: uge_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.olt.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.olt.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -282,15 +269,13 @@ define i32 @uge_f32(float %a, float %b) nounwind { define i32 @ult_f32(float %a, float %b) nounwind { ; ALL-LABEL: ult_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ult.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ult.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -300,6 +285,7 @@ define i32 @ult_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 + %1 = fcmp ult float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -308,15 +294,13 @@ define i32 @ult_f32(float %a, float %b) nounwind { define i32 @ule_f32(float %a, float %b) nounwind { ; ALL-LABEL: ule_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ule.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ule.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -334,15 +318,13 @@ define i32 @ule_f32(float %a, float %b) nounwind { define i32 @une_f32(float %a, float %b) nounwind { ; ALL-LABEL: une_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.eq.s $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.eq.s $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -362,15 +344,13 @@ define i32 @une_f32(float %a, float %b) nounwind { define i32 @uno_f32(float %a, float %b) nounwind { ; ALL-LABEL: uno_f32: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.un.s $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.un.s $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -406,15 +386,13 @@ define i32 @false_f64(double %a, double %b) nounwind { define i32 @oeq_f64(double %a, double %b) nounwind { ; ALL-LABEL: oeq_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.eq.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.eq.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -432,15 +410,13 @@ define i32 @oeq_f64(double %a, double %b) nounwind { define i32 @ogt_f64(double %a, double %b) nounwind { ; ALL-LABEL: ogt_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ule.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ule.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -458,15 +434,13 @@ define i32 @ogt_f64(double %a, double %b) nounwind { define i32 @oge_f64(double %a, double %b) nounwind { ; ALL-LABEL: oge_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ult.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ult.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -484,15 +458,13 @@ define i32 @oge_f64(double %a, double %b) nounwind { define i32 @olt_f64(double %a, double %b) nounwind { ; ALL-LABEL: olt_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.olt.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.olt.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -510,15 +482,13 @@ define i32 @olt_f64(double %a, double %b) nounwind { define i32 @ole_f64(double %a, double %b) nounwind { ; ALL-LABEL: ole_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ole.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ole.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -536,15 +506,13 @@ define i32 @ole_f64(double %a, double %b) nounwind { define i32 @one_f64(double %a, double %b) nounwind { ; ALL-LABEL: one_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ueq.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ueq.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -564,15 +532,13 @@ define i32 @one_f64(double %a, double %b) nounwind { define i32 @ord_f64(double %a, double %b) nounwind { ; ALL-LABEL: ord_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.un.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.un.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -592,15 +558,13 @@ define i32 @ord_f64(double %a, double %b) nounwind { define i32 @ueq_f64(double %a, double %b) nounwind { ; ALL-LABEL: ueq_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ueq.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ueq.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -618,15 +582,13 @@ define i32 @ueq_f64(double %a, double %b) nounwind { define i32 @ugt_f64(double %a, double %b) nounwind { ; ALL-LABEL: ugt_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ole.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ole.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -644,15 +606,13 @@ define i32 @ugt_f64(double %a, double %b) nounwind { define i32 @uge_f64(double %a, double %b) nounwind { ; ALL-LABEL: uge_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.olt.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.olt.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -670,15 +630,13 @@ define i32 @uge_f64(double %a, double %b) nounwind { define i32 @ult_f64(double %a, double %b) nounwind { ; ALL-LABEL: ult_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ult.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ult.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -696,15 +654,13 @@ define i32 @ult_f64(double %a, double %b) nounwind { define i32 @ule_f64(double %a, double %b) nounwind { ; ALL-LABEL: ule_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.ule.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.ule.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -722,15 +678,13 @@ define i32 @ule_f64(double %a, double %b) nounwind { define i32 @une_f64(double %a, double %b) nounwind { ; ALL-LABEL: une_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.eq.d $f12, $f14 -; 32-C-DAG: movf $[[T0]], $1, $fcc0 +; 32-C: movt $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.eq.d $f12, $f13 -; 64-C-DAG: movf $[[T0]], $1, $fcc0 +; 64-C: movt $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] @@ -750,15 +704,13 @@ define i32 @une_f64(double %a, double %b) nounwind { define i32 @uno_f64(double %a, double %b) nounwind { ; ALL-LABEL: uno_f64: -; 32-C-DAG: addiu $[[T0:2]], $zero, 0 -; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 32-C-DAG: addiu $2, $zero, 1 ; 32-C-DAG: c.un.d $f12, $f14 -; 32-C-DAG: movt $[[T0]], $1, $fcc0 +; 32-C: movf $2, $zero, $fcc0 -; 64-C-DAG: addiu $[[T0:2]], $zero, 0 -; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1 +; 64-C-DAG: addiu $2, $zero, 1 ; 64-C-DAG: c.un.d $f12, $f13 -; 64-C-DAG: movt $[[T0]], $1, $fcc0 +; 64-C: movf $2, $zero, $fcc0 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] diff --git a/test/CodeGen/Mips/fmadd1.ll b/test/CodeGen/Mips/fmadd1.ll index 271631efb40a..f0667eec3b33 100644 --- a/test/CodeGen/Mips/fmadd1.ll +++ b/test/CodeGen/Mips/fmadd1.ll @@ -39,10 +39,9 @@ entry: ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]] -; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13 -; 64-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14 -; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]] -; 64-DAG: add.s $f0, $[[T1]], $[[T2]] +; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 +; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] +; 64-DAG: add.s $f0, $[[T0]], $[[T1]] ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] @@ -80,10 +79,9 @@ entry: ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]] -; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13 -; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14 -; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]] -; 64-DAG: add.s $f0, $[[T1]], $[[T2]] +; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 +; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] +; 64-DAG: add.s $f0, $[[T0]], $[[T1]] ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] @@ -124,10 +122,11 @@ entry: ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-DAG: sub.s $f0, $[[T2]], $[[T1]] -; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13 -; 64-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14 -; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]] -; 64-DAG: sub.s $f0, $[[T2]], $[[T1]] +; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13 + +; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13 +; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]] +; 64-NAN: sub.s $f0, $[[T1]], $[[T0]] ; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13 @@ -164,10 +163,11 @@ entry: ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]] -; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13 -; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14 -; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]] -; 64-DAG: sub.s $f0, $[[T2]], $[[T1]] +; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 +; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]] +; 64-NAN: sub.s $f0, $[[T1]], $[[T0]] + +; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]] @@ -206,10 +206,9 @@ entry: ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]] -; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13 -; 64-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14 -; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]] -; 64-DAG: add.d $f0, $[[T1]], $[[T2]] +; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13 +; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] +; 64-DAG: add.d $f0, $[[T0]], $[[T1]] ; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] @@ -248,10 +247,9 @@ entry: ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]] -; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13 -; 64-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14 -; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]] -; 64-DAG: add.d $f0, $[[T1]], $[[T2]] +; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13 +; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]] +; 64-DAG: add.d $f0, $[[T0]], $[[T1]] ; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]] @@ -293,10 +291,11 @@ entry: ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]] -; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13 -; 64-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14 -; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]] -; 64-DAG: sub.d $f0, $[[T2]], $[[T1]] +; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13 + +; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13 +; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]] +; 64-NAN: sub.d $f0, $[[T1]], $[[T0]] ; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13 @@ -340,10 +339,11 @@ entry: ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]] ; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]] -; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13 -; 64-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14 -; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]] -; 64-DAG: sub.d $f0, $[[T2]], $[[T1]] +; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13 + +; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13 +; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]] +; 64-NAN: sub.d $f0, $[[T1]], $[[T0]] ; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13 diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll new file mode 100644 index 000000000000..83774eda634f --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -0,0 +1,115 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 + +define signext i1 @add_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: add_i1: + + ; ALL: addu $[[T0:[0-9]+]], $4, $5 + ; ALL: sll $[[T0]], $[[T0]], 31 + ; ALL: sra $2, $[[T0]], 31 + + %r = add i1 %a, %b + ret i1 %r +} + +define signext i8 @add_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: add_i8: + + ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seb $2, $[[T0:[0-9]+]] + + %r = add i8 %a, %b + ret i8 %r +} + +define signext i16 @add_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: add_i16: + + ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seh $2, $[[T0:[0-9]+]] + + %r = add i16 %a, %b + ret i16 %r +} + +define signext i32 @add_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: add_i32: + + ; ALL: addu $2, $4, $5 + + %r = add i32 %a, %b + ret i32 %r +} + +define signext i64 @add_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: add_i64: + + ; GP32: addu $3, $5, $7 + ; GP32: sltu $[[T0:[0-9]+]], $3, $7 + ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP32: addu $2, $4, $[[T1]] + + ; GP64: daddu $2, $4, $5 + + %r = add i64 %a, %b + ret i64 %r +} + +define signext i128 @add_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: add_i128: + + ; GP32: lw $[[T0:[0-9]+]], 28($sp) + ; GP32: addu $[[T1:[0-9]+]], $7, $[[T0]] + ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 24($sp) + ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]] + ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; GP32: lw $[[T7:[0-9]+]], 20($sp) + ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] + ; GP32: lw $[[T9:[0-9]+]], 16($sp) + ; GP32: addu $3, $5, $[[T8]] + ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]] + ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]] + ; GP32: addu $2, $4, $[[T11]] + ; GP32: move $4, $[[T5]] + ; GP32: move $5, $[[T1]] + + ; GP64: daddu $3, $5, $7 + ; GP64: sltu $[[T0:[0-9]+]], $3, $7 + ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP64: daddu $2, $4, $[[T1]] + + %r = add i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll new file mode 100644 index 000000000000..09d0ef9238af --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -0,0 +1,94 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 + +define signext i1 @and_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: and_i1: + + ; ALL: and $2, $4, $5 + + %r = and i1 %a, %b + ret i1 %r +} + +define signext i8 @and_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: and_i8: + + ; ALL: and $2, $4, $5 + + %r = and i8 %a, %b + ret i8 %r +} + +define signext i16 @and_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: and_i16: + + ; ALL: and $2, $4, $5 + + %r = and i16 %a, %b + ret i16 %r +} + +define signext i32 @and_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: and_i32: + + ; GP32: and $2, $4, $5 + + ; GP64: and $[[T0:[0-9]+]], $4, $5 + ; GP64: sll $2, $[[T0]], 0 + + %r = and i32 %a, %b + ret i32 %r +} + +define signext i64 @and_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: and_i64: + + ; GP32: and $2, $4, $6 + ; GP32: and $3, $5, $7 + + ; GP64: and $2, $4, $5 + + %r = and i64 %a, %b + ret i64 %r +} + +define signext i128 @and_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: and_i128: + + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: and $2, $4, $[[T2]] + ; GP32: and $3, $5, $[[T1]] + ; GP32: and $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: and $5, $7, $[[T3]] + + ; GP64: and $2, $4, $6 + ; GP64: and $3, $5, $7 + + %r = and i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll new file mode 100644 index 000000000000..415998929aa0 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -0,0 +1,188 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ +; RUN: -check-prefix=32R1-R2 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=64R6 -check-prefix=R2-R6 + +define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: ashr_i1: + + ; ALL: move $2, $4 + + %r = ashr i1 %a, %b + ret i1 %r +} + +define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: ashr_i8: + + ; FIXME: The andi instruction is redundant. + ; ALL: andi $[[T0:[0-9]+]], $5, 255 + ; ALL: srav $2, $4, $[[T0]] + + %r = ashr i8 %a, %b + ret i8 %r +} + +define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: ashr_i16: + + ; FIXME: The andi instruction is redundant. + ; ALL: andi $[[T0:[0-9]+]], $5, 65535 + ; ALL: srav $2, $4, $[[T0]] + + %r = ashr i16 %a, %b + ret i16 %r +} + +define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: ashr_i32: + + ; ALL: srav $2, $4, $5 + + %r = ashr i32 %a, %b + ret i32 %r +} + +define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: ashr_i64: + + ; M2: srav $[[T0:[0-9]+]], $4, $7 + ; M2: andi $[[T1:[0-9]+]], $7, 32 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: move $3, $[[T0]] + ; M2: srlv $[[T2:[0-9]+]], $5, $7 + ; M2: not $[[T3:[0-9]+]], $7 + ; M2: sll $[[T4:[0-9]+]], $4, 1 + ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; M2: or $3, $[[T3]], $[[T2]] + ; M2: $[[BB0]]: + ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: nop + ; M2: sra $2, $4, 31 + ; M2: $[[BB1]]: + ; M2: jr $ra + ; M2: nop + + ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7 + ; 32R1-R2: not $[[T1:[0-9]+]], $7 + ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1 + ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R1-R2: or $3, $[[T3]], $[[T0]] + ; 32R1-R2: srav $[[T4:[0-9]+]], $4, $7 + ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32 + ; 32R1-R2: movn $3, $[[T4]], $[[T5]] + ; 32R1-R2: sra $4, $4, 31 + ; 32R1-R2: jr $ra + ; 32R1-R2: movn $2, $4, $[[T5]] + + ; 32R6: srav $[[T0:[0-9]+]], $4, $7 + ; 32R6: andi $[[T1:[0-9]+]], $7, 32 + ; 32R6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; 32R6: sra $[[T3:[0-9]+]], $4, 31 + ; 32R6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] + ; 32R6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] + ; 32R6: srlv $[[T6:[0-9]+]], $5, $7 + ; 32R6: not $[[T7:[0-9]+]], $7 + ; 32R6: sll $[[T8:[0-9]+]], $4, 1 + ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] + ; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]] + ; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] + ; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] + ; 32R6: jr $ra + ; 32R6: or $3, $[[T0]], $[[T11]] + + ; FIXME: The sll instruction below is redundant. + ; GP64: sll $[[T0:[0-9]+]], $5, 0 + ; GP64: dsrav $2, $4, $[[T0]] + + %r = ashr i64 %a, %b + ret i64 %r +} + +define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: ashr_i128: + + ; GP32: lw $25, %call16(__ashrti3)($gp) + + ; M3: sll $[[T0:[0-9]+]], $7, 0 + ; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]] + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 + ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: move $3, $[[T1]] + ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] + ; M3: dsll $[[T5:[0-9]+]], $4, 1 + ; M3: not $[[T6:[0-9]+]], $[[T0]] + ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; M3: or $3, $[[T7]], $[[T4]] + ; M3: $[[BB0]]: + ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: nop + ; M3: dsra $2, $4, 63 + ; M3: $[[BB1]]: + ; M3: jr $ra + ; M3: nop + + ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 + ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] + ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] + ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] + ; GP64-NOT-R6: dsrav $2, $4, $[[T0]] + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64 + + ; GP64-NOT-R6: movn $3, $2, $[[T5]] + ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63 + ; GP64-NOT-R6: jr $ra + ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]] + + ; 64R6: sll $[[T0:[0-9]+]], $7, 0 + ; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]] + ; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 64 + ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0 + ; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]] + ; 64R6: dsra $[[T5:[0-9]+]], $4, 63 + ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; 64R6: or $2, $[[T6]], $[[T4]] + ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]] + ; 64R6: dsll $[[T8:[0-9]+]], $4, 1 + ; 64R6: not $[[T9:[0-9]+]], $[[T0]] + ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]] + ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]] + ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]] + ; 64R6: selnez $[[T13:[0-9]+]], $[[T1]], $[[T3]] + ; 64R6: jr $ra + ; 64R6: or $3, $[[T13]], $[[T12]] + + %r = ashr i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll new file mode 100644 index 000000000000..59f4330dde6c --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -0,0 +1,176 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ +; RUN: -check-prefix=32R1-R2 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=64R6 -check-prefix=R2-R6 + +define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: lshr_i1: + + ; ALL: move $2, $4 + + %r = lshr i1 %a, %b + ret i1 %r +} + +define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) { +entry: +; ALL-LABEL: lshr_i8: + + ; ALL: srlv $[[T0:[0-9]+]], $4, $5 + ; ALL: andi $2, $[[T0]], 255 + + %r = lshr i8 %a, %b + ret i8 %r +} + +define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) { +entry: +; ALL-LABEL: lshr_i16: + + ; ALL: srlv $[[T0:[0-9]+]], $4, $5 + ; ALL: andi $2, $[[T0]], 65535 + + %r = lshr i16 %a, %b + ret i16 %r +} + +define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: lshr_i32: + + ; ALL: srlv $2, $4, $5 + + %r = lshr i32 %a, %b + ret i32 %r +} + +define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: lshr_i64: + + ; M2: srlv $[[T0:[0-9]+]], $4, $7 + ; M2: andi $[[T1:[0-9]+]], $7, 32 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: move $3, $[[T0]] + ; M2: srlv $[[T2:[0-9]+]], $5, $7 + ; M2: not $[[T3:[0-9]+]], $7 + ; M2: sll $[[T4:[0-9]+]], $4, 1 + ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; M2: or $3, $[[T3]], $[[T2]] + ; M2: $[[BB0]]: + ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: addiu $2, $zero, 0 + ; M2: move $2, $[[T0]] + ; M2: $[[BB1]]: + ; M2: jr $ra + ; M2: nop + + ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7 + ; 32R1-R2: not $[[T1:[0-9]+]], $7 + ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1 + ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R1-R2: or $3, $[[T3]], $[[T0]] + ; 32R1-R2: srlv $[[T4:[0-9]+]], $4, $7 + ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32 + ; 32R1-R2: movn $3, $[[T4]], $[[T5]] + ; 32R1-R2: jr $ra + ; 32R1-R2: movn $2, $zero, $[[T5]] + + ; 32R6: srlv $[[T0:[0-9]+]], $5, $7 + ; 32R6: not $[[T1:[0-9]+]], $7 + ; 32R6: sll $[[T2:[0-9]+]], $4, 1 + ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]] + ; 32R6: andi $[[T5:[0-9]+]], $7, 32 + ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]] + ; 32R6: srlv $[[T7:[0-9]+]], $4, $7 + ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; 32R6: or $3, $[[T8]], $[[T6]] + ; 32R6: jr $ra + ; 32R6: seleqz $2, $[[T7]], $[[T5]] + + ; GP64: sll $[[T0:[0-9]+]], $5, 0 + ; GP64: dsrlv $2, $4, $[[T0]] + + %r = lshr i64 %a, %b + ret i64 %r +} + +define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: lshr_i128: + + ; GP32: lw $25, %call16(__lshrti3)($gp) + + ; M3: sll $[[T0:[0-9]+]], $7, 0 + ; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]] + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 + ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: move $3, $[[T1]] + ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] + ; M3: dsll $[[T5:[0-9]+]], $4, 1 + ; M3: not $[[T6:[0-9]+]], $[[T0]] + ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; M3: or $3, $[[T7]], $[[T4]] + ; M3: $[[BB0]]: + ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: daddiu $2, $zero, 0 + ; M3: move $2, $[[T1]] + ; M3: $[[BB1]]: + ; M3: jr $ra + ; M3: nop + + ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 + ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] + ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] + ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] + ; GP64-NOT-R6: dsrlv $2, $4, $[[T0]] + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64 + ; GP64-NOT-R6: movn $3, $2, $[[T5]] + ; GP64-NOT-R6: jr $ra + ; GP64-NOT-R6: movn $2, $zero, $1 + + ; 64R6: sll $[[T0:[0-9]+]], $7, 0 + ; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] + ; 64R6: dsll $[[T2:[0-9]+]], $4, 1 + ; 64R6: not $[[T3:[0-9]+]], $[[T0]] + ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]] + ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 64 + ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 + ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] + ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]] + ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] + ; 64R6: or $3, $[[T10]], $[[T8]] + ; 64R6: jr $ra + ; 64R6: seleqz $2, $[[T0]], $[[T7]] + + %r = lshr i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll index 167412407cdc..5f7f338c7789 100644 --- a/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/test/CodeGen/Mips/llvm-ir/mul.ll @@ -1,19 +1,19 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=M2 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R1 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R2 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=M4 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=64R1-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=64R1-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=M2 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=32R1-R2 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=32R1-R2 -check-prefix=32R2 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=32R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=64R1-R2 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=64R1-R2 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=64R6 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { entry: @@ -179,3 +179,30 @@ entry: %r = mul i64 %a, %b ret i64 %r } + +define signext i128 @mul_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: mul_i128: + + ; GP32: lw $25, %call16(__multi3)($gp) + + ; GP64-NOT-R6: dmult $4, $7 + ; GP64-NOT-R6: mflo $[[T0:[0-9]+]] + ; GP64-NOT-R6: dmult $5, $6 + ; GP64-NOT-R6: mflo $[[T1:[0-9]+]] + ; GP64-NOT-R6: dmultu $5, $7 + ; GP64-NOT-R6: mflo $3 + ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]] + ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] + + ; 64R6: dmul $[[T0:[0-9]+]], $5, $6 + ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7 + ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; 64R6: dmul $[[T3:[0-9]+]], $4, $7 + ; 64R6: daddu $2, $[[T2]], $[[T3]] + ; 64R6: dmul $3, $5, $7 + + %r = mul i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll new file mode 100644 index 000000000000..21d1d4fca2a3 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/or.ll @@ -0,0 +1,95 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 + +define signext i1 @or_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: or_i1: + + ; ALL: or $2, $4, $5 + + %r = or i1 %a, %b + ret i1 %r +} + +define signext i8 @or_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: or_i8: + + ; ALL: or $2, $4, $5 + + %r = or i8 %a, %b + ret i8 %r +} + +define signext i16 @or_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: or_i16: + + ; ALL: or $2, $4, $5 + + %r = or i16 %a, %b + ret i16 %r +} + +define signext i32 @or_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: or_i32: + + ; GP32: or $2, $4, $5 + + ; GP64: or $[[T0:[0-9]+]], $4, $5 + ; FIXME: The sll instruction below is redundant. + ; GP64: sll $2, $[[T0]], 0 + + %r = or i32 %a, %b + ret i32 %r +} + +define signext i64 @or_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: or_i64: + + ; GP32: or $2, $4, $6 + ; GP32: or $3, $5, $7 + + ; GP64: or $2, $4, $5 + + %r = or i64 %a, %b + ret i64 %r +} + +define signext i128 @or_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: or_i128: + + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: or $2, $4, $[[T2]] + ; GP32: or $3, $5, $[[T1]] + ; GP32: or $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: or $5, $7, $[[T3]] + + ; GP64: or $2, $4, $6 + ; GP64: or $3, $5, $7 + + %r = or i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll new file mode 100644 index 000000000000..54b7f70b1dac --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -0,0 +1,136 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=R6 -check-prefix=64R6 + +define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: sdiv_i1: + + ; NOT-R6: div $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $[[T0:[0-9]+]] + ; FIXME: The sll/sra instructions are redundant since div is signed. + ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; NOT-R6: sra $2, $[[T1]], 31 + + ; R6: div $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; FIXME: The sll/sra instructions are redundant since div is signed. + ; R6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; R6: sra $2, $[[T1]], 31 + + %r = sdiv i1 %a, %b + ret i1 %r +} + +define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: sdiv_i8: + + ; NOT-R2-R6: div $zero, $4, $5 + ; NOT-R2-R6: teq $5, $zero, 7 + ; NOT-R2-R6: mflo $[[T0:[0-9]+]] + ; FIXME: The sll/sra instructions are redundant since div is signed. + ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 + ; NOT-R2-R6: sra $2, $[[T1]], 24 + + ; R2: div $zero, $4, $5 + ; R2: teq $5, $zero, 7 + ; R2: mflo $[[T0:[0-9]+]] + ; FIXME: This instruction is redundant. + ; R2: seb $2, $[[T0]] + + ; R6: div $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; FIXME: This instruction is redundant. + ; R6: seb $2, $[[T0]] + + %r = sdiv i8 %a, %b + ret i8 %r +} + +define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: sdiv_i16: + + ; NOT-R2-R6: div $zero, $4, $5 + ; NOT-R2-R6: teq $5, $zero, 7 + ; NOT-R2-R6: mflo $[[T0:[0-9]+]] + ; FIXME: The sll/sra instructions are redundant since div is signed. + ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 + ; NOT-R2-R6: sra $2, $[[T1]], 16 + + ; R2: div $zero, $4, $5 + ; R2: teq $5, $zero, 7 + ; R2: mflo $[[T0:[0-9]+]] + ; FIXME: This is instruction is redundant since div is signed. + ; R2: seh $2, $[[T0]] + + ; R6: div $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; FIXME: This is instruction is redundant since div is signed. + ; R6: seh $2, $[[T0]] + + %r = sdiv i16 %a, %b + ret i16 %r +} + +define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: sdiv_i32: + + ; NOT-R6: div $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: div $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = sdiv i32 %a, %b + ret i32 %r +} + +define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: sdiv_i64: + + ; GP32: lw $25, %call16(__divdi3)($gp) + + ; GP64-NOT-R6: ddiv $zero, $4, $5 + ; GP64-NOT-R6: teq $5, $zero, 7 + ; GP64-NOT-R6: mflo $2 + + ; 64R6: ddiv $2, $4, $5 + ; 64R6: teq $5, $zero, 7 + + %r = sdiv i64 %a, %b + ret i64 %r +} + +define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { +entry: + ; ALL-LABEL: sdiv_i128: + + ; GP32: lw $25, %call16(__divti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) + ; 64R6: ld $25, %call16(__divti3)($gp) + + %r = sdiv i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll new file mode 100644 index 000000000000..fc5243cc97f2 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/shl.ll @@ -0,0 +1,188 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ +; RUN: -check-prefix=32R1-R2 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=64R6 -check-prefix=R2-R6 + +define signext i1 @shl_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: shl_i1: + + ; ALL: move $2, $4 + + %r = shl i1 %a, %b + ret i1 %r +} + +define signext i8 @shl_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: shl_i8: + + ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 + ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 24 + ; NOT-R2-R6: sra $2, $[[T2]], 24 + + ; R2-R6: andi $[[T0:[0-9]+]], $5, 255 + ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; R2-R6: seb $2, $[[T1]] + + %r = shl i8 %a, %b + ret i8 %r +} + +define signext i16 @shl_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: shl_i16: + + ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 + ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 16 + ; NOT-R2-R6: sra $2, $[[T2]], 16 + + ; R2-R6: andi $[[T0:[0-9]+]], $5, 65535 + ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; R2-R6: seh $2, $[[T1]] + + %r = shl i16 %a, %b + ret i16 %r +} + +define signext i32 @shl_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: shl_i32: + + ; ALL: sllv $2, $4, $5 + + %r = shl i32 %a, %b + ret i32 %r +} + +define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: shl_i64: + + ; M2: sllv $[[T0:[0-9]+]], $5, $7 + ; M2: andi $[[T1:[0-9]+]], $7, 32 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: move $2, $[[T0]] + ; M2: sllv $[[T2:[0-9]+]], $4, $7 + ; M2: not $[[T3:[0-9]+]], $7 + ; M2: srl $[[T4:[0-9]+]], $5, 1 + ; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; M2: or $2, $[[T2]], $[[T3]] + ; M2: $[[BB0]]: + ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: addiu $3, $zero, 0 + ; M2: move $3, $[[T0]] + ; M2: $[[BB1]]: + ; M2: jr $ra + ; M2: nop + + ; 32R1-R2: sllv $[[T0:[0-9]+]], $4, $7 + ; 32R1-R2: not $[[T1:[0-9]+]], $7 + ; 32R1-R2: srl $[[T2:[0-9]+]], $5, 1 + ; 32R1-R2: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R1-R2: or $2, $[[T0]], $[[T3]] + ; 32R1-R2: sllv $[[T4:[0-9]+]], $5, $7 + ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32 + ; 32R1-R2: movn $2, $[[T4]], $[[T5]] + ; 32R1-R2: jr $ra + ; 32R1-R2: movn $3, $zero, $[[T5]] + + ; 32R6: sllv $[[T0:[0-9]+]], $4, $7 + ; 32R6: not $[[T1:[0-9]+]], $7 + ; 32R6: srl $[[T2:[0-9]+]], $5, 1 + ; 32R6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R6: or $[[T4:[0-9]+]], $[[T0]], $[[T3]] + ; 32R6: andi $[[T5:[0-9]+]], $7, 32 + ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T2]] + ; 32R6: sllv $[[T7:[0-9]+]], $5, $7 + ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; 32R6: or $2, $[[T8]], $[[T6]] + ; 32R6: jr $ra + ; 32R6: seleqz $3, $[[T7]], $[[T5]] + + ; GP64: sll $[[T0:[0-9]+]], $5, 0 + ; GP64: dsllv $2, $4, $1 + + %r = shl i64 %a, %b + ret i64 %r +} + +define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: shl_i128: + + ; GP32: lw $25, %call16(__ashlti3)($gp) + + ; M3: sll $[[T0:[0-9]+]], $7, 0 + ; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]] + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 + ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: move $2, $[[T1]] + ; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]] + ; M3: dsrl $[[T5:[0-9]+]], $5, 1 + ; M3: not $[[T6:[0-9]+]], $[[T0]] + ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; M3: or $2, $[[T4]], $[[T7]] + ; M3: $[[BB0]]: + ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: daddiu $3, $zero, 0 + ; M3: move $3, $[[T1]] + ; M3: $[[BB1]]: + ; M3: jr $ra + ; M3: nop + + ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 + ; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] + ; GP64-NOT-R6: dsrl $[[T2:[0-9]+]], $5, 1 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] + ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP64-NOT-R6: or $2, $[[T1]], $[[T4]] + ; GP64-NOT-R6: dsllv $3, $5, $[[T0]] + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64 + ; GP64-NOT-R6: movn $2, $3, $[[T5]] + ; GP64-NOT-R6: jr $ra + ; GP64-NOT-R6: movn $3, $zero, $1 + + ; 64R6: sll $[[T0:[0-9]+]], $7, 0 + ; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] + ; 64R6: dsrl $[[T2:[0-9]+]], $5, 1 + ; 64R6: not $[[T3:[0-9]+]], $[[T0]] + ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]] + ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 64 + ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 + ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] + ; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]] + ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] + ; 64R6: or $2, $[[T10]], $[[T8]] + ; 64R6: jr $ra + ; 64R6: seleqz $3, $[[T0]], $[[T7]] + + %r = shl i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll new file mode 100644 index 000000000000..1e949d24678b --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/srem.ll @@ -0,0 +1,129 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ +; RUN: -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=R2 -check-prefix=R2-R6 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 + +define signext i1 @srem_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: srem_i1: + + ; NOT-R6: div $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mfhi $[[T0:[0-9]+]] + ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; NOT-R6: sra $2, $[[T1]], 31 + + ; R6: mod $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; R6: sll $[[T3:[0-9]+]], $[[T0]], 31 + ; R6: sra $2, $[[T3]], 31 + + %r = srem i1 %a, %b + ret i1 %r +} + +define signext i8 @srem_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: srem_i8: + + ; NOT-R2-R6: div $zero, $4, $5 + ; NOT-R2-R6: teq $5, $zero, 7 + ; NOT-R2-R6: mfhi $[[T0:[0-9]+]] + ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 + ; NOT-R2-R6: sra $2, $[[T1]], 24 + + ; R2: div $zero, $4, $5 + ; R2: teq $5, $zero, 7 + ; R2: mfhi $[[T0:[0-9]+]] + ; R2: seb $2, $[[T0]] + + ; R6: mod $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; R6: seb $2, $[[T0]] + + %r = srem i8 %a, %b + ret i8 %r +} + +define signext i16 @srem_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: srem_i16: + + ; NOT-R2-R6: div $zero, $4, $5 + ; NOT-R2-R6: teq $5, $zero, 7 + ; NOT-R2-R6: mfhi $[[T0:[0-9]+]] + ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 + ; NOT-R2-R6: sra $2, $[[T1]], 16 + + ; R2: div $zero, $4, $5 + ; R2: teq $5, $zero, 7 + ; R2: mfhi $[[T0:[0-9]+]] + ; R2: seh $2, $[[T1]] + + ; R6: mod $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; R6: seh $2, $[[T0]] + + %r = srem i16 %a, %b + ret i16 %r +} + +define signext i32 @srem_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: srem_i32: + + ; NOT-R6: div $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mfhi $2 + + ; R6: mod $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = srem i32 %a, %b + ret i32 %r +} + +define signext i64 @srem_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: srem_i64: + + ; GP32: lw $25, %call16(__moddi3)($gp) + + ; GP64-NOT-R6: ddiv $zero, $4, $5 + ; GP64-NOT-R6: teq $5, $zero, 7 + ; GP64-NOT-R6: mfhi $2 + + ; 64R6: dmod $2, $4, $5 + ; 64R6: teq $5, $zero, 7 + + %r = srem i64 %a, %b + ret i64 %r +} + +define signext i128 @srem_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: srem_i128: + + ; GP32: lw $25, %call16(__modti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp) + ; 64-R6: ld $25, %call16(__modti3)($gp) + + %r = srem i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll new file mode 100644 index 000000000000..6d592be38211 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/sub.ll @@ -0,0 +1,114 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 + +define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: sub_i1: + + ; ALL: subu $[[T0:[0-9]+]], $4, $5 + ; ALL: sll $[[T0]], $[[T0]], 31 + ; ALL: sra $2, $[[T0]], 31 + + %r = sub i1 %a, %b + ret i1 %r +} + +define signext i8 @sub_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: sub_i8: + + ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seb $2, $[[T0:[0-9]+]] + + %r = sub i8 %a, %b + ret i8 %r +} + +define signext i16 @sub_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: sub_i16: + + ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seh $2, $[[T0:[0-9]+]] + + %r = sub i16 %a, %b + ret i16 %r +} + +define signext i32 @sub_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: sub_i32: + + ; ALL: subu $2, $4, $5 + + %r = sub i32 %a, %b + ret i32 %r +} + +define signext i64 @sub_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: sub_i64: + + ; GP32: subu $3, $5, $7 + ; GP32: sltu $[[T0:[0-9]+]], $5, $7 + ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP32: subu $2, $4, $[[T1]] + + ; GP64: dsubu $2, $4, $5 + + %r = sub i64 %a, %b + ret i64 %r +} + +define signext i128 @sub_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: sub_i128: + + ; GP32: lw $[[T0:[0-9]+]], 20($sp) + ; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]] + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; GP32: lw $[[T4:[0-9]+]], 24($sp) + ; GP32: lw $[[T5:[0-9]+]], 28($sp) + ; GP32: subu $[[T6:[0-9]+]], $7, $[[T5]] + ; GP32: subu $2, $4, $[[T3]] + ; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]] + ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]] + ; GP32: subu $3, $5, $[[T9]] + ; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]] + ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]] + ; GP32: subu $4, $6, $[[T11]] + ; GP32: move $5, $[[T6]] + + ; GP64: dsubu $3, $5, $7 + ; GP64: sltu $[[T0:[0-9]+]], $5, $7 + ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP64: dsubu $2, $4, $[[T1]] + + %r = sub i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll new file mode 100644 index 000000000000..1f7aa0d5f4ce --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/udiv.ll @@ -0,0 +1,108 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=R6 -check-prefix=64R6 + +define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) { +entry: +; ALL-LABEL: udiv_i1: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i1 %a, %b + ret i1 %r +} + +define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) { +entry: +; ALL-LABEL: udiv_i8: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i8 %a, %b + ret i8 %r +} + +define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) { +entry: +; ALL-LABEL: udiv_i16: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i16 %a, %b + ret i16 %r +} + +define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: udiv_i32: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i32 %a, %b + ret i32 %r +} + +define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: udiv_i64: + + ; GP32: lw $25, %call16(__udivdi3)($gp) + + ; GP64-NOT-R6: ddivu $zero, $4, $5 + ; GP64-NOT-R6: teq $5, $zero, 7 + ; GP64-NOT-R6: mflo $2 + + ; 64R6: ddivu $2, $4, $5 + ; 64R6: teq $5, $zero, 7 + + %r = udiv i64 %a, %b + ret i64 %r +} + +define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: udiv_i128: + + ; GP32: lw $25, %call16(__udivti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) + ; 64-R6: ld $25, %call16(__udivti3)($gp) + + %r = udiv i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll new file mode 100644 index 000000000000..73235341a42f --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/urem.ll @@ -0,0 +1,145 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ +; RUN: -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=R2 -check-prefix=R2-R6 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 + +define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: urem_i1: + + ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1 + ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1 + ; NOT-R6: divu $zero, $[[T1]], $[[T0]] + ; NOT-R6: teq $[[T0]], $zero, 7 + ; NOT-R6: mfhi $[[T2:[0-9]+]] + ; NOT-R6: sll $[[T3:[0-9]+]], $[[T2]], 31 + ; NOT-R6: sra $2, $[[T3]], 31 + + ; R6: andi $[[T0:[0-9]+]], $5, 1 + ; R6: andi $[[T1:[0-9]+]], $4, 1 + ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; R6: teq $[[T0]], $zero, 7 + ; R6: sll $[[T3:[0-9]+]], $[[T2]], 31 + ; R6: sra $2, $[[T3]], 31 + + %r = urem i1 %a, %b + ret i1 %r +} + +define signext i8 @urem_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: urem_i8: + + ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 + ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255 + ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] + ; NOT-R2-R6: teq $[[T0]], $zero, 7 + ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] + ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 24 + ; NOT-R2-R6: sra $2, $[[T3]], 24 + + ; R2: andi $[[T0:[0-9]+]], $5, 255 + ; R2: andi $[[T1:[0-9]+]], $4, 255 + ; R2: divu $zero, $[[T1]], $[[T0]] + ; R2: teq $[[T0]], $zero, 7 + ; R2: mfhi $[[T2:[0-9]+]] + ; R2: seb $2, $[[T2]] + + ; R6: andi $[[T0:[0-9]+]], $5, 255 + ; R6: andi $[[T1:[0-9]+]], $4, 255 + ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; R6: teq $[[T0]], $zero, 7 + ; R6: seb $2, $[[T2]] + + %r = urem i8 %a, %b + ret i8 %r +} + +define signext i16 @urem_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: urem_i16: + + ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 + ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 65535 + ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] + ; NOT-R2-R6: teq $[[T0]], $zero, 7 + ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] + ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 16 + ; NOT-R2-R6: sra $2, $[[T3]], 16 + + ; R2: andi $[[T0:[0-9]+]], $5, 65535 + ; R2: andi $[[T1:[0-9]+]], $4, 65535 + ; R2: divu $zero, $[[T1]], $[[T0]] + ; R2: teq $[[T0]], $zero, 7 + ; R2: mfhi $[[T3:[0-9]+]] + ; R2: seh $2, $[[T2]] + + ; R6: andi $[[T0:[0-9]+]], $5, 65535 + ; R6: andi $[[T1:[0-9]+]], $4, 65535 + ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; R6: teq $[[T0]], $zero, 7 + ; R6: seh $2, $[[T2]] + + %r = urem i16 %a, %b + ret i16 %r +} + +define signext i32 @urem_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: urem_i32: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mfhi $2 + + ; R6: modu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = urem i32 %a, %b + ret i32 %r +} + +define signext i64 @urem_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: urem_i64: + + ; GP32: lw $25, %call16(__umoddi3)($gp) + + ; GP64-NOT-R6: ddivu $zero, $4, $5 + ; GP64-NOT-R6: teq $5, $zero, 7 + ; GP64-NOT-R6: mfhi $2 + + ; 64R6: dmodu $2, $4, $5 + ; 64R6: teq $5, $zero, 7 + + %r = urem i64 %a, %b + ret i64 %r +} + +define signext i128 @urem_i128(i128 signext %a, i128 signext %b) { +entry: + ; ALL-LABEL: urem_i128: + + ; GP32: lw $25, %call16(__umodti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) + ; 64-R6: ld $25, %call16(__umodti3)($gp) + + %r = urem i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll new file mode 100644 index 000000000000..94dead1eff41 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/xor.ll @@ -0,0 +1,94 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 + +define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: xor_i1: + + ; ALL: xor $2, $4, $5 + + %r = xor i1 %a, %b + ret i1 %r +} + +define signext i8 @xor_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: xor_i8: + + ; ALL: xor $2, $4, $5 + + %r = xor i8 %a, %b + ret i8 %r +} + +define signext i16 @xor_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: xor_i16: + + ; ALL: xor $2, $4, $5 + + %r = xor i16 %a, %b + ret i16 %r +} + +define signext i32 @xor_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: xor_i32: + + ; GP32: xor $2, $4, $5 + + ; GP64: xor $[[T0:[0-9]+]], $4, $5 + ; GP64: sll $2, $[[T0]], 0 + + %r = xor i32 %a, %b + ret i32 %r +} + +define signext i64 @xor_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: xor_i64: + + ; GP32: xor $2, $4, $6 + ; GP32: xor $3, $5, $7 + + ; GP64: xor $2, $4, $5 + + %r = xor i64 %a, %b + ret i64 %r +} + +define signext i128 @xor_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: xor_i128: + + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: xor $2, $4, $[[T2]] + ; GP32: xor $3, $5, $[[T1]] + ; GP32: xor $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: xor $5, $7, $[[T3]] + + ; GP64: xor $2, $4, $6 + ; GP64: xor $3, $5, $7 + + %r = xor i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll index 6987d4ab0734..f0cbbd08d79a 100644 --- a/test/CodeGen/Mips/mips64-f128.ll +++ b/test/CodeGen/Mips/mips64-f128.ll @@ -545,7 +545,7 @@ entry: ; ALL-LABEL: load_LD_float: ; ALL: ld $[[R0:[0-9]+]], %got_disp(gf1) -; ALL: lwu $4, 0($[[R0]]) +; ALL: lw $4, 0($[[R0]]) ; ALL: ld $25, %call16(__extendsftf2) ; ALL: jalr $25 diff --git a/test/CodeGen/Mips/mips64signextendsesf.ll b/test/CodeGen/Mips/mips64signextendsesf.ll new file mode 100644 index 000000000000..dec83b80afea --- /dev/null +++ b/test/CodeGen/Mips/mips64signextendsesf.ll @@ -0,0 +1,214 @@ +; RUN: llc -march=mips64 -mcpu=mips64r2 -soft-float -O2 < %s | FileCheck %s + +define void @foosf() #0 { +entry: + %in = alloca float, align 4 + %out = alloca float, align 4 + store volatile float 0xBFD59E1380000000, float* %in, align 4 + %in.0.in.0. = load volatile float* %in, align 4 + %rintf = tail call float @rintf(float %in.0.in.0.) #1 + store volatile float %rintf, float* %out, align 4 + ret void + +; CHECK-LABEL: foosf +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare float @rintf(float) + +define float @foosf1(float* nocapture readonly %a) #0 { +entry: + %0 = load float* %a, align 4 + %call = tail call float @roundf(float %0) #2 + ret float %call + +; CHECK-LABEL: foosf1 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare float @roundf(float) #1 + +define float @foosf2(float* nocapture readonly %a) #0 { +entry: + %0 = load float* %a, align 4 + %call = tail call float @truncf(float %0) #2 + ret float %call + +; CHECK-LABEL: foosf2 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare float @truncf(float) #1 + +define float @foosf3(float* nocapture readonly %a) #0 { +entry: + %0 = load float* %a, align 4 + %call = tail call float @floorf(float %0) #2 + ret float %call + +; CHECK-LABEL: foosf3 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare float @floorf(float) #1 + +define float @foosf4(float* nocapture readonly %a) #0 { +entry: + %0 = load float* %a, align 4 + %call = tail call float @nearbyintf(float %0) #2 + ret float %call + +; CHECK-LABEL: foosf4 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare float @nearbyintf(float) #1 + +define float @foosf5(float* nocapture readonly %a) #0 { +entry: + %0 = load float* %a, align 4 + %mul = fmul float %0, undef + ret float %mul + +; CHECK-LABEL: foosf5 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +define float @foosf6(float* nocapture readonly %a) #0 { +entry: + %0 = load float* %a, align 4 + %sub = fsub float %0, undef + ret float %sub + +; CHECK-LABEL: foosf6 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +define float @foosf7(float* nocapture readonly %a) #0 { +entry: + %0 = load float* %a, align 4 + %add = fadd float %0, undef + ret float %add + +; CHECK-LABEL: foosf7 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +define float @foosf8(float* nocapture readonly %a) #0 { +entry: + %b = alloca float, align 4 + %b.0.b.0. = load volatile float* %b, align 4 + %0 = load float* %a, align 4 + %div = fdiv float %b.0.b.0., %0 + ret float %div + +; CHECK-LABEL: foosf8 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +define float @foosf9() #0 { +entry: + %b = alloca float, align 4 + %b.0.b.0. = load volatile float* %b, align 4 + %conv = fpext float %b.0.b.0. to double + %b.0.b.0.3 = load volatile float* %b, align 4 + %conv1 = fpext float %b.0.b.0.3 to double + %call = tail call double @pow(double %conv, double %conv1) #1 + %conv2 = fptrunc double %call to float + ret float %conv2 + +; CHECK-LABEL: foosf9 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare double @pow(double, double) #0 + +define float @foosf10() #0 { +entry: + %a = alloca float, align 4 + %a.0.a.0. = load volatile float* %a, align 4 + %conv = fpext float %a.0.a.0. to double + %call = tail call double @sin(double %conv) #1 + %conv1 = fptrunc double %call to float + ret float %conv1 + +; CHECK-LABEL: foosf10 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare double @sin(double) #0 + +define float @foosf11() #0 { +entry: + %b = alloca float, align 4 + %b.0.b.0. = load volatile float* %b, align 4 + %call = tail call float @ceilf(float %b.0.b.0.) #2 + ret float %call + +; CHECK-LABEL: foosf11 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare float @ceilf(float) #1 + +define float @foosf12() #0 { +entry: + %b = alloca float, align 4 + %a = alloca float, align 4 + %b.0.b.0. = load volatile float* %b, align 4 + %a.0.a.0. = load volatile float* %a, align 4 + %call = tail call float @fmaxf(float %b.0.b.0., float %a.0.a.0.) #2 + ret float %call + +; CHECK-LABEL: foosf12 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare float @fmaxf(float, float) #1 + +define float @foosf13() #0 { +entry: + %b = alloca float, align 4 + %a = alloca float, align 4 + %b.0.b.0. = load volatile float* %b, align 4 + %a.0.a.0. = load volatile float* %a, align 4 + %call = tail call float @fminf(float %b.0.b.0., float %a.0.a.0.) #2 + ret float %call + +; CHECK-LABEL: foosf13 +; CHECK-NOT: dsll +; CHECK-NOT: dsrl +; CHECK-NOT: lwu +} + +declare float @fminf(float, float) #1 + + +attributes #0 = { nounwind "use-soft-float"="true" } +attributes #1 = { nounwind readnone "use-soft-float"="true" } diff --git a/test/CodeGen/Mips/mips64sinttofpsf.ll b/test/CodeGen/Mips/mips64sinttofpsf.ll new file mode 100644 index 000000000000..d3d46036f7da --- /dev/null +++ b/test/CodeGen/Mips/mips64sinttofpsf.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mips64 -mcpu=mips64r2 -soft-float -O0 < %s | FileCheck %s + + +define double @foo() #0 { +entry: + %x = alloca i32, align 4 + store volatile i32 -32, i32* %x, align 4 + %0 = load volatile i32* %x, align 4 + %conv = sitofp i32 %0 to double + ret double %conv + +; CHECK-NOT: dsll +; CHECK-NOT: dsrl + +} diff --git a/test/CodeGen/Mips/no-odd-spreg-msa.ll b/test/CodeGen/Mips/no-odd-spreg-msa.ll new file mode 100644 index 000000000000..30dd1ff82d73 --- /dev/null +++ b/test/CodeGen/Mips/no-odd-spreg-msa.ll @@ -0,0 +1,131 @@ +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG + +@v4f32 = global <4 x float> zeroinitializer + +define void @msa_insert_0(float %a) { +entry: + ; Force the float into an odd-numbered register using named registers and + ; load the vector. + %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a) + %0 = load volatile <4 x float>* @v4f32 + + ; Clobber all except $f12/$w12 and $f13 + ; + ; The intention is that if odd single precision registers are permitted, the + ; allocator will choose $f12/$w12 for the vector and $f13 for the float to + ; avoid the spill/reload. + ; + ; On the other hand, if odd single precision registers are not permitted, it + ; must copy $f13 to an even-numbered register before inserting into the + ; vector. + call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() + %1 = insertelement <4 x float> %0, float %b, i32 0 + store <4 x float> %1, <4 x float>* @v4f32 + ret void +} + +; ALL-LABEL: msa_insert_0: +; ALL: mov.s $f13, $f12 +; ALL: lw $[[R0:[0-9]+]], %got(v4f32)( +; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]]) +; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13 +; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0] +; ODDSPREG: insve.w $w[[W0]][0], $w13[0] +; ALL: # Clobber +; ALL-NOT: sdc1 +; ALL-NOT: ldc1 +; ALL: st.w $w[[W0]], 0($[[R0]]) + +define void @msa_insert_1(float %a) { +entry: + ; Force the float into an odd-numbered register using named registers and + ; load the vector. + %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a) + %0 = load volatile <4 x float>* @v4f32 + + ; Clobber all except $f12/$w12 and $f13 + ; + ; The intention is that if odd single precision registers are permitted, the + ; allocator will choose $f12/$w12 for the vector and $f13 for the float to + ; avoid the spill/reload. + ; + ; On the other hand, if odd single precision registers are not permitted, it + ; must copy $f13 to an even-numbered register before inserting into the + ; vector. + call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() + %1 = insertelement <4 x float> %0, float %b, i32 1 + store <4 x float> %1, <4 x float>* @v4f32 + ret void +} + +; ALL-LABEL: msa_insert_1: +; ALL: mov.s $f13, $f12 +; ALL: lw $[[R0:[0-9]+]], %got(v4f32)( +; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]]) +; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13 +; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0] +; ODDSPREG: insve.w $w[[W0]][1], $w13[0] +; ALL: # Clobber +; ALL-NOT: sdc1 +; ALL-NOT: ldc1 +; ALL: st.w $w[[W0]], 0($[[R0]]) + +define float @msa_extract_0() { +entry: + %0 = load volatile <4 x float>* @v4f32 + %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0) + + ; Clobber all except $f12, and $f13 + ; + ; The intention is that if odd single precision registers are permitted, the + ; allocator will choose $f13/$w13 for the vector since that saves on moves. + ; + ; On the other hand, if odd single precision registers are not permitted, it + ; must move it to $f12/$w12. + call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() + + %2 = extractelement <4 x float> %1, i32 0 + ret float %2 +} + +; ALL-LABEL: msa_extract_0: +; ALL: lw $[[R0:[0-9]+]], %got(v4f32)( +; ALL: ld.w $w12, 0($[[R0]]) +; ALL: move.v $w[[W0:13]], $w12 +; NOODDSPREG: move.v $w[[W0:12]], $w13 +; ALL: # Clobber +; ALL-NOT: st.w +; ALL-NOT: ld.w +; ALL: mov.s $f0, $f[[W0]] + +define float @msa_extract_1() { +entry: + %0 = load volatile <4 x float>* @v4f32 + %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0) + + ; Clobber all except $f13 + ; + ; The intention is that if odd single precision registers are permitted, the + ; allocator will choose $f13/$w13 for the vector since that saves on moves. + ; + ; On the other hand, if odd single precision registers are not permitted, it + ; must be spilled. + call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() + + %2 = extractelement <4 x float> %1, i32 1 + ret float %2 +} + +; ALL-LABEL: msa_extract_1: +; ALL: lw $[[R0:[0-9]+]], %got(v4f32)( +; ALL: ld.w $w12, 0($[[R0]]) +; ALL: splati.w $w[[W0:[0-9]+]], $w13[1] +; NOODDSPREG: st.w $w[[W0]], 0($sp) +; ODDSPREG-NOT: st.w +; ODDSPREG-NOT: ld.w +; ALL: # Clobber +; ODDSPREG-NOT: st.w +; ODDSPREG-NOT: ld.w +; NOODDSPREG: ld.w $w0, 0($sp) +; ODDSPREG: mov.s $f0, $f[[W0]] |