diff options
Diffstat (limited to 'test/CodeGen/PowerPC')
82 files changed, 6254 insertions, 440 deletions
diff --git a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll index fde330321aa4..d20e3b05c091 100644 --- a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll +++ b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s +; REQUIRES: default_triple define void @iterative_hash_host_wide_int() { %zero = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll index c63fd9ae1700..3d5fa52d0abd 100644 --- a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll +++ b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s +; REQUIRES: default_triple %struct..0anon = type { i32 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] } diff --git a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll index 0e7709857406..c064c273173f 100644 --- a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll +++ b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=ppc64 ; RUN: llc < %s -march=ppc32 ; RUN: llc < %s +; REQUIRES: default_triple define void @bitap() { entry: diff --git a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll index 9660d450cb4c..8536dda0a9ba 100644 --- a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll +++ b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=ppc64 ; RUN: llc < %s -march=ppc32 ; RUN: llc < %s +; REQUIRES: default_triple @qsz.b = external global i1 ; <i1*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll index 4830ca60f9ff..aa39dfd03748 100644 --- a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll +++ b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -march=ppc32 -mcpu=g3 ; RUN: llc < %s -march=ppc32 -mcpu=g5 ; PR1811 +; REQUIRES: default_triple define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) { diff --git a/test/CodeGen/PowerPC/BoolRetToIntTest.ll b/test/CodeGen/PowerPC/BoolRetToIntTest.ll new file mode 100644 index 000000000000..a7b79789b4ca --- /dev/null +++ b/test/CodeGen/PowerPC/BoolRetToIntTest.ll @@ -0,0 +1,203 @@ +; RUN: opt -bool-ret-to-int -S -o - < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; CHECK-LABEL: notBoolRet +define signext i32 @notBoolRet() { +entry: +; CHECK: ret i32 1 + ret i32 1 +} + +; CHECK-LABEL: find +define zeroext i1 @find(i8** readonly %begin, i8** readnone %end, i1 (i8*)* nocapture %hasProp) { +entry: + %cmp.4 = icmp eq i8** %begin, %end + br i1 %cmp.4, label %cleanup, label %for.body.preheader + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond: ; preds = %for.body + %cmp = icmp eq i8** %incdec.ptr, %end + br i1 %cmp, label %cleanup.loopexit, label %for.body + +for.body: ; preds = %for.body.preheader, %for.cond + %curr.05 = phi i8** [ %incdec.ptr, %for.cond ], [ %begin, %for.body.preheader ] + %0 = load i8*, i8** %curr.05, align 8 + %call = tail call zeroext i1 %hasProp(i8* %0) + %incdec.ptr = getelementptr inbounds i8*, i8** %curr.05, i64 1 + br i1 %call, label %cleanup.loopexit, label %for.cond + +cleanup.loopexit: ; preds = %for.body, %for.cond +; CHECK: [[PHI:%.+]] = phi i32 [ 1, %for.body ], [ 0, %for.cond ] + %cleanup.dest.slot.0.ph = phi i1 [ true, %for.body ], [ false, %for.cond ] + br label %cleanup + +cleanup: ; preds = %cleanup.loopexit, %entry +; CHECK: = phi i32 [ 0, %entry ], [ [[PHI]], %cleanup.loopexit ] + %cleanup.dest.slot.0 = phi i1 [ false, %entry ], [ %cleanup.dest.slot.0.ph, %cleanup.loopexit ] +; CHECK: [[REG:%.+]] = trunc i32 {{%.+}} to i1 +; CHECK: ret i1 [[REG]] + ret i1 %cleanup.dest.slot.0 +} + +; CHECK-LABEL: retFalse +define zeroext i1 @retFalse() { +entry: +; CHECK: ret i1 false + ret i1 false +} + +; CHECK-LABEL: retCvtFalse +define zeroext i1 @retCvtFalse() { +entry: +; CHECK: ret i1 false + ret i1 trunc(i32 0 to i1) +} + +; CHECK-LABEL: find_cont +define void @find_cont(i8** readonly %begin, i8** readnone %end, i1 (i8*)* nocapture %hasProp, void (i1)* nocapture %cont) { +entry: + %cmp.4 = icmp eq i8** %begin, %end + br i1 %cmp.4, label %cleanup, label %for.body.preheader + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond: ; preds = %for.body + %cmp = icmp eq i8** %incdec.ptr, %end + br i1 %cmp, label %cleanup.loopexit, label %for.body + +for.body: ; preds = %for.body.preheader, %for.cond + %curr.05 = phi i8** [ %incdec.ptr, %for.cond ], [ %begin, %for.body.preheader ] + %0 = load i8*, i8** %curr.05, align 8 + %call = tail call zeroext i1 %hasProp(i8* %0) + %incdec.ptr = getelementptr inbounds i8*, i8** %curr.05, i64 1 + br i1 %call, label %cleanup.loopexit, label %for.cond + +cleanup.loopexit: ; preds = %for.body, %for.cond +; CHECK: [[PHI:%.+]] = phi i32 [ 1, %for.body ], [ 0, %for.cond ] + %cleanup.dest.slot.0.ph = phi i1 [ true, %for.body ], [ false, %for.cond ] + br label %cleanup + +cleanup: ; preds = %cleanup.loopexit, %entry +; CHECK: = phi i32 [ 0, %entry ], [ [[PHI]], %cleanup.loopexit ] + %cleanup.dest.slot.0 = phi i1 [ false, %entry ], [ %cleanup.dest.slot.0.ph, %cleanup.loopexit ] +; CHECK: [[REG:%.+]] = trunc i32 {{%.+}} to i1 +; CHECK: call void %cont(i1 [[REG]] + tail call void %cont(i1 %cleanup.dest.slot.0) + ret void +} + +; CHECK-LABEL: find_cont_ret +define zeroext i1 @find_cont_ret(i8** readonly %begin, i8** readnone %end, i1 (i8*)* nocapture %hasProp, void (i1)* nocapture %cont) { +entry: + %cmp.4 = icmp eq i8** %begin, %end + br i1 %cmp.4, label %cleanup, label %for.body.preheader + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond: ; preds = %for.body + %cmp = icmp eq i8** %incdec.ptr, %end + br i1 %cmp, label %cleanup.loopexit, label %for.body + +for.body: ; preds = %for.body.preheader, %for.cond + %curr.05 = phi i8** [ %incdec.ptr, %for.cond ], [ %begin, %for.body.preheader ] + %0 = load i8*, i8** %curr.05, align 8 + %call = tail call zeroext i1 %hasProp(i8* %0) + %incdec.ptr = getelementptr inbounds i8*, i8** %curr.05, i64 1 + br i1 %call, label %cleanup.loopexit, label %for.cond + +cleanup.loopexit: ; preds = %for.body, %for.cond +; CHECK: [[PHI:%.+]] = phi i32 [ 1, %for.body ], [ 0, %for.cond ] + %cleanup.dest.slot.0.ph = phi i1 [ true, %for.body ], [ false, %for.cond ] + br label %cleanup + +cleanup: ; preds = %cleanup.loopexit, %entry +; CHECK: = phi i32 [ 0, %entry ], [ [[PHI]], %cleanup.loopexit ] + %cleanup.dest.slot.0 = phi i1 [ false, %entry ], [ %cleanup.dest.slot.0.ph, %cleanup.loopexit ] +; CHECK: [[REG:%.+]] = trunc i32 {{%.+}} to i1 +; CHECK: call void %cont(i1 [[REG]] + tail call void %cont(i1 %cleanup.dest.slot.0) +; CHECK: [[REG:%.+]] = trunc i32 {{%.+}} to i1 +; CHECK: ret i1 [[REG]] + ret i1 %cleanup.dest.slot.0 +} + +; CHECK-LABEL: arg_operand +define zeroext i1 @arg_operand(i1 %operand) { +entry: + br i1 %operand, label %foo, label %cleanup + +foo: + br label %cleanup + +cleanup: +; CHECK: [[REG:%.+]] = trunc i32 {{%.+}} to i1 +; CHECK: ret i1 [[REG]] + %result = phi i1 [ false, %foo ], [ %operand, %entry ] + ret i1 %result +} + +; CHECK-LABEL: bad_use +define zeroext i1 @bad_use(i1 %operand) { +entry: + br i1 %operand, label %foo, label %cleanup + +foo: + br label %cleanup + +cleanup: +; CHECK: [[REG:%.+]] = phi i1 +; CHECK: ret i1 [[REG]] + %result = phi i1 [ false, %foo], [ true, %entry ] + %0 = icmp eq i1 %result, %operand + ret i1 %result +} + +; CHECK-LABEL: bad_use_closure +define zeroext i1 @bad_use_closure(i1 %operand) { +entry: + br i1 %operand, label %foo, label %cleanup + +foo: + %bar = phi i1 [ false, %entry ] + %0 = icmp eq i1 %bar, %operand + br label %cleanup + +cleanup: +; CHECK: [[REG:%.+]] = phi i1 [ true +; CHECK: ret i1 [[REG]] + %result = phi i1 [ true, %entry ], [ %bar, %foo] + ret i1 %result +} + +; CHECK-LABEL: arg_test +define zeroext i1 @arg_test(i1 %operand) { +entry: + br i1 %operand, label %foo, label %cleanup + +foo: + %bar = phi i1 [ false, %entry ] + br label %cleanup + +; CHECK-LABEL: cleanup +cleanup: +; CHECK: [[REG:%.+]] = trunc i32 {{%.+}} to i1 +; CHECK: ret i1 [[REG]] + %result = phi i1 [ %bar, %foo], [ %operand, %entry ] + ret i1 %result +} + +declare zeroext i1 @return_i1() + +; CHECK-LABEL: call_test +define zeroext i1 @call_test() { +; CHECK: [[REG:%.+]] = call i1 + %result = call i1 @return_i1() +; CHECK: ret i1 [[REG]] + ret i1 %result +}
\ No newline at end of file diff --git a/test/CodeGen/PowerPC/BreakableToken-reduced.ll b/test/CodeGen/PowerPC/BreakableToken-reduced.ll new file mode 100644 index 000000000000..2077dbb820f7 --- /dev/null +++ b/test/CodeGen/PowerPC/BreakableToken-reduced.ll @@ -0,0 +1,335 @@ +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-shrink-wrap=true %s -o - | FileCheck %s --check-prefix=CHECK +; +; Test the use of a non-R0 register to save/restore the LR in function +; prologue/epilogue. +; This problem can occur as a result of shrink wrapping, where the function +; prologue and epilogue are moved from the beginning/ending of the function. If +; register R0 is used before the prologue/epilogue blocks, then it cannot be +; used to save/restore the LR. +; +; TODO: Convert this to an MIR test once the infrastructure can support it. +; To convert this to an MIR pass, generate MIR after register allocation +; but before shrink wrapping and verify that has been used in the body of +; the function. This can be done with something like: +; llc -stop-after stack-slot-coloring BreakableToken-reduced.ll > BreakableToken-reduced.mir +; +; The resulting MIR file can then be used as input to llc, and only run +; shrink wrapping and Prologue/Epilogue insertion on it. For example: +; llc -start-after stack-slot-coloring -stop-after prologepilog BreakableToken-reduced.mir +; +; Verify in the resulting code that R0 is not used in the prologue/epilogue. +; +; This currently cannot be done because the PrologEpilogInserter pass has +; a dependency on the TargetPassConfig and StackProtector classes, which +; are currently not serialized when generating the MIR. +; + +; ModuleID = 'BreakableToken.cpp' +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +%"class.clang::format::BreakableStringLiteral" = type { %"class.clang::format::BreakableSingleLineToken" } +%"class.clang::format::BreakableSingleLineToken" = type { %"class.clang::format::BreakableToken", i32, %"class.llvm::StringRef", %"class.llvm::StringRef", %"class.llvm::StringRef" } +%"class.clang::format::BreakableToken" = type { i32 (...)**, %"struct.clang::format::FormatToken"*, i32, i8, i32, %"struct.clang::format::FormatStyle"* } +%"class.llvm::StringRef" = type { i8*, i64 } +%"struct.clang::format::FormatToken" = type <{ %"class.clang::Token", i32, i8, [3 x i8], %"class.clang::SourceRange", i32, i32, i32, i8, i8, i8, i8, %"class.llvm::StringRef", i8, [3 x i8], i32, i32, i32, i8, i8, [2 x i8], i32, i32, i16, [2 x i8], %"class.std::unique_ptr", i32, i32, i32, i32, i32, i32, i32, i32, %"class.llvm::SmallVector", i32, i8, i8, [2 x i8], i32, i8, i8, [2 x i8], %"struct.clang::format::FormatToken"*, %"struct.clang::format::FormatToken"*, %"struct.clang::format::FormatToken"*, %"class.llvm::SmallVector.6", i32, i8, [3 x i8] }> +%"class.clang::Token" = type <{ i32, i32, i8*, i16, i16, [4 x i8] }> +%"class.clang::SourceRange" = type { %"class.clang::SourceLocation", %"class.clang::SourceLocation" } +%"class.clang::SourceLocation" = type { i32 } +%"class.std::unique_ptr" = type { %"class.std::tuple" } +%"class.std::tuple" = type { %"struct.std::_Tuple_impl" } +%"struct.std::_Tuple_impl" = type { %"struct.std::_Head_base.2" } +%"struct.std::_Head_base.2" = type { %"class.clang::format::TokenRole"* } +%"class.clang::format::TokenRole" = type { i32 (...)**, %"struct.clang::format::FormatStyle"* } +%"class.llvm::SmallVector" = type { %"class.llvm::SmallVectorImpl.base", %"struct.llvm::SmallVectorStorage" } +%"class.llvm::SmallVectorImpl.base" = type { %"class.llvm::SmallVectorTemplateBase.base" } +%"class.llvm::SmallVectorTemplateBase.base" = type { %"class.llvm::SmallVectorTemplateCommon.base" } +%"class.llvm::SmallVectorTemplateCommon.base" = type <{ %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion" }> +%"class.llvm::SmallVectorBase" = type { i8*, i8*, i8* } +%"struct.llvm::AlignedCharArrayUnion" = type { %"struct.llvm::AlignedCharArray" } +%"struct.llvm::AlignedCharArray" = type { [4 x i8] } +%"struct.llvm::SmallVectorStorage" = type { [3 x %"struct.llvm::AlignedCharArrayUnion"] } +%"class.llvm::SmallVector.6" = type <{ %"class.llvm::SmallVectorImpl.7", %"struct.llvm::SmallVectorStorage.12", [7 x i8] }> +%"class.llvm::SmallVectorImpl.7" = type { %"class.llvm::SmallVectorTemplateBase.8" } +%"class.llvm::SmallVectorTemplateBase.8" = type { %"class.llvm::SmallVectorTemplateCommon.9" } +%"class.llvm::SmallVectorTemplateCommon.9" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.10" } +%"struct.llvm::AlignedCharArrayUnion.10" = type { %"struct.llvm::AlignedCharArray.11" } +%"struct.llvm::AlignedCharArray.11" = type { [8 x i8] } +%"struct.llvm::SmallVectorStorage.12" = type { i8 } +%"struct.clang::format::FormatStyle" = type { i32, i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, i8, i32, i8, i8, i8, i8, i32, i32, i8, i8, i32, %"class.std::basic_string", i8, i32, i32, i8, i8, i8, i8, %"class.std::vector", i8, i32, i8, i8, i32, %"class.std::basic_string", %"class.std::basic_string", i32, i32, i32, i8, i8, i32, i32, i32, i32, i32, i32, i32, i8, i8, i32, i8, i32, i8, i8, i8, i8, i8, i32, i32, i32 } +%"class.std::vector" = type { %"struct.std::_Vector_base" } +%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::basic_string<char>, std::allocator<std::basic_string<char> > >::_Vector_impl" } +%"struct.std::_Vector_base<std::basic_string<char>, std::allocator<std::basic_string<char> > >::_Vector_impl" = type { %"class.std::basic_string"*, %"class.std::basic_string"*, %"class.std::basic_string"* } +%"class.std::basic_string" = type { %"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider" } +%"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider" = type { i8* } +%"struct.llvm::AlignedCharArray.52" = type { [16 x i8] } +%"class.clang::format::WhitespaceManager" = type <{ %"class.llvm::SmallVector.13", %"class.clang::SourceManager"*, %"class.std::set", %"struct.clang::format::FormatStyle"*, i8, [7 x i8] }> +%"class.llvm::SmallVector.13" = type { %"class.llvm::SmallVectorImpl.14", %"struct.llvm::SmallVectorStorage.19" } +%"class.llvm::SmallVectorImpl.14" = type { %"class.llvm::SmallVectorTemplateBase.15" } +%"class.llvm::SmallVectorTemplateBase.15" = type { %"class.llvm::SmallVectorTemplateCommon.16" } +%"class.llvm::SmallVectorTemplateCommon.16" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.17" } +%"struct.llvm::AlignedCharArrayUnion.17" = type { %"struct.llvm::AlignedCharArray.18" } +%"struct.llvm::AlignedCharArray.18" = type { [88 x i8] } +%"struct.llvm::SmallVectorStorage.19" = type { [15 x %"struct.llvm::AlignedCharArrayUnion.17"] } +%"class.clang::SourceManager" = type { %"class.llvm::RefCountedBase", %"class.clang::DiagnosticsEngine"*, %"class.clang::FileManager"*, %"class.llvm::BumpPtrAllocatorImpl", %"class.llvm::DenseMap.65", i8, i8, %"class.std::unique_ptr.78", %"class.std::vector.94", %"class.llvm::SmallVector.99", %"class.llvm::SmallVector.99", i32, i32, %"class.std::vector.107", %"class.clang::ExternalSLocEntrySource"*, %"class.clang::FileID", %"class.clang::LineTableInfo"*, %"class.clang::FileID", %"class.clang::SrcMgr::ContentCache"*, i32, i32, %"class.clang::FileID", %"class.clang::FileID", i32, i32, %"class.llvm::DenseMap.111", %"class.llvm::DenseMap.115", %"class.clang::InBeforeInTUCacheEntry", %"class.std::unique_ptr.119", %"class.std::unique_ptr.127", %"class.llvm::DenseMap.135", %"class.llvm::SmallVector.139" } +%"class.llvm::RefCountedBase" = type { i32 } +%"class.clang::DiagnosticsEngine" = type opaque +%"class.clang::FileManager" = type { %"class.llvm::RefCountedBase.20", %"class.llvm::IntrusiveRefCntPtr", %"class.clang::FileSystemOptions", %"class.std::map", %"class.std::map.24", %"class.llvm::SmallVector.29", %"class.llvm::SmallVector.35", %"class.llvm::StringMap", %"class.llvm::StringMap.56", %"class.llvm::DenseMap", %"class.llvm::BumpPtrAllocatorImpl", i32, i32, i32, i32, i32, %"class.std::unique_ptr.57" } +%"class.llvm::RefCountedBase.20" = type { i32 } +%"class.llvm::IntrusiveRefCntPtr" = type { %"class.clang::vfs::FileSystem"* } +%"class.clang::vfs::FileSystem" = type <{ i32 (...)**, %"class.llvm::ThreadSafeRefCountedBase", [4 x i8] }> +%"class.llvm::ThreadSafeRefCountedBase" = type { %"struct.std::atomic" } +%"struct.std::atomic" = type { %"struct.std::__atomic_base" } +%"struct.std::__atomic_base" = type { i32 } +%"class.clang::FileSystemOptions" = type { %"class.std::basic_string" } +%"class.std::map" = type { %"class.std::_Rb_tree" } +%"class.std::_Rb_tree" = type { %"struct.std::_Rb_tree<llvm::sys::fs::UniqueID, std::pair<const llvm::sys::fs::UniqueID, clang::DirectoryEntry>, std::_Select1st<std::pair<const llvm::sys::fs::UniqueID, clang::DirectoryEntry> >, std::less<llvm::sys::fs::UniqueID>, std::allocator<std::pair<const llvm::sys::fs::UniqueID, clang::DirectoryEntry> > >::_Rb_tree_impl" } +%"struct.std::_Rb_tree<llvm::sys::fs::UniqueID, std::pair<const llvm::sys::fs::UniqueID, clang::DirectoryEntry>, std::_Select1st<std::pair<const llvm::sys::fs::UniqueID, clang::DirectoryEntry> >, std::less<llvm::sys::fs::UniqueID>, std::allocator<std::pair<const llvm::sys::fs::UniqueID, clang::DirectoryEntry> > >::_Rb_tree_impl" = type { %"struct.std::less", %"struct.std::_Rb_tree_node_base", i64 } +%"struct.std::less" = type { i8 } +%"struct.std::_Rb_tree_node_base" = type { i32, %"struct.std::_Rb_tree_node_base"*, %"struct.std::_Rb_tree_node_base"*, %"struct.std::_Rb_tree_node_base"* } +%"class.std::map.24" = type { %"class.std::_Rb_tree.25" } +%"class.std::_Rb_tree.25" = type { %"struct.std::_Rb_tree<llvm::sys::fs::UniqueID, std::pair<const llvm::sys::fs::UniqueID, clang::FileEntry>, std::_Select1st<std::pair<const llvm::sys::fs::UniqueID, clang::FileEntry> >, std::less<llvm::sys::fs::UniqueID>, std::allocator<std::pair<const llvm::sys::fs::UniqueID, clang::FileEntry> > >::_Rb_tree_impl" } +%"struct.std::_Rb_tree<llvm::sys::fs::UniqueID, std::pair<const llvm::sys::fs::UniqueID, clang::FileEntry>, std::_Select1st<std::pair<const llvm::sys::fs::UniqueID, clang::FileEntry> >, std::less<llvm::sys::fs::UniqueID>, std::allocator<std::pair<const llvm::sys::fs::UniqueID, clang::FileEntry> > >::_Rb_tree_impl" = type { %"struct.std::less", %"struct.std::_Rb_tree_node_base", i64 } +%"class.llvm::SmallVector.29" = type { %"class.llvm::SmallVectorImpl.30", %"struct.llvm::SmallVectorStorage.34" } +%"class.llvm::SmallVectorImpl.30" = type { %"class.llvm::SmallVectorTemplateBase.31" } +%"class.llvm::SmallVectorTemplateBase.31" = type { %"class.llvm::SmallVectorTemplateCommon.32" } +%"class.llvm::SmallVectorTemplateCommon.32" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.33" } +%"struct.llvm::AlignedCharArrayUnion.33" = type { %"struct.llvm::AlignedCharArray.11" } +%"struct.llvm::SmallVectorStorage.34" = type { [3 x %"struct.llvm::AlignedCharArrayUnion.33"] } +%"class.llvm::SmallVector.35" = type { %"class.llvm::SmallVectorImpl.36", %"struct.llvm::SmallVectorStorage.40" } +%"class.llvm::SmallVectorImpl.36" = type { %"class.llvm::SmallVectorTemplateBase.37" } +%"class.llvm::SmallVectorTemplateBase.37" = type { %"class.llvm::SmallVectorTemplateCommon.38" } +%"class.llvm::SmallVectorTemplateCommon.38" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.39" } +%"struct.llvm::AlignedCharArrayUnion.39" = type { %"struct.llvm::AlignedCharArray.11" } +%"struct.llvm::SmallVectorStorage.40" = type { [3 x %"struct.llvm::AlignedCharArrayUnion.39"] } +%"class.llvm::StringMap" = type { %"class.llvm::StringMapImpl", %"class.llvm::BumpPtrAllocatorImpl" } +%"class.llvm::StringMapImpl" = type { %"class.llvm::StringMapEntryBase"**, i32, i32, i32, i32 } +%"class.llvm::StringMapEntryBase" = type { i32 } +%"class.llvm::StringMap.56" = type { %"class.llvm::StringMapImpl", %"class.llvm::BumpPtrAllocatorImpl" } +%"class.llvm::DenseMap" = type <{ %"struct.llvm::detail::DenseMapPair"*, i32, i32, i32, [4 x i8] }> +%"struct.llvm::detail::DenseMapPair" = type opaque +%"class.std::unique_ptr.57" = type { %"class.std::tuple.58" } +%"class.std::tuple.58" = type { %"struct.std::_Tuple_impl.59" } +%"struct.std::_Tuple_impl.59" = type { %"struct.std::_Head_base.64" } +%"struct.std::_Head_base.64" = type { %"class.clang::FileSystemStatCache"* } +%"class.clang::FileSystemStatCache" = type opaque +%"class.llvm::BumpPtrAllocatorImpl" = type <{ i8*, i8*, %"class.llvm::SmallVector.41", %"class.llvm::SmallVector.47", i64, %"class.llvm::MallocAllocator", [7 x i8] }> +%"class.llvm::SmallVector.41" = type { %"class.llvm::SmallVectorImpl.42", %"struct.llvm::SmallVectorStorage.46" } +%"class.llvm::SmallVectorImpl.42" = type { %"class.llvm::SmallVectorTemplateBase.43" } +%"class.llvm::SmallVectorTemplateBase.43" = type { %"class.llvm::SmallVectorTemplateCommon.44" } +%"class.llvm::SmallVectorTemplateCommon.44" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.45" } +%"struct.llvm::AlignedCharArrayUnion.45" = type { %"struct.llvm::AlignedCharArray.11" } +%"struct.llvm::SmallVectorStorage.46" = type { [3 x %"struct.llvm::AlignedCharArrayUnion.45"] } +%"class.llvm::SmallVector.47" = type <{ %"class.llvm::SmallVectorImpl.48", %"struct.llvm::SmallVectorStorage.53", [7 x i8] }> +%"class.llvm::SmallVectorImpl.48" = type { %"class.llvm::SmallVectorTemplateBase.49" } +%"class.llvm::SmallVectorTemplateBase.49" = type { %"class.llvm::SmallVectorTemplateCommon.50" } +%"class.llvm::SmallVectorTemplateCommon.50" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.51" } +%"struct.llvm::AlignedCharArrayUnion.51" = type { %"struct.llvm::AlignedCharArray.52" } +%"struct.llvm::SmallVectorStorage.53" = type { i8 } +%"class.llvm::MallocAllocator" = type { i8 } +%"class.llvm::DenseMap.65" = type <{ %"struct.llvm::detail::DenseMapPair.67"*, i32, i32, i32, [4 x i8] }> +%"struct.llvm::detail::DenseMapPair.67" = type { %"struct.std::pair.68" } +%"struct.std::pair.68" = type { %"class.clang::FileEntry"*, %"class.clang::SrcMgr::ContentCache"* } +%"class.clang::FileEntry" = type { i8*, i64, i64, %"class.clang::DirectoryEntry"*, i32, %"class.llvm::sys::fs::UniqueID", i8, i8, i8, %"class.std::unique_ptr.69" } +%"class.clang::DirectoryEntry" = type { i8* } +%"class.llvm::sys::fs::UniqueID" = type { i64, i64 } +%"class.std::unique_ptr.69" = type { %"class.std::tuple.70" } +%"class.std::tuple.70" = type { %"struct.std::_Tuple_impl.71" } +%"struct.std::_Tuple_impl.71" = type { %"struct.std::_Head_base.76" } +%"struct.std::_Head_base.76" = type { %"class.clang::vfs::File"* } +%"class.clang::vfs::File" = type { i32 (...)** } +%"class.std::unique_ptr.78" = type { %"class.std::tuple.79" } +%"class.std::tuple.79" = type { %"struct.std::_Tuple_impl.80" } +%"struct.std::_Tuple_impl.80" = type { %"struct.std::_Head_base.85" } +%"struct.std::_Head_base.85" = type { %"struct.clang::SourceManager::OverriddenFilesInfoTy"* } +%"struct.clang::SourceManager::OverriddenFilesInfoTy" = type { %"class.llvm::DenseMap.86", %"class.llvm::DenseSet" } +%"class.llvm::DenseMap.86" = type <{ %"struct.llvm::detail::DenseMapPair.88"*, i32, i32, i32, [4 x i8] }> +%"struct.llvm::detail::DenseMapPair.88" = type { %"struct.std::pair.89" } +%"struct.std::pair.89" = type { %"class.clang::FileEntry"*, %"class.clang::FileEntry"* } +%"class.llvm::DenseSet" = type { %"class.llvm::DenseMap.91" } +%"class.llvm::DenseMap.91" = type <{ %"class.llvm::detail::DenseSetPair"*, i32, i32, i32, [4 x i8] }> +%"class.llvm::detail::DenseSetPair" = type { %"class.clang::FileEntry"* } +%"class.std::vector.94" = type { %"struct.std::_Vector_base.95" } +%"struct.std::_Vector_base.95" = type { %"struct.std::_Vector_base<clang::SrcMgr::ContentCache *, std::allocator<clang::SrcMgr::ContentCache *> >::_Vector_impl" } +%"struct.std::_Vector_base<clang::SrcMgr::ContentCache *, std::allocator<clang::SrcMgr::ContentCache *> >::_Vector_impl" = type { %"class.clang::SrcMgr::ContentCache"**, %"class.clang::SrcMgr::ContentCache"**, %"class.clang::SrcMgr::ContentCache"** } +%"class.llvm::SmallVector.99" = type <{ %"class.llvm::SmallVectorImpl.100", %"struct.llvm::SmallVectorStorage.105", [7 x i8] }> +%"class.llvm::SmallVectorImpl.100" = type { %"class.llvm::SmallVectorTemplateBase.101" } +%"class.llvm::SmallVectorTemplateBase.101" = type { %"class.llvm::SmallVectorTemplateCommon.102" } +%"class.llvm::SmallVectorTemplateCommon.102" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.103" } +%"struct.llvm::AlignedCharArrayUnion.103" = type { %"struct.llvm::AlignedCharArray.104" } +%"struct.llvm::AlignedCharArray.104" = type { [24 x i8] } +%"struct.llvm::SmallVectorStorage.105" = type { i8 } +%"class.std::vector.107" = type { %"struct.std::_Bvector_base" } +%"struct.std::_Bvector_base" = type { %"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl" } +%"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl" = type { %"struct.std::_Bit_iterator", %"struct.std::_Bit_iterator", i64* } +%"struct.std::_Bit_iterator" = type { %"struct.std::_Bit_iterator_base.base", [4 x i8] } +%"struct.std::_Bit_iterator_base.base" = type <{ i64*, i32 }> +%"class.clang::ExternalSLocEntrySource" = type { i32 (...)** } +%"class.clang::LineTableInfo" = type opaque +%"class.clang::SrcMgr::ContentCache" = type <{ %"class.llvm::PointerIntPair", %"class.clang::FileEntry"*, %"class.clang::FileEntry"*, i32*, [5 x i8], [3 x i8] }> +%"class.llvm::PointerIntPair" = type { i64 } +%"class.clang::FileID" = type { i32 } +%"class.llvm::DenseMap.111" = type <{ %"struct.llvm::detail::DenseMapPair.113"*, i32, i32, i32, [4 x i8] }> +%"struct.llvm::detail::DenseMapPair.113" = type opaque +%"class.llvm::DenseMap.115" = type <{ %"struct.llvm::detail::DenseMapPair.117"*, i32, i32, i32, [4 x i8] }> +%"struct.llvm::detail::DenseMapPair.117" = type opaque +%"class.clang::InBeforeInTUCacheEntry" = type { %"class.clang::FileID", %"class.clang::FileID", i8, %"class.clang::FileID", i32, i32 } +%"class.std::unique_ptr.119" = type { %"class.std::tuple.120" } +%"class.std::tuple.120" = type { %"struct.std::_Tuple_impl.121" } +%"struct.std::_Tuple_impl.121" = type { %"struct.std::_Head_base.126" } +%"struct.std::_Head_base.126" = type { %"class.llvm::MemoryBuffer"* } +%"class.llvm::MemoryBuffer" = type { i32 (...)**, i8*, i8* } +%"class.std::unique_ptr.127" = type { %"class.std::tuple.128" } +%"class.std::tuple.128" = type { %"struct.std::_Tuple_impl.129" } +%"struct.std::_Tuple_impl.129" = type { %"struct.std::_Head_base.134" } +%"struct.std::_Head_base.134" = type { %"class.clang::SrcMgr::ContentCache"* } +%"class.llvm::DenseMap.135" = type <{ %"struct.llvm::detail::DenseMapPair.137"*, i32, i32, i32, [4 x i8] }> +%"struct.llvm::detail::DenseMapPair.137" = type opaque +%"class.llvm::SmallVector.139" = type { %"class.llvm::SmallVectorImpl.140", %"struct.llvm::SmallVectorStorage.144" } +%"class.llvm::SmallVectorImpl.140" = type { %"class.llvm::SmallVectorTemplateBase.141" } +%"class.llvm::SmallVectorTemplateBase.141" = type { %"class.llvm::SmallVectorTemplateCommon.142" } +%"class.llvm::SmallVectorTemplateCommon.142" = type { %"class.llvm::SmallVectorBase", %"struct.llvm::AlignedCharArrayUnion.143" } +%"struct.llvm::AlignedCharArrayUnion.143" = type { %"struct.llvm::AlignedCharArray.104" } +%"struct.llvm::SmallVectorStorage.144" = type { [1 x %"struct.llvm::AlignedCharArrayUnion.143"] } +%"class.std::set" = type { %"class.std::_Rb_tree.145" } +%"class.std::_Rb_tree.145" = type { %"struct.std::_Rb_tree<clang::tooling::Replacement, clang::tooling::Replacement, std::_Identity<clang::tooling::Replacement>, std::less<clang::tooling::Replacement>, std::allocator<clang::tooling::Replacement> >::_Rb_tree_impl" } +%"struct.std::_Rb_tree<clang::tooling::Replacement, clang::tooling::Replacement, std::_Identity<clang::tooling::Replacement>, std::less<clang::tooling::Replacement>, std::allocator<clang::tooling::Replacement> >::_Rb_tree_impl" = type { %"struct.std::less.149", %"struct.std::_Rb_tree_node_base", i64 } +%"struct.std::less.149" = type { i8 } + + +; Function Attrs: nounwind +; CHECK-LABEL: @_ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE + +; Load a value into R0 before saving the LR +; CHECK: lwz 0, {{[0-9]+([0-9]+)}} + +; Ensure the LR is saved using a different register +; CHECK: mflr {{[1-9]+}} + +; Ensure the LR is restored using a different register +; CHECK: mtlr {{[0-9]+}} +; CHECK: blr +define void @_ZN5clang6format22BreakableStringLiteral11insertBreakEjjSt4pairImjERNS0_17WhitespaceManagerE(%"class.clang::format::BreakableStringLiteral"* nocapture readonly %this, i32 zeroext %LineIndex, i32 zeroext %TailOffset, [2 x i64] %Split.coerce, %"class.clang::format::WhitespaceManager"* dereferenceable(1504) %Whitespaces) unnamed_addr #1 align 2 { +entry: + %Split.coerce.fca.0.extract = extractvalue [2 x i64] %Split.coerce, 0 + %Split.coerce.fca.1.extract = extractvalue [2 x i64] %Split.coerce, 1 + %StartColumn = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", %"class.clang::format::BreakableStringLiteral"* %this, i64 0, i32 0, i32 1 + %0 = load i32, i32* %StartColumn, align 8, !tbaa !2 + %Prefix = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", %"class.clang::format::BreakableStringLiteral"* %this, i64 0, i32 0, i32 2 + %Length.i.19 = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", %"class.clang::format::BreakableStringLiteral"* %this, i64 0, i32 0, i32 2, i32 1 + %1 = load i64, i64* %Length.i.19, align 8, !tbaa !10 + %cmp.i = icmp eq i64 %1, 0 + br i1 %cmp.i, label %entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge, label %if.end.i.i + +entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge: ; preds = %entry + %agg.tmp7.sroa.0.0..sroa_cast.phi.trans.insert = bitcast %"class.llvm::StringRef"* %Prefix to i64* + %agg.tmp7.sroa.0.0.copyload.pre = load i64, i64* %agg.tmp7.sroa.0.0..sroa_cast.phi.trans.insert, align 8 + br label %_ZNK4llvm9StringRef10startswithES0_.exit + +if.end.i.i: ; preds = %entry + %Data.i.20 = getelementptr inbounds %"class.llvm::StringRef", %"class.llvm::StringRef"* %Prefix, i64 0, i32 0 + %2 = load i8*, i8** %Data.i.20, align 8, !tbaa !12 + %lhsc = load i8, i8* %2, align 1 + %phitmp.i = icmp eq i8 %lhsc, 64 + %3 = ptrtoint i8* %2 to i64 + br label %_ZNK4llvm9StringRef10startswithES0_.exit + +_ZNK4llvm9StringRef10startswithES0_.exit: ; preds = %entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge, %if.end.i.i + %agg.tmp7.sroa.0.0.copyload = phi i64 [ %agg.tmp7.sroa.0.0.copyload.pre, %entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge ], [ %3, %if.end.i.i ] + %4 = phi i1 [ false, %entry._ZNK4llvm9StringRef10startswithES0_.exit_crit_edge ], [ %phitmp.i, %if.end.i.i ] + %dec = sext i1 %4 to i32 + %dec. = add i32 %dec, %0 + %Tok = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", %"class.clang::format::BreakableStringLiteral"* %this, i64 0, i32 0, i32 0, i32 1 + %ref = load %"struct.clang::format::FormatToken"*, %"struct.clang::format::FormatToken"** %Tok, align 8, !tbaa !13 + %conv = zext i32 %TailOffset to i64 + %add = add i64 %Split.coerce.fca.0.extract, %conv + %add4 = add i64 %add, %1 + %conv5 = trunc i64 %add4 to i32 + %Split.sroa.2.8.extract.trunc = trunc i64 %Split.coerce.fca.1.extract to i32 + %agg.tmp6.sroa.0.0..sroa_idx13 = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", %"class.clang::format::BreakableStringLiteral"* %this, i64 0, i32 0, i32 3 + %agg.tmp6.sroa.0.0..sroa_cast = bitcast %"class.llvm::StringRef"* %agg.tmp6.sroa.0.0..sroa_idx13 to i64* + %agg.tmp6.sroa.0.0.copyload = load i64, i64* %agg.tmp6.sroa.0.0..sroa_cast, align 8 + %agg.tmp6.sroa.2.0..sroa_idx14 = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", %"class.clang::format::BreakableStringLiteral"* %this, i64 0, i32 0, i32 3, i32 1 + %agg.tmp6.sroa.2.0.copyload = load i64, i64* %agg.tmp6.sroa.2.0..sroa_idx14, align 8 + %InPPDirective = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", %"class.clang::format::BreakableStringLiteral"* %this, i64 0, i32 0, i32 0, i32 3 + %5 = load i8, i8* %InPPDirective, align 4, !tbaa !34, !range !39 + %tobool = icmp ne i8 %5, 0 + %IndentLevel = getelementptr inbounds %"class.clang::format::BreakableStringLiteral", %"class.clang::format::BreakableStringLiteral"* %this, i64 0, i32 0, i32 0, i32 2 + %6 = load i32, i32* %IndentLevel, align 8, !tbaa !33 + %.fca.0.insert11 = insertvalue [2 x i64] undef, i64 %agg.tmp6.sroa.0.0.copyload, 0 + %.fca.1.insert12 = insertvalue [2 x i64] %.fca.0.insert11, i64 %agg.tmp6.sroa.2.0.copyload, 1 + %.fca.0.insert = insertvalue [2 x i64] undef, i64 %agg.tmp7.sroa.0.0.copyload, 0 + %.fca.1.insert = insertvalue [2 x i64] %.fca.0.insert, i64 %1, 1 + tail call void @_ZN5clang6format17WhitespaceManager24replaceWhitespaceInTokenERKNS0_11FormatTokenEjjN4llvm9StringRefES6_bjji(%"class.clang::format::WhitespaceManager"* nonnull %Whitespaces, %"struct.clang::format::FormatToken"* dereferenceable(272) %ref, i32 zeroext %conv5, i32 zeroext %Split.sroa.2.8.extract.trunc, [2 x i64] %.fca.1.insert12, [2 x i64] %.fca.1.insert, i1 zeroext %tobool, i32 zeroext 1, i32 zeroext %6, i32 signext %dec.) #9 + ret void +} + +; Function Attrs: nounwind argmemonly +declare void @llvm.lifetime.start(i64, i8* nocapture) #2 + +declare void @_ZN5clang6format17WhitespaceManager24replaceWhitespaceInTokenERKNS0_11FormatTokenEjjN4llvm9StringRefES6_bjji(%"class.clang::format::WhitespaceManager"*, %"struct.clang::format::FormatToken"* dereferenceable(272), i32 zeroext, i32 zeroext, [2 x i64], [2 x i64], i1 zeroext, i32 zeroext, i32 zeroext, i32 signext) #3 + +; Function Attrs: nounwind argmemonly +declare void @llvm.lifetime.end(i64, i8* nocapture) #2 + +attributes #9 = { nounwind } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"PIC Level", i32 2} +!1 = !{!"clang version 3.8.0 (trunk 248714) (llvm/trunk 248719)"} +!2 = !{!3, !4, i64 40} +!3 = !{!"_ZTSN5clang6format24BreakableSingleLineTokenE", !4, i64 40, !7, i64 48, !7, i64 64, !7, i64 80} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"_ZTSN4llvm9StringRefE", !8, i64 0, !9, i64 8} +!8 = !{!"any pointer", !5, i64 0} +!9 = !{!"long", !5, i64 0} +!10 = !{!7, !9, i64 8} +!11 = !{!9, !9, i64 0} +!12 = !{!7, !8, i64 0} +!13 = !{!5, !5, i64 0} +!14 = !{!15, !4, i64 200} +!15 = !{!"_ZTSN5clang6format11FormatStyleE", !4, i64 0, !16, i64 4, !16, i64 5, !16, i64 6, !16, i64 7, !16, i64 8, !16, i64 9, !16, i64 10, !16, i64 11, !17, i64 12, !16, i64 16, !16, i64 17, !18, i64 20, !16, i64 24, !16, i64 25, !16, i64 26, !16, i64 27, !19, i64 28, !20, i64 32, !16, i64 36, !16, i64 37, !4, i64 40, !21, i64 48, !16, i64 56, !4, i64 60, !4, i64 64, !16, i64 68, !16, i64 69, !16, i64 70, !16, i64 71, !23, i64 72, !16, i64 96, !4, i64 100, !16, i64 104, !16, i64 105, !24, i64 108, !21, i64 112, !21, i64 120, !4, i64 128, !25, i64 132, !4, i64 136, !16, i64 140, !16, i64 141, !4, i64 144, !4, i64 148, !4, i64 152, !4, i64 156, !4, i64 160, !4, i64 164, !26, i64 168, !16, i64 172, !16, i64 173, !27, i64 176, !16, i64 180, !4, i64 184, !16, i64 188, !16, i64 189, !16, i64 190, !16, i64 191, !16, i64 192, !28, i64 196, !4, i64 200, !29, i64 204} +!16 = !{!"bool", !5, i64 0} +!17 = !{!"_ZTSN5clang6format11FormatStyle18ShortFunctionStyleE", !5, i64 0} +!18 = !{!"_ZTSN5clang6format11FormatStyle33DefinitionReturnTypeBreakingStyleE", !5, i64 0} +!19 = !{!"_ZTSN5clang6format11FormatStyle19BinaryOperatorStyleE", !5, i64 0} +!20 = !{!"_ZTSN5clang6format11FormatStyle18BraceBreakingStyleE", !5, i64 0} +!21 = !{!"_ZTSSs", !22, i64 0} +!22 = !{!"_ZTSNSs12_Alloc_hiderE", !8, i64 0} +!23 = !{!"_ZTSSt6vectorISsSaISsEE"} +!24 = !{!"_ZTSN5clang6format11FormatStyle12LanguageKindE", !5, i64 0} +!25 = !{!"_ZTSN5clang6format11FormatStyle24NamespaceIndentationKindE", !5, i64 0} +!26 = !{!"_ZTSN5clang6format11FormatStyle21PointerAlignmentStyleE", !5, i64 0} +!27 = !{!"_ZTSN5clang6format11FormatStyle24SpaceBeforeParensOptionsE", !5, i64 0} +!28 = !{!"_ZTSN5clang6format11FormatStyle16LanguageStandardE", !5, i64 0} +!29 = !{!"_ZTSN5clang6format11FormatStyle11UseTabStyleE", !5, i64 0} +!30 = !{!31, !32, i64 24} +!31 = !{!"_ZTSN5clang6format14BreakableTokenE", !5, i64 8, !4, i64 16, !16, i64 20, !32, i64 24, !5, i64 32} +!32 = !{!"_ZTSN5clang6format8encoding8EncodingE", !5, i64 0} +!33 = !{!31, !4, i64 16} +!34 = !{!31, !16, i64 20} +!35 = !{!36, !36, i64 0} +!36 = !{!"vtable pointer", !6, i64 0} +!37 = !{!38, !38, i64 0} +!38 = !{!"short", !5, i64 0} +!39 = !{i8 0, i8 2} +!40 = !{i64 0, i64 8, !41, i64 8, i64 8, !11} +!41 = !{!8, !8, i64 0} +!42 = !{!43, !8, i64 16} +!43 = !{!"_ZTSN4llvm15SmallVectorBaseE", !8, i64 0, !8, i64 8, !8, i64 16} +!44 = !{!43, !8, i64 8} +!45 = !{!43, !8, i64 0} +!46 = !{!4, !4, i64 0} +!47 = !{!48, !16, i64 500} +!48 = !{!"_ZTSN5clang6format21BreakableBlockCommentE", !49, i64 40, !51, i64 320, !53, i64 408, !4, i64 496, !16, i64 500, !7, i64 504} +!49 = !{!"_ZTSN4llvm11SmallVectorINS_9StringRefELj16EEE", !50, i64 40} +!50 = !{!"_ZTSN4llvm18SmallVectorStorageINS_9StringRefELj16EEE", !5, i64 0} +!51 = !{!"_ZTSN4llvm11SmallVectorIjLj16EEE", !52, i64 28} +!52 = !{!"_ZTSN4llvm18SmallVectorStorageIjLj16EEE", !5, i64 0} +!53 = !{!"_ZTSN4llvm11SmallVectorIiLj16EEE", !54, i64 28} +!54 = !{!"_ZTSN4llvm18SmallVectorStorageIiLj16EEE", !5, i64 0} +!55 = !{!48, !4, i64 496} diff --git a/test/CodeGen/PowerPC/aantidep-def-ec.mir b/test/CodeGen/PowerPC/aantidep-def-ec.mir new file mode 100644 index 000000000000..d1cb6782f038 --- /dev/null +++ b/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -0,0 +1,117 @@ +# RUN: llc -o - %s -start-after=if-converter | FileCheck %s + +--- | + target datalayout = "E-m:e-i64:64-n32:64" + target triple = "powerpc64-unknown-linux-gnu" + + %struct.rwlock_t.0.22.58.68.242.244 = type {} + + @tasklist_lock = external global %struct.rwlock_t.0.22.58.68.242.244, align 1 + + ; Function Attrs: nounwind + define void @mm_update_next_owner(i8** %p1, i32* %p2) #0 { + entry: + %0 = load i8*, i8** %p1, align 8 + br i1 undef, label %do.body.92, label %for.body.21 + + for.body.21: ; preds = %entry + unreachable + + do.body.92: ; preds = %entry + %usage = getelementptr inbounds i8, i8* %0, i64 -48 + %counter.i = bitcast i8* %usage to i32* + %call95 = tail call signext i32 bitcast (i32 (...)* @__raw_read_unlock to i32 (%struct.rwlock_t.0.22.58.68.242.244*)*)(%struct.rwlock_t.0.22.58.68.242.244* nonnull @tasklist_lock) #1 + store volatile i32 0, i32* %p2, align 4 + tail call void asm sideeffect "#compiler barrier", "~{memory}"() #1 + %1 = tail call i32 asm sideeffect "\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", "=&r,r,~{cc},~{xer},~{memory}"(i32* %counter.i) #1 + %cmp.i = icmp eq i32 %1, 0 + br i1 %cmp.i, label %if.then.i, label %put_task_struct.exit + + if.then.i: ; preds = %do.body.92 + unreachable + + put_task_struct.exit: ; preds = %do.body.92 + ret void + } + + declare signext i32 @__raw_read_unlock(...) + + attributes #0 = { nounwind "target-cpu"="pwr7" } + attributes #1 = { nounwind } + +... +--- +name: mm_update_next_owner +alignment: 4 +exposesReturnsTwice: false +hasInlineAsm: true +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: false +liveins: + - { reg: '%x3' } + - { reg: '%x4' } +calleeSavedRegisters: [ '%cr2', '%cr3', '%cr4', '%f14', '%f15', '%f16', + '%f17', '%f18', '%f19', '%f20', '%f21', '%f22', + '%f23', '%f24', '%f25', '%f26', '%f27', '%f28', + '%f29', '%f30', '%f31', '%r14', '%r15', '%r16', + '%r17', '%r18', '%r19', '%r20', '%r21', '%r22', + '%r23', '%r24', '%r25', '%r26', '%r27', '%r28', + '%r29', '%r30', '%r31', '%v20', '%v21', '%v22', + '%v23', '%v24', '%v25', '%v26', '%v27', '%v28', + '%v29', '%v30', '%v31', '%vf20', '%vf21', '%vf22', + '%vf23', '%vf24', '%vf25', '%vf26', '%vf27', '%vf28', + '%vf29', '%vf30', '%vf31', '%x14', '%x15', '%x16', + '%x17', '%x18', '%x19', '%x20', '%x21', '%x22', + '%x23', '%x24', '%x25', '%x26', '%x27', '%x28', + '%x29', '%x30', '%x31', '%cr2eq', '%cr3eq', '%cr4eq', + '%cr2gt', '%cr3gt', '%cr4gt', '%cr2lt', '%cr3lt', + '%cr4lt', '%cr2un', '%cr3un', '%cr4un' ] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 144 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 112 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' } + - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' } +body: | + bb.0.entry: + liveins: %x3, %x4, %x29, %x30, %x29, %x30 + + %x0 = MFLR8 implicit %lr8 + STD %x0, 16, %x1 + %x1 = STDU %x1, -144, %x1 + STD killed %x29, 120, %x1 :: (store 8 into %fixed-stack.1) + STD killed %x30, 128, %x1 :: (store 8 into %fixed-stack.0, align 16) + %x30 = OR8 %x4, %x4 + %x3 = LD 0, killed %x3 :: (load 8 from %ir.p1) + %x29 = ADDI8 killed %x3, -48 + %x3 = ADDIStocHA %x2, @tasklist_lock + %x3 = LDtocL @tasklist_lock, killed %x3, implicit %x2 :: (load 8 from got) + BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def %lr8, implicit %rm, implicit %x3, implicit %x2, implicit-def %r1, implicit-def dead %x3 + %r3 = LI 0 + STW killed %r3, 0, killed %x30 :: (volatile store 4 into %ir.p2) + INLINEASM $"#compiler barrier", 25 + INLINEASM $"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber %r3, 851977, killed %x29, 12, implicit-def dead early-clobber %cr0 + ; CHECK-LABEL: @mm_update_next_owner + ; CHECK-NOT: lwarx 29, 0, 29 + ; CHECK-NOT: stwcx. 29, 0, 29 + %cr0 = CMPLWI killed %r3, 0 + %x30 = LD 128, %x1 :: (load 8 from %fixed-stack.0, align 16) + %x29 = LD 120, %x1 :: (load 8 from %fixed-stack.1) + %x1 = ADDI8 %x1, 144 + %x0 = LD 16, %x1 + MTLR8 %x0, implicit-def %lr8 + BLR8 implicit %lr8, implicit %rm + +... diff --git a/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll b/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll new file mode 100644 index 000000000000..f0c0deacf4dd --- /dev/null +++ b/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll @@ -0,0 +1,305 @@ +; RUN: llc -O2 < %s | FileCheck %s +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-grtev4-linux-gnu" + +; Function Attrs: nounwind +define void @_ZN10SubProcess19ScrubbedForkAndExecEiPiS0_PNS_7ResultsE() #0 align 2 { +; CHECK: lis 3, 1234 +; CHECK-NOT: li 3 +; CHECK-NOT: ori 3 +; CHECK-NOT: addi 3 +; CHECK-NOT: addis 3 +; CHECK-NOT: lis 3 +; CHECK: sc + br i1 undef, label %1, label %2 + +; <label>:1 ; preds = %0 + br label %60 + +; <label>:2 ; preds = %0 + br i1 undef, label %3, label %4 + +; <label>:3 ; preds = %2 + unreachable + +; <label>:4 ; preds = %2 + br i1 undef, label %.lr.ph111, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit + +.lr.ph111: ; preds = %4 + br label %5 + +_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit: ; preds = %12, %4 + br i1 undef, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader, label %13 + +; <label>:5 ; preds = %12, %.lr.ph111 + br i1 undef, label %6, label %9 + +; <label>:6 ; preds = %5 + br i1 undef, label %7, label %8 + +; <label>:7 ; preds = %6 + unreachable + +; <label>:8 ; preds = %6 + br label %12 + +; <label>:9 ; preds = %5 + br i1 undef, label %10, label %11 + +; <label>:10 ; preds = %9 + br label %12 + +; <label>:11 ; preds = %9 + br label %12 + +; <label>:12 ; preds = %11, %10, %8 + br i1 undef, label %5, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit + +; <label>:13 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit + br i1 undef, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader, label %14 + +; <label>:14 ; preds = %13 + br label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader + +_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader: ; preds = %14, %13, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit + br i1 undef, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge + +_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader: ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader + br label %_ZN10SubProcess12SafeSyscalls5closeEi.exit + +_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge: ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19, %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19.preheader + br i1 undef, label %15, label %19 + +_ZN10SubProcess12SafeSyscalls5closeEi.exit: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit, %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader + br i1 undef, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19 + +_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit + br i1 undef, label %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit.preheader + +; <label>:15 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge + br label %16 + +; <label>:16 ; preds = %17, %15 + br i1 undef, label %17, label %.critedge.preheader + +; <label>:17 ; preds = %16 + br i1 undef, label %16, label %.critedge.preheader + +.critedge.preheader: ; preds = %17, %16 + br label %.critedge + +.critedge: ; preds = %18, %.critedge.preheader + br i1 undef, label %18, label %.critedge8 + +; <label>:18 ; preds = %.critedge + br i1 undef, label %.critedge, label %.critedge8 + +.critedge8: ; preds = %18, %.critedge + br label %59 + +; <label>:19 ; preds = %_ZN10SubProcess12SafeSyscalls11sigprocmaskEiPKNS0_15kernel_sigset_tEPS1_.exit19._crit_edge + br label %_ZN10SubProcess12SafeSyscalls5closeEi.exit22 + +_ZN10SubProcess12SafeSyscalls5closeEi.exit22: ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit22, %19 + br i1 undef, label %_ZN10SubProcess12SafeSyscalls5closeEi.exit22, label %20 + +; <label>:20 ; preds = %_ZN10SubProcess12SafeSyscalls5closeEi.exit22 + %21 = alloca i8, i64 undef, align 1 + br label %.thread.outer + +.thread.outer: ; preds = %._crit_edge, %20 + br label %.thread + +.thread: ; preds = %45, %.thread.outer + call void @llvm.memset.p0i8.i64(i8* undef, i8 0, i64 56, i32 8, i1 false) + store i8* %21, i8** undef, align 8 + store i32 1073741824, i32* undef, align 8 + %22 = call { i64, i64, i64, i64, i64, i64, i64 } asm sideeffect "sc\0A\09mfcr $0", "=&{r0},=&{r3},=&{r4},=&{r5},=&{r6},=&{r7},=&{r8},{r0},{r3},{r4},{r5},~{cr0},~{ctr},~{memory},~{r11},~{r12}"(i64 342, i64 80871424, i64 undef, i64 0) #2, !srcloc !1 + br i1 undef, label %.lr.ph, label %.critedge15.preheader + +.critedge15.preheader: ; preds = %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge, %.thread + br i1 undef, label %.lr.ph93.preheader, label %.critedge15._crit_edge + +.lr.ph93.preheader: ; preds = %.critedge15.preheader + br label %.lr.ph93 + +.lr.ph: ; preds = %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge, %.thread + switch i32 undef, label %.critedge9 [ + i32 11, label %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge + i32 4, label %_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge + ] + +_ZN10SubProcess12SafeSyscalls7recvmsgEiPNS0_13kernel_msghdrEi.exit.backedge: ; preds = %.lr.ph, %.lr.ph + br i1 undef, label %.lr.ph, label %.critedge15.preheader + +.critedge9: ; preds = %.lr.ph + unreachable + +.critedge15._crit_edge: ; preds = %.critedge15, %.critedge15.preheader + br i1 undef, label %35, label %34 + +.lr.ph93: ; preds = %.critedge15, %.lr.ph93.preheader + switch i32 undef, label %33 [ + i32 0, label %23 + i32 1, label %23 + i32 2, label %23 + i32 3, label %23 + i32 4, label %23 + i32 5, label %23 + i32 6, label %23 + i32 7, label %23 + i32 8, label %27 + i32 9, label %30 + ] + +; <label>:23 ; preds = %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93, %.lr.ph93 + br i1 undef, label %24, label %.critedge15 + +; <label>:24 ; preds = %23 + br i1 undef, label %.critedge15, label %25 + +; <label>:25 ; preds = %24 + br i1 undef, label %.critedge15, label %26 + +; <label>:26 ; preds = %25 + unreachable + +; <label>:27 ; preds = %.lr.ph93 + br i1 undef, label %.critedge15, label %28 + +; <label>:28 ; preds = %27 + br i1 undef, label %29, label %.critedge15 + +; <label>:29 ; preds = %28 + br label %.critedge15 + +; <label>:30 ; preds = %.lr.ph93 + br i1 undef, label %.critedge15, label %31 + +; <label>:31 ; preds = %30 + br i1 undef, label %32, label %.critedge15 + +; <label>:32 ; preds = %31 + br label %.critedge15 + +; <label>:33 ; preds = %.lr.ph93 + unreachable + +.critedge15: ; preds = %32, %31, %30, %29, %28, %27, %25, %24, %23 + br i1 undef, label %.lr.ph93, label %.critedge15._crit_edge + +; <label>:34 ; preds = %.critedge15._crit_edge + unreachable + +; <label>:35 ; preds = %.critedge15._crit_edge + br i1 undef, label %45, label %36 + +; <label>:36 ; preds = %35 + br i1 undef, label %37, label %38 + +; <label>:37 ; preds = %36 + br i1 undef, label %.preheader, label %38 + +.preheader: ; preds = %37 + br i1 undef, label %.lr.ph101, label %._crit_edge + +.lr.ph101: ; preds = %.preheader + br label %39 + +; <label>:38 ; preds = %37, %36 + unreachable + +; <label>:39 ; preds = %43, %.lr.ph101 + br i1 undef, label %40, label %43 + +; <label>:40 ; preds = %39 + br i1 undef, label %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17, label %41 + +; <label>:41 ; preds = %40 + unreachable + +_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17: ; preds = %40 + br i1 undef, label %42, label %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit + +; <label>:42 ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17 + unreachable + +_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit: ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit17 + br i1 undef, label %.thread27, label %43 + +; <label>:43 ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit, %39 + br i1 undef, label %39, label %._crit_edge + +.thread27: ; preds = %_ZN10SubProcess12SafeSyscalls5fcntlEiil.exit + br label %58 + +._crit_edge: ; preds = %43, %.preheader + br i1 undef, label %.thread.outer, label %44 + +; <label>:44 ; preds = %._crit_edge + unreachable + +; <label>:45 ; preds = %35 + br i1 undef, label %46, label %.thread + +; <label>:46 ; preds = %45 + br i1 undef, label %48, label %47 + +; <label>:47 ; preds = %46 + unreachable + +; <label>:48 ; preds = %46 + br i1 undef, label %55, label %49 + +; <label>:49 ; preds = %48 + br i1 undef, label %50, label %51 + +; <label>:50 ; preds = %49 + br label %52 + +; <label>:51 ; preds = %49 + br label %52 + +; <label>:52 ; preds = %51, %50 + br label %53 + +; <label>:53 ; preds = %54, %52 + br i1 undef, label %54, label %.critedge13 + +; <label>:54 ; preds = %53 + br i1 undef, label %53, label %.critedge13 + +.critedge13: ; preds = %54, %53 + br label %58 + +; <label>:55 ; preds = %48 + br label %56 + +; <label>:56 ; preds = %57, %55 + br i1 undef, label %57, label %.critedge14 + +; <label>:57 ; preds = %56 + br i1 undef, label %56, label %.critedge14 + +.critedge14: ; preds = %57, %56 + br label %58 + +; <label>:58 ; preds = %.critedge14, %.critedge13, %.thread27 + br label %59 + +; <label>:59 ; preds = %58, %.critedge8 + br label %60 + +; <label>:60 ; preds = %59, %1 + ret void +} + +; Function Attrs: nounwind argmemonly +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1 + +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind argmemonly } +attributes #2 = { nounwind } + +!1 = !{i32 -2140527538, i32 -2140527533} diff --git a/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir new file mode 100644 index 000000000000..e4aaaf30f90f --- /dev/null +++ b/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -0,0 +1,80 @@ +# RUN: llc -relocation-model=pic -start-after=block-placement -o - %s | FileCheck %s + +--- | + target datalayout = "E-m:e-i64:64-n32:64" + target triple = "powerpc64-unknown-linux-gnu" + + @x = internal thread_local unnamed_addr global i1 false + @y = external thread_local global i32, align 4 + + ; Function Attrs: nounwind + define void @test1() #0 { + entry: + store i1 true, i1* @x, align 1 + store i32 20, i32* @y, align 4 + ret void + } + + attributes #0 = { nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="pwr7" } + + !llvm.module.flags = !{!0} + + !0 = !{i32 1, !"PIC Level", i32 2} + +... +--- +name: test1 +alignment: 4 +exposesReturnsTwice: false +hasInlineAsm: false +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: false +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 64 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 48 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' } + - { id: 1, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false } +body: | + bb.0.entry: + liveins: %x30, %x30 + + %x0 = MFLR8 implicit %lr8 + STD %x31, -8, %x1 + STD killed %x0, 16, %x1 + %x1 = STDU %x1, -64, %x1 + %x3 = ADDIStlsldHA %x2, @x + %x31 = OR8 %x1, %x1 + %x3 = ADDItlsldL killed %x3, @x + STD killed %x30, 48, %x31 :: (store 8 into %fixed-stack.0, align 16) + %x3 = GETtlsldADDR killed %x3, @x, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7 + %x12 = ADDIStlsgdHA %x2, @y + %x30 = OR8 killed %x3, %x3 + %x3 = ADDItlsgdL killed %x12, @y + %x3 = GETtlsADDR killed %x3, @y, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7 + %x4 = ADDISdtprelHA killed %x30, @x + ; CHECK: addis 4, 30, x@dtprel@ha + %x5 = LI8 1 + %r6 = LI 20 + %x30 = LD 48, %x31 :: (load 8 from %fixed-stack.0, align 16) + STB8 killed %x5, target-flags(ppc-dtprel-lo) @x, killed %x4 :: (store 1 into @x) + STW killed %r6, 0, killed %x3 :: (store 4 into @y) + %x1 = ADDI8 %x1, 64 + %x0 = LD 16, %x1 + %x31 = LD -8, %x1 + MTLR8 killed %x0, implicit-def %lr8 + BLR8 implicit %lr8, implicit %rm + +... diff --git a/test/CodeGen/PowerPC/alias.ll b/test/CodeGen/PowerPC/alias.ll index 524abd5da3ef..3650cd9d8a06 100644 --- a/test/CodeGen/PowerPC/alias.ll +++ b/test/CodeGen/PowerPC/alias.ll @@ -2,10 +2,10 @@ ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -code-model=large | FileCheck --check-prefix=CHECK --check-prefix=LARGE %s @foo = global i32 42 -@fooa = alias i32* @foo +@fooa = alias i32, i32* @foo @foo2 = global i64 42 -@foo2a = alias i64* @foo2 +@foo2a = alias i64, i64* @foo2 ; CHECK-LABEL: bar: define i32 @bar() { diff --git a/test/CodeGen/PowerPC/bitcasts-direct-move.ll b/test/CodeGen/PowerPC/bitcasts-direct-move.ll new file mode 100644 index 000000000000..756f57917548 --- /dev/null +++ b/test/CodeGen/PowerPC/bitcasts-direct-move.ll @@ -0,0 +1,83 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ +; RUN: --check-prefix=CHECK-P7 + +define signext i32 @f32toi32(float %a) { +entry: + %0 = bitcast float %a to i32 + ret i32 %0 +; CHECK-P7: stfs 1, +; CHECK-P7: lwa 3, +; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1 +; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3 +; CHECK: mfvsrwz 3, [[SHIFTREG]] +} + +define i64 @f64toi64(double %a) { +entry: + %0 = bitcast double %a to i64 + ret i64 %0 +; CHECK-P7: stxsdx 1, +; CHECK-P7: ld 3, +; CHECK: mfvsrd 3, 1 +} + +define float @i32tof32(i32 signext %a) { +entry: + %0 = bitcast i32 %a to float + ret float %0 +; CHECK-P7: stw 3, +; CHECK-P7: lfs 1, +; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3 +; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1 +; CHECK: xscvspdpn 1, [[SHIFTREG]] +} + +define double @i64tof64(i64 %a) { +entry: + %0 = bitcast i64 %a to double + ret double %0 +; CHECK-P7: std 3, +; CHECK-P7: lxsdx 1, +; CHECK: mtvsrd 1, 3 +} + +define zeroext i32 @f32toi32u(float %a) { +entry: + %0 = bitcast float %a to i32 + ret i32 %0 +; CHECK-P7: stfs 1, +; CHECK-P7: lwz 3, +; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1 +; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3 +; CHECK: mfvsrwz 3, [[SHIFTREG]] +} + +define i64 @f64toi64u(double %a) { +entry: + %0 = bitcast double %a to i64 + ret i64 %0 +; CHECK-P7: stxsdx 1, +; CHECK-P7: ld 3, +; CHECK: mfvsrd 3, 1 +} + +define float @i32utof32(i32 zeroext %a) { +entry: + %0 = bitcast i32 %a to float + ret float %0 +; CHECK-P7: stw 3, +; CHECK-P7: lfs 1, +; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3 +; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1 +; CHECK: xscvspdpn 1, [[SHIFTREG]] +} + +define double @i64utof64(i64 %a) { +entry: + %0 = bitcast i64 %a to double + ret double %0 +; CHECK-P7: std 3, +; CHECK-P7: lxsdx 1, +; CHECK: mtvsrd 1, 3 +} diff --git a/test/CodeGen/PowerPC/bitreverse.ll b/test/CodeGen/PowerPC/bitreverse.ll new file mode 100644 index 000000000000..1c3741a9a696 --- /dev/null +++ b/test/CodeGen/PowerPC/bitreverse.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=ppc64 %s -o - | FileCheck %s + +; These tests just check that the plumbing is in place for @llvm.bitreverse. The +; actual output is massive at the moment as llvm.bitreverse is not yet legal. + +declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone + +define <2 x i16> @f(<2 x i16> %a) { +; CHECK-LABEL: f: +; CHECK: rlwinm + %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a) + ret <2 x i16> %b +} + +declare i8 @llvm.bitreverse.i8(i8) readnone + +define i8 @g(i8 %a) { +; CHECK-LABEL: g: +; CHECK: rlwinm +; CHECK: rlwimi + %b = call i8 @llvm.bitreverse.i8(i8 %a) + ret i8 %b +} diff --git a/test/CodeGen/PowerPC/branch-hint.ll b/test/CodeGen/PowerPC/branch-hint.ll new file mode 100644 index 000000000000..46160507105f --- /dev/null +++ b/test/CodeGen/PowerPC/branch-hint.ll @@ -0,0 +1,135 @@ +; RUN: llc < %s -O1 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -ppc-use-branch-hint=false | FileCheck %s +; RUN: llc < %s -O1 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -ppc-use-branch-hint=true | FileCheck %s -check-prefix=CHECK-HINT +define void @branch_hint_1(i32 %src) { +entry: + %cmp = icmp eq i32 %src, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + tail call void @foo() #0 + unreachable + +if.end: + call void @goo() + ret void + +; CHECK-LABEL: branch_hint_1: +; CHECK: beq + +; CHECK-HINT-LABEL: branch_hint_1: +; CHECK-HINT: beq- +} + +define void @branch_hint_2(i32 %src) { +entry: + %cmp = icmp eq i32 %src, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + call void @goo() + ret void + +if.end: + tail call void @foo() #0 + unreachable + +; CHECK-LABEL: @branch_hint_2 +; CHECK: bne + +; CHECK-HINT-LABEL: @branch_hint_2 +; CHECK-HINT: bne- +} + +declare void @foo() +attributes #0 = { noreturn } + +define void @branch_hint_3(i32 %src) { +entry: + %cmp = icmp eq i32 %src, 0 + br i1 %cmp, label %if.then, label %if.end, !prof !0 + +if.then: + call void @foo() + ret void + +if.end: + call void @goo() + ret void + +; CHECK-LABEL: @branch_hint_3 +; CHECK: bne + +; CHECK-HINT-LABEL: @branch_hint_3 +; CHECK-HINT: bne +} + +!0 = !{!"branch_weights", i32 64, i32 4} + +define void @branch_hint_4(i32 %src) { +entry: + %cmp = icmp eq i32 %src, 0 + br i1 %cmp, label %if.then, label %if.end, !prof !1 + +if.then: + call void @foo() + ret void + +if.end: + call void @goo() + ret void + +; CHECK-HINT-LABEL: branch_hint_4 +; CHECK-HINT: bne +} + +!1 = !{!"branch_weights", i32 64, i32 8} + +define void @branch_hint_5(i32 %src) { +entry: + %cmp = icmp eq i32 %src, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + ret void + +if.end: + call void @goo() + ret void + +; CHECK-HINT-LABEL: branch_hint_5: +; CHECK-HINT: beq +} + +declare void @goo() + +define void @branch_hint_6(i32 %src1, i32 %src2, i32 %src3) { +entry: + %cmp = icmp eq i32 %src1, 0 + br i1 %cmp, label %if.end.6, label %if.end, !prof !3 + +if.end: + %cmp1 = icmp eq i32 %src2, 0 + br i1 %cmp1, label %if.end.3, label %if.then.2 + +if.then.2: + tail call void @foo() #0 + unreachable + +if.end.3: + %cmp4 = icmp eq i32 %src3, 1 + br i1 %cmp4, label %if.then.5, label %if.end.6 + +if.then.5: + tail call void @foo() #0 + unreachable + +if.end.6: + ret void + +; CHECK-HINT-LABEL: branch_hint_6: +; CHECK-HINT: bne +; CHECK-HINT: bne- +; CHECK-HINT: bne+ +} + +!3 = !{!"branch_weights", i32 64, i32 4} diff --git a/test/CodeGen/PowerPC/coal-sections.ll b/test/CodeGen/PowerPC/coal-sections.ll new file mode 100644 index 000000000000..377891c47143 --- /dev/null +++ b/test/CodeGen/PowerPC/coal-sections.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple powerpc-apple-darwin8 -march=ppc32 | FileCheck %s + +; Check that *coal* sections are emitted. + +; CHECK: .section __TEXT,__textcoal_nt,coalesced,pure_instructions +; CHECK: .section __TEXT,__textcoal_nt,coalesced,pure_instructions +; CHECK-NEXT: .globl _foo + +; CHECK: .section __TEXT,__const_coal,coalesced +; CHECK-NEXT: .globl _a + +; CHECK: .section __DATA,__datacoal_nt,coalesced +; CHECK-NEXT: .globl _b + +@a = weak_odr constant [4 x i32] [i32 1, i32 2, i32 3, i32 4], align 16 +@b = weak global i32 5, align 4 +@g = common global i32* null, align 8 + +; Function Attrs: nounwind ssp uwtable +define weak i32* @foo() { +entry: + store i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i64 0, i64 0), i32** @g, align 8 + ret i32* @b +} diff --git a/test/CodeGen/PowerPC/crbit-asm-disabled.ll b/test/CodeGen/PowerPC/crbit-asm-disabled.ll new file mode 100644 index 000000000000..56ec8ecb85d7 --- /dev/null +++ b/test/CodeGen/PowerPC/crbit-asm-disabled.ll @@ -0,0 +1,16 @@ +; RUN: not llc -mcpu=pwr7 -o /dev/null %s 2>&1 | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 { +entry: + %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0 + %1 = and i8 %0, 1 + %tobool3 = icmp ne i8 %1, 0 + ret i1 %tobool3 + +; CHECK: error: couldn't allocate output register for constraint 'wc' +} + +attributes #0 = { nounwind "target-features"="-crbits" } + diff --git a/test/CodeGen/PowerPC/crbit-asm.ll b/test/CodeGen/PowerPC/crbit-asm.ll index 36de3435a081..41e65af29a8a 100644 --- a/test/CodeGen/PowerPC/crbit-asm.ll +++ b/test/CodeGen/PowerPC/crbit-asm.ll @@ -1,4 +1,5 @@ ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -O1 -mcpu=pwr7 < %s | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -55,5 +56,5 @@ entry: ; CHECK: blr } -attributes #0 = { nounwind } +attributes #0 = { nounwind "target-features"="+crbits" } diff --git a/test/CodeGen/PowerPC/cttz.ll b/test/CodeGen/PowerPC/cttz.ll index 60de982d91a1..3757fa3e2f29 100644 --- a/test/CodeGen/PowerPC/cttz.ll +++ b/test/CodeGen/PowerPC/cttz.ll @@ -6,7 +6,7 @@ declare i32 @llvm.cttz.i32(i32, i1) define i32 @bar(i32 %x) { entry: ; CHECK: @bar -; CHECK: cntlz +; CHECK: cntlzw %tmp.1 = call i32 @llvm.cttz.i32( i32 %x, i1 true ) ; <i32> [#uses=1] ret i32 %tmp.1 } diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll index 87914025b733..b636cff0f205 100644 --- a/test/CodeGen/PowerPC/dbg.ll +++ b/test/CodeGen/PowerPC/dbg.ll @@ -4,7 +4,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readnone { +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readnone !dbg !5 { entry: tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !15, metadata !DIExpression()), !dbg !17 tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !16, metadata !DIExpression()), !dbg !18 @@ -17,10 +17,10 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22} -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1", isOptimized: true, emissionKind: 0, file: !21, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports: !1) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1", isOptimized: true, emissionKind: 0, file: !21, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports: !1) !1 = !{} !3 = !{!5} -!5 = !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !21, scope: null, type: !7, function: i32 (i32, i8**)* @main, variables: !13) +!5 = distinct !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !21, scope: null, type: !7, variables: !13) !6 = !DIFile(filename: "dbg.c", directory: "/src") !7 = !DISubroutineType(types: !8) !8 = !{!9, !9, !10} @@ -29,8 +29,8 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !11 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !12) !12 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) !13 = !{!15, !16} -!15 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 1, arg: 1, scope: !5, file: !6, type: !9) -!16 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 1, arg: 2, scope: !5, file: !6, type: !10) +!15 = !DILocalVariable(name: "argc", line: 1, arg: 1, scope: !5, file: !6, type: !9) +!16 = !DILocalVariable(name: "argv", line: 1, arg: 2, scope: !5, file: !6, type: !10) !17 = !DILocation(line: 1, column: 14, scope: !5) !18 = !DILocation(line: 1, column: 26, scope: !5) !19 = !DILocation(line: 2, column: 3, scope: !20) diff --git a/test/CodeGen/PowerPC/dyn-alloca-offset.ll b/test/CodeGen/PowerPC/dyn-alloca-offset.ll new file mode 100644 index 000000000000..7159b9da736d --- /dev/null +++ b/test/CodeGen/PowerPC/dyn-alloca-offset.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +declare i64 @llvm.get.dynamic.area.offset.i64() + +declare i64 @bar(i64) + +attributes #0 = { nounwind } + +; Function Attrs: nounwind sanitize_address uwtable +define signext i64 @foo(i32 signext %N, i32 signext %M) #0 { + %1 = alloca i64, align 32 + %dynamic_area_offset = call i64 @llvm.get.dynamic.area.offset.i64() + %2 = call i64 @bar(i64 %dynamic_area_offset) + ret i64 %2 + +; CHECK-DAG: li [[REG1:[0-9]+]], 112 +; CHECK: blr + +} diff --git a/test/CodeGen/PowerPC/e500-1.ll b/test/CodeGen/PowerPC/e500-1.ll new file mode 100644 index 000000000000..7457c0e57e18 --- /dev/null +++ b/test/CodeGen/PowerPC/e500-1.ll @@ -0,0 +1,30 @@ +; RUN: llc -O0 -mcpu=e500mc < %s | FileCheck %s +; Check if e500 generates code with mfocrf insn. + +target datalayout = "E-m:e-p:32:32-i64:64-n32" +target triple = "powerpc-unknown-linux-gnu" + +define internal i32 @func_49(i64 %p_50, i16 zeroext %p_51, i8* %p_52, i32 %p_53) { +; CHECK-LABEL: @func_49 +; CHECK-NOT: mfocrf + + %1 = load i64, i64* undef, align 8 + %2 = load i64, i64* undef, align 8 + %3 = icmp sge i32 undef, undef + %4 = zext i1 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = icmp slt i64 %2, %5 + %7 = zext i1 %6 to i32 + %8 = call i64 @safe_sub_func_int64_t_s_s(i64 -6372137293439783564, i64 undef) + %9 = icmp slt i32 %7, undef + %10 = zext i1 %9 to i32 + %11 = sext i32 %10 to i64 + %12 = icmp sle i64 %1, %11 + %13 = zext i1 %12 to i32 + %14 = call i32 @safe_add_func_int32_t_s_s(i32 undef, i32 %13) + ret i32 undef +} + +declare i32 @safe_add_func_int32_t_s_s(i32, i32) + +declare i64 @safe_sub_func_int64_t_s_s(i64, i64) diff --git a/test/CodeGen/PowerPC/emutls_generic.ll b/test/CodeGen/PowerPC/emutls_generic.ll new file mode 100644 index 000000000000..a2e13a6723f8 --- /dev/null +++ b/test/CodeGen/PowerPC/emutls_generic.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -emulated-tls -mtriple=powerpc64-unknown-linux-gnu -relocation-model=pic \ +; RUN: | FileCheck %s +; RUN: llc < %s -emulated-tls -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic \ +; RUN: | FileCheck %s + +; Make sure that TLS symbols are emitted in expected order. + +@external_x = external thread_local global i32, align 8 +@external_y = thread_local global i8 7, align 2 +@internal_y = internal thread_local global i64 9, align 16 + +define i32* @get_external_x() { +entry: + ret i32* @external_x +} + +define i8* @get_external_y() { +entry: + ret i8* @external_y +} + +define i64* @get_internal_y() { +entry: + ret i64* @internal_y +} + +; CHECK-LABEL: get_external_x: +; CHECK-NOT: _tls_get_address +; CHECK: __emutls_get_address +; CHECK-LABEL: get_external_y: +; CHECK: __emutls_get_address +; CHECK-NOT: _tls_get_address +; CHECK-LABEL: get_internal_y: +; CHECK-NOT: __emutls_t.external_x: +; CHECK-NOT: __emutls_v.external_x: +; CHECK-LABEL: __emutls_v.external_y: +; CHECK-LABEL: __emutls_t.external_y: +; CHECK: __emutls_t.external_y +; CHECK-LABEL: __emutls_v.internal_y: +; CHECK-LABEL: __emutls_t.internal_y: +; CHECK: __emutls_t.internal_y diff --git a/test/CodeGen/PowerPC/fast-isel-binary.ll b/test/CodeGen/PowerPC/fast-isel-binary.ll index 2f1513f8aa11..1036689ff44d 100644 --- a/test/CodeGen/PowerPC/fast-isel-binary.ll +++ b/test/CodeGen/PowerPC/fast-isel-binary.ll @@ -2,7 +2,7 @@ ; Test add with non-legal types -define void @add_i8(i8 %a, i8 %b) nounwind ssp { +define void @add_i8(i8 %a, i8 %b) nounwind { entry: ; ELF64: add_i8 %a.addr = alloca i8, align 4 @@ -12,7 +12,7 @@ entry: ret void } -define void @add_i8_imm(i8 %a) nounwind ssp { +define void @add_i8_imm(i8 %a) nounwind { entry: ; ELF64: add_i8_imm %a.addr = alloca i8, align 4 @@ -22,7 +22,7 @@ entry: ret void } -define void @add_i16(i16 %a, i16 %b) nounwind ssp { +define void @add_i16(i16 %a, i16 %b) nounwind { entry: ; ELF64: add_i16 %a.addr = alloca i16, align 4 @@ -32,7 +32,7 @@ entry: ret void } -define void @add_i16_imm(i16 %a, i16 %b) nounwind ssp { +define void @add_i16_imm(i16 %a, i16 %b) nounwind { entry: ; ELF64: add_i16_imm %a.addr = alloca i16, align 4 @@ -44,7 +44,7 @@ entry: ; Test or with non-legal types -define void @or_i8(i8 %a, i8 %b) nounwind ssp { +define void @or_i8(i8 %a, i8 %b) nounwind { entry: ; ELF64: or_i8 %a.addr = alloca i8, align 4 @@ -54,7 +54,7 @@ entry: ret void } -define void @or_i8_imm(i8 %a) nounwind ssp { +define void @or_i8_imm(i8 %a) nounwind { entry: ; ELF64: or_i8_imm %a.addr = alloca i8, align 4 @@ -64,7 +64,7 @@ entry: ret void } -define void @or_i16(i16 %a, i16 %b) nounwind ssp { +define void @or_i16(i16 %a, i16 %b) nounwind { entry: ; ELF64: or_i16 %a.addr = alloca i16, align 4 @@ -74,7 +74,7 @@ entry: ret void } -define void @or_i16_imm(i16 %a) nounwind ssp { +define void @or_i16_imm(i16 %a) nounwind { entry: ; ELF64: or_i16_imm %a.addr = alloca i16, align 4 @@ -86,7 +86,7 @@ entry: ; Test sub with non-legal types -define void @sub_i8(i8 %a, i8 %b) nounwind ssp { +define void @sub_i8(i8 %a, i8 %b) nounwind { entry: ; ELF64: sub_i8 %a.addr = alloca i8, align 4 @@ -96,7 +96,7 @@ entry: ret void } -define void @sub_i8_imm(i8 %a) nounwind ssp { +define void @sub_i8_imm(i8 %a) nounwind { entry: ; ELF64: sub_i8_imm %a.addr = alloca i8, align 4 @@ -106,7 +106,7 @@ entry: ret void } -define void @sub_i16(i16 %a, i16 %b) nounwind ssp { +define void @sub_i16(i16 %a, i16 %b) nounwind { entry: ; ELF64: sub_i16 %a.addr = alloca i16, align 4 @@ -116,7 +116,7 @@ entry: ret void } -define void @sub_i16_imm(i16 %a) nounwind ssp { +define void @sub_i16_imm(i16 %a) nounwind { entry: ; ELF64: sub_i16_imm %a.addr = alloca i16, align 4 @@ -126,7 +126,7 @@ entry: ret void } -define void @sub_i16_badimm(i16 %a) nounwind ssp { +define void @sub_i16_badimm(i16 %a) nounwind { entry: ; ELF64: sub_i16_imm %a.addr = alloca i16, align 4 diff --git a/test/CodeGen/PowerPC/fast-isel-br-const.ll b/test/CodeGen/PowerPC/fast-isel-br-const.ll index 6be7fbf9e02f..f411d23fb288 100644 --- a/test/CodeGen/PowerPC/fast-isel-br-const.ll +++ b/test/CodeGen/PowerPC/fast-isel-br-const.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 -define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { +define i32 @t1(i32 %a, i32 %b) nounwind { entry: ; ELF64: t1 %x = add i32 %a, %b diff --git a/test/CodeGen/PowerPC/fast-isel-call.ll b/test/CodeGen/PowerPC/fast-isel-call.ll index 64d8f6e79195..5d541e3a01f1 100644 --- a/test/CodeGen/PowerPC/fast-isel-call.ll +++ b/test/CodeGen/PowerPC/fast-isel-call.ll @@ -56,7 +56,7 @@ declare zeroext i16 @t6(); declare signext i8 @t7(); declare zeroext i8 @t8(); -define i32 @t10(i32 %argc, i8** nocapture %argv) { +define i32 @t10(i32 %argc, i8** nocapture %argv) nounwind { entry: ; ELF64: t10 %call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70) @@ -97,9 +97,9 @@ define i32 @bar0(i32 %i) nounwind { ; ret i32 %tmp1 ;} -declare void @float_foo(float %f) ssp +declare void @float_foo(float %f) -define void @float_const() ssp { +define void @float_const() nounwind { entry: ; ELF64: float_const call void @float_foo(float 0x401C666660000000) @@ -108,7 +108,7 @@ entry: ret void } -define void @float_reg(float %dummy, float %f) ssp { +define void @float_reg(float %dummy, float %f) nounwind { entry: ; ELF64: float_reg call void @float_foo(float %f) @@ -116,9 +116,9 @@ entry: ret void } -declare void @double_foo(double %d) ssp +declare void @double_foo(double %d) -define void @double_const() ssp { +define void @double_const() nounwind { entry: ; ELF64: double_const call void @double_foo(double 0x1397723CCABD0000401C666660000000) @@ -127,7 +127,7 @@ entry: ret void } -define void @double_reg(double %dummy, double %d) ssp { +define void @double_reg(double %dummy, double %d) nounwind { entry: ; ELF64: double_reg call void @double_foo(double %d) diff --git a/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll b/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll index 5a9d15868b6b..5881dc3798ae 100644 --- a/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll +++ b/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll @@ -3,7 +3,7 @@ ; When fastisel better supports VSX fix up this test case. ; ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 -define void @t1a(float %a) uwtable ssp { +define void @t1a(float %a) nounwind { entry: ; ELF64: t1a %cmp = fcmp oeq float %a, 0.000000e+00 @@ -22,7 +22,7 @@ if.end: ; preds = %if.then, %entry declare void @foo() -define void @t1b(float %a) uwtable ssp { +define void @t1b(float %a) nounwind { entry: ; ELF64: t1b %cmp = fcmp oeq float %a, -0.000000e+00 @@ -39,7 +39,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t2a(double %a) uwtable ssp { +define void @t2a(double %a) nounwind { entry: ; ELF64: t2a %cmp = fcmp oeq double %a, 0.000000e+00 @@ -56,7 +56,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t2b(double %a) uwtable ssp { +define void @t2b(double %a) nounwind { entry: ; ELF64: t2b %cmp = fcmp oeq double %a, -0.000000e+00 @@ -73,7 +73,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t4(i8 signext %a) uwtable ssp { +define void @t4(i8 signext %a) nounwind { entry: ; ELF64: t4 %cmp = icmp eq i8 %a, -1 @@ -89,7 +89,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t5(i8 zeroext %a) uwtable ssp { +define void @t5(i8 zeroext %a) nounwind { entry: ; ELF64: t5 %cmp = icmp eq i8 %a, 1 @@ -105,7 +105,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t6(i16 signext %a) uwtable ssp { +define void @t6(i16 signext %a) nounwind { entry: ; ELF64: t6 %cmp = icmp eq i16 %a, -1 @@ -121,7 +121,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t7(i16 zeroext %a) uwtable ssp { +define void @t7(i16 zeroext %a) nounwind { entry: ; ELF64: t7 %cmp = icmp eq i16 %a, 1 @@ -137,7 +137,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t8(i32 %a) uwtable ssp { +define void @t8(i32 %a) nounwind { entry: ; ELF64: t8 %cmp = icmp eq i32 %a, -1 @@ -152,7 +152,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t9(i32 %a) uwtable ssp { +define void @t9(i32 %a) nounwind { entry: ; ELF64: t9 %cmp = icmp eq i32 %a, 1 @@ -167,7 +167,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t10(i32 %a) uwtable ssp { +define void @t10(i32 %a) nounwind { entry: ; ELF64: t10 %cmp = icmp eq i32 %a, 384 @@ -182,7 +182,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t11(i32 %a) uwtable ssp { +define void @t11(i32 %a) nounwind { entry: ; ELF64: t11 %cmp = icmp eq i32 %a, 4096 @@ -197,7 +197,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t12(i8 %a) uwtable ssp { +define void @t12(i8 %a) nounwind { entry: ; ELF64: t12 %cmp = icmp ugt i8 %a, -113 @@ -229,7 +229,7 @@ if.end: ; preds = %entry ret void } -define void @t14(i64 %a) uwtable ssp { +define void @t14(i64 %a) nounwind { entry: ; ELF64: t14 %cmp = icmp eq i64 %a, -1 @@ -244,7 +244,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t15(i64 %a) uwtable ssp { +define void @t15(i64 %a) nounwind { entry: ; ELF64: t15 %cmp = icmp eq i64 %a, 1 @@ -259,7 +259,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t16(i64 %a) uwtable ssp { +define void @t16(i64 %a) nounwind { entry: ; ELF64: t16 %cmp = icmp eq i64 %a, 384 @@ -274,7 +274,7 @@ if.end: ; preds = %if.then, %entry ret void } -define void @t17(i64 %a) uwtable ssp { +define void @t17(i64 %a) nounwind { entry: ; ELF64: t17 %cmp = icmp eq i64 %a, 32768 diff --git a/test/CodeGen/PowerPC/fast-isel-const.ll b/test/CodeGen/PowerPC/fast-isel-const.ll index a751a2be6c69..3987e54a8d1b 100644 --- a/test/CodeGen/PowerPC/fast-isel-const.ll +++ b/test/CodeGen/PowerPC/fast-isel-const.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 -define zeroext i1 @testi1(i8 %in) nounwind uwtable ssp { +define zeroext i1 @testi1(i8 %in) nounwind { entry: %c = icmp eq i8 %in, 5 br i1 %c, label %true, label %false diff --git a/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll b/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll index cfb934c6ab02..e4cdf8d7a9c3 100644 --- a/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll +++ b/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll @@ -2,7 +2,7 @@ ; Test sitofp -define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp { +define void @sitofp_double_i32(i32 %a, double %b) nounwind { entry: ; ELF64: sitofp_double_i32 %b.addr = alloca double, align 8 @@ -14,7 +14,7 @@ entry: ret void } -define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp { +define void @sitofp_double_i64(i64 %a, double %b) nounwind { entry: ; ELF64: sitofp_double_i64 %b.addr = alloca double, align 8 @@ -26,7 +26,7 @@ entry: ret void } -define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp { +define void @sitofp_double_i16(i16 %a, double %b) nounwind { entry: ; ELF64: sitofp_double_i16 %b.addr = alloca double, align 8 @@ -39,7 +39,7 @@ entry: ret void } -define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp { +define void @sitofp_double_i8(i8 %a, double %b) nounwind { entry: ; ELF64: sitofp_double_i8 %b.addr = alloca double, align 8 @@ -54,7 +54,7 @@ entry: ; Test fptosi -define void @fptosi_float_i32(float %a) nounwind ssp { +define void @fptosi_float_i32(float %a) nounwind { entry: ; ELF64: fptosi_float_i32 %b.addr = alloca i32, align 4 @@ -66,7 +66,7 @@ entry: ret void } -define void @fptosi_float_i64(float %a) nounwind ssp { +define void @fptosi_float_i64(float %a) nounwind { entry: ; ELF64: fptosi_float_i64 %b.addr = alloca i64, align 4 @@ -78,7 +78,7 @@ entry: ret void } -define void @fptosi_double_i32(double %a) nounwind ssp { +define void @fptosi_double_i32(double %a) nounwind { entry: ; ELF64: fptosi_double_i32 %b.addr = alloca i32, align 8 @@ -90,7 +90,7 @@ entry: ret void } -define void @fptosi_double_i64(double %a) nounwind ssp { +define void @fptosi_double_i64(double %a) nounwind { entry: ; ELF64: fptosi_double_i64 %b.addr = alloca i64, align 8 @@ -104,7 +104,7 @@ entry: ; Test fptoui -define void @fptoui_float_i32(float %a) nounwind ssp { +define void @fptoui_float_i32(float %a) nounwind { entry: ; ELF64: fptoui_float_i32 %b.addr = alloca i32, align 4 @@ -116,7 +116,7 @@ entry: ret void } -define void @fptoui_double_i32(double %a) nounwind ssp { +define void @fptoui_double_i32(double %a) nounwind { entry: ; ELF64: fptoui_double_i32 %b.addr = alloca i32, align 8 diff --git a/test/CodeGen/PowerPC/fast-isel-conversion.ll b/test/CodeGen/PowerPC/fast-isel-conversion.ll index f7557d456858..a9324592aeab 100644 --- a/test/CodeGen/PowerPC/fast-isel-conversion.ll +++ b/test/CodeGen/PowerPC/fast-isel-conversion.ll @@ -11,7 +11,7 @@ ; Test sitofp -define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp { +define void @sitofp_single_i64(i64 %a, float %b) nounwind { entry: ; ELF64: sitofp_single_i64 ; ELF64LE: sitofp_single_i64 @@ -32,7 +32,7 @@ entry: ret void } -define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp { +define void @sitofp_single_i32(i32 %a, float %b) nounwind { entry: ; ELF64: sitofp_single_i32 ; ELF64LE: sitofp_single_i32 @@ -57,7 +57,7 @@ entry: ret void } -define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp { +define void @sitofp_single_i16(i16 %a, float %b) nounwind { entry: ; ELF64: sitofp_single_i16 ; ELF64LE: sitofp_single_i16 @@ -81,7 +81,7 @@ entry: ret void } -define void @sitofp_single_i8(i8 %a) nounwind ssp { +define void @sitofp_single_i8(i8 %a) nounwind { entry: ; ELF64: sitofp_single_i8 ; ELF64LE: sitofp_single_i8 @@ -105,7 +105,7 @@ entry: ret void } -define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp { +define void @sitofp_double_i32(i32 %a, double %b) nounwind { entry: ; ELF64: sitofp_double_i32 ; ELF64LE: sitofp_double_i32 @@ -129,7 +129,7 @@ entry: ret void } -define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp { +define void @sitofp_double_i64(i64 %a, double %b) nounwind { entry: ; ELF64: sitofp_double_i64 ; ELF64LE: sitofp_double_i64 @@ -149,7 +149,7 @@ entry: ret void } -define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp { +define void @sitofp_double_i16(i16 %a, double %b) nounwind { entry: ; ELF64: sitofp_double_i16 ; ELF64LE: sitofp_double_i16 @@ -172,7 +172,7 @@ entry: ret void } -define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp { +define void @sitofp_double_i8(i8 %a, double %b) nounwind { entry: ; ELF64: sitofp_double_i8 ; ELF64LE: sitofp_double_i8 @@ -197,7 +197,7 @@ entry: ; Test uitofp -define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp { +define void @uitofp_single_i64(i64 %a, float %b) nounwind { entry: ; ELF64: uitofp_single_i64 ; ELF64LE: uitofp_single_i64 @@ -215,7 +215,7 @@ entry: ret void } -define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp { +define void @uitofp_single_i32(i32 %a, float %b) nounwind { entry: ; ELF64: uitofp_single_i32 ; ELF64LE: uitofp_single_i32 @@ -238,7 +238,7 @@ entry: ret void } -define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp { +define void @uitofp_single_i16(i16 %a, float %b) nounwind { entry: ; ELF64: uitofp_single_i16 ; ELF64LE: uitofp_single_i16 @@ -262,7 +262,7 @@ entry: ret void } -define void @uitofp_single_i8(i8 %a) nounwind ssp { +define void @uitofp_single_i8(i8 %a) nounwind { entry: ; ELF64: uitofp_single_i8 ; ELF64LE: uitofp_single_i8 @@ -286,7 +286,7 @@ entry: ret void } -define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp { +define void @uitofp_double_i64(i64 %a, double %b) nounwind { entry: ; ELF64: uitofp_double_i64 ; ELF64LE: uitofp_double_i64 @@ -304,7 +304,7 @@ entry: ret void } -define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp { +define void @uitofp_double_i32(i32 %a, double %b) nounwind { entry: ; ELF64: uitofp_double_i32 ; ELF64LE: uitofp_double_i32 @@ -327,7 +327,7 @@ entry: ret void } -define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp { +define void @uitofp_double_i16(i16 %a, double %b) nounwind { entry: ; ELF64: uitofp_double_i16 ; ELF64LE: uitofp_double_i16 @@ -350,7 +350,7 @@ entry: ret void } -define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp { +define void @uitofp_double_i8(i8 %a, double %b) nounwind { entry: ; ELF64: uitofp_double_i8 ; ELF64LE: uitofp_double_i8 @@ -375,7 +375,7 @@ entry: ; Test fptosi -define void @fptosi_float_i32(float %a) nounwind ssp { +define void @fptosi_float_i32(float %a) nounwind { entry: ; ELF64: fptosi_float_i32 ; ELF64LE: fptosi_float_i32 @@ -395,7 +395,7 @@ entry: ret void } -define void @fptosi_float_i64(float %a) nounwind ssp { +define void @fptosi_float_i64(float %a) nounwind { entry: ; ELF64: fptosi_float_i64 ; ELF64LE: fptosi_float_i64 @@ -415,7 +415,7 @@ entry: ret void } -define void @fptosi_double_i32(double %a) nounwind ssp { +define void @fptosi_double_i32(double %a) nounwind { entry: ; ELF64: fptosi_double_i32 ; ELF64LE: fptosi_double_i32 @@ -435,7 +435,7 @@ entry: ret void } -define void @fptosi_double_i64(double %a) nounwind ssp { +define void @fptosi_double_i64(double %a) nounwind { entry: ; ELF64: fptosi_double_i64 ; ELF64LE: fptosi_double_i64 @@ -457,7 +457,7 @@ entry: ; Test fptoui -define void @fptoui_float_i32(float %a) nounwind ssp { +define void @fptoui_float_i32(float %a) nounwind { entry: ; ELF64: fptoui_float_i32 ; ELF64LE: fptoui_float_i32 @@ -477,7 +477,7 @@ entry: ret void } -define void @fptoui_float_i64(float %a) nounwind ssp { +define void @fptoui_float_i64(float %a) nounwind { entry: ; ELF64: fptoui_float_i64 ; ELF64LE: fptoui_float_i64 @@ -495,7 +495,7 @@ entry: ret void } -define void @fptoui_double_i32(double %a) nounwind ssp { +define void @fptoui_double_i32(double %a) nounwind { entry: ; ELF64: fptoui_double_i32 ; ELF64LE: fptoui_double_i32 @@ -515,7 +515,7 @@ entry: ret void } -define void @fptoui_double_i64(double %a) nounwind ssp { +define void @fptoui_double_i64(double %a) nounwind { entry: ; ELF64: fptoui_double_i64 ; ELF64LE: fptoui_double_i64 diff --git a/test/CodeGen/PowerPC/fast-isel-crash.ll b/test/CodeGen/PowerPC/fast-isel-crash.ll index 55e87effcd82..e20ef6bcd5d3 100644 --- a/test/CodeGen/PowerPC/fast-isel-crash.ll +++ b/test/CodeGen/PowerPC/fast-isel-crash.ll @@ -11,12 +11,12 @@ entry: ret void } -define internal i32 @_Z13get_global_idj(i32 %dim) nounwind ssp { +define internal i32 @_Z13get_global_idj(i32 %dim) nounwind { entry: ret i32 undef } -define void @wrap(i8 addrspace(1)* addrspace(1)* %arglist, i32 addrspace(1)* %gtid) nounwind ssp { +define void @wrap(i8 addrspace(1)* addrspace(1)* %arglist, i32 addrspace(1)* %gtid) nounwind { entry: call void @stretch(<4 x i8> addrspace(1)* undef, <4 x i8> addrspace(1)* undef, i32 undef, i32 undef, i32 undef, i32 undef, <2 x float> undef, <4 x float> undef) ret void diff --git a/test/CodeGen/PowerPC/fast-isel-ext.ll b/test/CodeGen/PowerPC/fast-isel-ext.ll index 6fd3b4035122..ce8ac440b79c 100644 --- a/test/CodeGen/PowerPC/fast-isel-ext.ll +++ b/test/CodeGen/PowerPC/fast-isel-ext.ll @@ -2,35 +2,35 @@ ; zext -define i32 @zext_8_32(i8 %a) nounwind ssp { +define i32 @zext_8_32(i8 %a) nounwind { ; ELF64: zext_8_32 %r = zext i8 %a to i32 ; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ret i32 %r } -define i32 @zext_16_32(i16 %a) nounwind ssp { +define i32 @zext_16_32(i16 %a) nounwind { ; ELF64: zext_16_32 %r = zext i16 %a to i32 ; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 ret i32 %r } -define i64 @zext_8_64(i8 %a) nounwind ssp { +define i64 @zext_8_64(i8 %a) nounwind { ; ELF64: zext_8_64 %r = zext i8 %a to i64 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 ret i64 %r } -define i64 @zext_16_64(i16 %a) nounwind ssp { +define i64 @zext_16_64(i16 %a) nounwind { ; ELF64: zext_16_64 %r = zext i16 %a to i64 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 ret i64 %r } -define i64 @zext_32_64(i32 %a) nounwind ssp { +define i64 @zext_32_64(i32 %a) nounwind { ; ELF64: zext_32_64 %r = zext i32 %a to i64 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 @@ -39,35 +39,35 @@ define i64 @zext_32_64(i32 %a) nounwind ssp { ; sext -define i32 @sext_8_32(i8 %a) nounwind ssp { +define i32 @sext_8_32(i8 %a) nounwind { ; ELF64: sext_8_32 %r = sext i8 %a to i32 ; ELF64: extsb ret i32 %r } -define i32 @sext_16_32(i16 %a) nounwind ssp { +define i32 @sext_16_32(i16 %a) nounwind { ; ELF64: sext_16_32 %r = sext i16 %a to i32 ; ELF64: extsh ret i32 %r } -define i64 @sext_8_64(i8 %a) nounwind ssp { +define i64 @sext_8_64(i8 %a) nounwind { ; ELF64: sext_8_64 %r = sext i8 %a to i64 ; ELF64: extsb ret i64 %r } -define i64 @sext_16_64(i16 %a) nounwind ssp { +define i64 @sext_16_64(i16 %a) nounwind { ; ELF64: sext_16_64 %r = sext i16 %a to i64 ; ELF64: extsh ret i64 %r } -define i64 @sext_32_64(i32 %a) nounwind ssp { +define i64 @sext_32_64(i32 %a) nounwind { ; ELF64: sext_32_64 %r = sext i32 %a to i64 ; ELF64: extsw diff --git a/test/CodeGen/PowerPC/fast-isel-fold.ll b/test/CodeGen/PowerPC/fast-isel-fold.ll index e56101a28e2b..24cdca35b0dd 100644 --- a/test/CodeGen/PowerPC/fast-isel-fold.ll +++ b/test/CodeGen/PowerPC/fast-isel-fold.ll @@ -4,7 +4,7 @@ @b = global i16 2, align 2 @c = global i32 4, align 4 -define void @t1() nounwind uwtable ssp { +define void @t1() nounwind { ; ELF64: t1 %1 = load i8, i8* @a, align 1 call void @foo1(i8 zeroext %1) @@ -14,7 +14,7 @@ define void @t1() nounwind uwtable ssp { ret void } -define void @t2() nounwind uwtable ssp { +define void @t2() nounwind { ; ELF64: t2 %1 = load i16, i16* @b, align 2 call void @foo2(i16 zeroext %1) @@ -24,7 +24,7 @@ define void @t2() nounwind uwtable ssp { ret void } -define void @t2a() nounwind uwtable ssp { +define void @t2a() nounwind { ; ELF64: t2a %1 = load i32, i32* @c, align 4 call void @foo3(i32 zeroext %1) @@ -38,7 +38,7 @@ declare void @foo1(i8 zeroext) declare void @foo2(i16 zeroext) declare void @foo3(i32 zeroext) -define i32 @t3() nounwind uwtable ssp { +define i32 @t3() nounwind { ; ELF64: t3 %1 = load i8, i8* @a, align 1 %2 = zext i8 %1 to i32 @@ -47,7 +47,7 @@ define i32 @t3() nounwind uwtable ssp { ret i32 %2 } -define i32 @t4() nounwind uwtable ssp { +define i32 @t4() nounwind { ; ELF64: t4 %1 = load i16, i16* @b, align 2 %2 = zext i16 %1 to i32 @@ -56,7 +56,7 @@ define i32 @t4() nounwind uwtable ssp { ret i32 %2 } -define i32 @t5() nounwind uwtable ssp { +define i32 @t5() nounwind { ; ELF64: t5 %1 = load i16, i16* @b, align 2 %2 = sext i16 %1 to i32 @@ -65,7 +65,7 @@ define i32 @t5() nounwind uwtable ssp { ret i32 %2 } -define i32 @t6() nounwind uwtable ssp { +define i32 @t6() nounwind { ; ELF64: t6 %1 = load i8, i8* @a, align 2 %2 = sext i8 %1 to i32 @@ -74,7 +74,7 @@ define i32 @t6() nounwind uwtable ssp { ret i32 %2 } -define i64 @t7() nounwind uwtable ssp { +define i64 @t7() nounwind { ; ELF64: t7 %1 = load i8, i8* @a, align 1 %2 = zext i8 %1 to i64 @@ -83,7 +83,7 @@ define i64 @t7() nounwind uwtable ssp { ret i64 %2 } -define i64 @t8() nounwind uwtable ssp { +define i64 @t8() nounwind { ; ELF64: t8 %1 = load i16, i16* @b, align 2 %2 = zext i16 %1 to i64 @@ -92,7 +92,7 @@ define i64 @t8() nounwind uwtable ssp { ret i64 %2 } -define i64 @t9() nounwind uwtable ssp { +define i64 @t9() nounwind { ; ELF64: t9 %1 = load i16, i16* @b, align 2 %2 = sext i16 %1 to i64 @@ -101,7 +101,7 @@ define i64 @t9() nounwind uwtable ssp { ret i64 %2 } -define i64 @t10() nounwind uwtable ssp { +define i64 @t10() nounwind { ; ELF64: t10 %1 = load i8, i8* @a, align 2 %2 = sext i8 %1 to i64 @@ -110,7 +110,7 @@ define i64 @t10() nounwind uwtable ssp { ret i64 %2 } -define i64 @t11() nounwind uwtable ssp { +define i64 @t11() nounwind { ; ELF64: t11 %1 = load i32, i32* @c, align 4 %2 = zext i32 %1 to i64 @@ -119,7 +119,7 @@ define i64 @t11() nounwind uwtable ssp { ret i64 %2 } -define i64 @t12() nounwind uwtable ssp { +define i64 @t12() nounwind { ; ELF64: t12 %1 = load i32, i32* @c, align 4 %2 = sext i32 %1 to i64 diff --git a/test/CodeGen/PowerPC/fast-isel-indirectbr.ll b/test/CodeGen/PowerPC/fast-isel-indirectbr.ll index b5477134c517..d66fd1fb752d 100644 --- a/test/CodeGen/PowerPC/fast-isel-indirectbr.ll +++ b/test/CodeGen/PowerPC/fast-isel-indirectbr.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 -define void @t1(i8* %x) { +define void @t1(i8* %x) nounwind { entry: ; ELF64: t1 br label %L0 diff --git a/test/CodeGen/PowerPC/fast-isel-load-store.ll b/test/CodeGen/PowerPC/fast-isel-load-store.ll index f6a55f06b2cb..800e5aa66090 100644 --- a/test/CodeGen/PowerPC/fast-isel-load-store.ll +++ b/test/CodeGen/PowerPC/fast-isel-load-store.ll @@ -24,7 +24,7 @@ ; load -define i8 @t1() nounwind uwtable ssp { +define i8 @t1() nounwind { ; ELF64: t1 %1 = load i8, i8* @a, align 1 ; ELF64: lbz @@ -33,7 +33,7 @@ define i8 @t1() nounwind uwtable ssp { ret i8 %2 } -define i16 @t2() nounwind uwtable ssp { +define i16 @t2() nounwind { ; ELF64: t2 %1 = load i16, i16* @b, align 2 ; ELF64: lhz @@ -42,7 +42,7 @@ define i16 @t2() nounwind uwtable ssp { ret i16 %2 } -define i32 @t3() nounwind uwtable ssp { +define i32 @t3() nounwind { ; ELF64: t3 %1 = load i32, i32* @c, align 4 ; ELF64: lwz @@ -51,7 +51,7 @@ define i32 @t3() nounwind uwtable ssp { ret i32 %2 } -define i64 @t4() nounwind uwtable ssp { +define i64 @t4() nounwind { ; ELF64: t4 %1 = load i64, i64* @d, align 4 ; ELF64: ld @@ -60,7 +60,7 @@ define i64 @t4() nounwind uwtable ssp { ret i64 %2 } -define float @t5() nounwind uwtable ssp { +define float @t5() nounwind { ; ELF64: t5 %1 = load float, float* @e, align 4 ; ELF64: lfs @@ -69,7 +69,7 @@ define float @t5() nounwind uwtable ssp { ret float %2 } -define double @t6() nounwind uwtable ssp { +define double @t6() nounwind { ; ELF64: t6 %1 = load double, double* @f, align 8 ; ELF64: lfd @@ -80,7 +80,7 @@ define double @t6() nounwind uwtable ssp { ; store -define void @t7(i8 %v) nounwind uwtable ssp { +define void @t7(i8 %v) nounwind { ; ELF64: t7 %1 = add nsw i8 %v, 1 store i8 %1, i8* @a, align 1 @@ -91,7 +91,7 @@ define void @t7(i8 %v) nounwind uwtable ssp { ret void } -define void @t8(i16 %v) nounwind uwtable ssp { +define void @t8(i16 %v) nounwind { ; ELF64: t8 %1 = add nsw i16 %v, 1 store i16 %1, i16* @b, align 2 @@ -102,7 +102,7 @@ define void @t8(i16 %v) nounwind uwtable ssp { ret void } -define void @t9(i32 %v) nounwind uwtable ssp { +define void @t9(i32 %v) nounwind { ; ELF64: t9 %1 = add nsw i32 %v, 1 store i32 %1, i32* @c, align 4 @@ -113,7 +113,7 @@ define void @t9(i32 %v) nounwind uwtable ssp { ret void } -define void @t10(i64 %v) nounwind uwtable ssp { +define void @t10(i64 %v) nounwind { ; ELF64: t10 %1 = add nsw i64 %v, 1 store i64 %1, i64* @d, align 4 @@ -124,7 +124,7 @@ define void @t10(i64 %v) nounwind uwtable ssp { ret void } -define void @t11(float %v) nounwind uwtable ssp { +define void @t11(float %v) nounwind { ; ELF64: t11 %1 = fadd float %v, 1.0 store float %1, float* @e, align 4 @@ -133,7 +133,7 @@ define void @t11(float %v) nounwind uwtable ssp { ret void } -define void @t12(double %v) nounwind uwtable ssp { +define void @t12(double %v) nounwind { ; ELF64: t12 %1 = fadd double %v, 1.0 store double %1, double* @f, align 8 @@ -143,7 +143,7 @@ define void @t12(double %v) nounwind uwtable ssp { } ;; lwa requires an offset divisible by 4, so we need lwax here. -define i64 @t13() nounwind uwtable ssp { +define i64 @t13() nounwind { ; ELF64: t13 %1 = load i32, i32* getelementptr inbounds (%struct.s, %struct.s* @g, i32 0, i32 1), align 1 %2 = sext i32 %1 to i64 @@ -155,7 +155,7 @@ define i64 @t13() nounwind uwtable ssp { } ;; ld requires an offset divisible by 4, so we need ldx here. -define i64 @t14() nounwind uwtable ssp { +define i64 @t14() nounwind { ; ELF64: t14 %1 = load i64, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1 ; ELF64: li @@ -166,7 +166,7 @@ define i64 @t14() nounwind uwtable ssp { } ;; std requires an offset divisible by 4, so we need stdx here. -define void @t15(i64 %v) nounwind uwtable ssp { +define void @t15(i64 %v) nounwind { ; ELF64: t15 %1 = add nsw i64 %v, 1 store i64 %1, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1 @@ -179,7 +179,7 @@ define void @t15(i64 %v) nounwind uwtable ssp { } ;; ld requires an offset that fits in 16 bits, so we need ldx here. -define i64 @t16() nounwind uwtable ssp { +define i64 @t16() nounwind { ; ELF64: t16 %1 = load i64, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8 ; ELF64: lis @@ -191,7 +191,7 @@ define i64 @t16() nounwind uwtable ssp { } ;; std requires an offset that fits in 16 bits, so we need stdx here. -define void @t17(i64 %v) nounwind uwtable ssp { +define void @t17(i64 %v) nounwind { ; ELF64: t17 %1 = add nsw i64 %v, 1 store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8 diff --git a/test/CodeGen/PowerPC/fast-isel-redefinition.ll b/test/CodeGen/PowerPC/fast-isel-redefinition.ll index 60706a6e1438..19392c938e15 100644 --- a/test/CodeGen/PowerPC/fast-isel-redefinition.ll +++ b/test/CodeGen/PowerPC/fast-isel-redefinition.ll @@ -3,7 +3,7 @@ ; doesn't crash. (It crashed formerly on ARM, and proved useful in ; discovering a bug on PowerPC as well.) -define i32 @f(i32* %x) nounwind ssp { +define i32 @f(i32* %x) nounwind { %y = getelementptr inbounds i32, i32* %x, i32 5000 %tmp103 = load i32, i32* %y, align 4 ret i32 %tmp103 diff --git a/test/CodeGen/PowerPC/fast-isel-ret.ll b/test/CodeGen/PowerPC/fast-isel-ret.ll index 1e4566d94dfd..e05ef7d9ab82 100644 --- a/test/CodeGen/PowerPC/fast-isel-ret.ll +++ b/test/CodeGen/PowerPC/fast-isel-ret.ll @@ -4,7 +4,7 @@ ; ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 -define zeroext i1 @rettrue() nounwind uwtable ssp { +define zeroext i1 @rettrue() nounwind { entry: ; ELF64-LABEL: rettrue ; ELF64: li 3, 1 @@ -12,7 +12,7 @@ entry: ret i1 true } -define zeroext i1 @retfalse() nounwind uwtable ssp { +define zeroext i1 @retfalse() nounwind { entry: ; ELF64-LABEL: retfalse ; ELF64: li 3, 0 @@ -20,7 +20,7 @@ entry: ret i1 false } -define signext i1 @retstrue() nounwind uwtable ssp { +define signext i1 @retstrue() nounwind { entry: ; ELF64-LABEL: retstrue ; ELF64: li 3, -1 @@ -28,7 +28,7 @@ entry: ret i1 true } -define signext i1 @retsfalse() nounwind uwtable ssp { +define signext i1 @retsfalse() nounwind { entry: ; ELF64-LABEL: retsfalse ; ELF64: li 3, 0 @@ -36,7 +36,7 @@ entry: ret i1 false } -define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp { +define signext i8 @ret2(i8 signext %a) nounwind { entry: ; ELF64-LABEL: ret2 ; ELF64: extsb @@ -44,7 +44,7 @@ entry: ret i8 %a } -define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp { +define zeroext i8 @ret3(i8 signext %a) nounwind { entry: ; ELF64-LABEL: ret3 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 @@ -52,7 +52,7 @@ entry: ret i8 %a } -define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp { +define signext i16 @ret4(i16 signext %a) nounwind { entry: ; ELF64-LABEL: ret4 ; ELF64: extsh @@ -60,7 +60,7 @@ entry: ret i16 %a } -define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp { +define zeroext i16 @ret5(i16 signext %a) nounwind { entry: ; ELF64-LABEL: ret5 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 @@ -68,7 +68,7 @@ entry: ret i16 %a } -define i16 @ret6(i16 %a) nounwind uwtable ssp { +define i16 @ret6(i16 %a) nounwind { entry: ; ELF64-LABEL: ret6 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 @@ -76,7 +76,7 @@ entry: ret i16 %a } -define signext i32 @ret7(i32 signext %a) nounwind uwtable ssp { +define signext i32 @ret7(i32 signext %a) nounwind { entry: ; ELF64-LABEL: ret7 ; ELF64: extsw @@ -84,7 +84,7 @@ entry: ret i32 %a } -define zeroext i32 @ret8(i32 signext %a) nounwind uwtable ssp { +define zeroext i32 @ret8(i32 signext %a) nounwind { entry: ; ELF64-LABEL: ret8 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 @@ -92,7 +92,7 @@ entry: ret i32 %a } -define i32 @ret9(i32 %a) nounwind uwtable ssp { +define i32 @ret9(i32 %a) nounwind { entry: ; ELF64-LABEL: ret9 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 @@ -100,7 +100,7 @@ entry: ret i32 %a } -define i64 @ret10(i64 %a) nounwind uwtable ssp { +define i64 @ret10(i64 %a) nounwind { entry: ; ELF64-LABEL: ret10 ; ELF64-NOT: exts @@ -109,21 +109,21 @@ entry: ret i64 %a } -define float @ret11(float %a) nounwind uwtable ssp { +define float @ret11(float %a) nounwind { entry: ; ELF64-LABEL: ret11 ; ELF64: blr ret float %a } -define double @ret12(double %a) nounwind uwtable ssp { +define double @ret12(double %a) nounwind { entry: ; ELF64-LABEL: ret12 ; ELF64: blr ret double %a } -define i8 @ret13() nounwind uwtable ssp { +define i8 @ret13() nounwind { entry: ; ELF64-LABEL: ret13 ; ELF64: li @@ -131,7 +131,7 @@ entry: ret i8 15; } -define i16 @ret14() nounwind uwtable ssp { +define i16 @ret14() nounwind { entry: ; ELF64-LABEL: ret14 ; ELF64: li @@ -139,7 +139,7 @@ entry: ret i16 -225; } -define i32 @ret15() nounwind uwtable ssp { +define i32 @ret15() nounwind { entry: ; ELF64-LABEL: ret15 ; ELF64: lis @@ -148,7 +148,7 @@ entry: ret i32 278135; } -define i64 @ret16() nounwind uwtable ssp { +define i64 @ret16() nounwind { entry: ; ELF64-LABEL: ret16 ; ELF64: li @@ -159,7 +159,7 @@ entry: ret i64 27813515225; } -define float @ret17() nounwind uwtable ssp { +define float @ret17() nounwind { entry: ; ELF64-LABEL: ret17 ; ELF64: addis @@ -168,7 +168,7 @@ entry: ret float 2.5; } -define double @ret18() nounwind uwtable ssp { +define double @ret18() nounwind { entry: ; ELF64-LABEL: ret18 ; ELF64: addis @@ -176,3 +176,13 @@ entry: ; ELF64: blr ret double 2.5e-33; } + +define zeroext i32 @ret19() nounwind { +entry: +; ELF64-LABEL: ret19 +; ELF64: li +; ELF64: oris +; ELF64: ori +; ELF64: blr + ret i32 -1 +} diff --git a/test/CodeGen/PowerPC/fast-isel-shifter.ll b/test/CodeGen/PowerPC/fast-isel-shifter.ll index c18f659dde13..04cb41920605 100644 --- a/test/CodeGen/PowerPC/fast-isel-shifter.ll +++ b/test/CodeGen/PowerPC/fast-isel-shifter.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 -define i32 @shl() nounwind ssp { +define i32 @shl() nounwind { entry: ; ELF64: shl ; ELF64: slw @@ -8,7 +8,7 @@ entry: ret i32 %shl } -define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp { +define i32 @shl_reg(i32 %src1, i32 %src2) nounwind { entry: ; ELF64: shl_reg ; ELF64: slw @@ -16,7 +16,7 @@ entry: ret i32 %shl } -define i32 @lshr() nounwind ssp { +define i32 @lshr() nounwind { entry: ; ELF64: lshr ; ELF64: srw @@ -24,7 +24,7 @@ entry: ret i32 %lshr } -define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp { +define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind { entry: ; ELF64: lshr_reg ; ELF64: srw @@ -32,7 +32,7 @@ entry: ret i32 %lshr } -define i32 @ashr() nounwind ssp { +define i32 @ashr() nounwind { entry: ; ELF64: ashr ; ELF64: srawi @@ -40,7 +40,7 @@ entry: ret i32 %ashr } -define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp { +define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind { entry: ; ELF64: ashr_reg ; ELF64: sraw diff --git a/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll b/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll index 96cf67c869f9..32f4c23c2de2 100644 --- a/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll +++ b/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll @@ -2,7 +2,7 @@ ; sext(a) + sext(b) != sext(a + b) ; RUN: llc -mtriple=powerpc64-unknown-freebsd10.0 %s -O0 -o - | FileCheck %s -define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp { +define zeroext i8 @gep_promotion(i8* %ptr) nounwind { entry: %ptr.addr = alloca i8*, align 8 %add = add i8 64, 64 ; 0x40 + 0x40 diff --git a/test/CodeGen/PowerPC/fma-mutate-register-constraint.ll b/test/CodeGen/PowerPC/fma-mutate-register-constraint.ll new file mode 100644 index 000000000000..fd2ba4ec635e --- /dev/null +++ b/test/CodeGen/PowerPC/fma-mutate-register-constraint.ll @@ -0,0 +1,89 @@ +; RUN: llc -enable-unsafe-fp-math < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; CHECK-NOT: {{vmrg[hl]w.*(3[23456789]|[456][0-9])}} +define void @__f0() { +entry: + %0 = shufflevector <8 x float> zeroinitializer, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %1 = shufflevector <16 x float> %0, <16 x float> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + %2 = shufflevector <8 x float> zeroinitializer, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %3 = shufflevector <16 x float> %2, <16 x float> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + %4 = fmul <32 x float> %1, %3 + %5 = load <4 x float>, <4 x float>* undef, align 128 + %6 = load <4 x float>, <4 x float>* undef, align 128 + %7 = shufflevector <4 x float> undef, <4 x float> %5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %8 = shufflevector <4 x float> undef, <4 x float> %6, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %9 = shufflevector <8 x float> %7, <8 x float> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %10 = shufflevector <16 x float> undef, <16 x float> %9, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + %11 = load <4 x float>, <4 x float>* null, align 128 + %12 = load <4 x float>, <4 x float>* undef, align 128 + %13 = shufflevector <4 x float> undef, <4 x float> %11, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %14 = shufflevector <4 x float> undef, <4 x float> %12, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %15 = shufflevector <8 x float> %13, <8 x float> %14, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %16 = shufflevector <16 x float> undef, <16 x float> %15, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + %17 = fmul <32 x float> %10, %16 + %18 = fsub <32 x float> %4, %17 + %19 = shufflevector <32 x float> %18, <32 x float> undef, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63> + %20 = bitcast <64 x float> %19 to <32 x double> + %21 = shufflevector <32 x double> undef, <32 x double> %20, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63> + %22 = bitcast <64 x double> %21 to <128 x float> + %23 = shufflevector <128 x float> undef, <128 x float> %22, <256 x i32> <i32 0, i32 128, i32 1, i32 129, i32 2, i32 130, i32 3, i32 131, i32 4, i32 132, i32 5, i32 133, i32 6, i32 134, i32 7, i32 135, i32 8, i32 136, i32 9, i32 137, i32 10, i32 138, i32 11, i32 139, i32 12, i32 140, i32 13, i32 141, i32 14, i32 142, i32 15, i32 143, i32 16, i32 144, i32 17, i32 145, i32 18, i32 146, i32 19, i32 147, i32 20, i32 148, i32 21, i32 149, i32 22, i32 150, i32 23, i32 151, i32 24, i32 152, i32 25, i32 153, i32 26, i32 154, i32 27, i32 155, i32 28, i32 156, i32 29, i32 157, i32 30, i32 158, i32 31, i32 159, i32 32, i32 160, i32 33, i32 161, i32 34, i32 162, i32 35, i32 163, i32 36, i32 164, i32 37, i32 165, i32 38, i32 166, i32 39, i32 167, i32 40, i32 168, i32 41, i32 169, i32 42, i32 170, i32 43, i32 171, i32 44, i32 172, i32 45, i32 173, i32 46, i32 174, i32 47, i32 175, i32 48, i32 176, i32 49, i32 177, i32 50, i32 178, i32 51, i32 179, i32 52, i32 180, i32 53, i32 181, i32 54, i32 182, i32 55, i32 183, i32 56, i32 184, i32 57, i32 185, i32 58, i32 186, i32 59, i32 187, i32 60, i32 188, i32 61, i32 189, i32 62, i32 190, i32 63, i32 191, i32 64, i32 192, i32 65, i32 193, i32 66, i32 194, i32 67, i32 195, i32 68, i32 196, i32 69, i32 197, i32 70, i32 198, i32 71, i32 199, i32 72, i32 200, i32 73, i32 201, i32 74, i32 202, i32 75, i32 203, i32 76, i32 204, i32 77, i32 205, i32 78, i32 206, i32 79, i32 207, i32 80, i32 208, i32 81, i32 209, i32 82, i32 210, i32 83, i32 211, i32 84, i32 212, i32 85, i32 213, i32 86, i32 214, i32 87, i32 215, i32 88, i32 216, i32 89, i32 217, i32 90, i32 218, i32 91, i32 219, i32 92, i32 220, i32 93, i32 221, i32 94, i32 222, i32 95, i32 223, i32 96, i32 224, i32 97, i32 225, i32 98, i32 226, i32 99, i32 227, i32 100, i32 228, i32 101, i32 229, i32 102, i32 230, i32 103, i32 231, i32 104, i32 232, i32 105, i32 233, i32 106, i32 234, i32 107, i32 235, i32 108, i32 236, i32 109, i32 237, i32 110, i32 238, i32 111, i32 239, i32 112, i32 240, i32 113, i32 241, i32 114, i32 242, i32 115, i32 243, i32 116, i32 244, i32 117, i32 245, i32 118, i32 246, i32 119, i32 247, i32 120, i32 248, i32 121, i32 249, i32 122, i32 250, i32 123, i32 251, i32 124, i32 252, i32 125, i32 253, i32 126, i32 254, i32 127, i32 255> + %24 = shufflevector <256 x float> undef, <256 x float> %23, <512 x i32> <i32 0, i32 256, i32 1, i32 257, i32 2, i32 258, i32 3, i32 259, i32 4, i32 260, i32 5, i32 261, i32 6, i32 262, i32 7, i32 263, i32 8, i32 264, i32 9, i32 265, i32 10, i32 266, i32 11, i32 267, i32 12, i32 268, i32 13, i32 269, i32 14, i32 270, i32 15, i32 271, i32 16, i32 272, i32 17, i32 273, i32 18, i32 274, i32 19, i32 275, i32 20, i32 276, i32 21, i32 277, i32 22, i32 278, i32 23, i32 279, i32 24, i32 280, i32 25, i32 281, i32 26, i32 282, i32 27, i32 283, i32 28, i32 284, i32 29, i32 285, i32 30, i32 286, i32 31, i32 287, i32 32, i32 288, i32 33, i32 289, i32 34, i32 290, i32 35, i32 291, i32 36, i32 292, i32 37, i32 293, i32 38, i32 294, i32 39, i32 295, i32 40, i32 296, i32 41, i32 297, i32 42, i32 298, i32 43, i32 299, i32 44, i32 300, i32 45, i32 301, i32 46, i32 302, i32 47, i32 303, i32 48, i32 304, i32 49, i32 305, i32 50, i32 306, i32 51, i32 307, i32 52, i32 308, i32 53, i32 309, i32 54, i32 310, i32 55, i32 311, i32 56, i32 312, i32 57, i32 313, i32 58, i32 314, i32 59, i32 315, i32 60, i32 316, i32 61, i32 317, i32 62, i32 318, i32 63, i32 319, i32 64, i32 320, i32 65, i32 321, i32 66, i32 322, i32 67, i32 323, i32 68, i32 324, i32 69, i32 325, i32 70, i32 326, i32 71, i32 327, i32 72, i32 328, i32 73, i32 329, i32 74, i32 330, i32 75, i32 331, i32 76, i32 332, i32 77, i32 333, i32 78, i32 334, i32 79, i32 335, i32 80, i32 336, i32 81, i32 337, i32 82, i32 338, i32 83, i32 339, i32 84, i32 340, i32 85, i32 341, i32 86, i32 342, i32 87, i32 343, i32 88, i32 344, i32 89, i32 345, i32 90, i32 346, i32 91, i32 347, i32 92, i32 348, i32 93, i32 349, i32 94, i32 350, i32 95, i32 351, i32 96, i32 352, i32 97, i32 353, i32 98, i32 354, i32 99, i32 355, i32 100, i32 356, i32 101, i32 357, i32 102, i32 358, i32 103, i32 359, i32 104, i32 360, i32 105, i32 361, i32 106, i32 362, i32 107, i32 363, i32 108, i32 364, i32 109, i32 365, i32 110, i32 366, i32 111, i32 367, i32 112, i32 368, i32 113, i32 369, i32 114, i32 370, i32 115, i32 371, i32 116, i32 372, i32 117, i32 373, i32 118, i32 374, i32 119, i32 375, i32 120, i32 376, i32 121, i32 377, i32 122, i32 378, i32 123, i32 379, i32 124, i32 380, i32 125, i32 381, i32 126, i32 382, i32 127, i32 383, i32 128, i32 384, i32 129, i32 385, i32 130, i32 386, i32 131, i32 387, i32 132, i32 388, i32 133, i32 389, i32 134, i32 390, i32 135, i32 391, i32 136, i32 392, i32 137, i32 393, i32 138, i32 394, i32 139, i32 395, i32 140, i32 396, i32 141, i32 397, i32 142, i32 398, i32 143, i32 399, i32 144, i32 400, i32 145, i32 401, i32 146, i32 402, i32 147, i32 403, i32 148, i32 404, i32 149, i32 405, i32 150, i32 406, i32 151, i32 407, i32 152, i32 408, i32 153, i32 409, i32 154, i32 410, i32 155, i32 411, i32 156, i32 412, i32 157, i32 413, i32 158, i32 414, i32 159, i32 415, i32 160, i32 416, i32 161, i32 417, i32 162, i32 418, i32 163, i32 419, i32 164, i32 420, i32 165, i32 421, i32 166, i32 422, i32 167, i32 423, i32 168, i32 424, i32 169, i32 425, i32 170, i32 426, i32 171, i32 427, i32 172, i32 428, i32 173, i32 429, i32 174, i32 430, i32 175, i32 431, i32 176, i32 432, i32 177, i32 433, i32 178, i32 434, i32 179, i32 435, i32 180, i32 436, i32 181, i32 437, i32 182, i32 438, i32 183, i32 439, i32 184, i32 440, i32 185, i32 441, i32 186, i32 442, i32 187, i32 443, i32 188, i32 444, i32 189, i32 445, i32 190, i32 446, i32 191, i32 447, i32 192, i32 448, i32 193, i32 449, i32 194, i32 450, i32 195, i32 451, i32 196, i32 452, i32 197, i32 453, i32 198, i32 454, i32 199, i32 455, i32 200, i32 456, i32 201, i32 457, i32 202, i32 458, i32 203, i32 459, i32 204, i32 460, i32 205, i32 461, i32 206, i32 462, i32 207, i32 463, i32 208, i32 464, i32 209, i32 465, i32 210, i32 466, i32 211, i32 467, i32 212, i32 468, i32 213, i32 469, i32 214, i32 470, i32 215, i32 471, i32 216, i32 472, i32 217, i32 473, i32 218, i32 474, i32 219, i32 475, i32 220, i32 476, i32 221, i32 477, i32 222, i32 478, i32 223, i32 479, i32 224, i32 480, i32 225, i32 481, i32 226, i32 482, i32 227, i32 483, i32 228, i32 484, i32 229, i32 485, i32 230, i32 486, i32 231, i32 487, i32 232, i32 488, i32 233, i32 489, i32 234, i32 490, i32 235, i32 491, i32 236, i32 492, i32 237, i32 493, i32 238, i32 494, i32 239, i32 495, i32 240, i32 496, i32 241, i32 497, i32 242, i32 498, i32 243, i32 499, i32 244, i32 500, i32 245, i32 501, i32 246, i32 502, i32 247, i32 503, i32 248, i32 504, i32 249, i32 505, i32 250, i32 506, i32 251, i32 507, i32 252, i32 508, i32 253, i32 509, i32 254, i32 510, i32 255, i32 511> + %25 = shufflevector <512 x float> %24, <512 x float> undef, <1024 x i32> <i32 0, i32 512, i32 1, i32 513, i32 2, i32 514, i32 3, i32 515, i32 4, i32 516, i32 5, i32 517, i32 6, i32 518, i32 7, i32 519, i32 8, i32 520, i32 9, i32 521, i32 10, i32 522, i32 11, i32 523, i32 12, i32 524, i32 13, i32 525, i32 14, i32 526, i32 15, i32 527, i32 16, i32 528, i32 17, i32 529, i32 18, i32 530, i32 19, i32 531, i32 20, i32 532, i32 21, i32 533, i32 22, i32 534, i32 23, i32 535, i32 24, i32 536, i32 25, i32 537, i32 26, i32 538, i32 27, i32 539, i32 28, i32 540, i32 29, i32 541, i32 30, i32 542, i32 31, i32 543, i32 32, i32 544, i32 33, i32 545, i32 34, i32 546, i32 35, i32 547, i32 36, i32 548, i32 37, i32 549, i32 38, i32 550, i32 39, i32 551, i32 40, i32 552, i32 41, i32 553, i32 42, i32 554, i32 43, i32 555, i32 44, i32 556, i32 45, i32 557, i32 46, i32 558, i32 47, i32 559, i32 48, i32 560, i32 49, i32 561, i32 50, i32 562, i32 51, i32 563, i32 52, i32 564, i32 53, i32 565, i32 54, i32 566, i32 55, i32 567, i32 56, i32 568, i32 57, i32 569, i32 58, i32 570, i32 59, i32 571, i32 60, i32 572, i32 61, i32 573, i32 62, i32 574, i32 63, i32 575, i32 64, i32 576, i32 65, i32 577, i32 66, i32 578, i32 67, i32 579, i32 68, i32 580, i32 69, i32 581, i32 70, i32 582, i32 71, i32 583, i32 72, i32 584, i32 73, i32 585, i32 74, i32 586, i32 75, i32 587, i32 76, i32 588, i32 77, i32 589, i32 78, i32 590, i32 79, i32 591, i32 80, i32 592, i32 81, i32 593, i32 82, i32 594, i32 83, i32 595, i32 84, i32 596, i32 85, i32 597, i32 86, i32 598, i32 87, i32 599, i32 88, i32 600, i32 89, i32 601, i32 90, i32 602, i32 91, i32 603, i32 92, i32 604, i32 93, i32 605, i32 94, i32 606, i32 95, i32 607, i32 96, i32 608, i32 97, i32 609, i32 98, i32 610, i32 99, i32 611, i32 100, i32 612, i32 101, i32 613, i32 102, i32 614, i32 103, i32 615, i32 104, i32 616, i32 105, i32 617, i32 106, i32 618, i32 107, i32 619, i32 108, i32 620, i32 109, i32 621, i32 110, i32 622, i32 111, i32 623, i32 112, i32 624, i32 113, i32 625, i32 114, i32 626, i32 115, i32 627, i32 116, i32 628, i32 117, i32 629, i32 118, i32 630, i32 119, i32 631, i32 120, i32 632, i32 121, i32 633, i32 122, i32 634, i32 123, i32 635, i32 124, i32 636, i32 125, i32 637, i32 126, i32 638, i32 127, i32 639, i32 128, i32 640, i32 129, i32 641, i32 130, i32 642, i32 131, i32 643, i32 132, i32 644, i32 133, i32 645, i32 134, i32 646, i32 135, i32 647, i32 136, i32 648, i32 137, i32 649, i32 138, i32 650, i32 139, i32 651, i32 140, i32 652, i32 141, i32 653, i32 142, i32 654, i32 143, i32 655, i32 144, i32 656, i32 145, i32 657, i32 146, i32 658, i32 147, i32 659, i32 148, i32 660, i32 149, i32 661, i32 150, i32 662, i32 151, i32 663, i32 152, i32 664, i32 153, i32 665, i32 154, i32 666, i32 155, i32 667, i32 156, i32 668, i32 157, i32 669, i32 158, i32 670, i32 159, i32 671, i32 160, i32 672, i32 161, i32 673, i32 162, i32 674, i32 163, i32 675, i32 164, i32 676, i32 165, i32 677, i32 166, i32 678, i32 167, i32 679, i32 168, i32 680, i32 169, i32 681, i32 170, i32 682, i32 171, i32 683, i32 172, i32 684, i32 173, i32 685, i32 174, i32 686, i32 175, i32 687, i32 176, i32 688, i32 177, i32 689, i32 178, i32 690, i32 179, i32 691, i32 180, i32 692, i32 181, i32 693, i32 182, i32 694, i32 183, i32 695, i32 184, i32 696, i32 185, i32 697, i32 186, i32 698, i32 187, i32 699, i32 188, i32 700, i32 189, i32 701, i32 190, i32 702, i32 191, i32 703, i32 192, i32 704, i32 193, i32 705, i32 194, i32 706, i32 195, i32 707, i32 196, i32 708, i32 197, i32 709, i32 198, i32 710, i32 199, i32 711, i32 200, i32 712, i32 201, i32 713, i32 202, i32 714, i32 203, i32 715, i32 204, i32 716, i32 205, i32 717, i32 206, i32 718, i32 207, i32 719, i32 208, i32 720, i32 209, i32 721, i32 210, i32 722, i32 211, i32 723, i32 212, i32 724, i32 213, i32 725, i32 214, i32 726, i32 215, i32 727, i32 216, i32 728, i32 217, i32 729, i32 218, i32 730, i32 219, i32 731, i32 220, i32 732, i32 221, i32 733, i32 222, i32 734, i32 223, i32 735, i32 224, i32 736, i32 225, i32 737, i32 226, i32 738, i32 227, i32 739, i32 228, i32 740, i32 229, i32 741, i32 230, i32 742, i32 231, i32 743, i32 232, i32 744, i32 233, i32 745, i32 234, i32 746, i32 235, i32 747, i32 236, i32 748, i32 237, i32 749, i32 238, i32 750, i32 239, i32 751, i32 240, i32 752, i32 241, i32 753, i32 242, i32 754, i32 243, i32 755, i32 244, i32 756, i32 245, i32 757, i32 246, i32 758, i32 247, i32 759, i32 248, i32 760, i32 249, i32 761, i32 250, i32 762, i32 251, i32 763, i32 252, i32 764, i32 253, i32 765, i32 254, i32 766, i32 255, i32 767, i32 256, i32 768, i32 257, i32 769, i32 258, i32 770, i32 259, i32 771, i32 260, i32 772, i32 261, i32 773, i32 262, i32 774, i32 263, i32 775, i32 264, i32 776, i32 265, i32 777, i32 266, i32 778, i32 267, i32 779, i32 268, i32 780, i32 269, i32 781, i32 270, i32 782, i32 271, i32 783, i32 272, i32 784, i32 273, i32 785, i32 274, i32 786, i32 275, i32 787, i32 276, i32 788, i32 277, i32 789, i32 278, i32 790, i32 279, i32 791, i32 280, i32 792, i32 281, i32 793, i32 282, i32 794, i32 283, i32 795, i32 284, i32 796, i32 285, i32 797, i32 286, i32 798, i32 287, i32 799, i32 288, i32 800, i32 289, i32 801, i32 290, i32 802, i32 291, i32 803, i32 292, i32 804, i32 293, i32 805, i32 294, i32 806, i32 295, i32 807, i32 296, i32 808, i32 297, i32 809, i32 298, i32 810, i32 299, i32 811, i32 300, i32 812, i32 301, i32 813, i32 302, i32 814, i32 303, i32 815, i32 304, i32 816, i32 305, i32 817, i32 306, i32 818, i32 307, i32 819, i32 308, i32 820, i32 309, i32 821, i32 310, i32 822, i32 311, i32 823, i32 312, i32 824, i32 313, i32 825, i32 314, i32 826, i32 315, i32 827, i32 316, i32 828, i32 317, i32 829, i32 318, i32 830, i32 319, i32 831, i32 320, i32 832, i32 321, i32 833, i32 322, i32 834, i32 323, i32 835, i32 324, i32 836, i32 325, i32 837, i32 326, i32 838, i32 327, i32 839, i32 328, i32 840, i32 329, i32 841, i32 330, i32 842, i32 331, i32 843, i32 332, i32 844, i32 333, i32 845, i32 334, i32 846, i32 335, i32 847, i32 336, i32 848, i32 337, i32 849, i32 338, i32 850, i32 339, i32 851, i32 340, i32 852, i32 341, i32 853, i32 342, i32 854, i32 343, i32 855, i32 344, i32 856, i32 345, i32 857, i32 346, i32 858, i32 347, i32 859, i32 348, i32 860, i32 349, i32 861, i32 350, i32 862, i32 351, i32 863, i32 352, i32 864, i32 353, i32 865, i32 354, i32 866, i32 355, i32 867, i32 356, i32 868, i32 357, i32 869, i32 358, i32 870, i32 359, i32 871, i32 360, i32 872, i32 361, i32 873, i32 362, i32 874, i32 363, i32 875, i32 364, i32 876, i32 365, i32 877, i32 366, i32 878, i32 367, i32 879, i32 368, i32 880, i32 369, i32 881, i32 370, i32 882, i32 371, i32 883, i32 372, i32 884, i32 373, i32 885, i32 374, i32 886, i32 375, i32 887, i32 376, i32 888, i32 377, i32 889, i32 378, i32 890, i32 379, i32 891, i32 380, i32 892, i32 381, i32 893, i32 382, i32 894, i32 383, i32 895, i32 384, i32 896, i32 385, i32 897, i32 386, i32 898, i32 387, i32 899, i32 388, i32 900, i32 389, i32 901, i32 390, i32 902, i32 391, i32 903, i32 392, i32 904, i32 393, i32 905, i32 394, i32 906, i32 395, i32 907, i32 396, i32 908, i32 397, i32 909, i32 398, i32 910, i32 399, i32 911, i32 400, i32 912, i32 401, i32 913, i32 402, i32 914, i32 403, i32 915, i32 404, i32 916, i32 405, i32 917, i32 406, i32 918, i32 407, i32 919, i32 408, i32 920, i32 409, i32 921, i32 410, i32 922, i32 411, i32 923, i32 412, i32 924, i32 413, i32 925, i32 414, i32 926, i32 415, i32 927, i32 416, i32 928, i32 417, i32 929, i32 418, i32 930, i32 419, i32 931, i32 420, i32 932, i32 421, i32 933, i32 422, i32 934, i32 423, i32 935, i32 424, i32 936, i32 425, i32 937, i32 426, i32 938, i32 427, i32 939, i32 428, i32 940, i32 429, i32 941, i32 430, i32 942, i32 431, i32 943, i32 432, i32 944, i32 433, i32 945, i32 434, i32 946, i32 435, i32 947, i32 436, i32 948, i32 437, i32 949, i32 438, i32 950, i32 439, i32 951, i32 440, i32 952, i32 441, i32 953, i32 442, i32 954, i32 443, i32 955, i32 444, i32 956, i32 445, i32 957, i32 446, i32 958, i32 447, i32 959, i32 448, i32 960, i32 449, i32 961, i32 450, i32 962, i32 451, i32 963, i32 452, i32 964, i32 453, i32 965, i32 454, i32 966, i32 455, i32 967, i32 456, i32 968, i32 457, i32 969, i32 458, i32 970, i32 459, i32 971, i32 460, i32 972, i32 461, i32 973, i32 462, i32 974, i32 463, i32 975, i32 464, i32 976, i32 465, i32 977, i32 466, i32 978, i32 467, i32 979, i32 468, i32 980, i32 469, i32 981, i32 470, i32 982, i32 471, i32 983, i32 472, i32 984, i32 473, i32 985, i32 474, i32 986, i32 475, i32 987, i32 476, i32 988, i32 477, i32 989, i32 478, i32 990, i32 479, i32 991, i32 480, i32 992, i32 481, i32 993, i32 482, i32 994, i32 483, i32 995, i32 484, i32 996, i32 485, i32 997, i32 486, i32 998, i32 487, i32 999, i32 488, i32 1000, i32 489, i32 1001, i32 490, i32 1002, i32 491, i32 1003, i32 492, i32 1004, i32 493, i32 1005, i32 494, i32 1006, i32 495, i32 1007, i32 496, i32 1008, i32 497, i32 1009, i32 498, i32 1010, i32 499, i32 1011, i32 500, i32 1012, i32 501, i32 1013, i32 502, i32 1014, i32 503, i32 1015, i32 504, i32 1016, i32 505, i32 1017, i32 506, i32 1018, i32 507, i32 1019, i32 508, i32 1020, i32 509, i32 1021, i32 510, i32 1022, i32 511, i32 1023> + %26 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + store <4 x float> %26, <4 x float>* undef, align 128 + %27 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 56, i32 57, i32 58, i32 59> + store <4 x float> %27, <4 x float>* undef, align 128 + %28 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 164, i32 165, i32 166, i32 167> + store <4 x float> %28, <4 x float>* undef, align 128 + %29 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 168, i32 169, i32 170, i32 171> + store <4 x float> %29, <4 x float>* undef, align 128 + %30 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 172, i32 173, i32 174, i32 175> + store <4 x float> %30, <4 x float>* undef, align 128 + %31 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 176, i32 177, i32 178, i32 179> + store <4 x float> %31, <4 x float>* undef, align 128 + %32 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 284, i32 285, i32 286, i32 287> + store <4 x float> %32, <4 x float>* undef, align 128 + %33 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 328, i32 329, i32 330, i32 331> + store <4 x float> %33, <4 x float>* undef, align 128 + %34 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 332, i32 333, i32 334, i32 335> + store <4 x float> %34, <4 x float>* undef, align 128 + %35 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 524, i32 525, i32 526, i32 527> + store <4 x float> %35, <4 x float>* undef, align 128 + %36 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 528, i32 529, i32 530, i32 531> + store <4 x float> %36, <4 x float>* undef, align 128 + %37 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 648, i32 649, i32 650, i32 651> + store <4 x float> %37, <4 x float>* undef, align 128 + %38 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 652, i32 653, i32 654, i32 655> + store <4 x float> %38, <4 x float>* undef, align 128 + %39 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 656, i32 657, i32 658, i32 659> + store <4 x float> %39, <4 x float>* undef, align 128 + %40 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 732, i32 733, i32 734, i32 735> + store <4 x float> %40, <4 x float>* undef, align 128 + %41 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 736, i32 737, i32 738, i32 739> + store <4 x float> %41, <4 x float>* undef, align 128 + %42 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 740, i32 741, i32 742, i32 743> + store <4 x float> %42, <4 x float>* undef, align 128 + %43 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 872, i32 873, i32 874, i32 875> + store <4 x float> %43, <4 x float>* undef, align 128 + %44 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 968, i32 969, i32 970, i32 971> + store <4 x float> %44, <4 x float>* undef, align 128 + %45 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 1016, i32 1017, i32 1018, i32 1019> + store <4 x float> %45, <4 x float>* undef, align 128 + %46 = shufflevector <1024 x float> %25, <1024 x float> undef, <4 x i32> <i32 1020, i32 1021, i32 1022, i32 1023> + store <4 x float> %46, <4 x float>* undef, align 128 + %47 = shufflevector <1024 x float> undef, <1024 x float> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11> + store <4 x float> %47, <4 x float>* undef, align 128 + %48 = shufflevector <1024 x float> undef, <1024 x float> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15> + store <4 x float> %48, <4 x float>* undef, align 128 + %49 = shufflevector <1024 x float> undef, <1024 x float> undef, <4 x i32> <i32 16, i32 17, i32 18, i32 19> + store <4 x float> %49, <4 x float>* undef, align 128 + %50 = shufflevector <1024 x float> undef, <1024 x float> undef, <4 x i32> <i32 20, i32 21, i32 22, i32 23> + store <4 x float> %50, <4 x float>* undef, align 128 + %51 = shufflevector <1024 x float> undef, <1024 x float> undef, <4 x i32> <i32 148, i32 149, i32 150, i32 151> + store <4 x float> %51, <4 x float>* undef, align 128 + %52 = shufflevector <1024 x float> undef, <1024 x float> undef, <4 x i32> <i32 632, i32 633, i32 634, i32 635> + store <4 x float> %52, <4 x float>* undef, align 128 + ret void +} diff --git a/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll b/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll index 1d9b64823140..4868a18a95a0 100644 --- a/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll +++ b/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll @@ -24,8 +24,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfcc ; CHECK: mtvsrwz [[MOVEREG01:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG01]] +; CHECK: xscvuxdsp 1, [[MOVEREG01]] } ; Function Attrs: nounwind @@ -77,8 +76,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfuch ; CHECK: mtvsrwz [[MOVEREG03:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG03]] +; CHECK: xscvuxdsp 1, [[MOVEREG03]] } ; Function Attrs: nounwind @@ -130,8 +128,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfss ; CHECK: mtvsrwa [[MOVEREG05:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG05]] +; CHECK: xscvsxdsp 1, [[MOVEREG05]] } ; Function Attrs: nounwind @@ -183,8 +180,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfust ; CHECK: mtvsrwz [[MOVEREG07:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG07]] +; CHECK: xscvuxdsp 1, [[MOVEREG07]] } ; Function Attrs: nounwind @@ -236,8 +232,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfii ; CHECK: mtvsrwa [[MOVEREG09:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG09]] +; CHECK: xscvsxdsp 1, [[MOVEREG09]] } ; Function Attrs: nounwind @@ -289,8 +284,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfuij ; CHECK: mtvsrwz [[MOVEREG11:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG11]] +; CHECK: xscvuxdsp 1, [[MOVEREG11]] } ; Function Attrs: nounwind @@ -342,8 +336,7 @@ entry: ret float %conv ; CHECK-LABEL:@_Z7testfllx ; CHECK: mtvsrd [[MOVEREG13:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG13]] +; CHECK: xscvsxdsp 1, [[MOVEREG13]] } ; Function Attrs: nounwind @@ -395,8 +388,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z8testfully ; CHECK: mtvsrd [[MOVEREG15:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG15]] +; CHECK: xscvuxdsp 1, [[MOVEREG15]] } ; Function Attrs: nounwind diff --git a/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll b/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll new file mode 100644 index 000000000000..f5b0a3a59bf3 --- /dev/null +++ b/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll @@ -0,0 +1,137 @@ +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8 +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64 +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8 +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64 +; RUN: llc -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 + +define i128 @test_abs(ppc_fp128 %x) nounwind { +entry: +; PPC64-LABEL: test_abs: +; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]] +; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]] +; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]] +; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]] +; PPC64-DAG: li [[MASK_REG:[0-9]+]], 1 +; PPC64: sldi [[MASK_REG]], [[MASK_REG]], 63 +; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]]) +; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]]) +; PPC64: and [[FLIP_BIT:[0-9]+]], [[HI]], [[MASK_REG]] +; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]] +; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]] +; PPC64: blr + +; PPC64-P8-LABEL: test_abs: +; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2 +; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1 +; PPC64-P8-DAG: li [[MASK_REG:[0-9]+]], 1 +; PPC64-P8-DAG: sldi [[SHIFT_REG:[0-9]+]], [[MASK_REG]], 63 +; PPC64-P8: and [[FLIP_BIT:[0-9]+]], [[HI]], [[SHIFT_REG]] +; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]] +; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]] +; PPC64-P8: blr + +; PPC32-DAG: stfd 1, 24(1) +; PPC32-DAG: stfd 2, 16(1) +; PPC32: nop +; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1) +; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1) +; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1) +; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1) +; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI0]], 0, 0, 0 +; PPC32-DAG: xor [[HI0]], [[HI0]], [[FLIP_BIT]] +; PPC32-DAG: xor [[LO0]], [[LO0]], [[FLIP_BIT]] +; PPC32: blr + %0 = tail call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 %x) + %1 = bitcast ppc_fp128 %0 to i128 + ret i128 %1 +} + +define i128 @test_neg(ppc_fp128 %x) nounwind { +entry: +; PPC64-LABEL: test_neg: +; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]] +; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]] +; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]] +; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]] +; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1 +; PPC64-DAG: sldi [[FLIP_BIT]], [[FLIP_BIT]], 63 +; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]]) +; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]]) +; PPC64-NOT: BARRIER +; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]] +; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]] +; PPC64: blr + +; PPC64-P8-LABEL: test_neg: +; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2 +; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1 +; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1 +; PPC64-P8-DAG: sldi [[FLIP_BIT]], [[IMM1]], 63 +; PPC64-P8-NOT: BARRIER +; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]] +; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]] +; PPC64-P8: blr + +; PPC32-DAG: stfd 1, 24(1) +; PPC32-DAG: stfd 2, 16(1) +; PPC32: nop +; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1) +; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1) +; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1) +; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1) +; PPC32-NOT: BARRIER +; PPC32-DAG: xoris [[HI0]], [[HI0]], 32768 +; PPC32-DAG: xoris [[LO0]], [[LO0]], 32768 +; PPC32: blr + %0 = fsub ppc_fp128 0xM80000000000000000000000000000000, %x + %1 = bitcast ppc_fp128 %0 to i128 + ret i128 %1 +} + +define i128 @test_copysign(ppc_fp128 %x) nounwind { +entry: +; PPC64-LABEL: test_copysign: +; PPC64-DAG: stxsdx 1, 0, [[ADDR_REG:[0-9]+]] +; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]] +; PPC64-DAG: li [[SIGN:[0-9]+]], 1 +; PPC64-DAG: sldi [[SIGN]], [[SIGN]], 63 +; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399 +; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48 +; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019 +; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52 +; PPC64-NOT: BARRIER +; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1) +; PPC64-DAG: and [[NEW_HI_TMP:[0-9]+]], [[X_HI]], [[SIGN]] +; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]] +; PPC64-DAG: xor 4, [[SIGN]], [[CST_LO]] +; PPC64: blr + +; PPC64-P8-LABEL: test_copysign: +; PPC64-P8-DAG: mfvsrd [[X_HI:[0-9]+]], 1 +; PPC64-P8-DAG: li [[SIGN:[0-9]+]], 1 +; PPC64-P8-DAG: sldi [[SIGN]], [[SIGN]], 63 +; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399 +; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48 +; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019 +; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52 +; PPC64-P8-NOT: BARRIER +; PPC64-P8-DAG: and [[NEW_HI_TMP:[0-9]+]], [[X_HI]], [[SIGN]] +; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]] +; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]] +; PPC64-P8: blr + +; PPC32: stfd 1, [[STACK:[0-9]+]](1) +; PPC32: nop +; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1) +; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0 +; PPC32-NOT: BARRIER +; PPC32-DAG: oris {{[0-9]+}}, [[FLIP_BIT]], 16399 +; PPC32-DAG: xoris {{[0-9]+}}, [[FLIP_BIT]], 48304 +; PPC32: blr + %0 = tail call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xMBCB0000000000000400F000000000000, ppc_fp128 %x) + %1 = bitcast ppc_fp128 %0 to i128 + ret i128 %1 +} + +declare ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128) +declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128, ppc_fp128) diff --git a/test/CodeGen/PowerPC/load-shift-combine.ll b/test/CodeGen/PowerPC/load-shift-combine.ll index 8d1f8146db95..3b4685725216 100644 --- a/test/CodeGen/PowerPC/load-shift-combine.ll +++ b/test/CodeGen/PowerPC/load-shift-combine.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s +; REQUIRES: default_triple ; This used to cause a crash. A standard load is converted to a pre-increment ; load. Later the pre-increment load is combined with a subsequent SRL to diff --git a/test/CodeGen/PowerPC/long-compare.ll b/test/CodeGen/PowerPC/long-compare.ll index e53356a5ddf2..d596068cbb71 100644 --- a/test/CodeGen/PowerPC/long-compare.ll +++ b/test/CodeGen/PowerPC/long-compare.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 | grep cntlz +; RUN: llc < %s -march=ppc32 | grep cntlzw ; RUN: llc < %s -march=ppc32 | not grep xori ; RUN: llc < %s -march=ppc32 | not grep "li " ; RUN: llc < %s -march=ppc32 | not grep "mr " diff --git a/test/CodeGen/PowerPC/machine-combiner.ll b/test/CodeGen/PowerPC/machine-combiner.ll new file mode 100644 index 000000000000..93fb2020d530 --- /dev/null +++ b/test/CodeGen/PowerPC/machine-combiner.ll @@ -0,0 +1,188 @@ +; RUN: llc -O3 -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR +; RUN: llc -O3 -mcpu=a2q -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-QPX +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Verify that the first two adds are independent regardless of how the inputs are +; commuted. The destination registers are used as source registers for the third add. + +define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds1: +; CHECK: # BB#0: +; CHECK: fadds [[REG0:[0-9]+]], 1, 2 +; CHECK: fadds [[REG1:[0-9]+]], 3, 4 +; CHECK: fadds 1, [[REG0]], [[REG1]] +; CHECK-NEXT: blr + + %t0 = fadd float %x0, %x1 + %t1 = fadd float %t0, %x2 + %t2 = fadd float %t1, %x3 + ret float %t2 +} + +define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds2: +; CHECK: # BB#0: +; CHECK: fadds [[REG0:[0-9]+]], 1, 2 +; CHECK: fadds [[REG1:[0-9]+]], 3, 4 +; CHECK: fadds 1, [[REG0]], [[REG1]] +; CHECK-NEXT: blr + + %t0 = fadd float %x0, %x1 + %t1 = fadd float %x2, %t0 + %t2 = fadd float %t1, %x3 + ret float %t2 +} + +define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds3: +; CHECK: # BB#0: +; CHECK: fadds [[REG0:[0-9]+]], 1, 2 +; CHECK: fadds [[REG1:[0-9]+]], 3, 4 +; CHECK: fadds 1, [[REG0]], [[REG1]] +; CHECK-NEXT: blr + + %t0 = fadd float %x0, %x1 + %t1 = fadd float %t0, %x2 + %t2 = fadd float %x3, %t1 + ret float %t2 +} + +define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { +; CHECK-LABEL: reassociate_adds4: +; CHECK: # BB#0: +; CHECK: fadds [[REG0:[0-9]+]], 1, 2 +; CHECK: fadds [[REG1:[0-9]+]], 3, 4 +; CHECK: fadds 1, [[REG0]], [[REG1]] +; CHECK-NEXT: blr + + %t0 = fadd float %x0, %x1 + %t1 = fadd float %x2, %t0 + %t2 = fadd float %x3, %t1 + ret float %t2 +} + +; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not +; produced because that would cost more compile time. + +define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) { +; CHECK-LABEL: reassociate_adds5: +; CHECK: # BB#0: +; CHECK: fadds [[REG12:[0-9]+]], 5, 6 +; CHECK: fadds [[REG0:[0-9]+]], 1, 2 +; CHECK: fadds [[REG11:[0-9]+]], 3, 4 +; CHECK: fadds [[REG13:[0-9]+]], [[REG12]], 7 +; CHECK: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]] +; CHECK: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]] +; CHECK: fadds 1, [[REG2]], 8 +; CHECK-NEXT: blr + + %t0 = fadd float %x0, %x1 + %t1 = fadd float %t0, %x2 + %t2 = fadd float %t1, %x3 + %t3 = fadd float %t2, %x4 + %t4 = fadd float %t3, %x5 + %t5 = fadd float %t4, %x6 + %t6 = fadd float %t5, %x7 + ret float %t6 +} + +; Verify that we reassociate vector instructions too. + +define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { +; CHECK-LABEL: vector_reassociate_adds1: +; CHECK: # BB#0: +; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 +; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 +; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] +; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 +; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 +; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] +; CHECK-NEXT: blr + + %t0 = fadd <4 x float> %x0, %x1 + %t1 = fadd <4 x float> %t0, %x2 + %t2 = fadd <4 x float> %t1, %x3 + ret <4 x float> %t2 +} + +define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { +; CHECK-LABEL: vector_reassociate_adds2: +; CHECK: # BB#0: +; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 +; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 +; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] +; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 +; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 +; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] +; CHECK-NEXT: blr + + %t0 = fadd <4 x float> %x0, %x1 + %t1 = fadd <4 x float> %x2, %t0 + %t2 = fadd <4 x float> %t1, %x3 + ret <4 x float> %t2 +} + +define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { +; CHECK-LABEL: vector_reassociate_adds3: +; CHECK: # BB#0: +; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 +; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 +; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] +; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 +; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 +; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] +; CHECK-NEXT: blr + + %t0 = fadd <4 x float> %x0, %x1 + %t1 = fadd <4 x float> %t0, %x2 + %t2 = fadd <4 x float> %x3, %t1 + ret <4 x float> %t2 +} + +define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { +; CHECK-LABEL: vector_reassociate_adds4: +; CHECK: # BB#0: +; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 +; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 +; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] +; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 +; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 +; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] +; CHECK-NEXT: blr + + %t0 = fadd <4 x float> %x0, %x1 + %t1 = fadd <4 x float> %x2, %t0 + %t2 = fadd <4 x float> %x3, %t1 + ret <4 x float> %t2 +} + +define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) { + %t0 = fdiv float %x0, %x1 + %t1 = fadd float %x2, %t0 + %t2 = fadd float %x3, %t1 + ret float %t2 +} + +define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) { + %t0 = fdiv float %x0, %x1 + %t1 = fmul float %x2, %t0 + %t2 = fmul float %x3, %t1 + ret float %t2 +} + +define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) { + %t0 = fdiv double %x0, %x1 + %t1 = fadd double %x2, %t0 + %t2 = fadd double %x3, %t1 + ret double %t2 +} + +define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) { + %t0 = fdiv double %x0, %x1 + %t1 = fmul double %x2, %t0 + %t2 = fmul double %x3, %t1 + ret double %t2 +} + + diff --git a/test/CodeGen/PowerPC/mc-instrlat.ll b/test/CodeGen/PowerPC/mc-instrlat.ll new file mode 100644 index 000000000000..0bbac14f6d3e --- /dev/null +++ b/test/CodeGen/PowerPC/mc-instrlat.ll @@ -0,0 +1,25 @@ +; RUN: llc -O3 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo(double %eps) #0 { +entry: + %0 = fmul fast double %eps, %eps + %div = fmul fast double %0, 0x3FD5555555555555 + tail call void @bar(double %div) #2 + unreachable + +; This used to crash because we'd call a function to compute instruction +; latency not supported with itineraries. +; CHECK-LABEL: @foo +; CHECK: bar + +} + +declare void @bar(double) #1 + +attributes #0 = { nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "target-cpu"="ppc64" "target-features"="+altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-qpx,-vsx" "unsafe-fp-math"="true" "use-soft-float"="false" } +attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64" "target-features"="+altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-qpx,-vsx" "unsafe-fp-math"="true" "use-soft-float"="false" } +attributes #2 = { nounwind } + diff --git a/test/CodeGen/PowerPC/mcm-13.ll b/test/CodeGen/PowerPC/mcm-13.ll new file mode 100644 index 000000000000..ba371c5026c1 --- /dev/null +++ b/test/CodeGen/PowerPC/mcm-13.ll @@ -0,0 +1,27 @@ +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s + +; Test correct code generation for medium and large code model +; for loading and storing a weak variable + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@wi = weak global i32 0, align 4 + +define signext i32 @test_weak() nounwind { +entry: + %0 = load i32, i32* @wi, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* @wi, align 4 + ret i32 %0 +} + +; CHECK-LABEL: test_weak: +; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha +; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) +; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) +; CHECK: stw {{[0-9]+}}, 0([[REG2]]) +; CHECK: .section .toc +; CHECK: .LC[[TOCNUM]]: +; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} diff --git a/test/CodeGen/PowerPC/memcpy-vec.ll b/test/CodeGen/PowerPC/memcpy-vec.ll index 70b8ea931a27..29baef55ce17 100644 --- a/test/CodeGen/PowerPC/memcpy-vec.ll +++ b/test/CodeGen/PowerPC/memcpy-vec.ll @@ -14,8 +14,11 @@ entry: ; PWR7-LABEL: @foo1 ; PWR7-NOT: bl memcpy -; PWR7: ld {{[0-9]+}}, {{[0-9]+}}(4) -; PWR7: std {{[0-9]+}}, {{[0-9]+}}(3) +; PWR7-DAG: li [[OFFSET:[0-9]+]], 16 +; PWR7-DAG: lxvd2x [[TMP0:[0-9]+]], 4, [[OFFSET]] +; PWR7-DAG: stxvd2x [[TMP0]], 0, 3 +; PWR7-DAG: lxvd2x [[TMP1:[0-9]+]], 0, 4 +; PWR7-DAG: stxvd2x [[TMP1]], 0, 3 ; PWR7: blr ; PWR8-LABEL: @foo1 diff --git a/test/CodeGen/PowerPC/merge-st-chain-op.ll b/test/CodeGen/PowerPC/merge-st-chain-op.ll new file mode 100644 index 000000000000..bfb911c01157 --- /dev/null +++ b/test/CodeGen/PowerPC/merge-st-chain-op.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@_ZNSs4_Rep20_S_empty_rep_storageE = external global [0 x i64], align 8 + +; Function Attrs: nounwind +define void @_ZN5clang7tooling15RefactoringTool10runAndSaveEPNS0_21FrontendActionFactoryE() #0 align 2 { +entry: + br i1 undef, label %_ZN4llvm18IntrusiveRefCntPtrIN5clang13DiagnosticIDsEEC2EPS2_.exit, label %return + +; CHECK: @_ZN5clang7tooling15RefactoringTool10runAndSaveEPNS0_21FrontendActionFactoryE + +_ZN4llvm18IntrusiveRefCntPtrIN5clang13DiagnosticIDsEEC2EPS2_.exit: ; preds = %entry + %call2 = call noalias i8* @_Znwm() #3 + %ref_cnt.i.i = bitcast i8* %call2 to i32* + store <2 x i8*> <i8* bitcast (i64* getelementptr inbounds ([0 x i64], [0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*), i8* bitcast (i64* getelementptr inbounds ([0 x i64], [0 x i64]* @_ZNSs4_Rep20_S_empty_rep_storageE, i64 0, i64 3) to i8*)>, <2 x i8*>* undef, align 8 + %IgnoreWarnings.i = getelementptr inbounds i8, i8* %call2, i64 4 + %0 = bitcast i8* %IgnoreWarnings.i to i32* + call void @llvm.memset.p0i8.i64(i8* null, i8 0, i64 48, i32 8, i1 false) #4 + store i32 251658240, i32* %0, align 4 + store i256 37662610426935100959726589394453639584271499769928088551424, i256* null, align 8 + store i32 1, i32* %ref_cnt.i.i, align 4 + unreachable + +return: ; preds = %entry + ret void +} + +; Function Attrs: nobuiltin +declare noalias i8* @_Znwm() #1 + +; Function Attrs: nounwind argmemonly +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #2 + +attributes #0 = { nounwind "target-cpu"="pwr7" } +attributes #1 = { nobuiltin "target-cpu"="pwr7" } +attributes #2 = { nounwind argmemonly } +attributes #3 = { builtin nounwind } +attributes #4 = { nounwind } + diff --git a/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll new file mode 100644 index 000000000000..8da8df58a85c --- /dev/null +++ b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -0,0 +1,1476 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE + +; The build[csilf] functions simply test the scalar_to_vector handling with +; direct moves. This corresponds to the "insertelement" instruction. Subsequent +; to this, there will be a splat corresponding to the shufflevector. + +@d = common global double 0.000000e+00, align 8 + +; Function Attrs: nounwind +define <16 x i8> @buildc(i8 zeroext %a) { +entry: + %a.addr = alloca i8, align 1 + store i8 %a, i8* %a.addr, align 1 + %0 = load i8, i8* %a.addr, align 1 + %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0 + %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer + ret <16 x i8> %splat.splat +; CHECK: sldi [[REG1:[0-9]+]], 3, 56 +; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +} + +; Function Attrs: nounwind +define <8 x i16> @builds(i16 zeroext %a) { +entry: + %a.addr = alloca i16, align 2 + store i16 %a, i16* %a.addr, align 2 + %0 = load i16, i16* %a.addr, align 2 + %splat.splatinsert = insertelement <8 x i16> undef, i16 %0, i32 0 + %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer + ret <8 x i16> %splat.splat +; CHECK: sldi [[REG1:[0-9]+]], 3, 48 +; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +} + +; Function Attrs: nounwind +define <4 x i32> @buildi(i32 zeroext %a) { +entry: + %a.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + %0 = load i32, i32* %a.addr, align 4 + %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 + %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + ret <4 x i32> %splat.splat +; CHECK: sldi [[REG1:[0-9]+]], 3, 32 +; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +} + +; Function Attrs: nounwind +define <2 x i64> @buildl(i64 %a) { +entry: + %a.addr = alloca i64, align 8 + store i64 %a, i64* %a.addr, align 8 + %0 = load i64, i64* %a.addr, align 8 + %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 + %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer + ret <2 x i64> %splat.splat +; CHECK: mtvsrd {{[0-9]+}}, 3 +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxspltd [[REG1]], [[REG1]], 0 +} + +; Function Attrs: nounwind +define <4 x float> @buildf(float %a) { +entry: + %a.addr = alloca float, align 4 + store float %a, float* %a.addr, align 4 + %0 = load float, float* %a.addr, align 4 + %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 + %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer + ret <4 x float> %splat.splat +; CHECK: xscvdpspn {{[0-9]+}}, 1 +; CHECK-LE: xscvdpspn [[REG1:[0-9]+]], 1 +; CHECK-LE: xxsldwi {{[0-9]+}}, [[REG1]], [[REG1]], 1 +} + +; The optimization to remove stack operations from PPCDAGToDAGISel::Select +; should still trigger for v2f64, producing an lxvdsx. +; Function Attrs: nounwind +define <2 x double> @buildd() #0 { +entry: + %0 = load double, double* @d, align 8 + %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0 + %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer + ret <2 x double> %splat.splat +; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l +; CHECK: lxvdsx 34, 0, [[REG1]] +; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l +; CHECK-LE: lxvdsx 34, 0, [[REG1]] +} + +; Function Attrs: nounwind +define signext i8 @getsc0(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 0 + ret i8 %vecext +; CHECK-LABEL: @getsc0 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 8, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc0 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: clrldi 3, 3, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc1(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 1 + ret i8 %vecext +; CHECK-LABEL: @getsc1 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 16, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc1 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 56, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc2(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 2 + ret i8 %vecext +; CHECK-LABEL: @getsc2 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 24, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc2 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 48, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc3(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 3 + ret i8 %vecext +; CHECK-LABEL: @getsc3 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 32, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc3 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 40, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc4(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 4 + ret i8 %vecext +; CHECK-LABEL: @getsc4 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 40, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc4 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 32, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc5(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 5 + ret i8 %vecext +; CHECK-LABEL: @getsc5 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 48, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc5 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 24, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc6(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 6 + ret i8 %vecext +; CHECK-LABEL: @getsc6 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 56, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc6 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 16, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc7(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 7 + ret i8 %vecext +; CHECK-LABEL: @getsc7 +; CHECK: mfvsrd 3, 34 +; CHECK: clrldi 3, 3, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc7 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 8, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc8(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 8 + ret i8 %vecext +; CHECK-LABEL: @getsc8 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 8, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc8 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: clrldi 3, 3, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc9(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 9 + ret i8 %vecext +; CHECK-LABEL: @getsc9 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 16, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc9 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 56, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc10(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 10 + ret i8 %vecext +; CHECK-LABEL: @getsc10 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 24, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc10 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 48, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc11(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 11 + ret i8 %vecext +; CHECK-LABEL: @getsc11 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 32, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc11 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 40, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc12(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 12 + ret i8 %vecext +; CHECK-LABEL: @getsc12 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 40, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc12 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 32, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc13(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 13 + ret i8 %vecext +; CHECK-LABEL: @getsc13 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 48, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc13 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 24, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc14(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 14 + ret i8 %vecext +; CHECK-LABEL: @getsc14 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 56, 56 +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc14 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 16, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define signext i8 @getsc15(<16 x i8> %vsc) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 15 + ret i8 %vecext +; CHECK-LABEL: @getsc15 +; CHECK: mfvsrd 3, +; CHECK: extsb 3, 3 +; CHECK-LE-LABEL: @getsc15 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 8, 56 +; CHECK-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc0(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 0 + ret i8 %vecext +; CHECK-LABEL: @getuc0 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 8, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc0 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc1(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 1 + ret i8 %vecext +; CHECK-LABEL: @getuc1 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 16, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc1 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 56, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc2(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 2 + ret i8 %vecext +; CHECK-LABEL: @getuc2 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 24, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc2 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 48, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc3(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 3 + ret i8 %vecext +; CHECK-LABEL: @getuc3 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 32, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc3 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 40, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc4(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 4 + ret i8 %vecext +; CHECK-LABEL: @getuc4 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 40, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc4 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 32, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc5(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 5 + ret i8 %vecext +; CHECK-LABEL: @getuc5 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 48, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc5 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 24, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc6(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 6 + ret i8 %vecext +; CHECK-LABEL: @getuc6 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 56, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc6 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 16, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc7(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 7 + ret i8 %vecext +; CHECK-LABEL: @getuc7 +; CHECK: mfvsrd 3, 34 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc7 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 8, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc8(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 8 + ret i8 %vecext +; CHECK-LABEL: @getuc8 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 8, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc8 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc9(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 9 + ret i8 %vecext +; CHECK-LABEL: @getuc9 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 16, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc9 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 56, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc10(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 10 + ret i8 %vecext +; CHECK-LABEL: @getuc10 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 24, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc10 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 48, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc11(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 11 + ret i8 %vecext +; CHECK-LABEL: @getuc11 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 32, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc11 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 40, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc12(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 12 + ret i8 %vecext +; CHECK-LABEL: @getuc12 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 40, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc12 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 32, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc13(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 13 + ret i8 %vecext +; CHECK-LABEL: @getuc13 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 48, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc13 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 24, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc14(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 14 + ret i8 %vecext +; CHECK-LABEL: @getuc14 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 56, 56 +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc14 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 16, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define zeroext i8 @getuc15(<16 x i8> %vuc) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %vecext = extractelement <16 x i8> %0, i32 15 + ret i8 %vecext +; CHECK-LABEL: @getuc15 +; CHECK: mfvsrd 3, +; CHECK: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getuc15 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 8, 56 +; CHECK-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) { +entry: + %vsc.addr = alloca <16 x i8>, align 16 + %i.addr = alloca i32, align 4 + store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <16 x i8> %0, i32 %1 + ret i8 %vecext +; CHECK-LABEL: @getvelsc +; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8 +; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]] +; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] +; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], +; CHECK-DAG: li [[IMM7:[0-9]+]], 7 +; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]] +; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3 +; CHECK-DAG: srd 3, [[MOV]], [[SHL]] +; CHECK-DAG: extsb 3, 3 +; CHECK-LE-LABEL: @getvelsc +; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8 +; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]] +; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]] +; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] +; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], +; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7 +; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]] +; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3 +; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] +; CHECK-DAG-LE: extsb 3, 3 +} + +; Function Attrs: nounwind +define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) { +entry: + %vuc.addr = alloca <16 x i8>, align 16 + %i.addr = alloca i32, align 4 + store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <16 x i8> %0, i32 %1 + ret i8 %vecext +; CHECK-LABEL: @getveluc +; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8 +; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]] +; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] +; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], +; CHECK-DAG: li [[IMM7:[0-9]+]], 7 +; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]] +; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3 +; CHECK-DAG: srd 3, [[MOV]], [[SHL]] +; CHECK-DAG: clrldi 3, 3, 56 +; CHECK-LE-LABEL: @getveluc +; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8 +; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]] +; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]] +; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] +; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], +; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7 +; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]] +; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3 +; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] +; CHECK-DAG-LE: clrldi 3, 3, 56 +} + +; Function Attrs: nounwind +define signext i16 @getss0(<8 x i16> %vss) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 0 + ret i16 %vecext +; CHECK-LABEL: @getss0 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 16, 48 +; CHECK: extsh 3, 3 +; CHECK-LE-LABEL: @getss0 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: clrldi 3, 3, 48 +; CHECK-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define signext i16 @getss1(<8 x i16> %vss) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 1 + ret i16 %vecext +; CHECK-LABEL: @getss1 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 32, 48 +; CHECK: extsh 3, 3 +; CHECK-LE-LABEL: @getss1 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 48, 48 +; CHECK-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define signext i16 @getss2(<8 x i16> %vss) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 2 + ret i16 %vecext +; CHECK-LABEL: @getss2 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 48, 48 +; CHECK: extsh 3, 3 +; CHECK-LE-LABEL: @getss2 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 32, 48 +; CHECK-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define signext i16 @getss3(<8 x i16> %vss) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 3 + ret i16 %vecext +; CHECK-LABEL: @getss3 +; CHECK: mfvsrd 3, 34 +; CHECK: clrldi 3, 3, 48 +; CHECK: extsh 3, 3 +; CHECK-LE-LABEL: @getss3 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 16, 48 +; CHECK-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define signext i16 @getss4(<8 x i16> %vss) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 4 + ret i16 %vecext +; CHECK-LABEL: @getss4 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 16, 48 +; CHECK: extsh 3, 3 +; CHECK-LE-LABEL: @getss4 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: clrldi 3, 3, 48 +; CHECK-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define signext i16 @getss5(<8 x i16> %vss) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 5 + ret i16 %vecext +; CHECK-LABEL: @getss5 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 32, 48 +; CHECK: extsh 3, 3 +; CHECK-LE-LABEL: @getss5 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 48, 48 +; CHECK-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define signext i16 @getss6(<8 x i16> %vss) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 6 + ret i16 %vecext +; CHECK-LABEL: @getss6 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 48, 48 +; CHECK: extsh 3, 3 +; CHECK-LE-LABEL: @getss6 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 32, 48 +; CHECK-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define signext i16 @getss7(<8 x i16> %vss) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 7 + ret i16 %vecext +; CHECK-LABEL: @getss7 +; CHECK: mfvsrd 3, +; CHECK: extsh 3, 3 +; CHECK-LE-LABEL: @getss7 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 16, 48 +; CHECK-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define zeroext i16 @getus0(<8 x i16> %vus) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 0 + ret i16 %vecext +; CHECK-LABEL: @getus0 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 16, 48 +; CHECK: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getus0 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define zeroext i16 @getus1(<8 x i16> %vus) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 1 + ret i16 %vecext +; CHECK-LABEL: @getus1 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 32, 48 +; CHECK: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getus1 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 48, 48 +; CHECK-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define zeroext i16 @getus2(<8 x i16> %vus) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 2 + ret i16 %vecext +; CHECK-LABEL: @getus2 +; CHECK: mfvsrd 3, 34 +; CHECK: rldicl 3, 3, 48, 48 +; CHECK: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getus2 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 32, 48 +; CHECK-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define zeroext i16 @getus3(<8 x i16> %vus) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 3 + ret i16 %vecext +; CHECK-LABEL: @getus3 +; CHECK: mfvsrd 3, 34 +; CHECK: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getus3 +; CHECK-LE: mfvsrd 3, +; CHECK-LE: rldicl 3, 3, 16, 48 +; CHECK-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define zeroext i16 @getus4(<8 x i16> %vus) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 4 + ret i16 %vecext +; CHECK-LABEL: @getus4 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 16, 48 +; CHECK: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getus4 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define zeroext i16 @getus5(<8 x i16> %vus) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 5 + ret i16 %vecext +; CHECK-LABEL: @getus5 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 32, 48 +; CHECK: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getus5 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 48, 48 +; CHECK-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define zeroext i16 @getus6(<8 x i16> %vus) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 6 + ret i16 %vecext +; CHECK-LABEL: @getus6 +; CHECK: mfvsrd 3, +; CHECK: rldicl 3, 3, 48, 48 +; CHECK: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getus6 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 32, 48 +; CHECK-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define zeroext i16 @getus7(<8 x i16> %vus) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %vecext = extractelement <8 x i16> %0, i32 7 + ret i16 %vecext +; CHECK-LABEL: @getus7 +; CHECK: mfvsrd 3, +; CHECK: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getus7 +; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: rldicl 3, 3, 16, 48 +; CHECK-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) { +entry: + %vss.addr = alloca <8 x i16>, align 16 + %i.addr = alloca i32, align 4 + store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <8 x i16> %0, i32 %1 + ret i16 %vecext +; CHECK-LABEL: @getvelss +; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4 +; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1 +; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] +; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] +; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], +; CHECK-DAG: li [[IMM3:[0-9]+]], 3 +; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]] +; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4 +; CHECK-DAG: srd 3, [[MOV]], [[SHL]] +; CHECK-DAG: extsh 3, 3 +; CHECK-LE-LABEL: @getvelss +; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4 +; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]] +; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1 +; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] +; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] +; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], +; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3 +; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]] +; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4 +; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] +; CHECK-DAG-LE: extsh 3, 3 +} + +; Function Attrs: nounwind +define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) { +entry: + %vus.addr = alloca <8 x i16>, align 16 + %i.addr = alloca i32, align 4 + store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <8 x i16> %0, i32 %1 + ret i16 %vecext +; CHECK-LABEL: @getvelus +; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4 +; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1 +; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] +; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] +; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], +; CHECK-DAG: li [[IMM3:[0-9]+]], 3 +; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]] +; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4 +; CHECK-DAG: srd 3, [[MOV]], [[SHL]] +; CHECK-DAG: clrldi 3, 3, 48 +; CHECK-LE-LABEL: @getvelus +; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4 +; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]] +; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1 +; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] +; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] +; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], +; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3 +; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]] +; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4 +; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] +; CHECK-DAG-LE: clrldi 3, 3, 48 +} + +; Function Attrs: nounwind +define signext i32 @getsi0(<4 x i32> %vsi) { +entry: + %vsi.addr = alloca <4 x i32>, align 16 + store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 + %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 + %vecext = extractelement <4 x i32> %0, i32 0 + ret i32 %vecext +; CHECK-LABEL: @getsi0 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 +; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: extsw 3, 3 +; CHECK-LE-LABEL: @getsi0 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 2 +; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: extsw 3, 3 +} + +; Function Attrs: nounwind +define signext i32 @getsi1(<4 x i32> %vsi) { +entry: + %vsi.addr = alloca <4 x i32>, align 16 + store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 + %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 + %vecext = extractelement <4 x i32> %0, i32 1 + ret i32 %vecext +; CHECK-LABEL: @getsi1 +; CHECK: mfvsrwz 3, 34 +; CHECK: extsw 3, 3 +; CHECK-LE-LABEL: @getsi1 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 +; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: extsw 3, 3 +} + +; Function Attrs: nounwind +define signext i32 @getsi2(<4 x i32> %vsi) { +entry: + %vsi.addr = alloca <4 x i32>, align 16 + store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 + %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 + %vecext = extractelement <4 x i32> %0, i32 2 + ret i32 %vecext +; CHECK-LABEL: @getsi2 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 +; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: extsw 3, 3 +; CHECK-LE-LABEL: @getsi2 +; CHECK-LE: mfvsrwz 3, 34 +; CHECK-LE: extsw 3, 3 +} + +; Function Attrs: nounwind +define signext i32 @getsi3(<4 x i32> %vsi) { +entry: + %vsi.addr = alloca <4 x i32>, align 16 + store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 + %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 + %vecext = extractelement <4 x i32> %0, i32 3 + ret i32 %vecext +; CHECK-LABEL: @getsi3 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 2 +; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: extsw 3, 3 +; CHECK-LE-LABEL: @getsi3 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 +; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: extsw 3, 3 +} + +; Function Attrs: nounwind +define zeroext i32 @getui0(<4 x i32> %vui) { +entry: + %vui.addr = alloca <4 x i32>, align 16 + store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 + %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 + %vecext = extractelement <4 x i32> %0, i32 0 + ret i32 %vecext +; CHECK-LABEL: @getui0 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 +; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: clrldi 3, 3, 32 +; CHECK-LE-LABEL: @getui0 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 2 +; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: clrldi 3, 3, 32 +} + +; Function Attrs: nounwind +define zeroext i32 @getui1(<4 x i32> %vui) { +entry: + %vui.addr = alloca <4 x i32>, align 16 + store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 + %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 + %vecext = extractelement <4 x i32> %0, i32 1 + ret i32 %vecext +; CHECK-LABEL: @getui1 +; CHECK: mfvsrwz 3, 34 +; CHECK: clrldi 3, 3, 32 +; CHECK-LE-LABEL: @getui1 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 +; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: clrldi 3, 3, 32 +} + +; Function Attrs: nounwind +define zeroext i32 @getui2(<4 x i32> %vui) { +entry: + %vui.addr = alloca <4 x i32>, align 16 + store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 + %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 + %vecext = extractelement <4 x i32> %0, i32 2 + ret i32 %vecext +; CHECK-LABEL: @getui2 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 +; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: clrldi 3, 3, 32 +; CHECK-LE-LABEL: @getui2 +; CHECK-LE: mfvsrwz 3, 34 +; CHECK-LE: clrldi 3, 3, 32 +} + +; Function Attrs: nounwind +define zeroext i32 @getui3(<4 x i32> %vui) { +entry: + %vui.addr = alloca <4 x i32>, align 16 + store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 + %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 + %vecext = extractelement <4 x i32> %0, i32 3 + ret i32 %vecext +; CHECK-LABEL: @getui3 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 2 +; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: clrldi 3, 3, 32 +; CHECK-LE-LABEL: @getui3 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 +; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: clrldi 3, 3, 32 +} + +; Function Attrs: nounwind +define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) { +entry: + %vsi.addr = alloca <4 x i32>, align 16 + %i.addr = alloca i32, align 4 + store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <4 x i32> %0, i32 %1 + ret i32 %vecext +; CHECK-LABEL: @getvelsi +; CHECK-LE-LABEL: @getvelsi +; FIXME: add check patterns when variable element extraction is implemented +} + +; Function Attrs: nounwind +define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) { +entry: + %vui.addr = alloca <4 x i32>, align 16 + %i.addr = alloca i32, align 4 + store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <4 x i32> %0, i32 %1 + ret i32 %vecext +; CHECK-LABEL: @getvelui +; CHECK-LE-LABEL: @getvelui +; FIXME: add check patterns when variable element extraction is implemented +} + +; Function Attrs: nounwind +define i64 @getsl0(<2 x i64> %vsl) { +entry: + %vsl.addr = alloca <2 x i64>, align 16 + store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 + %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 + %vecext = extractelement <2 x i64> %0, i32 0 + ret i64 %vecext +; CHECK-LABEL: @getsl0 +; CHECK: mfvsrd 3, 34 +; CHECK-LE-LABEL: @getsl0 +; CHECK-LE: xxswapd [[SWP:[0-9]+]], 34 +; CHECK-LE: mfvsrd 3, [[SWP]] +} + +; Function Attrs: nounwind +define i64 @getsl1(<2 x i64> %vsl) { +entry: + %vsl.addr = alloca <2 x i64>, align 16 + store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 + %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 + %vecext = extractelement <2 x i64> %0, i32 1 + ret i64 %vecext +; CHECK-LABEL: @getsl1 +; CHECK: xxswapd [[SWP:[0-9]+]], 34 +; CHECK: mfvsrd 3, [[SWP]] +; CHECK-LE-LABEL: @getsl1 +; CHECK-LE: mfvsrd 3, 34 +} + +; Function Attrs: nounwind +define i64 @getul0(<2 x i64> %vul) { +entry: + %vul.addr = alloca <2 x i64>, align 16 + store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 + %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 + %vecext = extractelement <2 x i64> %0, i32 0 + ret i64 %vecext +; CHECK-LABEL: @getul0 +; CHECK: mfvsrd 3, 34 +; CHECK-LE-LABEL: @getul0 +; CHECK-LE: xxswapd [[SWP:[0-9]+]], 34 +; CHECK-LE: mfvsrd 3, [[SWP]] +} + +; Function Attrs: nounwind +define i64 @getul1(<2 x i64> %vul) { +entry: + %vul.addr = alloca <2 x i64>, align 16 + store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 + %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 + %vecext = extractelement <2 x i64> %0, i32 1 + ret i64 %vecext +; CHECK-LABEL: @getul1 +; CHECK: xxswapd [[SWP:[0-9]+]], 34 +; CHECK: mfvsrd 3, [[SWP]] +; CHECK-LE-LABEL: @getul1 +; CHECK-LE: mfvsrd 3, 34 +} + +; Function Attrs: nounwind +define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) { +entry: + %vsl.addr = alloca <2 x i64>, align 16 + %i.addr = alloca i32, align 4 + store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <2 x i64> %0, i32 %1 + ret i64 %vecext +; CHECK-LABEL: @getvelsl +; CHECK-LE-LABEL: @getvelsl +; FIXME: add check patterns when variable element extraction is implemented +} + +; Function Attrs: nounwind +define i64 @getvelul(<2 x i64> %vul, i32 signext %i) { +entry: + %vul.addr = alloca <2 x i64>, align 16 + %i.addr = alloca i32, align 4 + store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <2 x i64> %0, i32 %1 + ret i64 %vecext +; CHECK-LABEL: @getvelul +; CHECK-LE-LABEL: @getvelul +; FIXME: add check patterns when variable element extraction is implemented +} + +; Function Attrs: nounwind +define float @getf0(<4 x float> %vf) { +entry: + %vf.addr = alloca <4 x float>, align 16 + store <4 x float> %vf, <4 x float>* %vf.addr, align 16 + %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 + %vecext = extractelement <4 x float> %0, i32 0 + ret float %vecext +; CHECK-LABEL: @getf0 +; CHECK: xscvspdpn 1, 34 +; CHECK-LE-LABEL: @getf0 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 +; CHECK-LE: xscvspdpn 1, [[SHL]] +} + +; Function Attrs: nounwind +define float @getf1(<4 x float> %vf) { +entry: + %vf.addr = alloca <4 x float>, align 16 + store <4 x float> %vf, <4 x float>* %vf.addr, align 16 + %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 + %vecext = extractelement <4 x float> %0, i32 1 + ret float %vecext +; CHECK-LABEL: @getf1 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 +; CHECK: xscvspdpn 1, [[SHL]] +; CHECK-LE-LABEL: @getf1 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 2 +; CHECK-LE: xscvspdpn 1, [[SHL]] +} + +; Function Attrs: nounwind +define float @getf2(<4 x float> %vf) { +entry: + %vf.addr = alloca <4 x float>, align 16 + store <4 x float> %vf, <4 x float>* %vf.addr, align 16 + %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 + %vecext = extractelement <4 x float> %0, i32 2 + ret float %vecext +; CHECK-LABEL: @getf2 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 2 +; CHECK: xscvspdpn 1, [[SHL]] +; CHECK-LE-LABEL: @getf2 +; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 +; CHECK-LE: xscvspdpn 1, [[SHL]] +} + +; Function Attrs: nounwind +define float @getf3(<4 x float> %vf) { +entry: + %vf.addr = alloca <4 x float>, align 16 + store <4 x float> %vf, <4 x float>* %vf.addr, align 16 + %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 + %vecext = extractelement <4 x float> %0, i32 3 + ret float %vecext +; CHECK-LABEL: @getf3 +; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 +; CHECK: xscvspdpn 1, [[SHL]] +; CHECK-LE-LABEL: @getf3 +; CHECK-LE: xscvspdpn 1, 34 +} + +; Function Attrs: nounwind +define float @getvelf(<4 x float> %vf, i32 signext %i) { +entry: + %vf.addr = alloca <4 x float>, align 16 + %i.addr = alloca i32, align 4 + store <4 x float> %vf, <4 x float>* %vf.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <4 x float> %0, i32 %1 + ret float %vecext +; CHECK-LABEL: @getvelf +; CHECK-LE-LABEL: @getvelf +; FIXME: add check patterns when variable element extraction is implemented +} + +; Function Attrs: nounwind +define double @getd0(<2 x double> %vd) { +entry: + %vd.addr = alloca <2 x double>, align 16 + store <2 x double> %vd, <2 x double>* %vd.addr, align 16 + %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 + %vecext = extractelement <2 x double> %0, i32 0 + ret double %vecext +; CHECK-LABEL: @getd0 +; CHECK: xxlor 1, 34, 34 +; CHECK-LE-LABEL: @getd0 +; CHECK-LE: xxswapd 1, 34 +} + +; Function Attrs: nounwind +define double @getd1(<2 x double> %vd) { +entry: + %vd.addr = alloca <2 x double>, align 16 + store <2 x double> %vd, <2 x double>* %vd.addr, align 16 + %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 + %vecext = extractelement <2 x double> %0, i32 1 + ret double %vecext +; CHECK-LABEL: @getd1 +; CHECK: xxswapd 1, 34 +; CHECK-LE-LABEL: @getd1 +; CHECK-LE: xxlor 1, 34, 34 +} + +; Function Attrs: nounwind +define double @getveld(<2 x double> %vd, i32 signext %i) { +entry: + %vd.addr = alloca <2 x double>, align 16 + %i.addr = alloca i32, align 4 + store <2 x double> %vd, <2 x double>* %vd.addr, align 16 + store i32 %i, i32* %i.addr, align 4 + %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 + %1 = load i32, i32* %i.addr, align 4 + %vecext = extractelement <2 x double> %0, i32 %1 + ret double %vecext +; CHECK-LABEL: @getveld +; CHECK-LE-LABEL: @getveld +; FIXME: add check patterns when variable element extraction is implemented +} diff --git a/test/CodeGen/PowerPC/peephole-align.ll b/test/CodeGen/PowerPC/peephole-align.ll new file mode 100644 index 000000000000..c8c2fe4d32ce --- /dev/null +++ b/test/CodeGen/PowerPC/peephole-align.ll @@ -0,0 +1,335 @@ +; RUN: llc -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck -check-prefix=POWER7 -check-prefix=CHECK %s +; RUN: llc -mcpu=pwr8 -O1 -code-model=medium <%s | FileCheck -check-prefix=POWER8 -check-prefix=CHECK %s + +; Test peephole optimization for medium code model (32-bit TOC offsets) +; for loading and storing small offsets within aligned values. +; For power8, verify that the optimization doesn't fire, as it prevents fusion +; opportunities. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.b4 = type<{ i8, i8, i8, i8 }> +%struct.h2 = type<{ i16, i16 }> + +%struct.b8 = type<{ i8, i8, i8, i8, i8, i8, i8, i8 }> +%struct.h4 = type<{ i16, i16, i16, i16 }> +%struct.w2 = type<{ i32, i32 }> + +%struct.d2 = type<{ i64, i64 }> +%struct.misalign = type<{ i8, i64 }> + +@b4v = global %struct.b4 <{ i8 1, i8 2, i8 3, i8 4 }>, align 4 +@h2v = global %struct.h2 <{ i16 1, i16 2 }>, align 4 + +@b8v = global %struct.b8 <{ i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8 }>, align 8 +@h4v = global %struct.h4 <{ i16 1, i16 2, i16 3, i16 4 }>, align 8 +@w2v = global %struct.w2 <{ i32 1, i32 2 }>, align 8 + +@d2v = global %struct.d2 <{ i64 1, i64 2 }>, align 16 +@misalign_v = global %struct.misalign <{ i8 1, i64 2 }>, align 16 + +; CHECK-LABEL: test_b4: +; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, b4v@toc@ha +; POWER7-DAG: lbz [[REG0_0:[0-9]+]], b4v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG1_0:[0-9]+]], b4v@toc@l+1([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG2_0:[0-9]+]], b4v@toc@l+2([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG3_0:[0-9]+]], b4v@toc@l+3([[REGSTRUCT]]) +; POWER7-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER7-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER7-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 3 +; POWER7-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 4 +; POWER7-DAG: stb [[REG0_1]], b4v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG1_1]], b4v@toc@l+1([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG2_1]], b4v@toc@l+2([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG3_1]], b4v@toc@l+3([[REGSTRUCT]]) + +; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, b4v@toc@ha +; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], b4v@toc@l +; POWER8-DAG: lbz [[REG0_0:[0-9]+]], 0([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG1_0:[0-9]+]], 1([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG2_0:[0-9]+]], 2([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG3_0:[0-9]+]], 3([[REGSTRUCT]]) +; POWER8-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER8-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER8-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 3 +; POWER8-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 4 +; POWER8-DAG: stb [[REG0_1]], 0([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG1_1]], 1([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG2_1]], 2([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG3_1]], 3([[REGSTRUCT]]) +define void @test_b4() nounwind { +entry: + %0 = load i8, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 0), align 1 + %inc0 = add nsw i8 %0, 1 + store i8 %inc0, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 0), align 1 + %1 = load i8, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 1), align 1 + %inc1 = add nsw i8 %1, 2 + store i8 %inc1, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 1), align 1 + %2 = load i8, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 2), align 1 + %inc2 = add nsw i8 %2, 3 + store i8 %inc2, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 2), align 1 + %3 = load i8, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 3), align 1 + %inc3 = add nsw i8 %3, 4 + store i8 %inc3, i8* getelementptr inbounds (%struct.b4, %struct.b4* @b4v, i32 0, i32 3), align 1 + ret void +} + +; CHECK-LABEL: test_h2: +; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, h2v@toc@ha +; POWER7-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]]) +; POWER7-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER7-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER7-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]]) + +; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, h2v@toc@ha +; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], h2v@toc@l +; POWER8-DAG: lhz [[REG0_0:[0-9]+]], 0([[REGSTRUCT]]) +; POWER8-DAG: lhz [[REG1_0:[0-9]+]], 2([[REGSTRUCT]]) +; POWER8-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER8-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER8-DAG: sth [[REG0_1]], 0([[REGSTRUCT]]) +; POWER8-DAG: sth [[REG1_1]], 2([[REGSTRUCT]]) +define void @test_h2() nounwind { +entry: + %0 = load i16, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 0), align 2 + %inc0 = add nsw i16 %0, 1 + store i16 %inc0, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 0), align 2 + %1 = load i16, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 1), align 2 + %inc1 = add nsw i16 %1, 2 + store i16 %inc1, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 1), align 2 + ret void +} + +; CHECK-LABEL: test_h2_optsize: +; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, h2v@toc@ha +; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]]) +; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]]) +; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; CHECK-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]]) +; CHECK-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]]) +define void @test_h2_optsize() optsize nounwind { +entry: + %0 = load i16, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 0), align 2 + %inc0 = add nsw i16 %0, 1 + store i16 %inc0, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 0), align 2 + %1 = load i16, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 1), align 2 + %inc1 = add nsw i16 %1, 2 + store i16 %inc1, i16* getelementptr inbounds (%struct.h2, %struct.h2* @h2v, i32 0, i32 1), align 2 + ret void +} + +; CHECK-LABEL: test_b8: +; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, b8v@toc@ha +; POWER7-DAG: lbz [[REG0_0:[0-9]+]], b8v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG1_0:[0-9]+]], b8v@toc@l+1([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG2_0:[0-9]+]], b8v@toc@l+2([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG3_0:[0-9]+]], b8v@toc@l+3([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG4_0:[0-9]+]], b8v@toc@l+4([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG5_0:[0-9]+]], b8v@toc@l+5([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG6_0:[0-9]+]], b8v@toc@l+6([[REGSTRUCT]]) +; POWER7-DAG: lbz [[REG7_0:[0-9]+]], b8v@toc@l+7([[REGSTRUCT]]) +; POWER7-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER7-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER7-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 3 +; POWER7-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 4 +; POWER7-DAG: addi [[REG4_1:[0-9]+]], [[REG4_0]], 5 +; POWER7-DAG: addi [[REG5_1:[0-9]+]], [[REG5_0]], 6 +; POWER7-DAG: addi [[REG6_1:[0-9]+]], [[REG6_0]], 7 +; POWER7-DAG: addi [[REG7_1:[0-9]+]], [[REG7_0]], 8 +; POWER7-DAG: stb [[REG0_1]], b8v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG1_1]], b8v@toc@l+1([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG2_1]], b8v@toc@l+2([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG3_1]], b8v@toc@l+3([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG4_1]], b8v@toc@l+4([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG5_1]], b8v@toc@l+5([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG6_1]], b8v@toc@l+6([[REGSTRUCT]]) +; POWER7-DAG: stb [[REG7_1]], b8v@toc@l+7([[REGSTRUCT]]) + +; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, b8v@toc@ha +; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], b8v@toc@l +; POWER8-DAG: lbz [[REG0_0:[0-9]+]], 0([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG1_0:[0-9]+]], 1([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG2_0:[0-9]+]], 2([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG3_0:[0-9]+]], 3([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG4_0:[0-9]+]], 4([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG5_0:[0-9]+]], 5([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG6_0:[0-9]+]], 6([[REGSTRUCT]]) +; POWER8-DAG: lbz [[REG7_0:[0-9]+]], 7([[REGSTRUCT]]) +; POWER8-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER8-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER8-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 3 +; POWER8-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 4 +; POWER8-DAG: addi [[REG4_1:[0-9]+]], [[REG4_0]], 5 +; POWER8-DAG: addi [[REG5_1:[0-9]+]], [[REG5_0]], 6 +; POWER8-DAG: addi [[REG6_1:[0-9]+]], [[REG6_0]], 7 +; POWER8-DAG: addi [[REG7_1:[0-9]+]], [[REG7_0]], 8 +; POWER8-DAG: stb [[REG0_1]], 0([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG1_1]], 1([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG2_1]], 2([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG3_1]], 3([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG4_1]], 4([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG5_1]], 5([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG6_1]], 6([[REGSTRUCT]]) +; POWER8-DAG: stb [[REG7_1]], 7([[REGSTRUCT]]) +define void @test_b8() nounwind { +entry: + %0 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 0), align 1 + %inc0 = add nsw i8 %0, 1 + store i8 %inc0, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 0), align 1 + %1 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 1), align 1 + %inc1 = add nsw i8 %1, 2 + store i8 %inc1, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 1), align 1 + %2 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 2), align 1 + %inc2 = add nsw i8 %2, 3 + store i8 %inc2, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 2), align 1 + %3 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 3), align 1 + %inc3 = add nsw i8 %3, 4 + store i8 %inc3, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 3), align 1 + %4 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 4), align 1 + %inc4 = add nsw i8 %4, 5 + store i8 %inc4, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 4), align 1 + %5 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 5), align 1 + %inc5 = add nsw i8 %5, 6 + store i8 %inc5, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 5), align 1 + %6 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 6), align 1 + %inc6 = add nsw i8 %6, 7 + store i8 %inc6, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 6), align 1 + %7 = load i8, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 7), align 1 + %inc7 = add nsw i8 %7, 8 + store i8 %inc7, i8* getelementptr inbounds (%struct.b8, %struct.b8* @b8v, i32 0, i32 7), align 1 + ret void +} + +; CHECK-LABEL: test_h4: +; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, h4v@toc@ha +; POWER7-DAG: lhz [[REG0_0:[0-9]+]], h4v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: lhz [[REG1_0:[0-9]+]], h4v@toc@l+2([[REGSTRUCT]]) +; POWER7-DAG: lhz [[REG2_0:[0-9]+]], h4v@toc@l+4([[REGSTRUCT]]) +; POWER7-DAG: lhz [[REG3_0:[0-9]+]], h4v@toc@l+6([[REGSTRUCT]]) +; POWER7-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER7-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER7-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 3 +; POWER7-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 4 +; POWER7-DAG: sth [[REG0_1]], h4v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: sth [[REG1_1]], h4v@toc@l+2([[REGSTRUCT]]) +; POWER7-DAG: sth [[REG2_1]], h4v@toc@l+4([[REGSTRUCT]]) +; POWER7-DAG: sth [[REG3_1]], h4v@toc@l+6([[REGSTRUCT]]) + +; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, h4v@toc@ha +; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], h4v@toc@l +; POWER8-DAG: lhz [[REG0_0:[0-9]+]], 0([[REGSTRUCT]]) +; POWER8-DAG: lhz [[REG1_0:[0-9]+]], 2([[REGSTRUCT]]) +; POWER8-DAG: lhz [[REG2_0:[0-9]+]], 4([[REGSTRUCT]]) +; POWER8-DAG: lhz [[REG3_0:[0-9]+]], 6([[REGSTRUCT]]) +; POWER8-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER8-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER8-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 3 +; POWER8-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 4 +; POWER8-DAG: sth [[REG0_1]], 0([[REGSTRUCT]]) +; POWER8-DAG: sth [[REG1_1]], 2([[REGSTRUCT]]) +; POWER8-DAG: sth [[REG2_1]], 4([[REGSTRUCT]]) +; POWER8-DAG: sth [[REG3_1]], 6([[REGSTRUCT]]) +define void @test_h4() nounwind { +entry: + %0 = load i16, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 0), align 2 + %inc0 = add nsw i16 %0, 1 + store i16 %inc0, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 0), align 2 + %1 = load i16, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 1), align 2 + %inc1 = add nsw i16 %1, 2 + store i16 %inc1, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 1), align 2 + %2 = load i16, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 2), align 2 + %inc2 = add nsw i16 %2, 3 + store i16 %inc2, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 2), align 2 + %3 = load i16, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 3), align 2 + %inc3 = add nsw i16 %3, 4 + store i16 %inc3, i16* getelementptr inbounds (%struct.h4, %struct.h4* @h4v, i32 0, i32 3), align 2 + ret void +} + +; CHECK-LABEL: test_w2: +; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, w2v@toc@ha +; POWER7-DAG: lwz [[REG0_0:[0-9]+]], w2v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: lwz [[REG1_0:[0-9]+]], w2v@toc@l+4([[REGSTRUCT]]) +; POWER7-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER7-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER7-DAG: stw [[REG0_1]], w2v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: stw [[REG1_1]], w2v@toc@l+4([[REGSTRUCT]]) + +; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, w2v@toc@ha +; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], w2v@toc@l +; POWER8-DAG: lwz [[REG0_0:[0-9]+]], 0([[REGSTRUCT]]) +; POWER8-DAG: lwz [[REG1_0:[0-9]+]], 4([[REGSTRUCT]]) +; POWER8-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER8-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER8-DAG: stw [[REG0_1]], 0([[REGSTRUCT]]) +; POWER8-DAG: stw [[REG1_1]], 4([[REGSTRUCT]]) +define void @test_w2() nounwind { +entry: + %0 = load i32, i32* getelementptr inbounds (%struct.w2, %struct.w2* @w2v, i32 0, i32 0), align 4 + %inc0 = add nsw i32 %0, 1 + store i32 %inc0, i32* getelementptr inbounds (%struct.w2, %struct.w2* @w2v, i32 0, i32 0), align 4 + %1 = load i32, i32* getelementptr inbounds (%struct.w2, %struct.w2* @w2v, i32 0, i32 1), align 4 + %inc1 = add nsw i32 %1, 2 + store i32 %inc1, i32* getelementptr inbounds (%struct.w2, %struct.w2* @w2v, i32 0, i32 1), align 4 + ret void +} + +; CHECK-LABEL: test_d2: +; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, d2v@toc@ha +; POWER7-DAG: ld [[REG0_0:[0-9]+]], d2v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: ld [[REG1_0:[0-9]+]], d2v@toc@l+8([[REGSTRUCT]]) +; POWER7-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER7-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER7-DAG: std [[REG0_1]], d2v@toc@l([[REGSTRUCT]]) +; POWER7-DAG: std [[REG1_1]], d2v@toc@l+8([[REGSTRUCT]]) + +; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, d2v@toc@ha +; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], d2v@toc@l +; POWER8-DAG: ld [[REG0_0:[0-9]+]], 0([[REGSTRUCT]]) +; POWER8-DAG: ld [[REG1_0:[0-9]+]], 8([[REGSTRUCT]]) +; POWER8-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER8-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2 +; POWER8-DAG: std [[REG0_1]], 0([[REGSTRUCT]]) +; POWER8-DAG: std [[REG1_1]], 8([[REGSTRUCT]]) +define void @test_d2() nounwind { +entry: + %0 = load i64, i64* getelementptr inbounds (%struct.d2, %struct.d2* @d2v, i32 0, i32 0), align 8 + %inc0 = add nsw i64 %0, 1 + store i64 %inc0, i64* getelementptr inbounds (%struct.d2, %struct.d2* @d2v, i32 0, i32 0), align 8 + %1 = load i64, i64* getelementptr inbounds (%struct.d2, %struct.d2* @d2v, i32 0, i32 1), align 8 + %inc1 = add nsw i64 %1, 2 + store i64 %inc1, i64* getelementptr inbounds (%struct.d2, %struct.d2* @d2v, i32 0, i32 1), align 8 + ret void +} + +; Make sure the optimization fires on power8 if there is a single use resulting +; in a better fusion opportunity. +; register 3 is the return value, so it should be chosen +; CHECK-LABEL: test_singleuse: +; CHECK: addis 3, 2, d2v@toc@ha +; CHECK: ld 3, d2v@toc@l+8(3) +define i64 @test_singleuse() nounwind { +entry: + %0 = load i64, i64* getelementptr inbounds (%struct.d2, %struct.d2* @d2v, i32 0, i32 1), align 8 + ret i64 %0 +} + +; Make sure the optimization fails to fire if the symbol is aligned, but the offset is not. +; CHECK-LABEL: test_misalign +; POWER7: addis [[REGSTRUCT_0:[0-9]+]], 2, misalign_v@toc@ha +; POWER7: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v@toc@l +; POWER7: li [[OFFSET_REG:[0-9]+]], 1 +; POWER7: ldx [[REG0_0:[0-9]+]], [[REGSTRUCT]], [[OFFSET_REG]] +; POWER7: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1 +; POWER7: stdx [[REG0_1]], [[REGSTRUCT]], [[OFFSET_REG]] +define void @test_misalign() nounwind { +entry: + %0 = load i64, i64* getelementptr inbounds (%struct.misalign, %struct.misalign* @misalign_v, i32 0, i32 1), align 1 + %inc0 = add nsw i64 %0, 1 + store i64 %inc0, i64* getelementptr inbounds (%struct.misalign, %struct.misalign* @misalign_v, i32 0, i32 1), align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll new file mode 100644 index 000000000000..2f75190327ef --- /dev/null +++ b/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll @@ -0,0 +1,784 @@ +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE +; +; Note: Lots of tests use inline asm instead of regular calls. +; This allows to have a better control on what the allocation will do. +; Otherwise, we may have spill right in the entry block, defeating +; shrink-wrapping. Moreover, some of the inline asm statement (nop) +; are here to ensure that the related paths do not end up as critical +; edges. + + +; Initial motivating example: Simple diamond with a call just on one side. +; CHECK-LABEL: foo: +; +; Compare the arguments and return +; No prologue needed. +; ENABLE: cmpw 0, 3, 4 +; ENABLE-NEXT: bgelr 0 +; +; Prologue code. +; At a minimum, we save/restore the link register. Other registers may be saved +; as well. +; CHECK: mflr +; +; Compare the arguments and jump to exit. +; After the prologue is set. +; DISABLE: cmpw 0, 3, 4 +; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]] +; +; Store %a on the stack +; CHECK: stw 3, {{[0-9]+([0-9]+)}} +; Set the alloca address in the second argument. +; CHECK-NEXT: addi 4, 1, {{[0-9]+}} +; Set the first argument to zero. +; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: bl doSomething +; +; With shrink-wrapping, epilogue is just after the call. +; Restore the link register and return. +; Note that there could be other epilog code before the link register is +; restored but we will not check for it here. +; ENABLE: mtlr +; ENABLE-NEXT: blr +; +; DISABLE: [[EXIT_LABEL]]: +; +; Without shrink-wrapping, epilogue is in the exit block. +; Epilogue code. (What we pop does not matter.) +; DISABLE: mtlr {{[0-9]+}} +; DISABLE-NEXT: blr +; + +define i32 @foo(i32 %a, i32 %b) { + %tmp = alloca i32, align 4 + %tmp2 = icmp slt i32 %a, %b + br i1 %tmp2, label %true, label %false + +true: + store i32 %a, i32* %tmp, align 4 + %tmp4 = call i32 @doSomething(i32 0, i32* %tmp) + br label %false + +false: + %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ] + ret i32 %tmp.0 +} + +; Function Attrs: optsize +declare i32 @doSomething(i32, i32*) + + + +; Check that we do not perform the restore inside the loop whereas the save +; is outside. +; CHECK-LABEL: freqSaveAndRestoreOutsideLoop: +; +; Shrink-wrapping allows to skip the prologue in the else case. +; ENABLE: cmplwi 0, 3, 0 +; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; Make sure we save the link register +; CHECK: mflr {{[0-9]+}} +; +; DISABLE: cmplwi 0, 3, 0 +; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; Loop preheader +; CHECK-DAG: li [[SUM:[0-9]+]], 0 +; CHECK-DAG: li [[IV:[0-9]+]], 10 +; +; Loop body +; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body +; CHECK: bl something +; CHECK-DAG: addi [[IV]], [[IV]], -1 +; CHECK-DAG: add [[SUM]], 3, [[SUM]] +; CHECK-NEXT: cmplwi [[IV]], 0 +; CHECK-NEXT: bne 0, .[[LOOP]] +; +; Next BB. +; CHECK: slwi 3, [[SUM]], 3 +; +; Jump to epilogue. +; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]] +; +; DISABLE: .[[ELSE_LABEL]]: # %if.else +; Shift second argument by one and store into returned register. +; DISABLE: slwi 3, 4, 1 +; DISABLE: .[[EPILOG_BB]]: # %if.end +; +; Epilogue code. +; CHECK: mtlr {{[0-9]+}} +; CHECK-NEXT: blr +; +; ENABLE: .[[ELSE_LABEL]]: # %if.else +; Shift second argument by one and store into returned register. +; ENABLE: slwi 3, 4, 1 +; ENABLE-NEXT: blr +define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %for.preheader + +for.preheader: + tail call void asm "nop", ""() + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ] + %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ] + %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)() + %add = add nsw i32 %call, %sum.04 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + %shl = shl i32 %add, 3 + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %if.else, %for.end + %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ] + ret i32 %sum.1 +} + +declare i32 @something(...) + +; Check that we do not perform the shrink-wrapping inside the loop even +; though that would be legal. The cost model must prevent that. +; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2: +; Prologue code. +; Make sure we save the link register before the call +; CHECK: mflr {{[0-9]+}} +; +; Loop preheader +; CHECK-DAG: li [[SUM:[0-9]+]], 0 +; CHECK-DAG: li [[IV:[0-9]+]], 10 +; +; Loop body +; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body +; CHECK: bl something +; CHECK-DAG: addi [[IV]], [[IV]], -1 +; CHECK-DAG: add [[SUM]], 3, [[SUM]] +; CHECK-NEXT: cmplwi [[IV]], 0 +; CHECK-NEXT: bne 0, .[[LOOP]] +; +; Next BB +; CHECK: %for.exit +; CHECK: mtlr {{[0-9]+}} +; CHECK-NEXT: blr +define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) { +entry: + br label %for.preheader + +for.preheader: + tail call void asm "nop", ""() + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ] + %sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ] + %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)() + %add = add nsw i32 %call, %sum.03 + %inc = add nuw nsw i32 %i.04, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.exit, label %for.body + +for.exit: + tail call void asm "nop", ""() + br label %for.end + +for.end: ; preds = %for.body + ret i32 %add +} + + +; Check with a more complex case that we do not have save within the loop and +; restore outside. +; CHECK-LABEL: loopInfoSaveOutsideLoop: +; +; ENABLE: cmplwi 0, 3, 0 +; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; Make sure we save the link register +; CHECK: mflr {{[0-9]+}} +; +; DISABLE: cmplwi 0, 3, 0 +; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; Loop preheader +; CHECK-DAG: li [[SUM:[0-9]+]], 0 +; CHECK-DAG: li [[IV:[0-9]+]], 10 +; +; Loop body +; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body +; CHECK: bl something +; CHECK-DAG: addi [[IV]], [[IV]], -1 +; CHECK-DAG: add [[SUM]], 3, [[SUM]] +; CHECK-NEXT: cmplwi [[IV]], 0 +; CHECK-NEXT: bne 0, .[[LOOP]] +; +; Next BB +; CHECK: bl somethingElse +; CHECK: slwi 3, [[SUM]], 3 +; +; Jump to epilogue +; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]] +; +; DISABLE: .[[ELSE_LABEL]]: # %if.else +; Shift second argument by one and store into returned register. +; DISABLE: slwi 3, 4, 1 +; +; DISABLE: .[[EPILOG_BB]]: # %if.end +; Epilog code +; CHECK: mtlr {{[0-9]+}} +; CHECK-NEXT: blr +; +; ENABLE: .[[ELSE_LABEL]]: # %if.else +; Shift second argument by one and store into returned register. +; ENABLE: slwi 3, 4, 1 +; ENABLE-NEXT: blr +define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %for.preheader + +for.preheader: + tail call void asm "nop", ""() + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ] + %sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ] + %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)() + %add = add nsw i32 %call, %sum.04 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + tail call void bitcast (void (...)* @somethingElse to void ()*)() + %shl = shl i32 %add, 3 + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %if.else, %for.end + %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ] + ret i32 %sum.1 +} + +declare void @somethingElse(...) + +; Check with a more complex case that we do not have restore within the loop and +; save outside. +; CHECK-LABEL: loopInfoRestoreOutsideLoop: +; +; ENABLE: cmplwi 0, 3, 0 +; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; Make sure we save the link register +; CHECK: mflr {{[0-9]+}} +; +; DISABLE: cmplwi 0, 3, 0 +; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; CHECK: bl somethingElse +; +; Loop preheader +; CHECK-DAG: li [[SUM:[0-9]+]], 0 +; CHECK-DAG: li [[IV:[0-9]+]], 10 +; +; Loop body +; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body +; CHECK: bl something +; CHECK-DAG: addi [[IV]], [[IV]], -1 +; CHECK-DAG: add [[SUM]], 3, [[SUM]] +; CHECK-NEXT: cmplwi [[IV]], 0 +; CHECK-NEXT: bne 0, .[[LOOP]] +; +; Next BB. +; slwi 3, [[SUM]], 3 +; +; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]] +; +; DISABLE: .[[ELSE_LABEL]]: # %if.else +; Shift second argument by one and store into returned register. +; DISABLE: slwi 3, 4, 1 +; DISABLE: .[[EPILOG_BB]]: # %if.end +; +; Epilogue code. +; CHECK: mtlr {{[0-9]+}} +; CHECK-NEXT: blr +; +; ENABLE: .[[ELSE_LABEL]]: # %if.else +; Shift second argument by one and store into returned register. +; ENABLE: slwi 3, 4, 1 +; ENABLE-NEXT: blr +define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + tail call void bitcast (void (...)* @somethingElse to void ()*)() + br label %for.body + +for.body: ; preds = %for.body, %if.then + %i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ] + %sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ] + %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)() + %add = add nsw i32 %call, %sum.04 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + %shl = shl i32 %add, 3 + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %if.else, %for.end + %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ] + ret i32 %sum.1 +} + +; Check that we handle function with no frame information correctly. +; CHECK-LABEL: emptyFrame: +; CHECK: # %entry +; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: blr +define i32 @emptyFrame() { +entry: + ret i32 0 +} + + +; Check that we handle inline asm correctly. +; CHECK-LABEL: inlineAsm: +; +; ENABLE: cmplwi 0, 3, 0 +; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; Make sure we save the CSR used in the inline asm: r14 +; ENABLE-DAG: li [[IV:[0-9]+]], 10 +; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill +; +; DISABLE: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill +; DISABLE: cmplwi 0, 3, 0 +; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; DISABLE: li [[IV:[0-9]+]], 10 +; +; CHECK: nop +; CHECK: mtctr [[IV]] +; +; CHECK: .[[LOOP_LABEL:LBB[0-9_]+]]: # %for.body +; Inline asm statement. +; CHECK: addi 14, 14, 1 +; CHECK: bdnz .[[LOOP_LABEL]] +; +; Epilogue code. +; CHECK: li 3, 0 +; CHECK-DAG: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload +; CHECK: nop +; CHECK: blr +; +; CHECK: [[ELSE_LABEL]] +; CHECK-NEXT: slwi 3, 4, 1 +; DISABLE: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload +; CHECK-NEXT blr +; +define i32 @inlineAsm(i32 %cond, i32 %N) { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %for.preheader + +for.preheader: + tail call void asm "nop", ""() + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ] + tail call void asm "addi 14, 14, 1", "~{r14}"() + %inc = add nuw nsw i32 %i.03, 1 + %exitcond = icmp eq i32 %inc, 10 + br i1 %exitcond, label %for.exit, label %for.body + +for.exit: + tail call void asm "nop", ""() + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %for.body, %if.else + %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ] + ret i32 %sum.0 +} + + +; Check that we handle calls to variadic functions correctly. +; CHECK-LABEL: callVariadicFunc: +; +; ENABLE: cmplwi 0, 3, 0 +; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; Prologue code. +; CHECK: mflr {{[0-9]+}} +; +; DISABLE: cmplwi 0, 3, 0 +; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] +; +; Setup of the varags. +; CHECK: mr 4, 3 +; CHECK-NEXT: mr 5, 3 +; CHECK-NEXT: mr 6, 3 +; CHECK-NEXT: mr 7, 3 +; CHECK-NEXT: mr 8, 3 +; CHECK-NEXT: mr 9, 3 +; CHECK-NEXT: bl someVariadicFunc +; CHECK: slwi 3, 3, 3 +; DISABLE: b .[[EPILOGUE_BB:LBB[0-9_]+]] +; +; ENABLE: mtlr {{[0-9]+}} +; ENABLE-NEXT: blr +; +; CHECK: .[[ELSE_LABEL]]: # %if.else +; CHECK-NEXT: slwi 3, 4, 1 +; +; DISABLE: .[[EPILOGUE_BB]]: # %if.end +; DISABLE: mtlr +; CHECK: blr +define i32 @callVariadicFunc(i32 %cond, i32 %N) { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + %call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N) + %shl = shl i32 %call, 3 + br label %if.end + +if.else: ; preds = %entry + %mul = shl nsw i32 %N, 1 + br label %if.end + +if.end: ; preds = %if.else, %if.then + %sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ] + ret i32 %sum.0 +} + +declare i32 @someVariadicFunc(i32, ...) + + + +; Make sure we do not insert unreachable code after noreturn function. +; Although this is not incorrect to insert such code, it is useless +; and it hurts the binary size. +; +; CHECK-LABEL: noreturn: +; DISABLE: mflr {{[0-9]+}} +; +; CHECK: cmplwi 3, 0 +; CHECK-NEXT: bne{{[-]?}} 0, .[[ABORT:LBB[0-9_]+]] +; +; CHECK: li 3, 42 +; +; DISABLE: mtlr {{[0-9]+}} +; +; CHECK-NEXT: blr +; +; CHECK: .[[ABORT]]: # %if.abort +; +; ENABLE: mflr {{[0-9]+}} +; +; CHECK: bl abort +; ENABLE-NOT: mtlr {{[0-9]+}} +define i32 @noreturn(i8 signext %bad_thing) { +entry: + %tobool = icmp eq i8 %bad_thing, 0 + br i1 %tobool, label %if.end, label %if.abort + +if.abort: + tail call void @abort() #0 + unreachable + +if.end: + ret i32 42 +} + +declare void @abort() #0 + +attributes #0 = { noreturn nounwind } + + +; Make sure that we handle infinite loops properly When checking that the Save +; and Restore blocks are control flow equivalent, the loop searches for the +; immediate (post) dominator for the (restore) save blocks. When either the Save +; or Restore block is located in an infinite loop the only immediate (post) +; dominator is itself. In this case, we cannot perform shrink wrapping, but we +; should return gracefully and continue compilation. +; The only condition for this test is the compilation finishes correctly. +; +; CHECK-LABEL: infiniteloop +; CHECK: blr +define void @infiniteloop() { +entry: + br i1 undef, label %if.then, label %if.end + +if.then: + %ptr = alloca i32, i32 4 + br label %for.body + +for.body: ; preds = %for.body, %entry + %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ] + %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)() + %add = add nsw i32 %call, %sum.03 + store i32 %add, i32* %ptr + br label %for.body + +if.end: + ret void +} + +; Another infinite loop test this time with a body bigger than just one block. +; CHECK-LABEL: infiniteloop2 +; CHECK: blr +define void @infiniteloop2() { +entry: + br i1 undef, label %if.then, label %if.end + +if.then: + %ptr = alloca i32, i32 4 + br label %for.body + +for.body: ; preds = %for.body, %entry + %sum.03 = phi i32 [ 0, %if.then ], [ %add, %body1 ], [ 1, %body2] + %call = tail call i32 asm "mftb $0, 268", "=r,~{r14}"() + %add = add nsw i32 %call, %sum.03 + store i32 %add, i32* %ptr + br i1 undef, label %body1, label %body2 + +body1: + tail call void asm sideeffect "nop", "~{r14}"() + br label %for.body + +body2: + tail call void asm sideeffect "nop", "~{r14}"() + br label %for.body + +if.end: + ret void +} + +; Another infinite loop test this time with two nested infinite loop. +; CHECK-LABEL: infiniteloop3 +; CHECK: # %end +define void @infiniteloop3() { +entry: + br i1 undef, label %loop2a, label %body + +body: ; preds = %entry + br i1 undef, label %loop2a, label %end + +loop1: ; preds = %loop2a, %loop2b + %var.phi = phi i32* [ %next.phi, %loop2b ], [ %var, %loop2a ] + %next.phi = phi i32* [ %next.load, %loop2b ], [ %next.var, %loop2a ] + %0 = icmp eq i32* %var, null + %next.load = load i32*, i32** undef + br i1 %0, label %loop2a, label %loop2b + +loop2a: ; preds = %loop1, %body, %entry + %var = phi i32* [ null, %body ], [ null, %entry ], [ %next.phi, %loop1 ] + %next.var = phi i32* [ undef, %body ], [ null, %entry ], [ %next.load, %loop1 ] + br label %loop1 + +loop2b: ; preds = %loop1 + %gep1 = bitcast i32* %var.phi to i32* + %next.ptr = bitcast i32* %gep1 to i32** + store i32* %next.phi, i32** %next.ptr + br label %loop1 + +end: + ret void +} + +@columns = external global [0 x i32], align 4 +@lock = common global i32 0, align 4 +@htindex = common global i32 0, align 4 +@stride = common global i32 0, align 4 +@ht = common global i32* null, align 8 +@he = common global i8* null, align 8 + +; Test for a bug that was caused when save point was equal to restore point. +; Function Attrs: nounwind +; CHECK-LABEL: transpose +; +; Store of callee-save register saved by shrink wrapping +; CHECK: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill +; +; Reload of callee-save register +; CHECK: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload +; +; Ensure no subsequent uses of callee-save register before end of function +; CHECK-NOT: {{[a-z]+}} [[CSR]] +; CHECK: blr +define signext i32 @transpose() { +entry: + %0 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 1), align 4 + %shl.i = shl i32 %0, 7 + %1 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 2), align 4 + %or.i = or i32 %shl.i, %1 + %shl1.i = shl i32 %or.i, 7 + %2 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 3), align 4 + %or2.i = or i32 %shl1.i, %2 + %3 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 7), align 4 + %shl3.i = shl i32 %3, 7 + %4 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 6), align 4 + %or4.i = or i32 %shl3.i, %4 + %shl5.i = shl i32 %or4.i, 7 + %5 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 5), align 4 + %or6.i = or i32 %shl5.i, %5 + %cmp.i = icmp ugt i32 %or2.i, %or6.i + br i1 %cmp.i, label %cond.true.i, label %cond.false.i + +cond.true.i: + %shl7.i = shl i32 %or2.i, 7 + %6 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 4), align 4 + %or8.i = or i32 %6, %shl7.i + %conv.i = zext i32 %or8.i to i64 + %shl9.i = shl nuw nsw i64 %conv.i, 21 + %conv10.i = zext i32 %or6.i to i64 + %or11.i = or i64 %shl9.i, %conv10.i + br label %hash.exit + +cond.false.i: + %shl12.i = shl i32 %or6.i, 7 + %7 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 4), align 4 + %or13.i = or i32 %7, %shl12.i + %conv14.i = zext i32 %or13.i to i64 + %shl15.i = shl nuw nsw i64 %conv14.i, 21 + %conv16.i = zext i32 %or2.i to i64 + %or17.i = or i64 %shl15.i, %conv16.i + br label %hash.exit + +hash.exit: + %cond.i = phi i64 [ %or11.i, %cond.true.i ], [ %or17.i, %cond.false.i ] + %shr.29.i = lshr i64 %cond.i, 17 + %conv18.i = trunc i64 %shr.29.i to i32 + store i32 %conv18.i, i32* @lock, align 4 + %rem.i = srem i64 %cond.i, 1050011 + %conv19.i = trunc i64 %rem.i to i32 + store i32 %conv19.i, i32* @htindex, align 4 + %rem20.i = urem i32 %conv18.i, 179 + %add.i = or i32 %rem20.i, 131072 + store i32 %add.i, i32* @stride, align 4 + %8 = load i32*, i32** @ht, align 8 + %arrayidx = getelementptr inbounds i32, i32* %8, i64 %rem.i + %9 = load i32, i32* %arrayidx, align 4 + %cmp1 = icmp eq i32 %9, %conv18.i + br i1 %cmp1, label %if.then, label %if.end + +if.then: + %idxprom.lcssa = phi i64 [ %rem.i, %hash.exit ], [ %idxprom.1, %if.end ], [ %idxprom.2, %if.end.1 ], [ %idxprom.3, %if.end.2 ], [ %idxprom.4, %if.end.3 ], [ %idxprom.5, %if.end.4 ], [ %idxprom.6, %if.end.5 ], [ %idxprom.7, %if.end.6 ] + %10 = load i8*, i8** @he, align 8 + %arrayidx3 = getelementptr inbounds i8, i8* %10, i64 %idxprom.lcssa + %11 = load i8, i8* %arrayidx3, align 1 + %conv = sext i8 %11 to i32 + br label %cleanup + +if.end: + %add = add nsw i32 %add.i, %conv19.i + %cmp4 = icmp sgt i32 %add, 1050010 + %sub = add nsw i32 %add, -1050011 + %sub.add = select i1 %cmp4, i32 %sub, i32 %add + %idxprom.1 = sext i32 %sub.add to i64 + %arrayidx.1 = getelementptr inbounds i32, i32* %8, i64 %idxprom.1 + %12 = load i32, i32* %arrayidx.1, align 4 + %cmp1.1 = icmp eq i32 %12, %conv18.i + br i1 %cmp1.1, label %if.then, label %if.end.1 + +cleanup: + %retval.0 = phi i32 [ %conv, %if.then ], [ -128, %if.end.6 ] + ret i32 %retval.0 + +if.end.1: + %add.1 = add nsw i32 %add.i, %sub.add + %cmp4.1 = icmp sgt i32 %add.1, 1050010 + %sub.1 = add nsw i32 %add.1, -1050011 + %sub.add.1 = select i1 %cmp4.1, i32 %sub.1, i32 %add.1 + %idxprom.2 = sext i32 %sub.add.1 to i64 + %arrayidx.2 = getelementptr inbounds i32, i32* %8, i64 %idxprom.2 + %13 = load i32, i32* %arrayidx.2, align 4 + %cmp1.2 = icmp eq i32 %13, %conv18.i + br i1 %cmp1.2, label %if.then, label %if.end.2 + +if.end.2: + %add.2 = add nsw i32 %add.i, %sub.add.1 + %cmp4.2 = icmp sgt i32 %add.2, 1050010 + %sub.2 = add nsw i32 %add.2, -1050011 + %sub.add.2 = select i1 %cmp4.2, i32 %sub.2, i32 %add.2 + %idxprom.3 = sext i32 %sub.add.2 to i64 + %arrayidx.3 = getelementptr inbounds i32, i32* %8, i64 %idxprom.3 + %14 = load i32, i32* %arrayidx.3, align 4 + %cmp1.3 = icmp eq i32 %14, %conv18.i + br i1 %cmp1.3, label %if.then, label %if.end.3 + +if.end.3: + %add.3 = add nsw i32 %add.i, %sub.add.2 + %cmp4.3 = icmp sgt i32 %add.3, 1050010 + %sub.3 = add nsw i32 %add.3, -1050011 + %sub.add.3 = select i1 %cmp4.3, i32 %sub.3, i32 %add.3 + %idxprom.4 = sext i32 %sub.add.3 to i64 + %arrayidx.4 = getelementptr inbounds i32, i32* %8, i64 %idxprom.4 + %15 = load i32, i32* %arrayidx.4, align 4 + %cmp1.4 = icmp eq i32 %15, %conv18.i + br i1 %cmp1.4, label %if.then, label %if.end.4 + +if.end.4: + %add.4 = add nsw i32 %add.i, %sub.add.3 + %cmp4.4 = icmp sgt i32 %add.4, 1050010 + %sub.4 = add nsw i32 %add.4, -1050011 + %sub.add.4 = select i1 %cmp4.4, i32 %sub.4, i32 %add.4 + %idxprom.5 = sext i32 %sub.add.4 to i64 + %arrayidx.5 = getelementptr inbounds i32, i32* %8, i64 %idxprom.5 + %16 = load i32, i32* %arrayidx.5, align 4 + %cmp1.5 = icmp eq i32 %16, %conv18.i + br i1 %cmp1.5, label %if.then, label %if.end.5 + +if.end.5: + %add.5 = add nsw i32 %add.i, %sub.add.4 + %cmp4.5 = icmp sgt i32 %add.5, 1050010 + %sub.5 = add nsw i32 %add.5, -1050011 + %sub.add.5 = select i1 %cmp4.5, i32 %sub.5, i32 %add.5 + %idxprom.6 = sext i32 %sub.add.5 to i64 + %arrayidx.6 = getelementptr inbounds i32, i32* %8, i64 %idxprom.6 + %17 = load i32, i32* %arrayidx.6, align 4 + %cmp1.6 = icmp eq i32 %17, %conv18.i + br i1 %cmp1.6, label %if.then, label %if.end.6 + +if.end.6: + %add.6 = add nsw i32 %add.i, %sub.add.5 + %cmp4.6 = icmp sgt i32 %add.6, 1050010 + %sub.6 = add nsw i32 %add.6, -1050011 + %sub.add.6 = select i1 %cmp4.6, i32 %sub.6, i32 %add.6 + %idxprom.7 = sext i32 %sub.add.6 to i64 + %arrayidx.7 = getelementptr inbounds i32, i32* %8, i64 %idxprom.7 + %18 = load i32, i32* %arrayidx.7, align 4 + %cmp1.7 = icmp eq i32 %18, %conv18.i + br i1 %cmp1.7, label %if.then, label %cleanup +} diff --git a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll index ad8ed38da7fa..028006320cb5 100644 --- a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll +++ b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll @@ -10,7 +10,7 @@ define void @main() { } ; CHECK-LABEL: @main -; CHECK-DAG li 4, 0 +; CHECK-DAG: li 4, 0 ; CHECK-DAG: crxor 6, 6, 6 ; CHECK: bl printf diff --git a/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll b/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll index e8617ccfc8a5..65b45ea555ae 100644 --- a/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll +++ b/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll @@ -10,10 +10,10 @@ entry: ret void ; FIXME: Crashing is not really the correct behavior here, we really should just emit nothing -; CHECK: Cannot select: 0x{{[0-9,a-f]+}}: ch = Prefetch -; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<0> -; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<3> -; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<0> +; CHECK: Cannot select: {{0x[0-9,a-f]+|t[0-9]+}}: ch = Prefetch +; CHECK: {{0x[0-9,a-f]+|t[0-9]+}}: i32 = Constant<0> +; CHECK-NEXT: {{0x[0-9,a-f]+|t[0-9]+}}: i32 = Constant<3> +; CHECK-NEXT: {{0x[0-9,a-f]+|t[0-9]+}}: i32 = Constant<0> } diff --git a/test/CodeGen/PowerPC/ppcsoftops.ll b/test/CodeGen/PowerPC/ppcsoftops.ll new file mode 100644 index 000000000000..56c057613bdc --- /dev/null +++ b/test/CodeGen/PowerPC/ppcsoftops.ll @@ -0,0 +1,50 @@ +; RUN: llc -mtriple=powerpc-unknown-linux-gnu -O0 < %s | FileCheck %s +define double @foo() #0 { +entry: + %a = alloca double, align 8 + %b = alloca double, align 8 + %0 = load double, double* %a, align 8 + %1 = load double, double* %b, align 8 + %add = fadd double %0, %1 + ret double %add + + ; CHECK-LABEL: __adddf3 +} + +define double @foo1() #0 { +entry: + %a = alloca double, align 8 + %b = alloca double, align 8 + %0 = load double, double* %a, align 8 + %1 = load double, double* %b, align 8 + %mul = fmul double %0, %1 + ret double %mul + + ; CHECK-LABEL: __muldf3 +} + +define double @foo2() #0 { +entry: + %a = alloca double, align 8 + %b = alloca double, align 8 + %0 = load double, double* %a, align 8 + %1 = load double, double* %b, align 8 + %sub = fsub double %0, %1 + ret double %sub + + ; CHECK-LABEL: __subdf3 +} + +define double @foo3() #0 { +entry: + %a = alloca double, align 8 + %b = alloca double, align 8 + %0 = load double, double* %a, align 8 + %1 = load double, double* %b, align 8 + %div = fdiv double %0, %1 + ret double %div + + ; CHECK-LABEL: __divdf3 +} + +attributes #0 = {"use-soft-float"="true" } diff --git a/test/CodeGen/PowerPC/pr17168.ll b/test/CodeGen/PowerPC/pr17168.ll index 096895491381..b1bac59c9ce1 100644 --- a/test/CodeGen/PowerPC/pr17168.ll +++ b/test/CodeGen/PowerPC/pr17168.ll @@ -9,7 +9,7 @@ target triple = "powerpc64-unknown-linux-gnu" @grid_points = external global [3 x i32], align 4 ; Function Attrs: nounwind -define fastcc void @compute_rhs() #0 { +define fastcc void @compute_rhs() #0 !dbg !114 { entry: br i1 undef, label %for.cond871.preheader.for.inc960_crit_edge, label %for.end1042, !dbg !439 @@ -54,11 +54,11 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!438, !464} -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 190311)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !298, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 190311)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !298, imports: !2) !1 = !DIFile(filename: "bt.c", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT") !2 = !{} !3 = !{!4, !82, !102, !114, !132, !145, !154, !155, !162, !183, !200, !201, !207, !208, !215, !221, !230, !238, !246, !255, !260, !261, !268, !274, !279, !280, !287, !293} -!4 = !DISubprogram(name: "main", line: 74, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 74, file: !1, scope: !5, type: !6, variables: !12) +!4 = distinct !DISubprogram(name: "main", line: 74, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 74, file: !1, scope: !5, type: !6, variables: !12) !5 = !DIFile(filename: "bt.c", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8, !9} @@ -67,20 +67,20 @@ attributes #1 = { nounwind readnone } !10 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !11) !11 = !DIBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) !12 = !{!13, !14, !15, !16, !17, !18, !19, !21, !22, !23, !25, !26} -!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 74, arg: 1, scope: !4, file: !5, type: !8) -!14 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 74, arg: 2, scope: !4, file: !5, type: !9) -!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "niter", line: 76, scope: !4, file: !5, type: !8) -!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "step", line: 76, scope: !4, file: !5, type: !8) -!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n3", line: 76, scope: !4, file: !5, type: !8) -!18 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "nthreads", line: 77, scope: !4, file: !5, type: !8) -!19 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "navg", line: 78, scope: !4, file: !5, type: !20) +!13 = !DILocalVariable(name: "argc", line: 74, arg: 1, scope: !4, file: !5, type: !8) +!14 = !DILocalVariable(name: "argv", line: 74, arg: 2, scope: !4, file: !5, type: !9) +!15 = !DILocalVariable(name: "niter", line: 76, scope: !4, file: !5, type: !8) +!16 = !DILocalVariable(name: "step", line: 76, scope: !4, file: !5, type: !8) +!17 = !DILocalVariable(name: "n3", line: 76, scope: !4, file: !5, type: !8) +!18 = !DILocalVariable(name: "nthreads", line: 77, scope: !4, file: !5, type: !8) +!19 = !DILocalVariable(name: "navg", line: 78, scope: !4, file: !5, type: !20) !20 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 64, encoding: DW_ATE_float) -!21 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "mflops", line: 78, scope: !4, file: !5, type: !20) -!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "tmax", line: 80, scope: !4, file: !5, type: !20) -!23 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "verified", line: 81, scope: !4, file: !5, type: !24) +!21 = !DILocalVariable(name: "mflops", line: 78, scope: !4, file: !5, type: !20) +!22 = !DILocalVariable(name: "tmax", line: 80, scope: !4, file: !5, type: !20) +!23 = !DILocalVariable(name: "verified", line: 81, scope: !4, file: !5, type: !24) !24 = !DIDerivedType(tag: DW_TAG_typedef, name: "boolean", line: 12, file: !1, baseType: !8) -!25 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "class", line: 82, scope: !4, file: !5, type: !11) -!26 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "fp", line: 83, scope: !4, file: !5, type: !27) +!25 = !DILocalVariable(name: "class", line: 82, scope: !4, file: !5, type: !11) +!26 = !DILocalVariable(name: "fp", line: 83, scope: !4, file: !5, type: !27) !27 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !28) !28 = !DIDerivedType(tag: DW_TAG_typedef, name: "FILE", line: 49, file: !1, baseType: !29) !29 = !DICompositeType(tag: DW_TAG_structure_type, name: "_IO_FILE", line: 271, size: 1728, align: 64, file: !30, elements: !31) @@ -136,222 +136,222 @@ attributes #1 = { nounwind readnone } !79 = !DICompositeType(tag: DW_TAG_array_type, size: 160, align: 8, baseType: !11, elements: !80) !80 = !{!81} !81 = !DISubrange(count: 20) -!82 = !DISubprogram(name: "verify", line: 2388, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2388, file: !1, scope: !5, type: !83, variables: !86) +!82 = distinct !DISubprogram(name: "verify", line: 2388, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2388, file: !1, scope: !5, type: !83, variables: !86) !83 = !DISubroutineType(types: !84) !84 = !{null, !8, !10, !85} !85 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !24) !86 = !{!87, !88, !89, !90, !94, !95, !96, !97, !98, !99, !100, !101} -!87 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "no_time_steps", line: 2388, arg: 1, scope: !82, file: !5, type: !8) -!88 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "class", line: 2388, arg: 2, scope: !82, file: !5, type: !10) -!89 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "verified", line: 2388, arg: 3, scope: !82, file: !5, type: !85) -!90 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xcrref", line: 2397, scope: !82, file: !5, type: !91) +!87 = !DILocalVariable(name: "no_time_steps", line: 2388, arg: 1, scope: !82, file: !5, type: !8) +!88 = !DILocalVariable(name: "class", line: 2388, arg: 2, scope: !82, file: !5, type: !10) +!89 = !DILocalVariable(name: "verified", line: 2388, arg: 3, scope: !82, file: !5, type: !85) +!90 = !DILocalVariable(name: "xcrref", line: 2397, scope: !82, file: !5, type: !91) !91 = !DICompositeType(tag: DW_TAG_array_type, size: 320, align: 64, baseType: !20, elements: !92) !92 = !{!93} !93 = !DISubrange(count: 5) -!94 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xceref", line: 2397, scope: !82, file: !5, type: !91) -!95 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xcrdif", line: 2397, scope: !82, file: !5, type: !91) -!96 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xcedif", line: 2397, scope: !82, file: !5, type: !91) -!97 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "epsilon", line: 2398, scope: !82, file: !5, type: !20) -!98 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xce", line: 2398, scope: !82, file: !5, type: !91) -!99 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xcr", line: 2398, scope: !82, file: !5, type: !91) -!100 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dtref", line: 2398, scope: !82, file: !5, type: !20) -!101 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 2399, scope: !82, file: !5, type: !8) -!102 = !DISubprogram(name: "rhs_norm", line: 266, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 266, file: !1, scope: !5, type: !103, variables: !106) +!94 = !DILocalVariable(name: "xceref", line: 2397, scope: !82, file: !5, type: !91) +!95 = !DILocalVariable(name: "xcrdif", line: 2397, scope: !82, file: !5, type: !91) +!96 = !DILocalVariable(name: "xcedif", line: 2397, scope: !82, file: !5, type: !91) +!97 = !DILocalVariable(name: "epsilon", line: 2398, scope: !82, file: !5, type: !20) +!98 = !DILocalVariable(name: "xce", line: 2398, scope: !82, file: !5, type: !91) +!99 = !DILocalVariable(name: "xcr", line: 2398, scope: !82, file: !5, type: !91) +!100 = !DILocalVariable(name: "dtref", line: 2398, scope: !82, file: !5, type: !20) +!101 = !DILocalVariable(name: "m", line: 2399, scope: !82, file: !5, type: !8) +!102 = distinct !DISubprogram(name: "rhs_norm", line: 266, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 266, file: !1, scope: !5, type: !103, variables: !106) !103 = !DISubroutineType(types: !104) !104 = !{null, !105} !105 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !20) !106 = !{!107, !108, !109, !110, !111, !112, !113} -!107 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "rms", line: 266, arg: 1, scope: !102, file: !5, type: !105) -!108 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 271, scope: !102, file: !5, type: !8) -!109 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 271, scope: !102, file: !5, type: !8) -!110 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 271, scope: !102, file: !5, type: !8) -!111 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "d", line: 271, scope: !102, file: !5, type: !8) -!112 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 271, scope: !102, file: !5, type: !8) -!113 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "add", line: 272, scope: !102, file: !5, type: !20) -!114 = !DISubprogram(name: "compute_rhs", line: 1767, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1767, file: !1, scope: !5, type: !115, function: void ()* @compute_rhs, variables: !117) +!107 = !DILocalVariable(name: "rms", line: 266, arg: 1, scope: !102, file: !5, type: !105) +!108 = !DILocalVariable(name: "i", line: 271, scope: !102, file: !5, type: !8) +!109 = !DILocalVariable(name: "j", line: 271, scope: !102, file: !5, type: !8) +!110 = !DILocalVariable(name: "k", line: 271, scope: !102, file: !5, type: !8) +!111 = !DILocalVariable(name: "d", line: 271, scope: !102, file: !5, type: !8) +!112 = !DILocalVariable(name: "m", line: 271, scope: !102, file: !5, type: !8) +!113 = !DILocalVariable(name: "add", line: 272, scope: !102, file: !5, type: !20) +!114 = distinct !DISubprogram(name: "compute_rhs", line: 1767, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1767, file: !1, scope: !5, type: !115, variables: !117) !115 = !DISubroutineType(types: !116) !116 = !{null} !117 = !{!118, !119, !120, !121, !122, !123, !124, !125, !126, !127, !128, !129, !130, !131} -!118 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 1769, scope: !114, file: !5, type: !8) -!119 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 1769, scope: !114, file: !5, type: !8) -!120 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 1769, scope: !114, file: !5, type: !8) -!121 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 1769, scope: !114, file: !5, type: !8) -!122 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "rho_inv", line: 1770, scope: !114, file: !5, type: !20) -!123 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "uijk", line: 1770, scope: !114, file: !5, type: !20) -!124 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "up1", line: 1770, scope: !114, file: !5, type: !20) -!125 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "um1", line: 1770, scope: !114, file: !5, type: !20) -!126 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vijk", line: 1770, scope: !114, file: !5, type: !20) -!127 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vp1", line: 1770, scope: !114, file: !5, type: !20) -!128 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vm1", line: 1770, scope: !114, file: !5, type: !20) -!129 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "wijk", line: 1770, scope: !114, file: !5, type: !20) -!130 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "wp1", line: 1770, scope: !114, file: !5, type: !20) -!131 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "wm1", line: 1770, scope: !114, file: !5, type: !20) -!132 = !DISubprogram(name: "error_norm", line: 225, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 225, file: !1, scope: !5, type: !103, variables: !133) +!118 = !DILocalVariable(name: "i", line: 1769, scope: !114, file: !5, type: !8) +!119 = !DILocalVariable(name: "j", line: 1769, scope: !114, file: !5, type: !8) +!120 = !DILocalVariable(name: "k", line: 1769, scope: !114, file: !5, type: !8) +!121 = !DILocalVariable(name: "m", line: 1769, scope: !114, file: !5, type: !8) +!122 = !DILocalVariable(name: "rho_inv", line: 1770, scope: !114, file: !5, type: !20) +!123 = !DILocalVariable(name: "uijk", line: 1770, scope: !114, file: !5, type: !20) +!124 = !DILocalVariable(name: "up1", line: 1770, scope: !114, file: !5, type: !20) +!125 = !DILocalVariable(name: "um1", line: 1770, scope: !114, file: !5, type: !20) +!126 = !DILocalVariable(name: "vijk", line: 1770, scope: !114, file: !5, type: !20) +!127 = !DILocalVariable(name: "vp1", line: 1770, scope: !114, file: !5, type: !20) +!128 = !DILocalVariable(name: "vm1", line: 1770, scope: !114, file: !5, type: !20) +!129 = !DILocalVariable(name: "wijk", line: 1770, scope: !114, file: !5, type: !20) +!130 = !DILocalVariable(name: "wp1", line: 1770, scope: !114, file: !5, type: !20) +!131 = !DILocalVariable(name: "wm1", line: 1770, scope: !114, file: !5, type: !20) +!132 = distinct !DISubprogram(name: "error_norm", line: 225, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 225, file: !1, scope: !5, type: !103, variables: !133) !133 = !{!134, !135, !136, !137, !138, !139, !140, !141, !142, !143, !144} -!134 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "rms", line: 225, arg: 1, scope: !132, file: !5, type: !105) -!135 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 232, scope: !132, file: !5, type: !8) -!136 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 232, scope: !132, file: !5, type: !8) -!137 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 232, scope: !132, file: !5, type: !8) -!138 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 232, scope: !132, file: !5, type: !8) -!139 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "d", line: 232, scope: !132, file: !5, type: !8) -!140 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xi", line: 233, scope: !132, file: !5, type: !20) -!141 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "eta", line: 233, scope: !132, file: !5, type: !20) -!142 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "zeta", line: 233, scope: !132, file: !5, type: !20) -!143 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "u_exact", line: 233, scope: !132, file: !5, type: !91) -!144 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "add", line: 233, scope: !132, file: !5, type: !20) -!145 = !DISubprogram(name: "exact_solution", line: 643, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 644, file: !1, scope: !5, type: !146, variables: !148) +!134 = !DILocalVariable(name: "rms", line: 225, arg: 1, scope: !132, file: !5, type: !105) +!135 = !DILocalVariable(name: "i", line: 232, scope: !132, file: !5, type: !8) +!136 = !DILocalVariable(name: "j", line: 232, scope: !132, file: !5, type: !8) +!137 = !DILocalVariable(name: "k", line: 232, scope: !132, file: !5, type: !8) +!138 = !DILocalVariable(name: "m", line: 232, scope: !132, file: !5, type: !8) +!139 = !DILocalVariable(name: "d", line: 232, scope: !132, file: !5, type: !8) +!140 = !DILocalVariable(name: "xi", line: 233, scope: !132, file: !5, type: !20) +!141 = !DILocalVariable(name: "eta", line: 233, scope: !132, file: !5, type: !20) +!142 = !DILocalVariable(name: "zeta", line: 233, scope: !132, file: !5, type: !20) +!143 = !DILocalVariable(name: "u_exact", line: 233, scope: !132, file: !5, type: !91) +!144 = !DILocalVariable(name: "add", line: 233, scope: !132, file: !5, type: !20) +!145 = distinct !DISubprogram(name: "exact_solution", line: 643, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 644, file: !1, scope: !5, type: !146, variables: !148) !146 = !DISubroutineType(types: !147) !147 = !{null, !20, !20, !20, !105} !148 = !{!149, !150, !151, !152, !153} -!149 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "xi", line: 643, arg: 1, scope: !145, file: !5, type: !20) -!150 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "eta", line: 643, arg: 2, scope: !145, file: !5, type: !20) -!151 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "zeta", line: 643, arg: 3, scope: !145, file: !5, type: !20) -!152 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "dtemp", line: 644, arg: 4, scope: !145, file: !5, type: !105) -!153 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 653, scope: !145, file: !5, type: !8) -!154 = !DISubprogram(name: "set_constants", line: 2191, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2191, file: !1, scope: !5, type: !115, variables: !2) -!155 = !DISubprogram(name: "lhsinit", line: 855, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 855, file: !1, scope: !5, type: !115, variables: !156) +!149 = !DILocalVariable(name: "xi", line: 643, arg: 1, scope: !145, file: !5, type: !20) +!150 = !DILocalVariable(name: "eta", line: 643, arg: 2, scope: !145, file: !5, type: !20) +!151 = !DILocalVariable(name: "zeta", line: 643, arg: 3, scope: !145, file: !5, type: !20) +!152 = !DILocalVariable(name: "dtemp", line: 644, arg: 4, scope: !145, file: !5, type: !105) +!153 = !DILocalVariable(name: "m", line: 653, scope: !145, file: !5, type: !8) +!154 = distinct !DISubprogram(name: "set_constants", line: 2191, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2191, file: !1, scope: !5, type: !115, variables: !2) +!155 = distinct !DISubprogram(name: "lhsinit", line: 855, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 855, file: !1, scope: !5, type: !115, variables: !156) !156 = !{!157, !158, !159, !160, !161} -!157 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 857, scope: !155, file: !5, type: !8) -!158 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 857, scope: !155, file: !5, type: !8) -!159 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 857, scope: !155, file: !5, type: !8) -!160 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 857, scope: !155, file: !5, type: !8) -!161 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n", line: 857, scope: !155, file: !5, type: !8) -!162 = !DISubprogram(name: "initialize", line: 669, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 669, file: !1, scope: !5, type: !115, variables: !163) +!157 = !DILocalVariable(name: "i", line: 857, scope: !155, file: !5, type: !8) +!158 = !DILocalVariable(name: "j", line: 857, scope: !155, file: !5, type: !8) +!159 = !DILocalVariable(name: "k", line: 857, scope: !155, file: !5, type: !8) +!160 = !DILocalVariable(name: "m", line: 857, scope: !155, file: !5, type: !8) +!161 = !DILocalVariable(name: "n", line: 857, scope: !155, file: !5, type: !8) +!162 = distinct !DISubprogram(name: "initialize", line: 669, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 669, file: !1, scope: !5, type: !115, variables: !163) !163 = !{!164, !165, !166, !167, !168, !169, !170, !171, !172, !173, !174, !179, !180, !181, !182} -!164 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 679, scope: !162, file: !5, type: !8) -!165 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 679, scope: !162, file: !5, type: !8) -!166 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 679, scope: !162, file: !5, type: !8) -!167 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 679, scope: !162, file: !5, type: !8) -!168 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "ix", line: 679, scope: !162, file: !5, type: !8) -!169 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "iy", line: 679, scope: !162, file: !5, type: !8) -!170 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "iz", line: 679, scope: !162, file: !5, type: !8) -!171 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xi", line: 680, scope: !162, file: !5, type: !20) -!172 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "eta", line: 680, scope: !162, file: !5, type: !20) -!173 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "zeta", line: 680, scope: !162, file: !5, type: !20) -!174 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Pface", line: 680, scope: !162, file: !5, type: !175) +!164 = !DILocalVariable(name: "i", line: 679, scope: !162, file: !5, type: !8) +!165 = !DILocalVariable(name: "j", line: 679, scope: !162, file: !5, type: !8) +!166 = !DILocalVariable(name: "k", line: 679, scope: !162, file: !5, type: !8) +!167 = !DILocalVariable(name: "m", line: 679, scope: !162, file: !5, type: !8) +!168 = !DILocalVariable(name: "ix", line: 679, scope: !162, file: !5, type: !8) +!169 = !DILocalVariable(name: "iy", line: 679, scope: !162, file: !5, type: !8) +!170 = !DILocalVariable(name: "iz", line: 679, scope: !162, file: !5, type: !8) +!171 = !DILocalVariable(name: "xi", line: 680, scope: !162, file: !5, type: !20) +!172 = !DILocalVariable(name: "eta", line: 680, scope: !162, file: !5, type: !20) +!173 = !DILocalVariable(name: "zeta", line: 680, scope: !162, file: !5, type: !20) +!174 = !DILocalVariable(name: "Pface", line: 680, scope: !162, file: !5, type: !175) !175 = !DICompositeType(tag: DW_TAG_array_type, size: 1920, align: 64, baseType: !20, elements: !176) !176 = !{!177, !178, !93} !177 = !DISubrange(count: 2) !178 = !DISubrange(count: 3) -!179 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Pxi", line: 680, scope: !162, file: !5, type: !20) -!180 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Peta", line: 680, scope: !162, file: !5, type: !20) -!181 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "Pzeta", line: 680, scope: !162, file: !5, type: !20) -!182 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "temp", line: 680, scope: !162, file: !5, type: !91) -!183 = !DISubprogram(name: "exact_rhs", line: 301, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 301, file: !1, scope: !5, type: !115, variables: !184) +!179 = !DILocalVariable(name: "Pxi", line: 680, scope: !162, file: !5, type: !20) +!180 = !DILocalVariable(name: "Peta", line: 680, scope: !162, file: !5, type: !20) +!181 = !DILocalVariable(name: "Pzeta", line: 680, scope: !162, file: !5, type: !20) +!182 = !DILocalVariable(name: "temp", line: 680, scope: !162, file: !5, type: !91) +!183 = distinct !DISubprogram(name: "exact_rhs", line: 301, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 301, file: !1, scope: !5, type: !115, variables: !184) !184 = !{!185, !186, !187, !188, !189, !190, !191, !192, !193, !194, !195, !196, !197, !198, !199} -!185 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dtemp", line: 310, scope: !183, file: !5, type: !91) -!186 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "xi", line: 310, scope: !183, file: !5, type: !20) -!187 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "eta", line: 310, scope: !183, file: !5, type: !20) -!188 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "zeta", line: 310, scope: !183, file: !5, type: !20) -!189 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "dtpp", line: 310, scope: !183, file: !5, type: !20) -!190 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 311, scope: !183, file: !5, type: !8) -!191 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 311, scope: !183, file: !5, type: !8) -!192 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 311, scope: !183, file: !5, type: !8) -!193 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 311, scope: !183, file: !5, type: !8) -!194 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "ip1", line: 311, scope: !183, file: !5, type: !8) -!195 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "im1", line: 311, scope: !183, file: !5, type: !8) -!196 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "jp1", line: 311, scope: !183, file: !5, type: !8) -!197 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "jm1", line: 311, scope: !183, file: !5, type: !8) -!198 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "km1", line: 311, scope: !183, file: !5, type: !8) -!199 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "kp1", line: 311, scope: !183, file: !5, type: !8) -!200 = !DISubprogram(name: "adi", line: 210, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 210, file: !1, scope: !5, type: !115, variables: !2) -!201 = !DISubprogram(name: "add", line: 187, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 187, file: !1, scope: !5, type: !115, variables: !202) +!185 = !DILocalVariable(name: "dtemp", line: 310, scope: !183, file: !5, type: !91) +!186 = !DILocalVariable(name: "xi", line: 310, scope: !183, file: !5, type: !20) +!187 = !DILocalVariable(name: "eta", line: 310, scope: !183, file: !5, type: !20) +!188 = !DILocalVariable(name: "zeta", line: 310, scope: !183, file: !5, type: !20) +!189 = !DILocalVariable(name: "dtpp", line: 310, scope: !183, file: !5, type: !20) +!190 = !DILocalVariable(name: "m", line: 311, scope: !183, file: !5, type: !8) +!191 = !DILocalVariable(name: "i", line: 311, scope: !183, file: !5, type: !8) +!192 = !DILocalVariable(name: "j", line: 311, scope: !183, file: !5, type: !8) +!193 = !DILocalVariable(name: "k", line: 311, scope: !183, file: !5, type: !8) +!194 = !DILocalVariable(name: "ip1", line: 311, scope: !183, file: !5, type: !8) +!195 = !DILocalVariable(name: "im1", line: 311, scope: !183, file: !5, type: !8) +!196 = !DILocalVariable(name: "jp1", line: 311, scope: !183, file: !5, type: !8) +!197 = !DILocalVariable(name: "jm1", line: 311, scope: !183, file: !5, type: !8) +!198 = !DILocalVariable(name: "km1", line: 311, scope: !183, file: !5, type: !8) +!199 = !DILocalVariable(name: "kp1", line: 311, scope: !183, file: !5, type: !8) +!200 = distinct !DISubprogram(name: "adi", line: 210, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 210, file: !1, scope: !5, type: !115, variables: !2) +!201 = distinct !DISubprogram(name: "add", line: 187, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 187, file: !1, scope: !5, type: !115, variables: !202) !202 = !{!203, !204, !205, !206} -!203 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 193, scope: !201, file: !5, type: !8) -!204 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 193, scope: !201, file: !5, type: !8) -!205 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 193, scope: !201, file: !5, type: !8) -!206 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 193, scope: !201, file: !5, type: !8) -!207 = !DISubprogram(name: "z_solve", line: 3457, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3457, file: !1, scope: !5, type: !115, variables: !2) -!208 = !DISubprogram(name: "z_backsubstitute", line: 3480, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3480, file: !1, scope: !5, type: !115, variables: !209) +!203 = !DILocalVariable(name: "i", line: 193, scope: !201, file: !5, type: !8) +!204 = !DILocalVariable(name: "j", line: 193, scope: !201, file: !5, type: !8) +!205 = !DILocalVariable(name: "k", line: 193, scope: !201, file: !5, type: !8) +!206 = !DILocalVariable(name: "m", line: 193, scope: !201, file: !5, type: !8) +!207 = distinct !DISubprogram(name: "z_solve", line: 3457, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3457, file: !1, scope: !5, type: !115, variables: !2) +!208 = distinct !DISubprogram(name: "z_backsubstitute", line: 3480, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3480, file: !1, scope: !5, type: !115, variables: !209) !209 = !{!210, !211, !212, !213, !214} -!210 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3492, scope: !208, file: !5, type: !8) -!211 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 3492, scope: !208, file: !5, type: !8) -!212 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3492, scope: !208, file: !5, type: !8) -!213 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 3492, scope: !208, file: !5, type: !8) -!214 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n", line: 3492, scope: !208, file: !5, type: !8) -!215 = !DISubprogram(name: "z_solve_cell", line: 3512, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3512, file: !1, scope: !5, type: !115, variables: !216) +!210 = !DILocalVariable(name: "i", line: 3492, scope: !208, file: !5, type: !8) +!211 = !DILocalVariable(name: "j", line: 3492, scope: !208, file: !5, type: !8) +!212 = !DILocalVariable(name: "k", line: 3492, scope: !208, file: !5, type: !8) +!213 = !DILocalVariable(name: "m", line: 3492, scope: !208, file: !5, type: !8) +!214 = !DILocalVariable(name: "n", line: 3492, scope: !208, file: !5, type: !8) +!215 = distinct !DISubprogram(name: "z_solve_cell", line: 3512, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3512, file: !1, scope: !5, type: !115, variables: !216) !216 = !{!217, !218, !219, !220} -!217 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3527, scope: !215, file: !5, type: !8) -!218 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 3527, scope: !215, file: !5, type: !8) -!219 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3527, scope: !215, file: !5, type: !8) -!220 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "ksize", line: 3527, scope: !215, file: !5, type: !8) -!221 = !DISubprogram(name: "binvrhs", line: 3154, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3154, file: !1, scope: !5, type: !222, variables: !225) +!217 = !DILocalVariable(name: "i", line: 3527, scope: !215, file: !5, type: !8) +!218 = !DILocalVariable(name: "j", line: 3527, scope: !215, file: !5, type: !8) +!219 = !DILocalVariable(name: "k", line: 3527, scope: !215, file: !5, type: !8) +!220 = !DILocalVariable(name: "ksize", line: 3527, scope: !215, file: !5, type: !8) +!221 = distinct !DISubprogram(name: "binvrhs", line: 3154, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3154, file: !1, scope: !5, type: !222, variables: !225) !222 = !DISubroutineType(types: !223) !223 = !{null, !224, !105} !224 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !91) !225 = !{!226, !227, !228, !229} -!226 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "lhs", line: 3154, arg: 1, scope: !221, file: !5, type: !224) -!227 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "r", line: 3154, arg: 2, scope: !221, file: !5, type: !105) -!228 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "pivot", line: 3159, scope: !221, file: !5, type: !20) -!229 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "coeff", line: 3159, scope: !221, file: !5, type: !20) -!230 = !DISubprogram(name: "matmul_sub", line: 2841, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2842, file: !1, scope: !5, type: !231, variables: !233) +!226 = !DILocalVariable(name: "lhs", line: 3154, arg: 1, scope: !221, file: !5, type: !224) +!227 = !DILocalVariable(name: "r", line: 3154, arg: 2, scope: !221, file: !5, type: !105) +!228 = !DILocalVariable(name: "pivot", line: 3159, scope: !221, file: !5, type: !20) +!229 = !DILocalVariable(name: "coeff", line: 3159, scope: !221, file: !5, type: !20) +!230 = distinct !DISubprogram(name: "matmul_sub", line: 2841, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2842, file: !1, scope: !5, type: !231, variables: !233) !231 = !DISubroutineType(types: !232) !232 = !{null, !224, !224, !224} !233 = !{!234, !235, !236, !237} -!234 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ablock", line: 2841, arg: 1, scope: !230, file: !5, type: !224) -!235 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bblock", line: 2841, arg: 2, scope: !230, file: !5, type: !224) -!236 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "cblock", line: 2842, arg: 3, scope: !230, file: !5, type: !224) -!237 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 2851, scope: !230, file: !5, type: !8) -!238 = !DISubprogram(name: "matvec_sub", line: 2814, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2814, file: !1, scope: !5, type: !239, variables: !241) +!234 = !DILocalVariable(name: "ablock", line: 2841, arg: 1, scope: !230, file: !5, type: !224) +!235 = !DILocalVariable(name: "bblock", line: 2841, arg: 2, scope: !230, file: !5, type: !224) +!236 = !DILocalVariable(name: "cblock", line: 2842, arg: 3, scope: !230, file: !5, type: !224) +!237 = !DILocalVariable(name: "j", line: 2851, scope: !230, file: !5, type: !8) +!238 = distinct !DISubprogram(name: "matvec_sub", line: 2814, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2814, file: !1, scope: !5, type: !239, variables: !241) !239 = !DISubroutineType(types: !240) !240 = !{null, !224, !105, !105} !241 = !{!242, !243, !244, !245} -!242 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "ablock", line: 2814, arg: 1, scope: !238, file: !5, type: !224) -!243 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "avec", line: 2814, arg: 2, scope: !238, file: !5, type: !105) -!244 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "bvec", line: 2814, arg: 3, scope: !238, file: !5, type: !105) -!245 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2823, scope: !238, file: !5, type: !8) -!246 = !DISubprogram(name: "binvcrhs", line: 2885, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2885, file: !1, scope: !5, type: !247, variables: !249) +!242 = !DILocalVariable(name: "ablock", line: 2814, arg: 1, scope: !238, file: !5, type: !224) +!243 = !DILocalVariable(name: "avec", line: 2814, arg: 2, scope: !238, file: !5, type: !105) +!244 = !DILocalVariable(name: "bvec", line: 2814, arg: 3, scope: !238, file: !5, type: !105) +!245 = !DILocalVariable(name: "i", line: 2823, scope: !238, file: !5, type: !8) +!246 = distinct !DISubprogram(name: "binvcrhs", line: 2885, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2885, file: !1, scope: !5, type: !247, variables: !249) !247 = !DISubroutineType(types: !248) !248 = !{null, !224, !224, !105} !249 = !{!250, !251, !252, !253, !254} -!250 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "lhs", line: 2885, arg: 1, scope: !246, file: !5, type: !224) -!251 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 2885, arg: 2, scope: !246, file: !5, type: !224) -!252 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "r", line: 2885, arg: 3, scope: !246, file: !5, type: !105) -!253 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "pivot", line: 2890, scope: !246, file: !5, type: !20) -!254 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "coeff", line: 2890, scope: !246, file: !5, type: !20) -!255 = !DISubprogram(name: "lhsz", line: 1475, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1475, file: !1, scope: !5, type: !115, variables: !256) +!250 = !DILocalVariable(name: "lhs", line: 2885, arg: 1, scope: !246, file: !5, type: !224) +!251 = !DILocalVariable(name: "c", line: 2885, arg: 2, scope: !246, file: !5, type: !224) +!252 = !DILocalVariable(name: "r", line: 2885, arg: 3, scope: !246, file: !5, type: !105) +!253 = !DILocalVariable(name: "pivot", line: 2890, scope: !246, file: !5, type: !20) +!254 = !DILocalVariable(name: "coeff", line: 2890, scope: !246, file: !5, type: !20) +!255 = distinct !DISubprogram(name: "lhsz", line: 1475, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1475, file: !1, scope: !5, type: !115, variables: !256) !256 = !{!257, !258, !259} -!257 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 1484, scope: !255, file: !5, type: !8) -!258 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 1484, scope: !255, file: !5, type: !8) -!259 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 1484, scope: !255, file: !5, type: !8) -!260 = !DISubprogram(name: "y_solve", line: 3299, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3299, file: !1, scope: !5, type: !115, variables: !2) -!261 = !DISubprogram(name: "y_backsubstitute", line: 3323, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3323, file: !1, scope: !5, type: !115, variables: !262) +!257 = !DILocalVariable(name: "i", line: 1484, scope: !255, file: !5, type: !8) +!258 = !DILocalVariable(name: "j", line: 1484, scope: !255, file: !5, type: !8) +!259 = !DILocalVariable(name: "k", line: 1484, scope: !255, file: !5, type: !8) +!260 = distinct !DISubprogram(name: "y_solve", line: 3299, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3299, file: !1, scope: !5, type: !115, variables: !2) +!261 = distinct !DISubprogram(name: "y_backsubstitute", line: 3323, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3323, file: !1, scope: !5, type: !115, variables: !262) !262 = !{!263, !264, !265, !266, !267} -!263 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3335, scope: !261, file: !5, type: !8) -!264 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 3335, scope: !261, file: !5, type: !8) -!265 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3335, scope: !261, file: !5, type: !8) -!266 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 3335, scope: !261, file: !5, type: !8) -!267 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n", line: 3335, scope: !261, file: !5, type: !8) -!268 = !DISubprogram(name: "y_solve_cell", line: 3355, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3355, file: !1, scope: !5, type: !115, variables: !269) +!263 = !DILocalVariable(name: "i", line: 3335, scope: !261, file: !5, type: !8) +!264 = !DILocalVariable(name: "j", line: 3335, scope: !261, file: !5, type: !8) +!265 = !DILocalVariable(name: "k", line: 3335, scope: !261, file: !5, type: !8) +!266 = !DILocalVariable(name: "m", line: 3335, scope: !261, file: !5, type: !8) +!267 = !DILocalVariable(name: "n", line: 3335, scope: !261, file: !5, type: !8) +!268 = distinct !DISubprogram(name: "y_solve_cell", line: 3355, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3355, file: !1, scope: !5, type: !115, variables: !269) !269 = !{!270, !271, !272, !273} -!270 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 3370, scope: !268, file: !5, type: !8) -!271 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 3370, scope: !268, file: !5, type: !8) -!272 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 3370, scope: !268, file: !5, type: !8) -!273 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "jsize", line: 3370, scope: !268, file: !5, type: !8) -!274 = !DISubprogram(name: "lhsy", line: 1181, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1181, file: !1, scope: !5, type: !115, variables: !275) +!270 = !DILocalVariable(name: "i", line: 3370, scope: !268, file: !5, type: !8) +!271 = !DILocalVariable(name: "j", line: 3370, scope: !268, file: !5, type: !8) +!272 = !DILocalVariable(name: "k", line: 3370, scope: !268, file: !5, type: !8) +!273 = !DILocalVariable(name: "jsize", line: 3370, scope: !268, file: !5, type: !8) +!274 = distinct !DISubprogram(name: "lhsy", line: 1181, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1181, file: !1, scope: !5, type: !115, variables: !275) !275 = !{!276, !277, !278} -!276 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 1190, scope: !274, file: !5, type: !8) -!277 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 1190, scope: !274, file: !5, type: !8) -!278 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 1190, scope: !274, file: !5, type: !8) -!279 = !DISubprogram(name: "x_solve", line: 2658, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2658, file: !1, scope: !5, type: !115, variables: !2) -!280 = !DISubprogram(name: "x_backsubstitute", line: 2684, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2684, file: !1, scope: !5, type: !115, variables: !281) +!276 = !DILocalVariable(name: "i", line: 1190, scope: !274, file: !5, type: !8) +!277 = !DILocalVariable(name: "j", line: 1190, scope: !274, file: !5, type: !8) +!278 = !DILocalVariable(name: "k", line: 1190, scope: !274, file: !5, type: !8) +!279 = distinct !DISubprogram(name: "x_solve", line: 2658, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2658, file: !1, scope: !5, type: !115, variables: !2) +!280 = distinct !DISubprogram(name: "x_backsubstitute", line: 2684, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2684, file: !1, scope: !5, type: !115, variables: !281) !281 = !{!282, !283, !284, !285, !286} -!282 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2696, scope: !280, file: !5, type: !8) -!283 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 2696, scope: !280, file: !5, type: !8) -!284 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 2696, scope: !280, file: !5, type: !8) -!285 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "m", line: 2696, scope: !280, file: !5, type: !8) -!286 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "n", line: 2696, scope: !280, file: !5, type: !8) -!287 = !DISubprogram(name: "x_solve_cell", line: 2716, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2716, file: !1, scope: !5, type: !115, variables: !288) +!282 = !DILocalVariable(name: "i", line: 2696, scope: !280, file: !5, type: !8) +!283 = !DILocalVariable(name: "j", line: 2696, scope: !280, file: !5, type: !8) +!284 = !DILocalVariable(name: "k", line: 2696, scope: !280, file: !5, type: !8) +!285 = !DILocalVariable(name: "m", line: 2696, scope: !280, file: !5, type: !8) +!286 = !DILocalVariable(name: "n", line: 2696, scope: !280, file: !5, type: !8) +!287 = distinct !DISubprogram(name: "x_solve_cell", line: 2716, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2716, file: !1, scope: !5, type: !115, variables: !288) !288 = !{!289, !290, !291, !292} -!289 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2728, scope: !287, file: !5, type: !8) -!290 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 2728, scope: !287, file: !5, type: !8) -!291 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 2728, scope: !287, file: !5, type: !8) -!292 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "isize", line: 2728, scope: !287, file: !5, type: !8) -!293 = !DISubprogram(name: "lhsx", line: 898, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 898, file: !1, scope: !5, type: !115, variables: !294) +!289 = !DILocalVariable(name: "i", line: 2728, scope: !287, file: !5, type: !8) +!290 = !DILocalVariable(name: "j", line: 2728, scope: !287, file: !5, type: !8) +!291 = !DILocalVariable(name: "k", line: 2728, scope: !287, file: !5, type: !8) +!292 = !DILocalVariable(name: "isize", line: 2728, scope: !287, file: !5, type: !8) +!293 = distinct !DISubprogram(name: "lhsx", line: 898, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 898, file: !1, scope: !5, type: !115, variables: !294) !294 = !{!295, !296, !297} -!295 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 907, scope: !293, file: !5, type: !8) -!296 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "j", line: 907, scope: !293, file: !5, type: !8) -!297 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "k", line: 907, scope: !293, file: !5, type: !8) +!295 = !DILocalVariable(name: "i", line: 907, scope: !293, file: !5, type: !8) +!296 = !DILocalVariable(name: "j", line: 907, scope: !293, file: !5, type: !8) +!297 = !DILocalVariable(name: "k", line: 907, scope: !293, file: !5, type: !8) !298 = !{!299, !304, !305, !309, !310, !311, !312, !313, !314, !315, !316, !317, !318, !319, !320, !321, !322, !323, !324, !325, !326, !327, !328, !329, !330, !331, !332, !333, !334, !335, !336, !337, !338, !339, !340, !341, !342, !343, !347, !350, !351, !352, !353, !354, !355, !356, !360, !361, !362, !363, !364, !365, !366, !367, !368, !369, !370, !371, !372, !373, !374, !375, !376, !377, !378, !379, !380, !381, !382, !383, !384, !385, !386, !387, !388, !389, !390, !391, !392, !393, !394, !395, !396, !397, !398, !399, !400, !401, !402, !403, !404, !405, !406, !407, !408, !409, !410, !411, !412, !413, !414, !415, !416, !417, !418, !419, !422, !426, !427, !430, !431, !434, !435, !436, !437} !299 = !DIGlobalVariable(name: "grid_points", line: 28, isLocal: true, isDefinition: true, scope: null, file: !300, type: !302, variable: [3 x i32]* @grid_points) !300 = !DIFile(filename: "./header.h", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT") diff --git a/test/CodeGen/PowerPC/pr24546.ll b/test/CodeGen/PowerPC/pr24546.ll index 3bb638af2343..06f6bc93da99 100644 --- a/test/CodeGen/PowerPC/pr24546.ll +++ b/test/CodeGen/PowerPC/pr24546.ll @@ -6,7 +6,7 @@ @php_intpow10.powers = external unnamed_addr constant [23 x double], align 8 ; Function Attrs: nounwind -define double @_php_math_round(double %value, i32 signext %places, i32 signext %mode) #0 { +define double @_php_math_round(double %value, i32 signext %places, i32 signext %mode) #0 !dbg !6 { entry: br i1 undef, label %if.then, label %if.else, !dbg !32 @@ -62,23 +62,23 @@ attributes #3 = { nounwind } !3 = !{!4} !4 = !DIBasicType(name: "double", size: 64, align: 64, encoding: DW_ATE_float) !5 = !{!6, !18} -!6 = !DISubprogram(name: "_php_math_round", scope: !1, file: !1, line: 15, type: !7, isLocal: false, isDefinition: true, scopeLine: 16, flags: DIFlagPrototyped, isOptimized: true, function: double (double, i32, i32)* @_php_math_round, variables: !10) +!6 = distinct !DISubprogram(name: "_php_math_round", scope: !1, file: !1, line: 15, type: !7, isLocal: false, isDefinition: true, scopeLine: 16, flags: DIFlagPrototyped, isOptimized: true, variables: !10) !7 = !DISubroutineType(types: !8) !8 = !{!4, !4, !9, !9} !9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !10 = !{!11, !12, !13, !14, !15, !16, !17} -!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", arg: 1, scope: !6, file: !1, line: 15, type: !4) -!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "places", arg: 2, scope: !6, file: !1, line: 15, type: !9) -!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "mode", arg: 3, scope: !6, file: !1, line: 15, type: !9) -!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "f1", scope: !6, file: !1, line: 17, type: !4) -!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "f2", scope: !6, file: !1, line: 17, type: !4) -!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "tmp_value", scope: !6, file: !1, line: 18, type: !4) -!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "precision_places", scope: !6, file: !1, line: 19, type: !9) -!18 = !DISubprogram(name: "php_intpow10", scope: !1, file: !1, line: 1, type: !19, isLocal: true, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, variables: !21) +!11 = !DILocalVariable(name: "value", arg: 1, scope: !6, file: !1, line: 15, type: !4) +!12 = !DILocalVariable(name: "places", arg: 2, scope: !6, file: !1, line: 15, type: !9) +!13 = !DILocalVariable(name: "mode", arg: 3, scope: !6, file: !1, line: 15, type: !9) +!14 = !DILocalVariable(name: "f1", scope: !6, file: !1, line: 17, type: !4) +!15 = !DILocalVariable(name: "f2", scope: !6, file: !1, line: 17, type: !4) +!16 = !DILocalVariable(name: "tmp_value", scope: !6, file: !1, line: 18, type: !4) +!17 = !DILocalVariable(name: "precision_places", scope: !6, file: !1, line: 19, type: !9) +!18 = distinct !DISubprogram(name: "php_intpow10", scope: !1, file: !1, line: 1, type: !19, isLocal: true, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, variables: !21) !19 = !DISubroutineType(types: !20) !20 = !{!4, !9} !21 = !{!22} -!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "power", arg: 1, scope: !18, file: !1, line: 1, type: !9) +!22 = !DILocalVariable(name: "power", arg: 1, scope: !18, file: !1, line: 1, type: !9) !23 = !{!24} !24 = !DIGlobalVariable(name: "powers", scope: !18, file: !1, line: 3, type: !25, isLocal: true, isDefinition: true, variable: [23 x double]* @php_intpow10.powers) !25 = !DICompositeType(tag: DW_TAG_array_type, baseType: !26, size: 1472, align: 64, elements: !27) diff --git a/test/CodeGen/PowerPC/pr24636.ll b/test/CodeGen/PowerPC/pr24636.ll new file mode 100644 index 000000000000..cc51dd38f9e2 --- /dev/null +++ b/test/CodeGen/PowerPC/pr24636.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +@c = external global i32, align 4 +@b = external global [1 x i32], align 4 + +; Function Attrs: nounwind +define void @fn2() #0 align 4 { + br i1 undef, label %.lr.ph, label %4 + +; We used to crash because a bad DAGCombine was creating i32-typed SETCC nodes, +; even when crbits are enabled. +; CHECK-LABEL: @fn2 +; CHECK: blr + +.lr.ph: ; preds = %0 + br i1 undef, label %.lr.ph.split, label %.preheader + +.preheader: ; preds = %.preheader, %.lr.ph + br i1 undef, label %.lr.ph.split, label %.preheader + +.lr.ph.split: ; preds = %.preheader, %.lr.ph + br i1 undef, label %._crit_edge, label %.lr.ph.split.split + +.lr.ph.split.split: ; preds = %.lr.ph.split.split, %.lr.ph.split + %1 = phi i32 [ %2, %.lr.ph.split.split ], [ undef, %.lr.ph.split ] + %2 = and i32 %1, and (i32 and (i32 and (i32 and (i32 and (i32 and (i32 and (i32 zext (i1 select (i1 icmp eq ([1 x i32]* bitcast (i32* @c to [1 x i32]*), [1 x i32]* @b), i1 true, i1 false) to i32), i32 zext (i1 select (i1 icmp eq ([1 x i32]* bitcast (i32* @c to [1 x i32]*), [1 x i32]* @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq ([1 x i32]* bitcast (i32* @c to [1 x i32]*), [1 x i32]* @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq ([1 x i32]* bitcast (i32* @c to [1 x i32]*), [1 x i32]* @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq ([1 x i32]* bitcast (i32* @c to [1 x i32]*), [1 x i32]* @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq ([1 x i32]* bitcast (i32* @c to [1 x i32]*), [1 x i32]* @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq ([1 x i32]* bitcast (i32* @c to [1 x i32]*), [1 x i32]* @b), i1 true, i1 false) to i32)), i32 zext (i1 select (i1 icmp eq ([1 x i32]* bitcast (i32* @c to [1 x i32]*), [1 x i32]* @b), i1 true, i1 false) to i32)) + %3 = icmp slt i32 undef, 4 + br i1 %3, label %.lr.ph.split.split, label %._crit_edge + +._crit_edge: ; preds = %.lr.ph.split.split, %.lr.ph.split + %.lcssa = phi i32 [ undef, %.lr.ph.split ], [ %2, %.lr.ph.split.split ] + br label %4 + +; <label>:4 ; preds = %._crit_edge, %0 + ret void +} + +attributes #0 = { nounwind "target-cpu"="ppc64le" } + diff --git a/test/CodeGen/PowerPC/pr25157-peephole.ll b/test/CodeGen/PowerPC/pr25157-peephole.ll new file mode 100644 index 000000000000..c5bd49b492cc --- /dev/null +++ b/test/CodeGen/PowerPC/pr25157-peephole.ll @@ -0,0 +1,61 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +; Verify peephole simplification of splats and swaps. Bugpoint-reduced +; test from Eric Schweitz. + +%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625 = type <{ [28 x i8] }> +%struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626 = type <{ [64 x i8] }> + +@.BSS38 = external global %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, align 32 +@_main1_2_ = external global %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, section ".comm", align 16 + +define void @aercalc_() { +L.entry: + br i1 undef, label %L.LB38_2426, label %L.LB38_2911 + +L.LB38_2911: + br i1 undef, label %L.LB38_2140, label %L.LB38_2640 + +L.LB38_2640: + unreachable + +L.LB38_2426: + br i1 undef, label %L.LB38_2438, label %L.LB38_2920 + +L.LB38_2920: + br i1 undef, label %L.LB38_2438, label %L.LB38_2921 + +L.LB38_2921: + br label %L.LB38_2140 + +L.LB38_2140: + ret void + +L.LB38_2438: + br i1 undef, label %L.LB38_2451, label %L.LB38_2935 + +L.LB38_2935: + br i1 undef, label %L.LB38_2451, label %L.LB38_2936 + +L.LB38_2936: + unreachable + +L.LB38_2451: + br i1 undef, label %L.LB38_2452, label %L.LB38_2937 + +L.LB38_2937: + unreachable + +L.LB38_2452: + %0 = load float, float* bitcast (i8* getelementptr inbounds (%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625* @.BSS38, i64 0, i32 0, i64 16) to float*), align 16 + %1 = fpext float %0 to double + %2 = insertelement <2 x double> undef, double %1, i32 1 + store <2 x double> %2, <2 x double>* bitcast (i8* getelementptr inbounds (%struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626* @_main1_2_, i64 0, i32 0, i64 32) to <2 x double>*), align 16 + unreachable +} + +; CHECK-LABEL: @aercalc_ +; CHECK: lxsspx +; CHECK: xxspltd +; CHECK: stxvd2x +; CHECK-NOT: xxswapd diff --git a/test/CodeGen/PowerPC/preincprep-nontrans-crash.ll b/test/CodeGen/PowerPC/preincprep-nontrans-crash.ll new file mode 100644 index 000000000000..cfec302d4690 --- /dev/null +++ b/test/CodeGen/PowerPC/preincprep-nontrans-crash.ll @@ -0,0 +1,94 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:64:64-i64:64-n32:64" +target triple = "powerpc64le-linux" + +%struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144 = type <{ [220 x i8] }> + +@.BSS1 = external unnamed_addr global %struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144, align 32 + +; Function Attrs: noinline nounwind +define void @ety2_() #0 { + +; This test case used to crash because the preinc prep pass would assume that +; if X-Y could be simplified to a constant, than so could Y-X. While not +; desirable, we cannot actually make this guarantee. +; CHECK-LABEL: @ety2_ + +L.entry: + %0 = load i32, i32* undef, align 4 + %1 = sext i32 %0 to i64 + %2 = shl nsw i64 %1, 3 + %3 = add nsw i64 %2, 8 + br label %L.LB1_425 + +L.LB1_425: ; preds = %L.LB1_427, %L.entry + %4 = phi i64 [ %21, %L.LB1_427 ], [ undef, %L.entry ] + br i1 undef, label %L.LB1_427, label %L.LB1_816 + +L.LB1_816: ; preds = %L.LB1_425 + switch i32 undef, label %L.LB1_432 [ + i32 30, label %L.LB1_805 + i32 10, label %L.LB1_451 + i32 20, label %L.LB1_451 + ] + +L.LB1_451: ; preds = %L.LB1_816, %L.LB1_816 + unreachable + +L.LB1_432: ; preds = %L.LB1_816 + %.in.31 = lshr i64 %4, 32 + %5 = trunc i64 %.in.31 to i32 + br i1 undef, label %L.LB1_769, label %L.LB1_455 + +L.LB1_455: ; preds = %L.LB1_432 + unreachable + +L.LB1_769: ; preds = %L.LB1_432 + %6 = sext i32 %5 to i64 + %7 = add nsw i64 %6, 2 + %8 = add nsw i64 %6, -1 + %9 = mul i64 %8, %1 + %10 = add i64 %9, %7 + %11 = shl i64 %10, 3 + %12 = getelementptr i8, i8* undef, i64 %11 + %13 = mul nsw i64 %6, %1 + %14 = add i64 %7, %13 + %15 = shl i64 %14, 3 + %16 = getelementptr i8, i8* undef, i64 %15 + br i1 undef, label %L.LB1_662, label %L.LB1_662.prol + +L.LB1_662.prol: ; preds = %L.LB1_662.prol, %L.LB1_769 + %indvars.iv.next20.prol = add nuw nsw i64 undef, 1 + br i1 undef, label %L.LB1_662, label %L.LB1_662.prol + +L.LB1_662: ; preds = %L.LB1_437.2, %L.LB1_662.prol, %L.LB1_769 + %indvars.iv19 = phi i64 [ %indvars.iv.next20.3, %L.LB1_437.2 ], [ 0, %L.LB1_769 ], [ %indvars.iv.next20.prol, %L.LB1_662.prol ] + %indvars.iv.next20 = add nuw nsw i64 %indvars.iv19, 1 + %17 = mul i64 %indvars.iv.next20, %3 + %18 = getelementptr i8, i8* %16, i64 %17 + %19 = bitcast i8* %18 to double* + store double 0.000000e+00, double* %19, align 8 + %indvars.iv.next20.1 = add nsw i64 %indvars.iv19, 2 + %20 = mul i64 %indvars.iv.next20.1, %3 + br i1 undef, label %L.LB1_437.2, label %L.LB1_824.2 + +L.LB1_427: ; preds = %L.LB1_425 + %21 = load i64, i64* bitcast (i8* getelementptr inbounds (%struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144, %struct.BSS1.0.9.28.39.43.46.47.54.56.57.64.65.69.71.144* @.BSS1, i64 0, i32 0, i64 8) to i64*), align 8 + br label %L.LB1_425 + +L.LB1_805: ; preds = %L.LB1_816 + ret void + +L.LB1_824.2: ; preds = %L.LB1_662 + %22 = getelementptr i8, i8* %12, i64 %20 + %23 = bitcast i8* %22 to double* + store double 0.000000e+00, double* %23, align 8 + br label %L.LB1_437.2 + +L.LB1_437.2: ; preds = %L.LB1_824.2, %L.LB1_662 + %indvars.iv.next20.3 = add nsw i64 %indvars.iv19, 4 + br label %L.LB1_662 +} + +attributes #0 = { noinline nounwind } + diff --git a/test/CodeGen/PowerPC/qpx-unal-cons-lds.ll b/test/CodeGen/PowerPC/qpx-unal-cons-lds.ll new file mode 100644 index 000000000000..606c0551a56c --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-unal-cons-lds.ll @@ -0,0 +1,217 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo(double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 { +entry: + br label %vector.body + +; CHECK-LABEL: @foo +; Make sure that the offset constants we use are all even (only the last should be odd). +; CHECK-DAG: li {{[0-9]+}}, 1056 +; CHECK-DAG: li {{[0-9]+}}, 1088 +; CHECK-DAG: li {{[0-9]+}}, 1152 +; CHECK-DAG: li {{[0-9]+}}, 1216 +; CHECK-DAG: li {{[0-9]+}}, 1280 +; CHECK-DAG: li {{[0-9]+}}, 1344 +; CHECK-DAG: li {{[0-9]+}}, 1408 +; CHECK-DAG: li {{[0-9]+}}, 1472 +; CHECK-DAG: li {{[0-9]+}}, 1536 +; CHECK-DAG: li {{[0-9]+}}, 1600 +; CHECK-DAG: li {{[0-9]+}}, 1568 +; CHECK-DAG: li {{[0-9]+}}, 1664 +; CHECK-DAG: li {{[0-9]+}}, 1632 +; CHECK-DAG: li {{[0-9]+}}, 1728 +; CHECK-DAG: li {{[0-9]+}}, 1696 +; CHECK-DAG: li {{[0-9]+}}, 1792 +; CHECK-DAG: li {{[0-9]+}}, 1760 +; CHECK-DAG: li {{[0-9]+}}, 1856 +; CHECK-DAG: li {{[0-9]+}}, 1824 +; CHECK-DAG: li {{[0-9]+}}, 1920 +; CHECK-DAG: li {{[0-9]+}}, 1888 +; CHECK-DAG: li {{[0-9]+}}, 1984 +; CHECK-DAG: li {{[0-9]+}}, 1952 +; CHECK-DAG: li {{[0-9]+}}, 2016 +; CHECK-DAG: li {{[0-9]+}}, 1024 +; CHECK-DAG: li {{[0-9]+}}, 1120 +; CHECK-DAG: li {{[0-9]+}}, 1184 +; CHECK-DAG: li {{[0-9]+}}, 1248 +; CHECK-DAG: li {{[0-9]+}}, 1312 +; CHECK-DAG: li {{[0-9]+}}, 1376 +; CHECK-DAG: li {{[0-9]+}}, 1440 +; CHECK-DAG: li {{[0-9]+}}, 1504 +; CHECK-DAG: li {{[0-9]+}}, 2047 +; CHECK: blr + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next.15, %vector.body ] + %0 = shl i64 %index, 1 + %1 = getelementptr inbounds double, double* %b, i64 %0 + %2 = bitcast double* %1 to <8 x double>* + %wide.vec = load <8 x double>, <8 x double>* %2, align 8 + %strided.vec = shufflevector <8 x double> %wide.vec, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %3 = fadd <4 x double> %strided.vec, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %4 = getelementptr inbounds double, double* %a, i64 %index + %5 = bitcast double* %4 to <4 x double>* + store <4 x double> %3, <4 x double>* %5, align 8 + %index.next = or i64 %index, 4 + %6 = shl i64 %index.next, 1 + %7 = getelementptr inbounds double, double* %b, i64 %6 + %8 = bitcast double* %7 to <8 x double>* + %wide.vec.1 = load <8 x double>, <8 x double>* %8, align 8 + %strided.vec.1 = shufflevector <8 x double> %wide.vec.1, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %9 = fadd <4 x double> %strided.vec.1, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %10 = getelementptr inbounds double, double* %a, i64 %index.next + %11 = bitcast double* %10 to <4 x double>* + store <4 x double> %9, <4 x double>* %11, align 8 + %index.next.1 = or i64 %index, 8 + %12 = shl i64 %index.next.1, 1 + %13 = getelementptr inbounds double, double* %b, i64 %12 + %14 = bitcast double* %13 to <8 x double>* + %wide.vec.2 = load <8 x double>, <8 x double>* %14, align 8 + %strided.vec.2 = shufflevector <8 x double> %wide.vec.2, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %15 = fadd <4 x double> %strided.vec.2, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %16 = getelementptr inbounds double, double* %a, i64 %index.next.1 + %17 = bitcast double* %16 to <4 x double>* + store <4 x double> %15, <4 x double>* %17, align 8 + %index.next.2 = or i64 %index, 12 + %18 = shl i64 %index.next.2, 1 + %19 = getelementptr inbounds double, double* %b, i64 %18 + %20 = bitcast double* %19 to <8 x double>* + %wide.vec.3 = load <8 x double>, <8 x double>* %20, align 8 + %strided.vec.3 = shufflevector <8 x double> %wide.vec.3, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %21 = fadd <4 x double> %strided.vec.3, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %22 = getelementptr inbounds double, double* %a, i64 %index.next.2 + %23 = bitcast double* %22 to <4 x double>* + store <4 x double> %21, <4 x double>* %23, align 8 + %index.next.3 = or i64 %index, 16 + %24 = shl i64 %index.next.3, 1 + %25 = getelementptr inbounds double, double* %b, i64 %24 + %26 = bitcast double* %25 to <8 x double>* + %wide.vec.4 = load <8 x double>, <8 x double>* %26, align 8 + %strided.vec.4 = shufflevector <8 x double> %wide.vec.4, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %27 = fadd <4 x double> %strided.vec.4, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %28 = getelementptr inbounds double, double* %a, i64 %index.next.3 + %29 = bitcast double* %28 to <4 x double>* + store <4 x double> %27, <4 x double>* %29, align 8 + %index.next.4 = or i64 %index, 20 + %30 = shl i64 %index.next.4, 1 + %31 = getelementptr inbounds double, double* %b, i64 %30 + %32 = bitcast double* %31 to <8 x double>* + %wide.vec.5 = load <8 x double>, <8 x double>* %32, align 8 + %strided.vec.5 = shufflevector <8 x double> %wide.vec.5, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %33 = fadd <4 x double> %strided.vec.5, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %34 = getelementptr inbounds double, double* %a, i64 %index.next.4 + %35 = bitcast double* %34 to <4 x double>* + store <4 x double> %33, <4 x double>* %35, align 8 + %index.next.5 = or i64 %index, 24 + %36 = shl i64 %index.next.5, 1 + %37 = getelementptr inbounds double, double* %b, i64 %36 + %38 = bitcast double* %37 to <8 x double>* + %wide.vec.6 = load <8 x double>, <8 x double>* %38, align 8 + %strided.vec.6 = shufflevector <8 x double> %wide.vec.6, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %39 = fadd <4 x double> %strided.vec.6, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %40 = getelementptr inbounds double, double* %a, i64 %index.next.5 + %41 = bitcast double* %40 to <4 x double>* + store <4 x double> %39, <4 x double>* %41, align 8 + %index.next.6 = or i64 %index, 28 + %42 = shl i64 %index.next.6, 1 + %43 = getelementptr inbounds double, double* %b, i64 %42 + %44 = bitcast double* %43 to <8 x double>* + %wide.vec.7 = load <8 x double>, <8 x double>* %44, align 8 + %strided.vec.7 = shufflevector <8 x double> %wide.vec.7, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %45 = fadd <4 x double> %strided.vec.7, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %46 = getelementptr inbounds double, double* %a, i64 %index.next.6 + %47 = bitcast double* %46 to <4 x double>* + store <4 x double> %45, <4 x double>* %47, align 8 + %index.next.7 = or i64 %index, 32 + %48 = shl i64 %index.next.7, 1 + %49 = getelementptr inbounds double, double* %b, i64 %48 + %50 = bitcast double* %49 to <8 x double>* + %wide.vec.8 = load <8 x double>, <8 x double>* %50, align 8 + %strided.vec.8 = shufflevector <8 x double> %wide.vec.8, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %51 = fadd <4 x double> %strided.vec.8, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %52 = getelementptr inbounds double, double* %a, i64 %index.next.7 + %53 = bitcast double* %52 to <4 x double>* + store <4 x double> %51, <4 x double>* %53, align 8 + %index.next.8 = or i64 %index, 36 + %54 = shl i64 %index.next.8, 1 + %55 = getelementptr inbounds double, double* %b, i64 %54 + %56 = bitcast double* %55 to <8 x double>* + %wide.vec.9 = load <8 x double>, <8 x double>* %56, align 8 + %strided.vec.9 = shufflevector <8 x double> %wide.vec.9, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %57 = fadd <4 x double> %strided.vec.9, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %58 = getelementptr inbounds double, double* %a, i64 %index.next.8 + %59 = bitcast double* %58 to <4 x double>* + store <4 x double> %57, <4 x double>* %59, align 8 + %index.next.9 = or i64 %index, 40 + %60 = shl i64 %index.next.9, 1 + %61 = getelementptr inbounds double, double* %b, i64 %60 + %62 = bitcast double* %61 to <8 x double>* + %wide.vec.10 = load <8 x double>, <8 x double>* %62, align 8 + %strided.vec.10 = shufflevector <8 x double> %wide.vec.10, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %63 = fadd <4 x double> %strided.vec.10, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %64 = getelementptr inbounds double, double* %a, i64 %index.next.9 + %65 = bitcast double* %64 to <4 x double>* + store <4 x double> %63, <4 x double>* %65, align 8 + %index.next.10 = or i64 %index, 44 + %66 = shl i64 %index.next.10, 1 + %67 = getelementptr inbounds double, double* %b, i64 %66 + %68 = bitcast double* %67 to <8 x double>* + %wide.vec.11 = load <8 x double>, <8 x double>* %68, align 8 + %strided.vec.11 = shufflevector <8 x double> %wide.vec.11, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %69 = fadd <4 x double> %strided.vec.11, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %70 = getelementptr inbounds double, double* %a, i64 %index.next.10 + %71 = bitcast double* %70 to <4 x double>* + store <4 x double> %69, <4 x double>* %71, align 8 + %index.next.11 = or i64 %index, 48 + %72 = shl i64 %index.next.11, 1 + %73 = getelementptr inbounds double, double* %b, i64 %72 + %74 = bitcast double* %73 to <8 x double>* + %wide.vec.12 = load <8 x double>, <8 x double>* %74, align 8 + %strided.vec.12 = shufflevector <8 x double> %wide.vec.12, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %75 = fadd <4 x double> %strided.vec.12, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %76 = getelementptr inbounds double, double* %a, i64 %index.next.11 + %77 = bitcast double* %76 to <4 x double>* + store <4 x double> %75, <4 x double>* %77, align 8 + %index.next.12 = or i64 %index, 52 + %78 = shl i64 %index.next.12, 1 + %79 = getelementptr inbounds double, double* %b, i64 %78 + %80 = bitcast double* %79 to <8 x double>* + %wide.vec.13 = load <8 x double>, <8 x double>* %80, align 8 + %strided.vec.13 = shufflevector <8 x double> %wide.vec.13, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %81 = fadd <4 x double> %strided.vec.13, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %82 = getelementptr inbounds double, double* %a, i64 %index.next.12 + %83 = bitcast double* %82 to <4 x double>* + store <4 x double> %81, <4 x double>* %83, align 8 + %index.next.13 = or i64 %index, 56 + %84 = shl i64 %index.next.13, 1 + %85 = getelementptr inbounds double, double* %b, i64 %84 + %86 = bitcast double* %85 to <8 x double>* + %wide.vec.14 = load <8 x double>, <8 x double>* %86, align 8 + %strided.vec.14 = shufflevector <8 x double> %wide.vec.14, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %87 = fadd <4 x double> %strided.vec.14, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %88 = getelementptr inbounds double, double* %a, i64 %index.next.13 + %89 = bitcast double* %88 to <4 x double>* + store <4 x double> %87, <4 x double>* %89, align 8 + %index.next.14 = or i64 %index, 60 + %90 = shl i64 %index.next.14, 1 + %91 = getelementptr inbounds double, double* %b, i64 %90 + %92 = bitcast double* %91 to <8 x double>* + %wide.vec.15 = load <8 x double>, <8 x double>* %92, align 8 + %strided.vec.15 = shufflevector <8 x double> %wide.vec.15, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %93 = fadd <4 x double> %strided.vec.15, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> + %94 = getelementptr inbounds double, double* %a, i64 %index.next.14 + %95 = bitcast double* %94 to <4 x double>* + store <4 x double> %93, <4 x double>* %95, align 8 + %index.next.15 = add nsw i64 %index, 64 + %96 = icmp eq i64 %index.next.15, 1600 + br i1 %96, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +attributes #0 = { nounwind "target-cpu"="a2q" } + diff --git a/test/CodeGen/PowerPC/retaddr2.ll b/test/CodeGen/PowerPC/retaddr2.ll index 8581f6cb9a38..1038cd03d154 100644 --- a/test/CodeGen/PowerPC/retaddr2.ll +++ b/test/CodeGen/PowerPC/retaddr2.ll @@ -10,11 +10,11 @@ entry: } ; CHECK-LABEL: @test1 -; CHECK: mflr 0 +; CHECK: mflr {{[0-9]+}} ; CHECK: std 0, 16(1) ; CHECK-DAG: ld 3, 64(1) -; CHECK-DAG: ld 0, 16(1) -; CHECK: mtlr 0 +; CHECK-DAG: ld [[SR:[0-9]+]], 16(1) +; CHECK: mtlr [[SR]] ; CHECK: blr ; Function Attrs: nounwind readnone diff --git a/test/CodeGen/PowerPC/rm-zext.ll b/test/CodeGen/PowerPC/rm-zext.ll index 97c546c0145f..df5fe4f7a154 100644 --- a/test/CodeGen/PowerPC/rm-zext.ll +++ b/test/CodeGen/PowerPC/rm-zext.ll @@ -9,7 +9,7 @@ entry: %shr2 = lshr i32 %mul, 5 ret i32 %shr2 -; CHECK-LABEL @foo +; CHECK-LABEL: @foo ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } @@ -23,7 +23,7 @@ entry: %or = or i32 %shr, %shl ret i32 %or -; CHECK-LABEL @test6 +; CHECK-LABEL: @test6 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } @@ -34,7 +34,7 @@ entry: %cond = select i1 %cmp, i32 %a, i32 %b ret i32 %cond -; CHECK-LABEL @min +; CHECK-LABEL: @min ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } diff --git a/test/CodeGen/PowerPC/rotl-rotr-crash.ll b/test/CodeGen/PowerPC/rotl-rotr-crash.ll new file mode 100644 index 000000000000..3fbb67ecf25e --- /dev/null +++ b/test/CodeGen/PowerPC/rotl-rotr-crash.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 + +; Ensure this does not crash + +; Function Attrs: norecurse nounwind +define <4 x i32> @func1 (<4 x i32> %a) { +entry: + %0 = lshr <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16> + %1 = shl <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16> + %2 = or <4 x i32> %1, %0 + ret <4 x i32> %2 +} diff --git a/test/CodeGen/PowerPC/sdiv-pow2.ll b/test/CodeGen/PowerPC/sdiv-pow2.ll index 5ec019dfb4af..d1f60da6c740 100644 --- a/test/CodeGen/PowerPC/sdiv-pow2.ll +++ b/test/CodeGen/PowerPC/sdiv-pow2.ll @@ -9,7 +9,7 @@ entry: %div = sdiv i32 %a, 8 ret i32 %div -; CHECK-LABEL @foo4 +; CHECK-LABEL: @foo4 ; CHECK: srawi [[REG1:[0-9]+]], 3, 3 ; CHECK: addze [[REG2:[0-9]+]], [[REG1]] ; CHECK: extsw 3, [[REG2]] @@ -22,12 +22,12 @@ entry: %div = sdiv i64 %a, 8 ret i64 %div -; CHECK-LABEL @foo8 +; CHECK-LABEL: @foo8 ; CHECK: sradi [[REG1:[0-9]+]], 3, 3 ; CHECK: addze 3, [[REG1]] ; CHECK: blr -; CHECK-32-LABEL @foo8 +; CHECK-32-LABEL: @foo8 ; CHECK-32-NOT: sradi ; CHECK-32: blr } @@ -58,7 +58,7 @@ entry: ; CHECK: neg 3, [[REG2]] ; CHECK: blr -; CHECK-32-LABEL @foo8n +; CHECK-32-LABEL: @foo8n ; CHECK-32-NOT: sradi ; CHECK-32: blr } diff --git a/test/CodeGen/PowerPC/selectiondag-extload-computeknownbits.ll b/test/CodeGen/PowerPC/selectiondag-extload-computeknownbits.ll new file mode 100644 index 000000000000..79dccaa98ca1 --- /dev/null +++ b/test/CodeGen/PowerPC/selectiondag-extload-computeknownbits.ll @@ -0,0 +1,12 @@ +; RUN: llc -mtriple=powerpc64-bgq-linux < %s + +; Check that llc does not crash due to an illegal APInt operation + +define i1 @f(i8* %ptr) { + entry: + %val = load i8, i8* %ptr, align 8, !range !0 + %tobool = icmp eq i8 %val, 0 + ret i1 %tobool +} + +!0 = !{i8 0, i8 2} diff --git a/test/CodeGen/PowerPC/seteq-0.ll b/test/CodeGen/PowerPC/seteq-0.ll index 4afb8fee1776..b7dd78085eb1 100644 --- a/test/CodeGen/PowerPC/seteq-0.ll +++ b/test/CodeGen/PowerPC/seteq-0.ll @@ -5,7 +5,7 @@ define i32 @eq0(i32 %a) { %tmp.2 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1] ret i32 %tmp.2 -; CHECK: cntlz [[REG:r[0-9]+]], r3 +; CHECK: cntlzw [[REG:r[0-9]+]], r3 ; CHECK: rlwinm r3, [[REG]], 27, 31, 31 ; CHECK: blr } diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll index dcbdd69d5d50..8c6682ca706e 100644 --- a/test/CodeGen/PowerPC/sjlj.ll +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -74,24 +74,24 @@ return: ; preds = %if.end, %if.then ; CHECK-DAG: std [[REGA]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill ; CHECK-DAG: std 1, 16([[REGA]]) ; CHECK-DAG: std 2, 24([[REGA]]) -; CHECK: bcl 20, 31, .LBB1_1 +; CHECK: bcl 20, 31, .LBB1_5 ; CHECK: li 3, 1 -; CHECK: #EH_SjLj_Setup .LBB1_1 -; CHECK: b .LBB1_2 +; CHECK: #EH_SjLj_Setup .LBB1_5 +; CHECK: b .LBB1_1 -; CHECK: .LBB1_1: -; CHECK: mflr [[REGL:[0-9]+]] -; CHECK: ld [[REG2:[0-9]+]], [[OFF]](31) # 8-byte Folded Reload -; CHECK: std [[REGL]], 8([[REG2]]) -; CHECK: li 3, 0 - -; CHECK: .LBB1_2: +; CHECK: .LBB1_4: ; CHECK: lfd ; CHECK: lvx ; CHECK: ld ; CHECK: blr +; CHECK: .LBB1_5: +; CHECK: mflr [[REGL:[0-9]+]] +; CHECK: ld [[REG2:[0-9]+]], [[OFF]](31) # 8-byte Folded Reload +; CHECK: std [[REGL]], 8([[REG2]]) +; CHECK: li 3, 0 + ; CHECK-NOAV: @main ; CHECK-NOAV-NOT: stvx ; CHECK-NOAV: bcl diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll index e91b563af72e..1c93d665c16d 100644 --- a/test/CodeGen/PowerPC/stack-realign.ll +++ b/test/CodeGen/PowerPC/stack-realign.ll @@ -29,7 +29,7 @@ entry: ; CHECK-LABEL: @goo -; CHECK-DAG: mflr 0 +; CHECK-DAG: mflr {{[0-9]+}} ; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-DAG: std 30, -16(1) ; CHECK-DAG: mr 30, 1 @@ -44,14 +44,14 @@ entry: ; CHECK: std 3, 48(30) ; CHECK: ld 1, 0(1) -; CHECK-DAG: ld 0, 16(1) +; CHECK-DAG: ld [[SR:[0-9]+]], 16(1) ; CHECK-DAG: ld 30, -16(1) -; CHECK-DAG: mtlr 0 +; CHECK-DAG: mtlr [[SR]] ; CHECK: blr ; CHECK-FP-LABEL: @goo -; CHECK-FP-DAG: mflr 0 +; CHECK-FP-DAG: mflr {{[0-9]+}} ; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-FP-DAG: std 31, -8(1) ; CHECK-FP-DAG: std 30, -16(1) @@ -70,14 +70,14 @@ entry: ; CHECK-FP: std 3, 48(30) ; CHECK-FP: ld 1, 0(1) -; CHECK-FP-DAG: ld 0, 16(1) +; CHECK-FP-DAG: ld [[SR:[0-9]+]], 16(1) ; CHECK-FP-DAG: ld 31, -8(1) ; CHECK-FP-DAG: ld 30, -16(1) -; CHECK-FP-DAG: mtlr 0 +; CHECK-FP-DAG: mtlr [[SR]] ; CHECK-FP: blr ; CHECK-32-LABEL: @goo -; CHECK-32-DAG: mflr 0 +; CHECK-32-DAG: mflr {{[0-9]+}} ; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27 ; CHECK-32-DAG: stw 30, -8(1) ; CHECK-32-DAG: mr 30, 1 @@ -86,7 +86,7 @@ entry: ; CHECK-32: stwux 1, 1, 0 ; CHECK-32-PIC-LABEL: @goo -; CHECK-32-PIC-DAG: mflr 0 +; CHECK-32-PIC-DAG: mflr {{[0-9]+}} ; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27 ; CHECK-32-PIC-DAG: stw 29, -12(1) ; CHECK-32-PIC-DAG: mr 29, 1 @@ -114,7 +114,7 @@ entry: ; CHECK-DAG: lis [[REG1:[0-9]+]], -13 ; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59 -; CHECK-DAG: mflr 0 +; CHECK-DAG: mflr {{[0-9]+}} ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808 ; CHECK-DAG: std 30, -16(1) ; CHECK-DAG: mr 30, 1 @@ -130,7 +130,7 @@ entry: ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13 ; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27 -; CHECK-32-DAG: mflr 0 +; CHECK-32-DAG: mflr {{[0-9]+}} ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904 ; CHECK-32-DAG: stw 30, -8(1) ; CHECK-32-DAG: mr 30, 1 @@ -144,7 +144,7 @@ entry: ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13 ; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27 -; CHECK-32-PIC-DAG: mflr 0 +; CHECK-32-PIC-DAG: mflr {{[0-9]+}} ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904 ; CHECK-32-PIC-DAG: stw 29, -12(1) ; CHECK-32-PIC-DAG: mr 29, 1 @@ -174,7 +174,7 @@ entry: ; CHECK-LABEL: @loo -; CHECK-DAG: mflr 0 +; CHECK-DAG: mflr {{[0-9]+}} ; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-DAG: std 30, -32(1) ; CHECK-DAG: mr 30, 1 @@ -190,7 +190,7 @@ entry: ; CHECK-FP-LABEL: @loo -; CHECK-FP-DAG: mflr 0 +; CHECK-FP-DAG: mflr {{[0-9]+}} ; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-FP-DAG: std 31, -24(1) ; CHECK-FP-DAG: std 30, -32(1) diff --git a/test/CodeGen/PowerPC/stackmap-frame-setup.ll b/test/CodeGen/PowerPC/stackmap-frame-setup.ll new file mode 100644 index 000000000000..487da00faa1c --- /dev/null +++ b/test/CodeGen/PowerPC/stackmap-frame-setup.ll @@ -0,0 +1,20 @@ +; RUN: llc -o /dev/null -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -stop-after machine-sink %s | FileCheck %s --check-prefix=ISEL +; RUN: llc -o /dev/null -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -fast-isel -fast-isel-abort=1 -stop-after machine-sink %s | FileCheck %s --check-prefix=FAST-ISEL + +define void @caller_meta_leaf() { +entry: + %metadata = alloca i64, i32 3, align 8 + store i64 11, i64* %metadata + store i64 12, i64* %metadata + store i64 13, i64* %metadata +; ISEL: ADJCALLSTACKDOWN 0, implicit-def +; ISEL-NEXT: STACKMAP +; ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata) +; FAST-ISEL: ADJCALLSTACKDOWN 0, implicit-def +; FAST-ISEL-NEXT: STACKMAP +; FAST-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def + ret void +} + +declare void @llvm.experimental.stackmap(i64, i32, ...) diff --git a/test/CodeGen/PowerPC/swaps-le-5.ll b/test/CodeGen/PowerPC/swaps-le-5.ll index 5cd739a0efa9..3e13bd16c23b 100644 --- a/test/CodeGen/PowerPC/swaps-le-5.ll +++ b/test/CodeGen/PowerPC/swaps-le-5.ll @@ -15,11 +15,11 @@ entry: } ; CHECK-LABEL: @bar0 -; CHECK-DAG: xxswapd {{[0-9]+}}, 1 ; CHECK-DAG: lxvd2x [[REG1:[0-9]+]] ; CHECK-DAG: xxspltd [[REG2:[0-9]+]] ; CHECK: xxpermdi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 1 ; CHECK: stxvd2x [[REG3]] +; CHECK-NOT: xxswapd define void @bar1(double %y) { entry: @@ -30,11 +30,11 @@ entry: } ; CHECK-LABEL: @bar1 -; CHECK-DAG: xxswapd {{[0-9]+}}, 1 ; CHECK-DAG: lxvd2x [[REG1:[0-9]+]] ; CHECK-DAG: xxspltd [[REG2:[0-9]+]] ; CHECK: xxmrghd [[REG3:[0-9]+]], [[REG1]], [[REG2]] ; CHECK: stxvd2x [[REG3]] +; CHECK-NOT: xxswapd define void @baz0() { entry: diff --git a/test/CodeGen/PowerPC/swaps-le-6.ll b/test/CodeGen/PowerPC/swaps-le-6.ll new file mode 100644 index 000000000000..df88322e4fd8 --- /dev/null +++ b/test/CodeGen/PowerPC/swaps-le-6.ll @@ -0,0 +1,42 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s + +; These tests verify that VSX swap optimization works when loading a scalar +; into a vector register. + + +@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16 +@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16 +@y = global double 1.780000e+00, align 8 + +define void @bar0() { +entry: + %0 = load <2 x double>, <2 x double>* @x, align 16 + %1 = load double, double* @y, align 8 + %vecins = insertelement <2 x double> %0, double %1, i32 0 + store <2 x double> %vecins, <2 x double>* @z, align 16 + ret void +} + +; CHECK-LABEL: @bar0 +; CHECK-DAG: lxvd2x [[REG1:[0-9]+]] +; CHECK-DAG: lxsdx [[REG2:[0-9]+]] +; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0 +; CHECK: xxpermdi [[REG5:[0-9]+]], [[REG4]], [[REG1]], 1 +; CHECK: stxvd2x [[REG5]] + +define void @bar1() { +entry: + %0 = load <2 x double>, <2 x double>* @x, align 16 + %1 = load double, double* @y, align 8 + %vecins = insertelement <2 x double> %0, double %1, i32 1 + store <2 x double> %vecins, <2 x double>* @z, align 16 + ret void +} + +; CHECK-LABEL: @bar1 +; CHECK-DAG: lxvd2x [[REG1:[0-9]+]] +; CHECK-DAG: lxsdx [[REG2:[0-9]+]] +; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0 +; CHECK: xxmrghd [[REG5:[0-9]+]], [[REG1]], [[REG4]] +; CHECK: stxvd2x [[REG5]] + diff --git a/test/CodeGen/PowerPC/unal-vec-ldst.ll b/test/CodeGen/PowerPC/unal-vec-ldst.ll new file mode 100644 index 000000000000..260e7f6115f9 --- /dev/null +++ b/test/CodeGen/PowerPC/unal-vec-ldst.ll @@ -0,0 +1,580 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 { +entry: + %r = load <16 x i8>, <16 x i8>* %p, align 1 + ret <16 x i8> %r + +; CHECK-LABEL: @test_l_v16i8 +; CHECK-DAG: li [[REG1:[0-9]+]], 15 +; CHECK-DAG: lvsl [[REG2:[0-9]+]], 0, 3 +; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3 +; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]] +; CHECK: blr +} + +define <32 x i8> @test_l_v32i8(<32 x i8>* %p) #0 { +entry: + %r = load <32 x i8>, <32 x i8>* %p, align 1 + ret <32 x i8> %r + +; CHECK-LABEL: @test_l_v32i8 +; CHECK-DAG: li [[REG1:[0-9]+]], 31 +; CHECK-DAG: li [[REG2:[0-9]+]], 16 +; CHECK-DAG: lvsl [[REG3:[0-9]+]], 0, 3 +; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]] +; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3 +; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]] +; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]] +; CHECK: blr +} + +define <8 x i16> @test_l_v8i16(<8 x i16>* %p) #0 { +entry: + %r = load <8 x i16>, <8 x i16>* %p, align 2 + ret <8 x i16> %r + +; CHECK-LABEL: @test_l_v8i16 +; CHECK-DAG: li [[REG1:[0-9]+]], 15 +; CHECK-DAG: lvsl [[REG2:[0-9]+]], 0, 3 +; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3 +; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]] +; CHECK: blr +} + +define <16 x i16> @test_l_v16i16(<16 x i16>* %p) #0 { +entry: + %r = load <16 x i16>, <16 x i16>* %p, align 2 + ret <16 x i16> %r + +; CHECK-LABEL: @test_l_v16i16 +; CHECK-DAG: li [[REG1:[0-9]+]], 31 +; CHECK-DAG: li [[REG2:[0-9]+]], 16 +; CHECK-DAG: lvsl [[REG3:[0-9]+]], 0, 3 +; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]] +; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3 +; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]] +; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]] +; CHECK: blr +} + +define <4 x i32> @test_l_v4i32(<4 x i32>* %p) #0 { +entry: + %r = load <4 x i32>, <4 x i32>* %p, align 4 + ret <4 x i32> %r + +; CHECK-LABEL: @test_l_v4i32 +; CHECK-DAG: li [[REG1:[0-9]+]], 15 +; CHECK-DAG: lvsl [[REG2:[0-9]+]], 0, 3 +; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3 +; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]] +; CHECK: blr +} + +define <8 x i32> @test_l_v8i32(<8 x i32>* %p) #0 { +entry: + %r = load <8 x i32>, <8 x i32>* %p, align 4 + ret <8 x i32> %r + +; CHECK-LABEL: @test_l_v8i32 +; CHECK-DAG: li [[REG1:[0-9]+]], 31 +; CHECK-DAG: li [[REG2:[0-9]+]], 16 +; CHECK-DAG: lvsl [[REG3:[0-9]+]], 0, 3 +; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]] +; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3 +; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]] +; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]] +; CHECK: blr +} + +define <2 x i64> @test_l_v2i64(<2 x i64>* %p) #0 { +entry: + %r = load <2 x i64>, <2 x i64>* %p, align 8 + ret <2 x i64> %r + +; CHECK-LABEL: @test_l_v2i64 +; CHECK: lxvd2x 34, 0, 3 +; CHECK: blr +} + +define <4 x i64> @test_l_v4i64(<4 x i64>* %p) #0 { +entry: + %r = load <4 x i64>, <4 x i64>* %p, align 8 + ret <4 x i64> %r + +; CHECK-LABEL: @test_l_v4i64 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: lxvd2x 34, 0, 3 +; CHECK-DAG: lxvd2x 35, 3, [[REG1]] +; CHECK: blr +} + +define <4 x float> @test_l_v4float(<4 x float>* %p) #0 { +entry: + %r = load <4 x float>, <4 x float>* %p, align 4 + ret <4 x float> %r + +; CHECK-LABEL: @test_l_v4float +; CHECK-DAG: li [[REG1:[0-9]+]], 15 +; CHECK-DAG: lvsl [[REG2:[0-9]+]], 0, 3 +; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3 +; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]] +; CHECK: blr +} + +define <8 x float> @test_l_v8float(<8 x float>* %p) #0 { +entry: + %r = load <8 x float>, <8 x float>* %p, align 4 + ret <8 x float> %r + +; CHECK-LABEL: @test_l_v8float +; CHECK-DAG: li [[REG1:[0-9]+]], 31 +; CHECK-DAG: li [[REG2:[0-9]+]], 16 +; CHECK-DAG: lvsl [[REG3:[0-9]+]], 0, 3 +; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]] +; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3 +; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]] +; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]] +; CHECK: blr +} + +define <2 x double> @test_l_v2double(<2 x double>* %p) #0 { +entry: + %r = load <2 x double>, <2 x double>* %p, align 8 + ret <2 x double> %r + +; CHECK-LABEL: @test_l_v2double +; CHECK: lxvd2x 34, 0, 3 +; CHECK: blr +} + +define <4 x double> @test_l_v4double(<4 x double>* %p) #0 { +entry: + %r = load <4 x double>, <4 x double>* %p, align 8 + ret <4 x double> %r + +; CHECK-LABEL: @test_l_v4double +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: lxvd2x 34, 0, 3 +; CHECK-DAG: lxvd2x 35, 3, [[REG1]] +; CHECK: blr +} + +define <16 x i8> @test_l_p8v16i8(<16 x i8>* %p) #2 { +entry: + %r = load <16 x i8>, <16 x i8>* %p, align 1 + ret <16 x i8> %r + +; CHECK-LABEL: @test_l_p8v16i8 +; CHECK: lxvw4x 34, 0, 3 +; CHECK: blr +} + +define <32 x i8> @test_l_p8v32i8(<32 x i8>* %p) #2 { +entry: + %r = load <32 x i8>, <32 x i8>* %p, align 1 + ret <32 x i8> %r + +; CHECK-LABEL: @test_l_p8v32i8 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: lxvw4x 34, 0, 3 +; CHECK-DAG: lxvw4x 35, 3, [[REG1]] +; CHECK: blr +} + +define <8 x i16> @test_l_p8v8i16(<8 x i16>* %p) #2 { +entry: + %r = load <8 x i16>, <8 x i16>* %p, align 2 + ret <8 x i16> %r + +; CHECK-LABEL: @test_l_p8v8i16 +; CHECK: lxvw4x 34, 0, 3 +; CHECK: blr +} + +define <16 x i16> @test_l_p8v16i16(<16 x i16>* %p) #2 { +entry: + %r = load <16 x i16>, <16 x i16>* %p, align 2 + ret <16 x i16> %r + +; CHECK-LABEL: @test_l_p8v16i16 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: lxvw4x 34, 0, 3 +; CHECK-DAG: lxvw4x 35, 3, [[REG1]] +; CHECK: blr +} + +define <4 x i32> @test_l_p8v4i32(<4 x i32>* %p) #2 { +entry: + %r = load <4 x i32>, <4 x i32>* %p, align 4 + ret <4 x i32> %r + +; CHECK-LABEL: @test_l_p8v4i32 +; CHECK: lxvw4x 34, 0, 3 +; CHECK: blr +} + +define <8 x i32> @test_l_p8v8i32(<8 x i32>* %p) #2 { +entry: + %r = load <8 x i32>, <8 x i32>* %p, align 4 + ret <8 x i32> %r + +; CHECK-LABEL: @test_l_p8v8i32 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: lxvw4x 34, 0, 3 +; CHECK-DAG: lxvw4x 35, 3, [[REG1]] +; CHECK: blr +} + +define <2 x i64> @test_l_p8v2i64(<2 x i64>* %p) #2 { +entry: + %r = load <2 x i64>, <2 x i64>* %p, align 8 + ret <2 x i64> %r + +; CHECK-LABEL: @test_l_p8v2i64 +; CHECK: lxvd2x 34, 0, 3 +; CHECK: blr +} + +define <4 x i64> @test_l_p8v4i64(<4 x i64>* %p) #2 { +entry: + %r = load <4 x i64>, <4 x i64>* %p, align 8 + ret <4 x i64> %r + +; CHECK-LABEL: @test_l_p8v4i64 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: lxvd2x 34, 0, 3 +; CHECK-DAG: lxvd2x 35, 3, [[REG1]] +; CHECK: blr +} + +define <4 x float> @test_l_p8v4float(<4 x float>* %p) #2 { +entry: + %r = load <4 x float>, <4 x float>* %p, align 4 + ret <4 x float> %r + +; CHECK-LABEL: @test_l_p8v4float +; CHECK: lxvw4x 34, 0, 3 +; CHECK: blr +} + +define <8 x float> @test_l_p8v8float(<8 x float>* %p) #2 { +entry: + %r = load <8 x float>, <8 x float>* %p, align 4 + ret <8 x float> %r + +; CHECK-LABEL: @test_l_p8v8float +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: lxvw4x 34, 0, 3 +; CHECK-DAG: lxvw4x 35, 3, [[REG1]] +; CHECK: blr +} + +define <2 x double> @test_l_p8v2double(<2 x double>* %p) #2 { +entry: + %r = load <2 x double>, <2 x double>* %p, align 8 + ret <2 x double> %r + +; CHECK-LABEL: @test_l_p8v2double +; CHECK: lxvd2x 34, 0, 3 +; CHECK: blr +} + +define <4 x double> @test_l_p8v4double(<4 x double>* %p) #2 { +entry: + %r = load <4 x double>, <4 x double>* %p, align 8 + ret <4 x double> %r + +; CHECK-LABEL: @test_l_p8v4double +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: lxvd2x 34, 0, 3 +; CHECK-DAG: lxvd2x 35, 3, [[REG1]] +; CHECK: blr +} + +define <4 x float> @test_l_qv4float(<4 x float>* %p) #1 { +entry: + %r = load <4 x float>, <4 x float>* %p, align 4 + ret <4 x float> %r + +; CHECK-LABEL: @test_l_qv4float +; CHECK-DAG: li [[REG1:[0-9]+]], 15 +; CHECK-DAG: qvlpclsx 0, 0, 3 +; CHECK-DAG: qvlfsx [[REG2:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: qvlfsx [[REG3:[0-9]+]], 0, 3 +; CHECK: qvfperm 1, [[REG3]], [[REG2]], 0 +; CHECK: blr +} + +define <8 x float> @test_l_qv8float(<8 x float>* %p) #1 { +entry: + %r = load <8 x float>, <8 x float>* %p, align 4 + ret <8 x float> %r + +; CHECK-LABEL: @test_l_qv8float +; CHECK-DAG: li [[REG1:[0-9]+]], 31 +; CHECK-DAG: li [[REG2:[0-9]+]], 16 +; CHECK-DAG: qvlfsx [[REG3:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: qvlfsx [[REG4:[0-9]+]], 3, [[REG2]] +; CHECK-DAG: qvlpclsx [[REG5:[0-5]+]], 0, 3 +; CHECK-DAG: qvlfsx [[REG6:[0-9]+]], 0, 3 +; CHECK-DAG: qvfperm 2, [[REG4]], [[REG3]], [[REG5]] +; CHECK-DAG: qvfperm 1, [[REG6]], [[REG4]], [[REG5]] +; CHECK: blr +} + +define <4 x double> @test_l_qv4double(<4 x double>* %p) #1 { +entry: + %r = load <4 x double>, <4 x double>* %p, align 8 + ret <4 x double> %r + +; CHECK-LABEL: @test_l_qv4double +; CHECK-DAG: li [[REG1:[0-9]+]], 31 +; CHECK-DAG: qvlpcldx 0, 0, 3 +; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: qvlfdx [[REG3:[0-9]+]], 0, 3 +; CHECK: qvfperm 1, [[REG3]], [[REG2]], 0 +; CHECK: blr +} + +define <8 x double> @test_l_qv8double(<8 x double>* %p) #1 { +entry: + %r = load <8 x double>, <8 x double>* %p, align 8 + ret <8 x double> %r + +; CHECK-LABEL: @test_l_qv8double +; CHECK-DAG: li [[REG1:[0-9]+]], 63 +; CHECK-DAG: li [[REG2:[0-9]+]], 32 +; CHECK-DAG: qvlfdx [[REG3:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: qvlfdx [[REG4:[0-9]+]], 3, [[REG2]] +; CHECK-DAG: qvlpcldx [[REG5:[0-5]+]], 0, 3 +; CHECK-DAG: qvlfdx [[REG6:[0-9]+]], 0, 3 +; CHECK-DAG: qvfperm 2, [[REG4]], [[REG3]], [[REG5]] +; CHECK-DAG: qvfperm 1, [[REG6]], [[REG4]], [[REG5]] +; CHECK: blr +} + +define void @test_s_v16i8(<16 x i8>* %p, <16 x i8> %v) #0 { +entry: + store <16 x i8> %v, <16 x i8>* %p, align 1 + ret void + +; CHECK-LABEL: @test_s_v16i8 +; CHECK: stxvw4x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v32i8(<32 x i8>* %p, <32 x i8> %v) #0 { +entry: + store <32 x i8> %v, <32 x i8>* %p, align 1 + ret void + +; CHECK-LABEL: @test_s_v32i8 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: stxvw4x 35, 3, [[REG1]] +; CHECK-DAG: stxvw4x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v8i16(<8 x i16>* %p, <8 x i16> %v) #0 { +entry: + store <8 x i16> %v, <8 x i16>* %p, align 2 + ret void + +; CHECK-LABEL: @test_s_v8i16 +; CHECK: stxvw4x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v16i16(<16 x i16>* %p, <16 x i16> %v) #0 { +entry: + store <16 x i16> %v, <16 x i16>* %p, align 2 + ret void + +; CHECK-LABEL: @test_s_v16i16 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: stxvw4x 35, 3, [[REG1]] +; CHECK-DAG: stxvw4x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v4i32(<4 x i32>* %p, <4 x i32> %v) #0 { +entry: + store <4 x i32> %v, <4 x i32>* %p, align 4 + ret void + +; CHECK-LABEL: @test_s_v4i32 +; CHECK: stxvw4x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v8i32(<8 x i32>* %p, <8 x i32> %v) #0 { +entry: + store <8 x i32> %v, <8 x i32>* %p, align 4 + ret void + +; CHECK-LABEL: @test_s_v8i32 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: stxvw4x 35, 3, [[REG1]] +; CHECK-DAG: stxvw4x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v2i64(<2 x i64>* %p, <2 x i64> %v) #0 { +entry: + store <2 x i64> %v, <2 x i64>* %p, align 8 + ret void + +; CHECK-LABEL: @test_s_v2i64 +; CHECK: stxvd2x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v4i64(<4 x i64>* %p, <4 x i64> %v) #0 { +entry: + store <4 x i64> %v, <4 x i64>* %p, align 8 + ret void + +; CHECK-LABEL: @test_s_v4i64 +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: stxvd2x 35, 3, [[REG1]] +; CHECK-DAG: stxvd2x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v4float(<4 x float>* %p, <4 x float> %v) #0 { +entry: + store <4 x float> %v, <4 x float>* %p, align 4 + ret void + +; CHECK-LABEL: @test_s_v4float +; CHECK: stxvw4x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v8float(<8 x float>* %p, <8 x float> %v) #0 { +entry: + store <8 x float> %v, <8 x float>* %p, align 4 + ret void + +; CHECK-LABEL: @test_s_v8float +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: stxvw4x 35, 3, [[REG1]] +; CHECK-DAG: stxvw4x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v2double(<2 x double>* %p, <2 x double> %v) #0 { +entry: + store <2 x double> %v, <2 x double>* %p, align 8 + ret void + +; CHECK-LABEL: @test_s_v2double +; CHECK: stxvd2x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_v4double(<4 x double>* %p, <4 x double> %v) #0 { +entry: + store <4 x double> %v, <4 x double>* %p, align 8 + ret void + +; CHECK-LABEL: @test_s_v4double +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK-DAG: stxvd2x 35, 3, [[REG1]] +; CHECK-DAG: stxvd2x 34, 0, 3 +; CHECK: blr +} + +define void @test_s_qv4float(<4 x float>* %p, <4 x float> %v) #1 { +entry: + store <4 x float> %v, <4 x float>* %p, align 4 + ret void + +; CHECK-LABEL: @test_s_qv4float +; CHECK-DAG: qvesplati [[REG1:[0-9]+]], 1, 3 +; CHECK-DAG: qvesplati [[REG2:[0-9]+]], 1, 2 +; CHECK-DAG: qvesplati [[REG3:[0-9]+]], 1, 1 +; CHECK-DAG: stfs 1, 0(3) +; CHECK-DAG: stfs [[REG1]], 12(3) +; CHECK-DAG: stfs [[REG2]], 8(3) +; CHECK-DAG: stfs [[REG3]], 4(3) +; CHECK: blr +} + +define void @test_s_qv8float(<8 x float>* %p, <8 x float> %v) #1 { +entry: + store <8 x float> %v, <8 x float>* %p, align 4 + ret void + +; CHECK-LABEL: @test_s_qv8float +; CHECK-DAG: qvesplati [[REG1:[0-9]+]], 2, 3 +; CHECK-DAG: qvesplati [[REG2:[0-9]+]], 2, 2 +; CHECK-DAG: qvesplati [[REG3:[0-9]+]], 2, 1 +; CHECK-DAG: qvesplati [[REG4:[0-9]+]], 1, 3 +; CHECK-DAG: qvesplati [[REG5:[0-9]+]], 1, 2 +; CHECK-DAG: qvesplati [[REG6:[0-9]+]], 1, 1 +; CHECK-DAG: stfs 2, 16(3) +; CHECK-DAG: stfs 1, 0(3) +; CHECK-DAG: stfs [[REG1]], 28(3) +; CHECK-DAG: stfs [[REG2]], 24(3) +; CHECK-DAG: stfs [[REG3]], 20(3) +; CHECK-DAG: stfs [[REG4]], 12(3) +; CHECK-DAG: stfs [[REG5]], 8(3) +; CHECK-DAG: stfs [[REG6]], 4(3) +; CHECK: blr +} + +define void @test_s_qv4double(<4 x double>* %p, <4 x double> %v) #1 { +entry: + store <4 x double> %v, <4 x double>* %p, align 8 + ret void + +; CHECK-LABEL: @test_s_qv4double +; CHECK-DAG: qvesplati [[REG1:[0-9]+]], 1, 3 +; CHECK-DAG: qvesplati [[REG2:[0-9]+]], 1, 2 +; CHECK-DAG: qvesplati [[REG3:[0-9]+]], 1, 1 +; CHECK-DAG: stfd 1, 0(3) +; CHECK-DAG: stfd [[REG1]], 24(3) +; CHECK-DAG: stfd [[REG2]], 16(3) +; CHECK-DAG: stfd [[REG3]], 8(3) +; CHECK: blr +} + +define void @test_s_qv8double(<8 x double>* %p, <8 x double> %v) #1 { +entry: + store <8 x double> %v, <8 x double>* %p, align 8 + ret void + +; CHECK-LABEL: @test_s_qv8double +; CHECK-DAG: qvesplati [[REG1:[0-9]+]], 2, 3 +; CHECK-DAG: qvesplati [[REG2:[0-9]+]], 2, 2 +; CHECK-DAG: qvesplati [[REG3:[0-9]+]], 2, 1 +; CHECK-DAG: qvesplati [[REG4:[0-9]+]], 1, 3 +; CHECK-DAG: qvesplati [[REG5:[0-9]+]], 1, 2 +; CHECK-DAG: qvesplati [[REG6:[0-9]+]], 1, 1 +; CHECK-DAG: stfd 2, 32(3) +; CHECK-DAG: stfd 1, 0(3) +; CHECK-DAG: stfd [[REG1]], 56(3) +; CHECK-DAG: stfd [[REG2]], 48(3) +; CHECK-DAG: stfd [[REG3]], 40(3) +; CHECK-DAG: stfd [[REG4]], 24(3) +; CHECK-DAG: stfd [[REG5]], 16(3) +; CHECK-DAG: stfd [[REG6]], 8(3) +; CHECK: blr +} + +attributes #0 = { nounwind "target-cpu"="pwr7" } +attributes #1 = { nounwind "target-cpu"="a2q" } +attributes #2 = { nounwind "target-cpu"="pwr8" } + diff --git a/test/CodeGen/PowerPC/unal-vec-negarith.ll b/test/CodeGen/PowerPC/unal-vec-negarith.ll new file mode 100644 index 000000000000..faac891f5c6f --- /dev/null +++ b/test/CodeGen/PowerPC/unal-vec-negarith.ll @@ -0,0 +1,17 @@ +; RUN: llc -debug-only=isel <%s >%t 2>&1 && FileCheck <%t %s +; REQUIRES: asserts + +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 { +entry: + %r = load <16 x i8>, <16 x i8>* %p, align 1 + ret <16 x i8> %r + +; CHECK-NOT: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+4294967281](align=1)> +; CHECK: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+-15](align=1)> +} + +attributes #0 = { nounwind "target-cpu"="pwr7" } + diff --git a/test/CodeGen/PowerPC/unwind-dw2-g.ll b/test/CodeGen/PowerPC/unwind-dw2-g.ll index 8bd158867c79..e44da85f5b36 100644 --- a/test/CodeGen/PowerPC/unwind-dw2-g.ll +++ b/test/CodeGen/PowerPC/unwind-dw2-g.ll @@ -3,7 +3,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind -define void @foo() #0 { +define void @foo() #0 !dbg !4 { entry: call void @llvm.eh.unwind.init(), !dbg !9 ret void, !dbg !10 @@ -21,11 +21,11 @@ attributes #0 = { nounwind } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!8, !11} -!0 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) !1 = !DIFile(filename: "/tmp/unwind-dw2.c", directory: "/tmp") !2 = !{} !3 = !{!4} -!4 = !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, function: void ()* @foo, variables: !2) +!4 = distinct !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "/tmp/unwind-dw2.c", directory: "/tmp") !6 = !DISubroutineType(types: !7) !7 = !{null} diff --git a/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll new file mode 100644 index 000000000000..3d4789360f55 --- /dev/null +++ b/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll @@ -0,0 +1,114 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ +; RUN: --check-prefix=CHECK-BE +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ +; RUN: --check-prefix=CHECK-P7 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @geti(<4 x i32> %a, i32 signext %b) { +entry: + %vecext = extractelement <4 x i32> %a, i32 %b + ret i32 %vecext +; CHECK-LABEL: @geti +; CHECK-P7-LABEL: @geti +; CHECK-BE-LABEL: @geti +; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 2 +; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5 +; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 2 +; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] +; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]] +; CHECK-DAG: li [[ONEREG:[0-9]+]], 1 +; CHECK-DAG: and [[ELEMSREG:[0-9]+]], [[ONEREG]], 5 +; CHECK-DAG: sldi [[SHAMREG:[0-9]+]], [[ELEMSREG]], 5 +; CHECK: mfvsrd [[TOGPR:[0-9]+]], +; CHECK: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]] +; CHECK: extsw 3, [[RSHREG]] +; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2 +; CHECK-P7-DAG: stxvw4x 34, +; CHECK-P7: lwax 3, [[ELEMOFFREG]], +; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2 +; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2 +; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] +; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] +; CHECK-BE-DAG: li [[IMMREG:[0-9]+]], 1 +; CHECK-BE-DAG: andc [[ANDCREG:[0-9]+]], [[IMMREG]], 5 +; CHECK-BE-DAG: sldi [[SHAMREG:[0-9]+]], [[ANDCREG]], 5 +; CHECK-BE: mfvsrd [[TOGPR:[0-9]+]], +; CHECK-BE: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]] +; CHECk-BE: extsw 3, [[RSHREG]] +} + +; Function Attrs: norecurse nounwind readnone +define i64 @getl(<2 x i64> %a, i32 signext %b) { +entry: + %vecext = extractelement <2 x i64> %a, i32 %b + ret i64 %vecext +; CHECK-LABEL: @getl +; CHECK-P7-LABEL: @getl +; CHECK-BE-LABEL: @getl +; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 1 +; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5 +; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3 +; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] +; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]] +; CHECK: mfvsrd 3, +; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 3 +; CHECK-P7-DAG: stxvd2x 34, +; CHECK-P7: ldx 3, [[ELEMOFFREG]], +; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 +; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3 +; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] +; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] +; CHECK-BE: mfvsrd 3, +} + +; Function Attrs: norecurse nounwind readnone +define float @getf(<4 x float> %a, i32 signext %b) { +entry: + %vecext = extractelement <4 x float> %a, i32 %b + ret float %vecext +; CHECK-LABEL: @getf +; CHECK-P7-LABEL: @getf +; CHECK-BE-LABEL: @getf +; CHECK: li [[IMMREG:[0-9]+]], 3 +; CHECK: xor [[TRUNCREG:[0-9]+]], [[IMMREG]], 5 +; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[TRUNCREG]] +; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] +; CHECK: xscvspdpn 1, +; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2 +; CHECK-P7-DAG: stxvw4x 34, +; CHECK-P7: lfsx 1, [[ELEMOFFREG]], +; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2 +; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] +; CHECK-BE: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] +; CHECK-BE: xscvspdpn 1, +} + +; Function Attrs: norecurse nounwind readnone +define double @getd(<2 x double> %a, i32 signext %b) { +entry: + %vecext = extractelement <2 x double> %a, i32 %b + ret double %vecext +; CHECK-LABEL: @getd +; CHECK-P7-LABEL: @getd +; CHECK-BE-LABEL: @getd +; CHECK: li [[TRUNCREG:[0-9]+]], 1 +; CHECK: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5 +; CHECK: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3 +; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] +; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] +; FIXME: the instruction below is a redundant regclass copy, to be removed +; CHECK: xxlor 1, +; CHECK-P7-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 +; CHECK-P7-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3 +; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] +; CHECK-P7-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] +; FIXME: the instruction below is a redundant regclass copy, to be removed +; CHECK-P7: xxlor 1, +; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 +; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3 +; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] +; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] +; FIXME: the instruction below is a redundant regclass copy, to be removed +; CHECK-BE: xxlor 1, +} diff --git a/test/CodeGen/PowerPC/vec-asm-disabled.ll b/test/CodeGen/PowerPC/vec-asm-disabled.ll new file mode 100644 index 000000000000..333ccce6b89f --- /dev/null +++ b/test/CodeGen/PowerPC/vec-asm-disabled.ll @@ -0,0 +1,14 @@ +; RUN: not llc -mcpu=pwr7 -o /dev/null %s 2>&1 | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define <4 x i32> @testi1(<4 x i32> %b1, <4 x i32> %b2) #0 { +entry: + %0 = call <4 x i32> asm "xxland $0, $1, $2", "=^wd,^wd,^wd"(<4 x i32> %b1, <4 x i32> %b2) #0 + ret <4 x i32> %0 + +; CHECK: error: couldn't allocate output register for constraint 'wd' +} + +attributes #0 = { nounwind "target-features"="-vsx" } + diff --git a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll index f7ebf479755c..9e79b52c4049 100644 --- a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll +++ b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll @@ -14,7 +14,7 @@ define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind { %result = add <1 x i128> %x, <i128 1> ret <1 x i128> %result ; CHECK-LABEL: @increment_by_one -; CHECK vadduqm 2, 2, 3 +; CHECK: vadduqm 2, 2, 3 } define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind { @@ -37,7 +37,7 @@ define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind { %result = sub <1 x i128> %x, <i128 1> ret <1 x i128> %result ; CHECK-LABEL: @decrement_by_one -; CHECK vsubuqm 2, 2, 3 +; CHECK: vsubuqm 2, 2, 3 } define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { @@ -46,7 +46,7 @@ define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { %result = sub <1 x i128> %x, %tmpvec2 ret <1 x i128> %result ; CHECK-LABEL: @decrement_by_val -; CHECK vsubuqm 2, 2, 3 +; CHECK: vsubuqm 2, 2, 3 } declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, diff --git a/test/CodeGen/PowerPC/vector-merge-store-fp-constants.ll b/test/CodeGen/PowerPC/vector-merge-store-fp-constants.ll new file mode 100644 index 000000000000..db92f20c352a --- /dev/null +++ b/test/CodeGen/PowerPC/vector-merge-store-fp-constants.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=ppc64 -mtriple=ppc64-apple-darwin < %s | FileCheck %s + +; CHECK-LABEL: {{^}}_merge_8_float_zero_stores: +; CHECK: li [[ZEROREG:r[0-9]+]], 0 +; CHECK-DAG: std [[ZEROREG]], 0([[PTR:r[0-9]+]]) +; CHECK-DAG: std [[ZEROREG]], 8([[PTR]]) +; CHECK-DAG: std [[ZEROREG]], 16([[PTR]]) +; CHECK-DAG: std [[ZEROREG]], 24([[PTR]]) +; CHECK: blr +define void @merge_8_float_zero_stores(float* %ptr) { + %idx0 = getelementptr float, float* %ptr, i64 0 + %idx1 = getelementptr float, float* %ptr, i64 1 + %idx2 = getelementptr float, float* %ptr, i64 2 + %idx3 = getelementptr float, float* %ptr, i64 3 + %idx4 = getelementptr float, float* %ptr, i64 4 + %idx5 = getelementptr float, float* %ptr, i64 5 + %idx6 = getelementptr float, float* %ptr, i64 6 + %idx7 = getelementptr float, float* %ptr, i64 7 + store float 0.0, float* %idx0, align 4 + store float 0.0, float* %idx1, align 4 + store float 0.0, float* %idx2, align 4 + store float 0.0, float* %idx3, align 4 + store float 0.0, float* %idx4, align 4 + store float 0.0, float* %idx5, align 4 + store float 0.0, float* %idx6, align 4 + store float 0.0, float* %idx7, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index dceb2516c696..b2eefb666760 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -1226,11 +1226,10 @@ define <2 x i32> @test80(i32 %v) { ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test80 -; CHECK-LE-DAG: addi [[R1:[0-9]+]], 1, -16 +; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3 ; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI -; CHECK-LE-DAG: lxvd2x [[V1:[0-9]+]], 0, [[R1]] ; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]] -; CHECK-LE-DAG: xxswapd 34, [[V1]] +; CHECK-LE-DAG: xxspltd 34, [[R1]] ; CHECK-LE-DAG: xxswapd 35, [[V2]] ; CHECK-LE: vaddudm 2, 2, 3 ; CHECK-LE: blr diff --git a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll index 6c89b1092bdf..97e1548f965f 100644 --- a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll +++ b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll @@ -33,12 +33,8 @@ define double @teste0(<2 x double>* %p1) { %r = extractelement <2 x double> %v, i32 0 ret double %r -; FIXME: Swap optimization will collapse this into lxvd2x 1, 0, 3. - ; CHECK-LABEL: teste0 -; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxswapd 0, 0 -; CHECK: xxswapd 1, 0 +; CHECK: lxvd2x 1, 0, 3 } define double @teste1(<2 x double>* %p1) { diff --git a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll index 102970885963..c2cb71c58881 100644 --- a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll +++ b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll @@ -55,8 +55,7 @@ entry: ret void ; CHECK-LABEL: @intToFlt ; CHECK: lxsiwax [[REGLD2:[0-9]+]], -; FIXME: the below will change when the VSX form is implemented -; CHECK: fcfids {{[0-9]}}, [[REGLD2]] +; CHECK: xscvsxdsp {{[0-9]}}, [[REGLD2]] } ; Function Attrs: nounwind @@ -108,8 +107,7 @@ entry: ret void ; CHECK-LABEL: @uIntToFlt ; CHECK: lxsiwzx [[REGLD4:[0-9]+]], -; FIXME: the below will change when the VSX form is implemented -; CHECK: fcfidus {{[0-9]+}}, [[REGLD4]] +; CHECK: xscvuxdsp {{[0-9]+}}, [[REGLD4]] } ; Function Attrs: nounwind diff --git a/test/CodeGen/PowerPC/vsx_shuffle_le.ll b/test/CodeGen/PowerPC/vsx_shuffle_le.ll index dcfa0e788867..4f767c7ca78f 100644 --- a/test/CodeGen/PowerPC/vsx_shuffle_le.ll +++ b/test/CodeGen/PowerPC/vsx_shuffle_le.ll @@ -8,8 +8,7 @@ define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: test00 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 34, 0, 1 +; CHECK: xxspltd 34, 0, 0 } define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) { @@ -58,9 +57,7 @@ define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) { ret <2 x double> %v3 ; CHECK-LABEL: @test10 -; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxswapd 0, 0 -; CHECK: xxswapd 34, 0 +; CHECK: lxvd2x 34, 0, 3 } define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) { @@ -71,8 +68,7 @@ define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test11 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 34, 0, 0 +; CHECK: xxspltd 34, 0, 1 } define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) { @@ -139,8 +135,7 @@ define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test22 ; CHECK: lxvd2x 0, 0, 4 -; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 34, 0, 1 +; CHECK: xxspltd 34, 0, 0 } define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) { @@ -189,9 +184,7 @@ define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) { ret <2 x double> %v3 ; CHECK-LABEL: @test32 -; CHECK: lxvd2x 0, 0, 4 -; CHECK: xxswapd 0, 0 -; CHECK: xxswapd 34, 0 +; CHECK: lxvd2x 34, 0, 4 } define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) { @@ -202,6 +195,5 @@ define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test33 ; CHECK: lxvd2x 0, 0, 4 -; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 34, 0, 0 +; CHECK: xxspltd 34, 0, 1 } |