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-rw-r--r--test/CodeGen/PowerPC/expand-isel.ll15
-rw-r--r--test/CodeGen/PowerPC/logic-ops-on-compares.ll130
-rw-r--r--test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll121
-rw-r--r--test/CodeGen/PowerPC/memcmp.ll87
-rw-r--r--test/CodeGen/PowerPC/memcmpIR.ll194
-rw-r--r--test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll49
-rw-r--r--test/CodeGen/PowerPC/pristine-and-livein.mir330
-rw-r--r--test/CodeGen/PowerPC/testComparesieqsll.ll134
-rw-r--r--test/CodeGen/PowerPC/testComparesiequll.ll134
-rw-r--r--test/CodeGen/PowerPC/testCompareslleqsll.ll133
-rw-r--r--test/CodeGen/PowerPC/testComparesllequll.ll133
-rw-r--r--test/CodeGen/PowerPC/vec_xxpermdi.ll307
12 files changed, 1430 insertions, 337 deletions
diff --git a/test/CodeGen/PowerPC/expand-isel.ll b/test/CodeGen/PowerPC/expand-isel.ll
index 553cc3c372e5..c8707bda8e84 100644
--- a/test/CodeGen/PowerPC/expand-isel.ll
+++ b/test/CodeGen/PowerPC/expand-isel.ll
@@ -212,13 +212,14 @@ cleanup:
ret i32 %retval.0
; CHECK-LABEL: @testComplexISEL
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
-; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
-; CHECK-NEXT: [[TRUE]]
-; CHECK-NEXT: addi r3, r12, 0
-; CHECK-NEXT: [[SUCCESSOR]]
-; CHECK-NEXT: clrldi r3, r3, 32
-; CHECK-NEXT: blr
+; CHECK-DAG: [[LI:r[0-9]+]], 1
+; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0
+; CHECK: beq cr0, [[EQ:.LBB[0-9_]+]]
+; CHECK: blr
+; CHECK: [[EQ]]
+; CHECK: xor [[XOR:r[0-9]+]]
+; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
+; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
}
!1 = !{!2, !2, i64 0}
diff --git a/test/CodeGen/PowerPC/logic-ops-on-compares.ll b/test/CodeGen/PowerPC/logic-ops-on-compares.ll
new file mode 100644
index 000000000000..df021c20ea86
--- /dev/null
+++ b/test/CodeGen/PowerPC/logic-ops-on-compares.ll
@@ -0,0 +1,130 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+; Function Attrs: nounwind
+define signext i32 @logic_ne_32(i32 signext %a, i32 signext %b, i32 signext %c) {
+; CHECK-LABEL: logic_ne_32:
+; CHECK: xor r7, r3, r4
+; CHECK-NEXT: li r6, 55
+; CHECK-NEXT: xor r5, r5, r6
+; CHECK-NEXT: or r7, r7, r4
+; CHECK-NEXT: cntlzw r5, r5
+; CHECK-NEXT: cntlzw r6, r7
+; CHECK-NEXT: srwi r6, r6, 5
+; CHECK-NEXT: srwi r5, r5, 5
+; CHECK-NEXT: or. r5, r6, r5
+; CHECK-NEXT: bc 4, 1
+entry:
+ %tobool = icmp eq i32 %a, %b
+ %tobool1 = icmp eq i32 %b, 0
+ %or.cond = and i1 %tobool, %tobool1
+ %tobool3 = icmp eq i32 %c, 55
+ %or.cond5 = or i1 %or.cond, %tobool3
+ br i1 %or.cond5, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ %call = tail call signext i32 @foo(i32 signext %a) #2
+ br label %return
+
+if.end: ; preds = %entry
+ %call4 = tail call signext i32 @bar(i32 signext %b) #2
+ br label %return
+
+return: ; preds = %if.end, %if.then
+ %retval.0 = phi i32 [ %call4, %if.end ], [ %call, %if.then ]
+ ret i32 %retval.0
+}
+
+define void @neg_truncate_i32(i32 *%ptr) {
+; CHECK-LABEL: neg_truncate_i32:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: lwz r3, 0(r3)
+; CHECK-NEXT: rldicl. r3, r3, 0, 63
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # BB#1: # %if.end29.thread136
+; CHECK-NEXT: .LBB1_2: # %if.end29
+entry:
+ %0 = load i32, i32* %ptr, align 4
+ %rem17127 = and i32 %0, 1
+ %cmp18 = icmp eq i32 %rem17127, 0
+ br label %if.else
+
+if.else: ; preds = %entry
+ br i1 %cmp18, label %if.end29, label %if.end29.thread136
+
+if.end29.thread136: ; preds = %if.else
+ unreachable
+
+if.end29: ; preds = %if.else
+ ret void
+
+}
+
+; Function Attrs: nounwind
+define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: logic_ne_64:
+; CHECK: xor r7, r3, r4
+; CHECK-NEXT: li r6, 55
+; CHECK-NEXT: xor r5, r5, r6
+; CHECK-NEXT: or r7, r7, r4
+; CHECK-NEXT: cntlzd r6, r7
+; CHECK-NEXT: cntlzd r5, r5
+; CHECK-NEXT: rldicl r6, r6, 58, 63
+; CHECK-NEXT: rldicl r5, r5, 58, 63
+; CHECK-NEXT: or. r5, r6, r5
+; CHECK-NEXT: bc 4, 1
+entry:
+ %tobool = icmp eq i64 %a, %b
+ %tobool1 = icmp eq i64 %b, 0
+ %or.cond = and i1 %tobool, %tobool1
+ %tobool3 = icmp eq i64 %c, 55
+ %or.cond5 = or i1 %or.cond, %tobool3
+ br i1 %or.cond5, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ %call = tail call i64 @foo64(i64 %a) #2
+ br label %return
+
+if.end: ; preds = %entry
+ %call4 = tail call i64 @bar64(i64 %b) #2
+ br label %return
+
+return: ; preds = %if.end, %if.then
+ %retval.0 = phi i64 [ %call4, %if.end ], [ %call, %if.then ]
+ ret i64 %retval.0
+}
+
+define void @neg_truncate_i64(i64 *%ptr) {
+; CHECK-LABEL: neg_truncate_i64:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: ld r3, 0(r3)
+; CHECK-NEXT: rldicl. r3, r3, 0, 63
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # BB#1: # %if.end29.thread136
+; CHECK-NEXT: .LBB3_2: # %if.end29
+entry:
+ %0 = load i64, i64* %ptr, align 4
+ %rem17127 = and i64 %0, 1
+ %cmp18 = icmp eq i64 %rem17127, 0
+ br label %if.else
+
+if.else: ; preds = %entry
+ br i1 %cmp18, label %if.end29, label %if.end29.thread136
+
+if.end29.thread136: ; preds = %if.else
+ unreachable
+
+if.end29: ; preds = %if.else
+ ret void
+
+}
+
+declare signext i32 @foo(i32 signext)
+declare signext i32 @bar(i32 signext)
+declare i64 @foo64(i64)
+declare i64 @bar64(i64)
diff --git a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
new file mode 100644
index 000000000000..3095429758f6
--- /dev/null
+++ b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -0,0 +1,121 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@zeroEqualityTest01.buffer1 = private unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 4], align 4
+@zeroEqualityTest01.buffer2 = private unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 3], align 4
+@zeroEqualityTest02.buffer1 = private unnamed_addr constant [4 x i32] [i32 4, i32 0, i32 0, i32 0], align 4
+@zeroEqualityTest02.buffer2 = private unnamed_addr constant [4 x i32] [i32 3, i32 0, i32 0, i32 0], align 4
+@zeroEqualityTest03.buffer1 = private unnamed_addr constant [4 x i32] [i32 0, i32 0, i32 0, i32 3], align 4
+@zeroEqualityTest03.buffer2 = private unnamed_addr constant [4 x i32] [i32 0, i32 0, i32 0, i32 4], align 4
+@zeroEqualityTest04.buffer1 = private unnamed_addr constant [15 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14], align 4
+@zeroEqualityTest04.buffer2 = private unnamed_addr constant [15 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 13], align 4
+
+; Function Attrs: nounwind readonly
+declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_addr #1
+
+; Validate with if(memcmp())
+; Function Attrs: nounwind readonly
+define signext i32 @zeroEqualityTest01() local_unnamed_addr #0 {
+entry:
+ %call = tail call signext i32 @memcmp(i8* bitcast ([3 x i32]* @zeroEqualityTest01.buffer1 to i8*), i8* bitcast ([3 x i32]* @zeroEqualityTest01.buffer2 to i8*), i64 16)
+ %not.tobool = icmp ne i32 %call, 0
+ %. = zext i1 %not.tobool to i32
+ ret i32 %.
+
+ ; CHECK-LABEL: @zeroEqualityTest01
+ ; CHECK-LABEL: %res_block
+ ; CHECK: li 3, 1
+ ; CHECK-NEXT: clrldi
+ ; CHECK-NEXT: blr
+ ; CHECK: li 3, 0
+ ; CHECK-NEXT: clrldi
+ ; CHECK-NEXT: blr
+}
+
+; Validate with if(memcmp() == 0)
+; Function Attrs: nounwind readonly
+define signext i32 @zeroEqualityTest02() local_unnamed_addr #0 {
+entry:
+ %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer2 to i8*), i64 16)
+ %not.cmp = icmp ne i32 %call, 0
+ %. = zext i1 %not.cmp to i32
+ ret i32 %.
+
+ ; CHECK-LABEL: @zeroEqualityTest02
+ ; CHECK-LABEL: %res_block
+ ; CHECK: li 3, 1
+ ; CHECK-NEXT: clrldi
+ ; CHECK-NEXT: blr
+ ; CHECK: li 3, 0
+ ; CHECK-NEXT: clrldi
+ ; CHECK-NEXT: blr
+}
+
+; Validate with > 0
+; Function Attrs: nounwind readonly
+define signext i32 @zeroEqualityTest03() local_unnamed_addr #0 {
+entry:
+ %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer2 to i8*), i64 16)
+ %not.cmp = icmp slt i32 %call, 1
+ %. = zext i1 %not.cmp to i32
+ ret i32 %.
+
+ ; CHECK-LABEL: @zeroEqualityTest03
+ ; CHECK-LABEL: %res_block
+ ; CHECK: cmpld
+ ; CHECK-NEXT: li [[LI:[0-9]+]], 1
+ ; CHECK-NEXT: li [[LI2:[0-9]+]], -1
+ ; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 0
+}
+
+; Validate with < 0
+; Function Attrs: nounwind readonly
+define signext i32 @zeroEqualityTest04() local_unnamed_addr #0 {
+entry:
+ %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest03.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest03.buffer2 to i8*), i64 16)
+ %call.lobit = lshr i32 %call, 31
+ %call.lobit.not = xor i32 %call.lobit, 1
+ ret i32 %call.lobit.not
+
+ ; CHECK-LABEL: @zeroEqualityTest04
+ ; CHECK-LABEL: %res_block
+ ; CHECK: cmpld
+ ; CHECK-NEXT: li [[LI:[0-9]+]], 1
+ ; CHECK-NEXT: li [[LI2:[0-9]+]], -1
+ ; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 0
+}
+
+; Validate with memcmp()?:
+; Function Attrs: nounwind readonly
+define signext i32 @zeroEqualityTest05() local_unnamed_addr #0 {
+entry:
+ %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16)
+ %not.tobool = icmp eq i32 %call, 0
+ %cond = zext i1 %not.tobool to i32
+ ret i32 %cond
+
+ ; CHECK-LABEL: @zeroEqualityTest05
+ ; CHECK-LABEL: %res_block
+ ; CHECK: li 3, 1
+ ; CHECK: li 3, 0
+}
+
+; Validate with !memcmp()?:
+; Function Attrs: nounwind readonly
+define signext i32 @zeroEqualityTest06() local_unnamed_addr #0 {
+entry:
+ %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16)
+ %not.lnot = icmp ne i32 %call, 0
+ %cond = zext i1 %not.lnot to i32
+ ret i32 %cond
+
+ ; CHECK-LABEL: @zeroEqualityTest06
+ ; CHECK-LABEL: %res_block
+ ; CHECK: li 3, 1
+ ; CHECK-NEXT: clrldi
+ ; CHECK-NEXT: blr
+ ; CHECK: li 3, 0
+ ; CHECK-NEXT: clrldi
+ ; CHECK-NEXT: blr
+}
diff --git a/test/CodeGen/PowerPC/memcmp.ll b/test/CodeGen/PowerPC/memcmp.ll
new file mode 100644
index 000000000000..bae713cb2072
--- /dev/null
+++ b/test/CodeGen/PowerPC/memcmp.ll
@@ -0,0 +1,87 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=CHECK
+
+; Check size 8
+; Function Attrs: nounwind readonly
+define signext i32 @test1(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) local_unnamed_addr #0 {
+entry:
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 8) #2
+ ret i32 %call
+
+; CHECK-LABEL: @test1
+; CHECK: ldbrx [[LOAD1:[0-9]+]]
+; CHECK-NEXT: ldbrx [[LOAD2:[0-9]+]]
+; CHECK-NEXT: li [[LI:[0-9]+]], 1
+; CHECK-NEXT: cmpld [[CMPLD:[0-9]+]], [[LOAD1]], [[LOAD2]]
+; CHECK-NEXT: subf. [[SUB:[0-9]+]], [[LOAD2]], [[LOAD1]]
+; CHECK-NEXT: li [[LI2:[0-9]+]], -1
+; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 4
+; CHECK-NEXT: isel [[ISEL2:[0-9]+]], 0, [[ISEL]], 2
+; CHECK-NEXT: extsw 3, [[ISEL2]]
+; CHECK-NEXT: blr
+}
+
+; Check size 4
+; Function Attrs: nounwind readonly
+define signext i32 @test2(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) local_unnamed_addr #0 {
+entry:
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 4) #2
+ ret i32 %call
+
+; CHECK-LABEL: @test2
+; CHECK: lwbrx [[LOAD1:[0-9]+]]
+; CHECK-NEXT: lwbrx [[LOAD2:[0-9]+]]
+; CHECK-NEXT: li [[LI:[0-9]+]], 1
+; CHECK-NEXT: cmpld [[CMPLD:[0-9]+]], [[LOAD1]], [[LOAD2]]
+; CHECK-NEXT: subf. [[SUB:[0-9]+]], [[LOAD2]], [[LOAD1]]
+; CHECK-NEXT: li [[LI2:[0-9]+]], -1
+; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 4
+; CHECK-NEXT: isel [[ISEL2:[0-9]+]], 0, [[ISEL]], 2
+; CHECK-NEXT: extsw 3, [[ISEL2]]
+; CHECK-NEXT: blr
+}
+
+; Check size 2
+; Function Attrs: nounwind readonly
+define signext i32 @test3(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) local_unnamed_addr #0 {
+entry:
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 2) #2
+ ret i32 %call
+
+; CHECK-LABEL: @test3
+; CHECK: lhbrx [[LOAD1:[0-9]+]]
+; CHECK-NEXT: lhbrx [[LOAD2:[0-9]+]]
+; CHECK-NEXT: li [[LI:[0-9]+]], 1
+; CHECK-NEXT: cmpld [[CMPLD:[0-9]+]], [[LOAD1]], [[LOAD2]]
+; CHECK-NEXT: subf. [[SUB:[0-9]+]], [[LOAD2]], [[LOAD1]]
+; CHECK-NEXT: li [[LI2:[0-9]+]], -1
+; CHECK-NEXT: isel [[ISEL:[0-9]+]], [[LI2]], [[LI]], 4
+; CHECK-NEXT: isel [[ISEL2:[0-9]+]], 0, [[ISEL]], 2
+; CHECK-NEXT: extsw 3, [[ISEL2]]
+; CHECK-NEXT: blr
+}
+
+; Check size 1
+; Function Attrs: nounwind readonly
+define signext i32 @test4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) local_unnamed_addr #0 {
+entry:
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 1) #2
+ ret i32 %call
+
+; CHECK-LABEL: @test4
+; CHECK: lbz [[LOAD1:[0-9]+]]
+; CHECK-NEXT: lbz [[LOAD2:[0-9]+]]
+; CHECK-NEXT: subf [[SUB:[0-9]+]], [[LOAD2]], [[LOAD1]]
+; CHECK-NEXT: extsw 3, [[SUB]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: nounwind readonly
+declare signext i32 @memcmp(i8*, i8*, i64) #1
diff --git a/test/CodeGen/PowerPC/memcmpIR.ll b/test/CodeGen/PowerPC/memcmpIR.ll
new file mode 100644
index 000000000000..f052cc258df8
--- /dev/null
+++ b/test/CodeGen/PowerPC/memcmpIR.ll
@@ -0,0 +1,194 @@
+; RUN: llc -o - -mtriple=powerpc64le-unknown-gnu-linux -stop-after codegenprepare %s | FileCheck %s
+; RUN: llc -o - -mtriple=powerpc64-unknown-gnu-linux -stop-after codegenprepare %s | FileCheck %s --check-prefix=CHECK-BE
+
+define signext i32 @test1(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
+entry:
+ ; CHECK: [[LOAD1:%[0-9]+]] = load i64, i64*
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, i64*
+ ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]])
+ ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]])
+ ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i64 [[BSWAP1]], [[BSWAP2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-NEXT: br i1 [[ICMP]], label %res_block, label
+
+ ; CHECK-LABEL: res_block:{{.*}}
+ ; CHECK: [[ICMP2:%[0-9]+]] = icmp ult i64
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
+ ; CHECK-NEXT: br label %endblock
+
+ ; CHECK: [[GEP1:%[0-9]+]] = getelementptr i64, i64* {{.*}}, i64 1
+ ; CHECK-NEXT: [[GEP2:%[0-9]+]] = getelementptr i64, i64* {{.*}}, i64 1
+ ; CHECK-NEXT: [[LOAD1:%[0-9]+]] = load i64, i64* [[GEP1]]
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, i64* [[GEP2]]
+ ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]])
+ ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]])
+ ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i64 [[BSWAP1]], [[BSWAP2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-NEXT: br i1 [[ICMP]], label %res_block, label %endblock
+
+
+ ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i64, i64*
+ ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, i64*
+ ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i64 [[LOAD1]], [[LOAD2]]
+ ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-BE-NEXT: br i1 [[ICMP]], label %res_block, label
+
+ ; CHECK-BE-LABEL: res_block:{{.*}}
+ ; CHECK-BE: [[ICMP2:%[0-9]+]] = icmp ult i64
+ ; CHECK-BE-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
+ ; CHECK-BE-NEXT: br label %endblock
+
+ ; CHECK-BE: [[GEP1:%[0-9]+]] = getelementptr i64, i64* {{.*}}, i64 1
+ ; CHECK-BE-NEXT: [[GEP2:%[0-9]+]] = getelementptr i64, i64* {{.*}}, i64 1
+ ; CHECK-BE-NEXT: [[LOAD1:%[0-9]+]] = load i64, i64* [[GEP1]]
+ ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, i64* [[GEP2]]
+ ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i64 [[LOAD1]], [[LOAD2]]
+ ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-BE-NEXT: br i1 [[ICMP]], label %res_block, label %endblock
+
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 16)
+ ret i32 %call
+}
+
+declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_addr #1
+
+define signext i32 @test2(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
+ ; CHECK: [[LOAD1:%[0-9]+]] = load i32, i32*
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, i32*
+ ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]])
+ ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]])
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[BSWAP1]] to i64
+ ; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[BSWAP2]] to i64
+ ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i64 [[ZEXT1]], [[ZEXT2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-NEXT: br i1 [[ICMP]], label %res_block, label %endblock
+
+ ; CHECK-LABEL: res_block:{{.*}}
+ ; CHECK: [[ICMP2:%[0-9]+]] = icmp ult i64
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
+ ; CHECK-NEXT: br label %endblock
+
+ ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, i32*
+ ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, i32*
+ ; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[LOAD1]] to i64
+ ; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[LOAD2]] to i64
+ ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i64 [[ZEXT1]], [[ZEXT2]]
+ ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-BE-NEXT: br i1 [[ICMP]], label %res_block, label %endblock
+
+ ; CHECK-BE-LABEL: res_block:{{.*}}
+ ; CHECK-BE: [[ICMP2:%[0-9]+]] = icmp ult i64
+ ; CHECK-BE-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
+ ; CHECK-BE-NEXT: br label %endblock
+
+entry:
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 4)
+ ret i32 %call
+}
+
+define signext i32 @test3(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
+ ; CHECK: [[LOAD1:%[0-9]+]] = load i64, i64*
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, i64*
+ ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]])
+ ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]])
+ ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i64 [[BSWAP1]], [[BSWAP2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-NEXT: br i1 [[ICMP]], label %res_block, label
+
+ ; CHECK-LABEL: res_block:{{.*}}
+ ; CHECK: [[ICMP2:%[0-9]+]] = icmp ult i64
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
+ ; CHECK-NEXT: br label %endblock
+
+ ; CHECK: [[LOAD1:%[0-9]+]] = load i32, i32*
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, i32*
+ ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]])
+ ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]])
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[BSWAP1]] to i64
+ ; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[BSWAP2]] to i64
+ ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i64 [[ZEXT1]], [[ZEXT2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-NEXT: br i1 [[ICMP]], label %res_block, label
+
+ ; CHECK: [[LOAD1:%[0-9]+]] = load i16, i16*
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i16, i16*
+ ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i16 @llvm.bswap.i16(i16 [[LOAD1]])
+ ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i16 @llvm.bswap.i16(i16 [[LOAD2]])
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i16 [[BSWAP1]] to i64
+ ; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i16 [[BSWAP2]] to i64
+ ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i64 [[ZEXT1]], [[ZEXT2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-NEXT: br i1 [[ICMP]], label %res_block, label
+
+ ; CHECK: [[LOAD1:%[0-9]+]] = load i8, i8*
+ ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i8, i8*
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i8 [[LOAD1]] to i32
+ ; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i8 [[LOAD2]] to i32
+ ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i32 [[ZEXT1]], [[ZEXT2]]
+ ; CHECK-NEXT: br label %endblock
+
+ ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i64, i64*
+ ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, i64*
+ ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i64 [[LOAD1]], [[LOAD2]]
+ ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-BE-NEXT: br i1 [[ICMP]], label %res_block, label
+
+ ; CHECK-BE-LABEL: res_block:{{.*}}
+ ; CHECK-BE: [[ICMP2:%[0-9]+]] = icmp ult i64
+ ; CHECK-BE-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
+ ; CHECK-BE-NEXT: br label %endblock
+
+ ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, i32*
+ ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, i32*
+ ; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[LOAD1]] to i64
+ ; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[LOAD2]] to i64
+ ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i64 [[ZEXT1]], [[ZEXT2]]
+ ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-BE-NEXT: br i1 [[ICMP]], label %res_block, label
+
+ ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i16, i16*
+ ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i16, i16*
+ ; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i16 [[LOAD1]] to i64
+ ; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i16 [[LOAD2]] to i64
+ ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i64 [[ZEXT1]], [[ZEXT2]]
+ ; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp ne i64 [[SUB]], 0
+ ; CHECK-BE-NEXT: br i1 [[ICMP]], label %res_block, label
+
+ ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i8, i8*
+ ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i8, i8*
+ ; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i8 [[LOAD1]] to i32
+ ; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i8 [[LOAD2]] to i32
+ ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i32 [[ZEXT1]], [[ZEXT2]]
+ ; CHECK-BE-NEXT: br label %endblock
+
+entry:
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 15)
+ ret i32 %call
+}
+ ; CHECK: call = tail call signext i32 @memcmp
+ ; CHECK-BE: call = tail call signext i32 @memcmp
+define signext i32 @test4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
+
+entry:
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 65)
+ ret i32 %call
+}
+
+define signext i32 @test5(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2, i32 signext %SIZE) {
+ ; CHECK: call = tail call signext i32 @memcmp
+ ; CHECK-BE: call = tail call signext i32 @memcmp
+entry:
+ %0 = bitcast i32* %buffer1 to i8*
+ %1 = bitcast i32* %buffer2 to i8*
+ %conv = sext i32 %SIZE to i64
+ %call = tail call signext i32 @memcmp(i8* %0, i8* %1, i64 %conv)
+ ret i32 %call
+}
diff --git a/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll b/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll
new file mode 100644
index 000000000000..7ca5332865ca
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-ppc-prefetching=true | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-ppc-prefetching=true -ppc-loop-prefetch-cache-line=64 | FileCheck %s -check-prefix=CHECK-DCBT
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-ppc-prefetching=true | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-ppc-prefetching=true -ppc-loop-prefetch-cache-line=64 | FileCheck %s -check-prefix=CHECK-DCBT
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -enable-ppc-prefetching=true | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -enable-ppc-prefetching=true -ppc-loop-prefetch-cache-line=64 | FileCheck %s -check-prefix=CHECK-DCBT
+; RUN: llc < %s -march=ppc64 -mcpu=a2 -enable-ppc-prefetching=true | FileCheck %s -check-prefix=CHECK-DCBT
+
+; Function Attrs: nounwind
+define signext i32 @check_cache_line() local_unnamed_addr {
+entry:
+ %call = tail call i32* bitcast (i32* (...)* @magici to i32* ()*)()
+ %call115 = tail call signext i32 bitcast (i32 (...)* @iter to i32 ()*)()
+ %cmp16 = icmp sgt i32 %call115, 0
+ br i1 %cmp16, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup: ; preds = %for.body, %entry
+ %res.0.lcssa = phi i32 [ 0, %entry ], [ %add5, %for.body ]
+ ret i32 %res.0.lcssa
+
+for.body: ; preds = %entry, %for.body
+ %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+ %res.017 = phi i32 [ %add5, %for.body ], [ 0, %entry ]
+ %arrayidx = getelementptr inbounds i32, i32* %call, i64 %indvars.iv
+ %0 = load i32, i32* %arrayidx, align 4
+ %add = add nsw i32 %0, %res.017
+ %1 = add nuw nsw i64 %indvars.iv, 16
+ %arrayidx4 = getelementptr inbounds i32, i32* %call, i64 %1
+ %2 = load i32, i32* %arrayidx4, align 4
+ %add5 = add nsw i32 %add, %2
+ %indvars.iv.next = add nuw i64 %indvars.iv, 1
+ %call1 = tail call signext i32 bitcast (i32 (...)* @iter to i32 ()*)()
+ %3 = sext i32 %call1 to i64
+ %cmp = icmp slt i64 %indvars.iv.next, %3
+ br i1 %cmp, label %for.body, label %for.cond.cleanup
+; CHECK-LABEL: check_cache_line
+; CHECK: dcbt
+; CHECK-NOT: dcbt
+; CHECK: blr
+; CHECK-DCBT-LABEL: check_cache_line
+; CHECK-DCBT: dcbt
+; CHECK-DCBT: dcbt
+; CHECK-DCBT: blr
+}
+
+declare i32* @magici(...) local_unnamed_addr
+
+declare signext i32 @iter(...) local_unnamed_addr
+
diff --git a/test/CodeGen/PowerPC/pristine-and-livein.mir b/test/CodeGen/PowerPC/pristine-and-livein.mir
deleted file mode 100644
index 6d93bb68c102..000000000000
--- a/test/CodeGen/PowerPC/pristine-and-livein.mir
+++ /dev/null
@@ -1,330 +0,0 @@
-# RUN: llc -run-pass=post-RA-sched %s -o - | FileCheck %s
-
-# CHECK: callee-saved-register: '[[REG:%x[0-9]+]]'
-# CHECK: callee-saved-register: '{{%x[0-9]+}}'
-# CHECK-NOT: [[REG]] = LI8 0
-# CHECK: STD killed [[REG]],
---- |
- ; ModuleID = '<stdin>'
- source_filename = "bugpoint-output-4d91ae2.bc"
- target datalayout = "e-m:e-i64:64-n32:64"
- target triple = "powerpc64le--linux-gnu"
-
- ; Function Attrs: norecurse nounwind readonly
- define i64 @adler32_z(i64 %adler, i8* readonly %buf, i64 %len) local_unnamed_addr #0 {
- entry:
- %shr = lshr i64 %adler, 16
- %and = and i64 %shr, 65535
- %and1 = and i64 %adler, 65535
- br i1 undef, label %if.then, label %if.end15
-
- if.then: ; preds = %entry
- %add5 = add nsw i64 %and1, %and
- %sub9 = add nsw i64 %add5, 281474976645135
- %shl = shl i64 %add5, 16
- %or = or i64 %shl, %and1
- br label %cleanup
-
- if.end15: ; preds = %entry
- br i1 undef, label %while.cond.preheader, label %while.cond30.preheader
-
- while.cond30.preheader: ; preds = %if.end15
- br i1 undef, label %while.body33.preheader, label %while.body109.preheader
-
- while.body33.preheader: ; preds = %while.cond30.preheader
- br label %while.body33
-
- while.cond.preheader: ; preds = %if.end15
- %sub25 = add i64 %and1, -65521
- %rem = urem i64 %and, 65521
- %shl27 = shl nuw nsw i64 %rem, 16
- %or28 = or i64 %shl27, %and1
- br label %cleanup
-
- while.body33: ; preds = %do.end, %while.body33.preheader
- %indvar = phi i64 [ %indvar.next, %do.end ], [ 0, %while.body33.preheader ]
- %sum2.2385 = phi i64 [ %rem102, %do.end ], [ %and, %while.body33.preheader ]
- %len.addr.1384 = phi i64 [ %sub34, %do.end ], [ %len, %while.body33.preheader ]
- %buf.addr.1383 = phi i8* [ %scevgep390, %do.end ], [ %buf, %while.body33.preheader ]
- %adler.addr.3382 = phi i64 [ %rem101, %do.end ], [ %and1, %while.body33.preheader ]
- %0 = mul i64 %indvar, 5552
- %1 = add i64 %0, -13
- %scevgep2 = getelementptr i8, i8* %buf, i64 %1
- %sub34 = add i64 %len.addr.1384, -5552
- call void @llvm.ppc.mtctr.i64(i64 347)
- br label %do.body
-
- do.body: ; preds = %do.body, %while.body33
- %adler.addr.4 = phi i64 [ %adler.addr.3382, %while.body33 ], [ %add49, %do.body ]
- %sum2.3 = phi i64 [ %sum2.2385, %while.body33 ], [ %add98, %do.body ]
- %tmp15.phi = phi i8* [ %scevgep2, %while.body33 ], [ %tmp15.inc, %do.body ]
- %tmp15.inc = getelementptr i8, i8* %tmp15.phi, i64 16
- %add38 = add i64 %adler.addr.4, %sum2.3
- %add42 = add i64 %add38, %adler.addr.4
- %add46 = add i64 %add42, %adler.addr.4
- %tmp15 = load i8, i8* %tmp15.inc, align 1, !tbaa !1
- %conv48 = zext i8 %tmp15 to i64
- %add49 = add i64 %adler.addr.4, %conv48
- %add50 = add i64 %add46, %add49
- %add54 = add i64 %add50, %add49
- %add58 = add i64 %add54, %add49
- %add62 = add i64 %add58, %add49
- %add66 = add i64 %add62, %add49
- %add70 = add i64 %add66, %add49
- %add74 = add i64 %add70, %add49
- %add78 = add i64 %add74, %add49
- %add82 = add i64 %add78, %add49
- %add86 = add i64 %add82, %add49
- %add90 = add i64 %add86, %add49
- %add94 = add i64 %add90, %add49
- %add98 = add i64 %add94, %add49
- %2 = call i1 @llvm.ppc.is.decremented.ctr.nonzero()
- br i1 %2, label %do.body, label %do.end
-
- do.end: ; preds = %do.body
- %scevgep390 = getelementptr i8, i8* %buf.addr.1383, i64 5552
- %rem101 = urem i64 %add49, 65521
- %rem102 = urem i64 %add98, 65521
- %cmp31 = icmp ugt i64 %sub34, 5551
- %indvar.next = add i64 %indvar, 1
- br i1 %cmp31, label %while.body33, label %while.end103
-
- while.end103: ; preds = %do.end
- br i1 undef, label %if.end188, label %while.body109.preheader
-
- while.body109.preheader: ; preds = %while.end103, %while.cond30.preheader
- %buf.addr.1.lcssa394400 = phi i8* [ %buf, %while.cond30.preheader ], [ %scevgep390, %while.end103 ]
- %arrayidx151 = getelementptr inbounds i8, i8* %buf.addr.1.lcssa394400, i64 10
- %tmp45 = load i8, i8* %arrayidx151, align 1, !tbaa !1
- %conv152 = zext i8 %tmp45 to i64
- br label %while.body109
-
- while.body109: ; preds = %while.body109, %while.body109.preheader
- %adler.addr.5373 = phi i64 [ %add153, %while.body109 ], [ undef, %while.body109.preheader ]
- %add153 = add i64 %adler.addr.5373, %conv152
- br label %while.body109
-
- if.end188: ; preds = %while.end103
- %shl189 = shl nuw nsw i64 %rem102, 16
- %or190 = or i64 %shl189, %rem101
- br label %cleanup
-
- cleanup: ; preds = %if.end188, %while.cond.preheader, %if.then
- %retval.0 = phi i64 [ %or, %if.then ], [ %or28, %while.cond.preheader ], [ %or190, %if.end188 ]
- ret i64 %retval.0
- }
-
- ; Function Attrs: nounwind
- declare void @llvm.ppc.mtctr.i64(i64) #1
-
- ; Function Attrs: nounwind
- declare i1 @llvm.ppc.is.decremented.ctr.nonzero() #1
-
- ; Function Attrs: nounwind
- declare void @llvm.stackprotector(i8*, i8**) #1
-
- attributes #0 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
- attributes #1 = { nounwind }
-
- !llvm.ident = !{!0}
-
- !0 = !{!"clang version 5.0.0 "}
- !1 = !{!2, !2, i64 0}
- !2 = !{!"omnipotent char", !3, i64 0}
- !3 = !{!"Simple C/C++ TBAA"}
-
-...
----
-name: adler32_z
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
- - { reg: '%x3' }
- - { reg: '%x4' }
- - { reg: '%x5' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-fixedStack:
- - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
- - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' }
- - { id: 2, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
-body: |
- bb.0.entry:
- successors: %bb.1.if.then(0x40000000), %bb.3.if.end15(0x40000000)
- liveins: %x3, %x4, %x5, %x29, %x30
-
- %x6 = RLWINM8 %x3, 16, 16, 31
- %x3 = RLDICL killed %x3, 0, 48
- BC undef %cr5lt, %bb.3.if.end15
-
- bb.1.if.then:
- successors: %bb.2.if.then(0x80000000)
- liveins: %x3, %x6, %x29, %x30
-
- %x4 = ADD8 %x3, killed %x6
-
- bb.2.if.then:
- liveins: %lr8, %rm, %x3, %x4
-
- %x4 = RLDICR killed %x4, 16, 47
- %x3 = OR8 killed %x4, killed %x3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
-
- bb.3.if.end15:
- successors: %bb.6.while.cond.preheader(0x40000000), %bb.4.while.cond30.preheader(0x40000000)
- liveins: %x3, %x4, %x5, %x6, %x29, %x30
-
- BC undef %cr5lt, %bb.6.while.cond.preheader
-
- bb.4.while.cond30.preheader:
- successors: %bb.7.while.body33.preheader(0x40000000), %bb.5(0x40000000)
- liveins: %x3, %x4, %x5, %x6, %x29, %x30
-
- BCn undef %cr5lt, %bb.7.while.body33.preheader
-
- bb.5:
- successors: %bb.12.while.body109.preheader(0x80000000)
- liveins: %x4, %x29, %x30
-
- %x7 = OR8 %x4, killed %x4
- B %bb.12.while.body109.preheader
-
- bb.6.while.cond.preheader:
- successors: %bb.2.if.then(0x80000000)
- liveins: %x3, %x6, %x29, %x30
-
- %x4 = LIS8 15
- %x4 = ORI8 killed %x4, 225
- %x4 = RLDICR killed %x4, 32, 31
- %x4 = ORIS8 killed %x4, 3375
- %x4 = ORI8 killed %x4, 50637
- %x4 = MULHDU %x6, killed %x4
- %x5 = SUBF8 %x4, %x6
- %x5 = RLDICL killed %x5, 63, 1
- %x4 = ADD8 killed %x5, killed %x4
- %x5 = LI8 0
- %x4 = RLDICL killed %x4, 49, 15
- %x5 = ORI8 killed %x5, 65521
- %x4 = MULLD killed %x4, killed %x5
- %x4 = SUBF8 killed %x4, killed %x6
- B %bb.2.if.then
-
- bb.7.while.body33.preheader:
- successors: %bb.8.while.body33(0x80000000)
- liveins: %x3, %x4, %x5, %x6, %x29, %x30
-
- STD killed %x29, -24, %x1 :: (store 8 into %fixed-stack.1)
- STD killed %x30, -16, %x1 :: (store 8 into %fixed-stack.0, align 16)
- %x7 = LIS8 15
- %x7 = ORI8 killed %x7, 225
- %x7 = RLDICR killed %x7, 32, 31
- %x8 = LI8 0
- %x7 = ORIS8 killed %x7, 3375
- %x9 = LI8 347
- %x10 = ORI8 killed %x7, 50637
- %x11 = ORI8 %x8, 65521
- %x7 = OR8 %x4, %x4
-
- bb.8.while.body33:
- successors: %bb.9.do.body(0x80000000)
- liveins: %x3, %x4, %x5, %x6, %x7, %x8, %x9, %x10, %x11
-
- %x12 = MULLI8 %x8, 5552
- %x12 = ADD8 %x4, killed %x12
- %x12 = ADDI8 killed %x12, -13
- %x5 = ADDI8 killed %x5, -5552
- MTCTR8loop %x9, implicit-def dead %ctr8
-
- bb.9.do.body:
- successors: %bb.9.do.body(0x7c000000), %bb.10.do.end(0x04000000)
- liveins: %x3, %x4, %x5, %x6, %x7, %x8, %x9, %x10, %x11, %x12
-
- %x0, %x12 = LBZU8 16, killed %x12 :: (load 1 from %ir.tmp15.inc, !tbaa !1)
- %x6 = ADD8 %x3, killed %x6
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x3 = ADD8 killed %x3, killed %x0
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- %x6 = ADD8 killed %x6, %x3
- BDNZ8 %bb.9.do.body, implicit-def %ctr8, implicit %ctr8
-
- bb.10.do.end:
- successors: %bb.8.while.body33(0x7c000000), %bb.11.while.end103(0x04000000)
- liveins: %x3, %x4, %x5, %x6, %x7, %x8, %x9, %x10, %x11
-
- %x12 = MULHDU %x3, %x10
- %x0 = MULHDU %x6, %x10
- %x30 = SUBF8 %x12, %x3
- %x29 = SUBF8 %x0, %x6
- %x30 = RLDICL killed %x30, 63, 1
- %x29 = RLDICL killed %x29, 63, 1
- %x12 = ADD8 killed %x30, killed %x12
- %x0 = ADD8 killed %x29, killed %x0
- %cr0 = CMPLDI %x5, 5551
- %x12 = RLDICL killed %x12, 49, 15
- %x0 = RLDICL killed %x0, 49, 15
- %x12 = MULLD killed %x12, %x11
- %x0 = MULLD killed %x0, %x11
- %x7 = ADDI8 killed %x7, 5552
- %x3 = SUBF8 killed %x12, killed %x3
- %x6 = SUBF8 killed %x0, killed %x6
- %x8 = ADDI8 killed %x8, 1
- BCC 44, killed %cr0, %bb.8.while.body33
-
- bb.11.while.end103:
- successors: %bb.14.if.end188(0x40000000), %bb.12.while.body109.preheader(0x40000000)
- liveins: %x3, %x6, %x7
-
- %x30 = LD -16, %x1 :: (load 8 from %fixed-stack.0, align 16)
- %x29 = LD -24, %x1 :: (load 8 from %fixed-stack.1)
- BC undef %cr5lt, %bb.14.if.end188
-
- bb.12.while.body109.preheader:
- successors: %bb.13.while.body109(0x80000000)
- liveins: %x7, %x29, %x30
-
- %x3 = LBZ8 10, killed %x7 :: (load 1 from %ir.arrayidx151, !tbaa !1)
- %x4 = IMPLICIT_DEF
-
- bb.13.while.body109:
- successors: %bb.13.while.body109(0x80000000)
- liveins: %x3, %x4, %x29, %x30
-
- %x4 = ADD8 killed %x4, %x3
- B %bb.13.while.body109
-
- bb.14.if.end188:
- liveins: %x3, %x6, %x29, %x30
-
- %x4 = RLDICR killed %x6, 16, 47
- %x3 = OR8 killed %x4, killed %x3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
-
-...
diff --git a/test/CodeGen/PowerPC/testComparesieqsll.ll b/test/CodeGen/PowerPC/testComparesieqsll.ll
new file mode 100644
index 000000000000..57c7365eff03
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesieqsll.ll
@@ -0,0 +1,134 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_z(i64 %a) {
+; CHECK-LABEL: test_ieqsll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_ieqsll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ieqsll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_z_store(i64 %a) {
+; CHECK-LABEL: test_ieqsll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ieqsll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesiequll.ll b/test/CodeGen/PowerPC/testComparesiequll.ll
new file mode 100644
index 000000000000..c28929071845
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesiequll.ll
@@ -0,0 +1,134 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_z(i64 %a) {
+; CHECK-LABEL: test_iequll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequll_sext_z(i64 %a) {
+; CHECK-LABEL: test_iequll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_iequll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_z_store(i64 %a) {
+; CHECK-LABEL: test_iequll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_iequll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/testCompareslleqsll.ll b/test/CodeGen/PowerPC/testCompareslleqsll.ll
new file mode 100644
index 000000000000..4797ddfbfe97
--- /dev/null
+++ b/test/CodeGen/PowerPC/testCompareslleqsll.ll
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_z(i64 %a) {
+; CHECK-LABEL: test_lleqsll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsll_sext_z(i64 %a) {
+; CHECK-LABEL: test_lleqsll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lleqsll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_z_store(i64 %a) {
+; CHECK-LABEL: test_lleqsll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_lleqsll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesllequll.ll b/test/CodeGen/PowerPC/testComparesllequll.ll
new file mode 100644
index 000000000000..4dc7be69d2c8
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesllequll.ll
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_z(i64 %a) {
+; CHECK-LABEL: test_llequll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llequll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llequll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: std r3, 0(r12)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_z_store(i64 %a) {
+; CHECK-LABEL: test_llequll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llequll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp eq i64 %a, 0
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/vec_xxpermdi.ll b/test/CodeGen/PowerPC/vec_xxpermdi.ll
new file mode 100644
index 000000000000..9be2a1864a04
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_xxpermdi.ll
@@ -0,0 +1,307 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \
+; RUN: FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \
+; RUN: FileCheck %s -check-prefix=CHECK-BE
+
+; Possible LE ShuffleVector masks (Case 1):
+; ShuffleVector((vector double)a, (vector double)b, 3, 1)
+; ShuffleVector((vector double)a, (vector double)b, 2, 1)
+; ShuffleVector((vector double)a, (vector double)b, 3, 0)
+; ShuffleVector((vector double)a, (vector double)b, 2, 0)
+; which targets at:
+; xxpermdi a, b, 0
+; xxpermdi a, b, 1
+; xxpermdi a, b, 2
+; xxpermdi a, b, 3
+; Possible LE Swap ShuffleVector masks (Case 2):
+; ShuffleVector((vector double)a, (vector double)b, 1, 3)
+; ShuffleVector((vector double)a, (vector double)b, 0, 3)
+; ShuffleVector((vector double)a, (vector double)b, 1, 2)
+; ShuffleVector((vector double)a, (vector double)b, 0, 2)
+; which targets at:
+; xxpermdi b, a, 0
+; xxpermdi b, a, 1
+; xxpermdi b, a, 2
+; xxpermdi b, a, 3
+; Possible LE ShuffleVector masks when a == b, b is undef (Case 3):
+; ShuffleVector((vector double)a, (vector double)a, 1, 1)
+; ShuffleVector((vector double)a, (vector double)a, 0, 1)
+; ShuffleVector((vector double)a, (vector double)a, 1, 0)
+; ShuffleVector((vector double)a, (vector double)a, 0, 0)
+; which targets at:
+; xxpermdi a, a, 0
+; xxpermdi a, a, 1
+; xxpermdi a, a, 2
+; xxpermdi a, a, 3
+
+; Possible BE ShuffleVector masks (Case 4):
+; ShuffleVector((vector double)a, (vector double)b, 0, 2)
+; ShuffleVector((vector double)a, (vector double)b, 0, 3)
+; ShuffleVector((vector double)a, (vector double)b, 1, 2)
+; ShuffleVector((vector double)a, (vector double)b, 1, 3)
+; which targets at:
+; xxpermdi a, b, 0
+; xxpermdi a, b, 1
+; xxpermdi a, b, 2
+; xxpermdi a, b, 3
+; Possible BE Swap ShuffleVector masks (Case 5):
+; ShuffleVector((vector double)a, (vector double)b, 2, 0)
+; ShuffleVector((vector double)a, (vector double)b, 3, 0)
+; ShuffleVector((vector double)a, (vector double)b, 2, 1)
+; ShuffleVector((vector double)a, (vector double)b, 3, 1)
+; which targets at:
+; xxpermdi b, a, 0
+; xxpermdi b, a, 1
+; xxpermdi b, a, 2
+; xxpermdi b, a, 3
+; Possible BE ShuffleVector masks when a == b, b is undef (Case 6):
+; ShuffleVector((vector double)a, (vector double)a, 0, 0)
+; ShuffleVector((vector double)a, (vector double)a, 0, 1)
+; ShuffleVector((vector double)a, (vector double)a, 1, 0)
+; ShuffleVector((vector double)a, (vector double)a, 1, 1)
+; which targets at:
+; xxpermdi a, a, 0
+; xxpermdi a, a, 1
+; xxpermdi a, a, 2
+; xxpermdi a, a, 3
+
+define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_0
+; CHECK-LE: xxmrghd 34, 34, 35
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_1
+; CHECK-LE: xxpermdi 34, 34, 35, 1
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_2
+; CHECK-LE: xxpermdi 34, 34, 35, 2
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_3
+; CHECK-LE: xxmrgld 34, 34, 35
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_0
+; CHECK-LE: xxmrghd 34, 35, 34
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 3>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_1
+; CHECK-LE: xxpermdi 34, 35, 34, 1
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 2>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_2
+; CHECK-LE: xxpermdi 34, 35, 34, 2
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 2>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_3
+; CHECK-LE: xxmrgld 34, 35, 34
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 1>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_0
+; CHECK-LE: xxspltd 34, 34, 0
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_1
+; CHECK-LE: blr
+}
+
+define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_2
+; CHCECK-LE: xxswapd 34, 34
+}
+
+define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+ ret <2 x double> %0
+; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_3
+; CHECK-LE: xxspltd 34, 34, 1
+; CHECK-LE: blr
+}
+
+; Start testing BE
+define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 2>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_0
+; CHECK-BE: xxmrghd 34, 34, 35
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 3>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_1
+; CHECK-BE: xxpermdi 34, 34, 35, 1
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 2>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_2
+; CHECK-BE: xxpermdi 34, 34, 35, 2
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_3
+; CHECK-BE: xxmrgld 34, 34, 35
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_0
+; CHECK-BE: xxmrghd 34, 35, 34
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_1
+; CHECK-BE: xxpermdi 34, 35, 34, 1
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_2
+; CHECK-BE: xxpermdi 34, 35, 34, 2
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_3
+; CHECK-BE: xxmrgld 34, 35, 34
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_0
+; CHECK-BE: xxspltd 34, 34, 0
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 1>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_1
+; CHECK-BE: blr
+}
+
+define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_2
+; CHCECK-LE: xxswapd 34, 34
+}
+
+define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) {
+ entry:
+ %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 1>
+ ret <2 x double> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_3
+; CHECK-BE: xxspltd 34, 34, 1
+; CHECK-BE: blr
+}
+
+; More test cases to test different types of vector inputs
+define <16 x i8> @test_be_vec_xxpermdi_v16i8_v16i8(<16 x i8> %VA, <16 x i8> %VB) {
+ entry:
+ %0 = shufflevector <16 x i8> %VA, <16 x i8> %VB,<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
+ ret <16 x i8> %0
+; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v16i8_v16i8
+; CHECK-BE: xxpermdi 34, 34, 35, 1
+; CHECK-BE: blr
+}
+
+define <8 x i16> @test_le_swap_vec_xxpermdi_v8i16_v8i16(<8 x i16> %VA, <8 x i16> %VB) {
+ entry:
+ %0 = shufflevector <8 x i16> %VA, <8 x i16> %VB,<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+ ret <8 x i16> %0
+; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v8i16_v8i16
+; CHECK-LE: xxpermdi 34, 35, 34, 1
+; CHECK-LE: blr
+}
+
+define <4 x i32> @test_le_swap_vec_xxpermdi_v4i32_v4i32(<4 x i32> %VA, <4 x i32> %VB) {
+ entry:
+ %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB,<4 x i32> <i32 0, i32 1, i32 6, i32 7>
+ ret <4 x i32> %0
+; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v4i32_v4i32
+; CHECK-LE: xxpermdi 34, 35, 34, 1
+; CHECK-LE: blr
+}
generated by cgit v1.3 (git 2.53.0) at 2026-03-10 18:45:53 +0000