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-rw-r--r--test/CodeGen/SPARC/2011-01-22-SRet.ll2
-rw-r--r--test/CodeGen/SPARC/32abi.ll191
-rw-r--r--test/CodeGen/SPARC/64abi.ll84
-rw-r--r--test/CodeGen/SPARC/basictest.ll21
-rw-r--r--test/CodeGen/SPARC/float-constants.ll41
-rw-r--r--test/CodeGen/SPARC/float.ll10
-rw-r--r--test/CodeGen/SPARC/fp128.ll4
-rw-r--r--test/CodeGen/SPARC/inlineasm.ll53
-rw-r--r--test/CodeGen/SPARC/missing-sret.ll9
-rw-r--r--test/CodeGen/SPARC/reserved-regs.ll135
-rw-r--r--test/CodeGen/SPARC/select-mask.ll17
-rw-r--r--test/CodeGen/SPARC/spill.ll64
-rw-r--r--test/CodeGen/SPARC/stack-align.ll22
-rw-r--r--test/CodeGen/SPARC/tls.ll2
-rw-r--r--test/CodeGen/SPARC/varargs.ll2
15 files changed, 593 insertions, 64 deletions
diff --git a/test/CodeGen/SPARC/2011-01-22-SRet.ll b/test/CodeGen/SPARC/2011-01-22-SRet.ll
index ae9764e82084..678544ebf2cb 100644
--- a/test/CodeGen/SPARC/2011-01-22-SRet.ll
+++ b/test/CodeGen/SPARC/2011-01-22-SRet.ll
@@ -19,8 +19,8 @@ entry:
define i32 @test() nounwind {
entry:
;CHECK-LABEL: test:
-;CHECK: st {{.+}}, [%sp+64]
;CHECK: call make_foo
+;CHECK: st {{.+}}, [%sp+64]
;CHECK: unimp 12
%f = alloca %struct.foo_t, align 8
call void @make_foo(%struct.foo_t* noalias sret %f, i32 10, i32 20, i32 30) nounwind
diff --git a/test/CodeGen/SPARC/32abi.ll b/test/CodeGen/SPARC/32abi.ll
new file mode 100644
index 000000000000..7ac1de5c0904
--- /dev/null
+++ b/test/CodeGen/SPARC/32abi.ll
@@ -0,0 +1,191 @@
+; RUN: llc < %s -march=sparc -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
+; RUN: llc < %s -march=sparcel -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
+
+; CHECK-LABEL: intarg:
+; The save/restore frame is not strictly necessary here, but we would need to
+; refer to %o registers instead.
+; CHECK: save %sp, -96, %sp
+; CHECK: ld [%fp+96], [[R2:%[gilo][0-7]]]
+; CHECK: ld [%fp+92], [[R1:%[gilo][0-7]]]
+; CHECK: stb %i0, [%i4]
+; CHECK: stb %i1, [%i4]
+; CHECK: sth %i2, [%i4]
+; CHECK: st %i3, [%i4]
+; CHECK: st %i4, [%i4]
+; CHECK: st %i5, [%i4]
+; CHECK: st [[R1]], [%i4]
+; CHECK: st [[R2]], [%i4]
+; CHECK: restore
+define void @intarg(i8 %a0, ; %i0
+ i8 %a1, ; %i1
+ i16 %a2, ; %i2
+ i32 %a3, ; %i3
+ i8* %a4, ; %i4
+ i32 %a5, ; %i5
+ i32 signext %a6, ; [%fp+92]
+ i8* %a7) { ; [%fp+96]
+ store i8 %a0, i8* %a4
+ store i8 %a1, i8* %a4
+ %p16 = bitcast i8* %a4 to i16*
+ store i16 %a2, i16* %p16
+ %p32 = bitcast i8* %a4 to i32*
+ store i32 %a3, i32* %p32
+ %pp = bitcast i8* %a4 to i8**
+ store i8* %a4, i8** %pp
+ store i32 %a5, i32* %p32
+ store i32 %a6, i32* %p32
+ store i8* %a7, i8** %pp
+ ret void
+}
+
+; CHECK-LABEL: call_intarg:
+; CHECK: save %sp, -104, %sp
+; Use %o0-%o5 for outgoing arguments
+; CHECK: mov 5, %o5
+; CHECK: st %i0, [%sp+92]
+; CHECK: call intarg
+; CHECK-NOT: add %sp
+; CHECK: restore
+define void @call_intarg(i32 %i0, i8* %i1) {
+ call void @intarg(i8 0, i8 1, i16 2, i32 3, i8* undef, i32 5, i32 %i0, i8* %i1)
+ ret void
+}
+
+;; Verify doubles starting with an even reg, starting with an odd reg,
+;; straddling the boundary of regs and mem, and floats in regs and mem.
+;
+; CHECK-LABEL: floatarg:
+; CHECK: save %sp, -120, %sp
+; CHECK: mov %i5, %g2
+; CHECK-NEXT: ld [%fp+92], %g3
+; CHECK-NEXT: mov %i4, %i5
+; CHECK-NEXT: std %g2, [%fp+-24]
+; CHECK-NEXT: mov %i3, %i4
+; CHECK-NEXT: std %i4, [%fp+-16]
+; CHECK-NEXT: std %i0, [%fp+-8]
+; CHECK-NEXT: st %i2, [%fp+-28]
+; CHECK-NEXT: ld [%fp+104], %f0
+; CHECK-NEXT: ldd [%fp+96], %f2
+; CHECK-NEXT: ld [%fp+-28], %f1
+; CHECK-NEXT: ldd [%fp+-8], %f4
+; CHECK-NEXT: ldd [%fp+-16], %f6
+; CHECK-NEXT: ldd [%fp+-24], %f8
+; CHECK-NEXT: fstod %f1, %f10
+; CHECK-NEXT: faddd %f4, %f10, %f4
+; CHECK-NEXT: faddd %f6, %f4, %f4
+; CHECK-NEXT: faddd %f8, %f4, %f4
+; CHECK-NEXT: faddd %f2, %f4, %f2
+; CHECK-NEXT: fstod %f0, %f0
+; CHECK-NEXT: faddd %f0, %f2, %f0
+; CHECK-NEXT: restore
+define double @floatarg(double %a0, ; %i0,%i1
+ float %a1, ; %i2
+ double %a2, ; %i3, %i4
+ double %a3, ; %i5, [%fp+92] (using 4 bytes)
+ double %a4, ; [%fp+96] (using 8 bytes)
+ float %a5) { ; [%fp+104] (using 4 bytes)
+ %d1 = fpext float %a1 to double
+ %s1 = fadd double %a0, %d1
+ %s2 = fadd double %a2, %s1
+ %s3 = fadd double %a3, %s2
+ %s4 = fadd double %a4, %s3
+ %d5 = fpext float %a5 to double
+ %s5 = fadd double %d5, %s4
+ ret double %s5
+}
+
+; CHECK-LABEL: call_floatarg:
+; CHECK: save %sp, -112, %sp
+; CHECK: mov %i2, %o1
+; CHECK-NEXT: mov %i1, %o0
+; CHECK-NEXT: st %i0, [%sp+104]
+; CHECK-NEXT: std %o0, [%sp+96]
+; CHECK-NEXT: st %o1, [%sp+92]
+; CHECK-NEXT: mov %i0, %o2
+; CHECK-NEXT: mov %o0, %o3
+; CHECK-NEXT: mov %o1, %o4
+; CHECK-NEXT: mov %o0, %o5
+; CHECK-NEXT: call floatarg
+; CHECK: std %f0, [%i4]
+; CHECK: restore
+define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) {
+ %r = call double @floatarg(double %d2, float %f1, double %d2, double %d2,
+ double %d2, float %f1)
+ store double %r, double* %p
+ ret void
+}
+
+;; i64 arguments should effectively work the same as double: split
+;; into two locations. This is different for little-endian vs big
+;; endian, since the 64-bit math needs to be split
+; CHECK-LABEL: i64arg:
+; CHECK: save %sp, -96, %sp
+; CHECK-BE: ld [%fp+100], %g2
+; CHECK-BE-NEXT: ld [%fp+96], %g3
+; CHECK-BE-NEXT: ld [%fp+92], %g4
+; CHECK-BE-NEXT: addcc %i1, %i2, %i1
+; CHECK-BE-NEXT: addxcc %i0, 0, %i0
+; CHECK-BE-NEXT: addcc %i4, %i1, %i1
+; CHECK-BE-NEXT: addxcc %i3, %i0, %i0
+; CHECK-BE-NEXT: addcc %g4, %i1, %i1
+; CHECK-BE-NEXT: ld [%fp+104], %i2
+; CHECK-BE-NEXT: addxcc %i5, %i0, %i0
+; CHECK-BE-NEXT: addcc %g2, %i1, %i1
+; CHECK-BE-NEXT: addxcc %g3, %i0, %i0
+; CHECK-BE-NEXT: addcc %i2, %i1, %i1
+; CHECK-BE-NEXT: addxcc %i0, 0, %i0
+;
+; CHECK-LE: ld [%fp+96], %g2
+; CHECK-LE-NEXT: ld [%fp+100], %g3
+; CHECK-LE-NEXT: ld [%fp+92], %g4
+; CHECK-LE-NEXT: addcc %i0, %i2, %i0
+; CHECK-LE-NEXT: addxcc %i1, 0, %i1
+; CHECK-LE-NEXT: addcc %i3, %i0, %i0
+; CHECK-LE-NEXT: addxcc %i4, %i1, %i1
+; CHECK-LE-NEXT: addcc %i5, %i0, %i0
+; CHECK-LE-NEXT: ld [%fp+104], %i2
+; CHECK-LE-NEXT: addxcc %g4, %i1, %i1
+; CHECK-LE-NEXT: addcc %g2, %i0, %i0
+; CHECK-LE-NEXT: addxcc %g3, %i1, %i1
+; CHECK-LE-NEXT: addcc %i2, %i0, %i0
+; CHECK-LE-NEXT: addxcc %i1, 0, %i1
+; CHECK-NEXT: restore
+
+
+define i64 @i64arg(i64 %a0, ; %i0,%i1
+ i32 %a1, ; %i2
+ i64 %a2, ; %i3, %i4
+ i64 %a3, ; %i5, [%fp+92] (using 4 bytes)
+ i64 %a4, ; [%fp+96] (using 8 bytes)
+ i32 %a5) { ; [%fp+104] (using 4 bytes)
+ %a1L = zext i32 %a1 to i64
+ %s1 = add i64 %a0, %a1L
+ %s2 = add i64 %a2, %s1
+ %s3 = add i64 %a3, %s2
+ %s4 = add i64 %a4, %s3
+ %a5L = zext i32 %a5 to i64
+ %s5 = add i64 %a5L, %s4
+ ret i64 %s5
+}
+
+; CHECK-LABEL: call_i64arg:
+; CHECK: save %sp, -112, %sp
+; CHECK: st %i0, [%sp+104]
+; CHECK-NEXT: st %i2, [%sp+100]
+; CHECK-NEXT: st %i1, [%sp+96]
+; CHECK-NEXT: st %i2, [%sp+92]
+; CHECK-NEXT: mov %i1, %o0
+; CHECK-NEXT: mov %i2, %o1
+; CHECK-NEXT: mov %i0, %o2
+; CHECK-NEXT: mov %i1, %o3
+; CHECK-NEXT: mov %i2, %o4
+; CHECK-NEXT: mov %i1, %o5
+; CHECK-NEXT: call i64arg
+; CHECK: std %o0, [%i3]
+; CHECK-NEXT: restore
+
+define void @call_i64arg(i32 %a0, i64 %a1, i64* %p) {
+ %r = call i64 @i64arg(i64 %a1, i32 %a0, i64 %a1, i64 %a1, i64 %a1, i32 %a0)
+ store i64 %r, i64* %p
+ ret void
+}
diff --git a/test/CodeGen/SPARC/64abi.ll b/test/CodeGen/SPARC/64abi.ll
index 7c08998a1427..96104ecc3c68 100644
--- a/test/CodeGen/SPARC/64abi.ll
+++ b/test/CodeGen/SPARC/64abi.ll
@@ -1,19 +1,19 @@
; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
-; CHECK: intarg
+; CHECK-LABEL: intarg:
; The save/restore frame is not strictly necessary here, but we would need to
; refer to %o registers instead.
; CHECK: save %sp, -128, %sp
+; CHECK: ldx [%fp+2231], [[R2:%[gilo][0-7]]]
+; CHECK: ld [%fp+2227], [[R1:%[gilo][0-7]]]
; CHECK: stb %i0, [%i4]
; CHECK: stb %i1, [%i4]
; CHECK: sth %i2, [%i4]
; CHECK: st %i3, [%i4]
; CHECK: stx %i4, [%i4]
; CHECK: st %i5, [%i4]
-; CHECK: ld [%fp+2227], [[R:%[gilo][0-7]]]
-; CHECK: st [[R]], [%i4]
-; CHECK: ldx [%fp+2231], [[R:%[gilo][0-7]]]
-; CHECK: stx [[R]], [%i4]
+; CHECK: st [[R1]], [%i4]
+; CHECK: stx [[R2]], [%i4]
; CHECK: restore
define void @intarg(i8 %a0, ; %i0
i8 %a1, ; %i1
@@ -37,14 +37,14 @@ define void @intarg(i8 %a0, ; %i0
ret void
}
-; CHECK: call_intarg
+; CHECK-LABEL: call_intarg:
; 16 saved + 8 args.
; CHECK: save %sp, -192, %sp
; Sign-extend and store the full 64 bits.
; CHECK: sra %i0, 0, [[R:%[gilo][0-7]]]
-; CHECK: stx [[R]], [%sp+2223]
; Use %o0-%o5 for outgoing arguments
; CHECK: mov 5, %o5
+; CHECK: stx [[R]], [%sp+2223]
; CHECK: call intarg
; CHECK-NOT: add %sp
; CHECK: restore
@@ -53,13 +53,13 @@ define void @call_intarg(i32 %i0, i8* %i1) {
ret void
}
-; CHECK: floatarg
+; CHECK-LABEL: floatarg:
; CHECK: save %sp, -128, %sp
+; CHECK: ld [%fp+2307], [[F:%f[0-9]+]]
; CHECK: fstod %f1,
; CHECK: faddd %f2,
; CHECK: faddd %f4,
; CHECK: faddd %f6,
-; CHECK: ld [%fp+2307], [[F:%f[0-9]+]]
; CHECK: fadds %f31, [[F]]
define double @floatarg(float %a0, ; %f1
double %a1, ; %d2
@@ -89,12 +89,12 @@ define double @floatarg(float %a0, ; %f1
ret double %s17
}
-; CHECK: call_floatarg
+; CHECK-LABEL: call_floatarg:
; CHECK: save %sp, -272, %sp
-; Store 4 bytes, right-aligned in slot.
-; CHECK: st %f1, [%sp+2307]
; Store 8 bytes in full slot.
; CHECK: std %f2, [%sp+2311]
+; Store 4 bytes, right-aligned in slot.
+; CHECK: st %f1, [%sp+2307]
; CHECK: fmovd %f2, %f4
; CHECK: call floatarg
; CHECK-NOT: add %sp
@@ -109,12 +109,12 @@ define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) {
ret void
}
-; CHECK: mixedarg
+; CHECK-LABEL: mixedarg:
+; CHECK: ldx [%fp+2247]
+; CHECK: ldx [%fp+2231]
; CHECK: fstod %f3
; CHECK: faddd %f6
; CHECK: faddd %f16
-; CHECK: ldx [%fp+2231]
-; CHECK: ldx [%fp+2247]
define void @mixedarg(i8 %a0, ; %i0
float %a1, ; %f3
i16 %a2, ; %i2
@@ -133,7 +133,7 @@ define void @mixedarg(i8 %a0, ; %i0
ret void
}
-; CHECK: call_mixedarg
+; CHECK-LABEL: call_mixedarg:
; CHECK: stx %i2, [%sp+2247]
; CHECK: stx %i0, [%sp+2223]
; CHECK: fmovd %f2, %f6
@@ -157,7 +157,7 @@ define void @call_mixedarg(i64 %i0, double %f2, i16* %i2) {
; The inreg attribute is used to indicate 32-bit sized struct elements that
; share an 8-byte slot.
-; CHECK: inreg_fi
+; CHECK-LABEL: inreg_fi:
; CHECK: fstoi %f1
; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]
; CHECK: sub [[R]],
@@ -168,7 +168,7 @@ define i32 @inreg_fi(i32 inreg %a0, ; high bits of %i0
ret i32 %rv
}
-; CHECK: call_inreg_fi
+; CHECK-LABEL: call_inreg_fi:
; Allocate space for 6 arguments, even when only 2 are used.
; CHECK: save %sp, -176, %sp
; CHECK: sllx %i1, 32, %o0
@@ -179,7 +179,7 @@ define void @call_inreg_fi(i32* %p, i32 %i1, float %f5) {
ret void
}
-; CHECK: inreg_ff
+; CHECK-LABEL: inreg_ff:
; CHECK: fsubs %f0, %f1, %f0
define float @inreg_ff(float inreg %a0, ; %f0
float inreg %a1) { ; %f1
@@ -187,7 +187,7 @@ define float @inreg_ff(float inreg %a0, ; %f0
ret float %rv
}
-; CHECK: call_inreg_ff
+; CHECK-LABEL: call_inreg_ff:
; CHECK: fmovs %f3, %f0
; CHECK: fmovs %f5, %f1
; CHECK: call inreg_ff
@@ -196,7 +196,7 @@ define void @call_inreg_ff(i32* %p, float %f3, float %f5) {
ret void
}
-; CHECK: inreg_if
+; CHECK-LABEL: inreg_if:
; CHECK: fstoi %f0
; CHECK: sub %i0
define i32 @inreg_if(float inreg %a0, ; %f0
@@ -206,7 +206,7 @@ define i32 @inreg_if(float inreg %a0, ; %f0
ret i32 %rv
}
-; CHECK: call_inreg_if
+; CHECK-LABEL: call_inreg_if:
; CHECK: fmovs %f3, %f0
; CHECK: mov %i2, %o0
; CHECK: call inreg_if
@@ -216,7 +216,7 @@ define void @call_inreg_if(i32* %p, float %f3, i32 %i2) {
}
; The frontend shouldn't do this. Just pass i64 instead.
-; CHECK: inreg_ii
+; CHECK-LABEL: inreg_ii:
; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]
; CHECK: sub %i0, [[R]], %i0
define i32 @inreg_ii(i32 inreg %a0, ; high bits of %i0
@@ -225,7 +225,7 @@ define i32 @inreg_ii(i32 inreg %a0, ; high bits of %i0
ret i32 %rv
}
-; CHECK: call_inreg_ii
+; CHECK-LABEL: call_inreg_ii:
; CHECK: srl %i2, 0, [[R2:%[gilo][0-7]]]
; CHECK: sllx %i1, 32, [[R1:%[gilo][0-7]]]
; CHECK: or [[R1]], [[R2]], %o0
@@ -236,7 +236,7 @@ define void @call_inreg_ii(i32* %p, i32 %i1, i32 %i2) {
}
; Structs up to 32 bytes in size can be returned in registers.
-; CHECK: ret_i64_pair
+; CHECK-LABEL: ret_i64_pair:
; CHECK: ldx [%i2], %i0
; CHECK: ldx [%i3], %i1
define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) {
@@ -248,7 +248,7 @@ define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) {
ret { i64, i64 } %rv2
}
-; CHECK: call_ret_i64_pair
+; CHECK-LABEL: call_ret_i64_pair:
; CHECK: call ret_i64_pair
; CHECK: stx %o0, [%i0]
; CHECK: stx %o1, [%i0]
@@ -263,7 +263,7 @@ define void @call_ret_i64_pair(i64* %i0) {
}
; This is not a C struct, the i32 member uses 8 bytes, but the float only 4.
-; CHECK: ret_i32_float_pair
+; CHECK-LABEL: ret_i32_float_pair:
; CHECK: ld [%i2], %i0
; CHECK: ld [%i3], %f2
define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
@@ -276,7 +276,7 @@ define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
ret { i32, float } %rv2
}
-; CHECK: call_ret_i32_float_pair
+; CHECK-LABEL: call_ret_i32_float_pair:
; CHECK: call ret_i32_float_pair
; CHECK: st %o0, [%i0]
; CHECK: st %f2, [%i1]
@@ -291,10 +291,10 @@ define void @call_ret_i32_float_pair(i32* %i0, float* %i1) {
}
; This is a C struct, each member uses 4 bytes.
-; CHECK: ret_i32_float_packed
+; CHECK-LABEL: ret_i32_float_packed:
; CHECK: ld [%i2], [[R:%[gilo][0-7]]]
-; CHECK: sllx [[R]], 32, %i0
; CHECK: ld [%i3], %f1
+; CHECK: sllx [[R]], 32, %i0
define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1,
i32* %p, float* %q) {
%r1 = load i32, i32* %p
@@ -305,7 +305,7 @@ define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1,
ret { i32, float } %rv2
}
-; CHECK: call_ret_i32_float_packed
+; CHECK-LABEL: call_ret_i32_float_packed:
; CHECK: call ret_i32_float_packed
; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]
; CHECK: st [[R]], [%i0]
@@ -322,7 +322,7 @@ define void @call_ret_i32_float_packed(i32* %i0, float* %i1) {
; The C frontend should use i64 to return { i32, i32 } structs, but verify that
; we don't miscompile thi case where both struct elements are placed in %i0.
-; CHECK: ret_i32_packed
+; CHECK-LABEL: ret_i32_packed:
; CHECK: ld [%i2], [[R1:%[gilo][0-7]]]
; CHECK: ld [%i3], [[R2:%[gilo][0-7]]]
; CHECK: sllx [[R2]], 32, [[R3:%[gilo][0-7]]]
@@ -337,7 +337,7 @@ define inreg { i32, i32 } @ret_i32_packed(i32 %a0, i32 %a1,
ret { i32, i32 } %rv2
}
-; CHECK: call_ret_i32_packed
+; CHECK-LABEL: call_ret_i32_packed:
; CHECK: call ret_i32_packed
; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]
; CHECK: st [[R]], [%i0]
@@ -353,31 +353,31 @@ define void @call_ret_i32_packed(i32* %i0, i32* %i1) {
}
; The return value must be sign-extended to 64 bits.
-; CHECK: ret_sext
+; CHECK-LABEL: ret_sext:
; CHECK: sra %i0, 0, %i0
define signext i32 @ret_sext(i32 %a0) {
ret i32 %a0
}
-; CHECK: ret_zext
+; CHECK-LABEL: ret_zext:
; CHECK: srl %i0, 0, %i0
define zeroext i32 @ret_zext(i32 %a0) {
ret i32 %a0
}
-; CHECK: ret_nosext
+; CHECK-LABEL: ret_nosext:
; CHECK-NOT: sra
define signext i32 @ret_nosext(i32 signext %a0) {
ret i32 %a0
}
-; CHECK: ret_nozext
+; CHECK-LABEL: ret_nozext:
; CHECK-NOT: srl
define signext i32 @ret_nozext(i32 signext %a0) {
ret i32 %a0
}
-; CHECK-LABEL: test_register_directive
+; CHECK-LABEL: test_register_directive:
; CHECK: .register %g2, #scratch
; CHECK: .register %g3, #scratch
; CHECK: add %i0, 2, %g2
@@ -391,7 +391,7 @@ entry:
ret i32 %2
}
-; CHECK-LABEL: test_large_stack
+; CHECK-LABEL: test_large_stack:
; CHECK: sethi 16, %g1
; CHECK: xor %g1, -176, %g1
@@ -412,7 +412,7 @@ entry:
declare i32 @use_buf(i32, i8*)
-; CHECK-LABEL: test_fp128_args
+; CHECK-LABEL: test_fp128_args:
; CHECK-DAG: std %f0, [%fp+{{.+}}]
; CHECK-DAG: std %f2, [%fp+{{.+}}]
; CHECK-DAG: std %f6, [%fp+{{.+}}]
@@ -428,7 +428,7 @@ entry:
declare i64 @receive_fp128(i64 %a, ...)
-; CHECK-LABEL: test_fp128_variable_args
+; CHECK-LABEL: test_fp128_variable_args:
; CHECK-DAG: std %f4, [%sp+[[Offset0:[0-9]+]]]
; CHECK-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
; CHECK-DAG: ldx [%sp+[[Offset0]]], %o2
@@ -440,7 +440,7 @@ entry:
ret i64 %0
}
-; CHECK-LABEL: test_call_libfunc
+; CHECK-LABEL: test_call_libfunc:
; CHECK: st %f1, [%fp+[[Offset0:[0-9]+]]]
; CHECK: fmovs %f3, %f1
; CHECK: call cosf
diff --git a/test/CodeGen/SPARC/basictest.ll b/test/CodeGen/SPARC/basictest.ll
index 3792100b2e63..889f5144413f 100644
--- a/test/CodeGen/SPARC/basictest.ll
+++ b/test/CodeGen/SPARC/basictest.ll
@@ -71,12 +71,12 @@ define i64 @signed_multiply_32x32_64(i32 %a, i32 %b) {
}
; CHECK-LABEL: unsigned_multiply_32x32_64:
-; CHECK: umul %o0, %o1, %o2
-; CHECK: rd %y, %o2
;FIXME: the smul in the output is totally redundant and should not there.
-; CHECK: smul %o0, %o1, %o1
+; CHECK: smul %o0, %o1, %o2
+; CHECK: umul %o0, %o1, %o0
+; CHECK: rd %y, %o0
; CHECK: retl
-; CHECK: mov %o2, %o0
+; CHECK: mov %o2, %o1
define i64 @unsigned_multiply_32x32_64(i32 %a, i32 %b) {
%xa = zext i32 %a to i64
%xb = zext i32 %b to i64
@@ -84,3 +84,16 @@ define i64 @unsigned_multiply_32x32_64(i32 %a, i32 %b) {
ret i64 %r
}
+; CHECK-LABEL: load_store_64bit:
+; CHECK: ldd [%o0], %o2
+; CHECK: addcc %o3, 3, %o5
+; CHECK: addxcc %o2, 0, %o4
+; CHECK: retl
+; CHECK: std %o4, [%o1]
+define void @load_store_64bit(i64* %x, i64* %y) {
+entry:
+ %0 = load i64, i64* %x
+ %add = add nsw i64 %0, 3
+ store i64 %add, i64* %y
+ ret void
+}
diff --git a/test/CodeGen/SPARC/float-constants.ll b/test/CodeGen/SPARC/float-constants.ll
new file mode 100644
index 000000000000..b3686ebdf440
--- /dev/null
+++ b/test/CodeGen/SPARC/float-constants.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=sparc | FileCheck %s
+
+; TODO: actually fix the codegen to be optimal. At least we don't
+; crash for now, though...
+
+;; Bitcast should not do a runtime conversion, but rather emit a
+;; constant into integer registers directly.
+
+; CHECK-LABEL: bitcast:
+; TODO-CHECK: sethi 1049856, %o0
+; TODO-CHECK: sethi 0, %o1
+define <2 x i32> @bitcast() {
+ %1 = bitcast double 5.0 to <2 x i32>
+ ret <2 x i32> %1
+}
+
+;; Same thing for a call using a double (which gets passed in integer
+;; registers)
+
+; CHECK-LABEL: test_call
+; TODO-CHECK: sethi 1049856, %o0
+; TODO-CHECK: sethi 0, %o1
+declare void @a(double)
+define void @test_call() {
+ call void @a(double 5.0)
+ ret void
+}
+
+;; And for a libcall emitted from the pow intrinsic. (libcall
+;; emission happens after SelectionDAG type legalization, so is a bit
+;; different than a normal function call. This was crashing before,
+;; due to an earlier broken workaround for this issue.)
+
+; CHECK-LABEL: test_intrins_call
+; TODO-CHECK: sethi 1049856, %o0
+; TODO-CHECK: sethi 0, %o1
+declare double @llvm.pow.f64(double, double)
+define double @test_intrins_call() {
+ %1 = call double @llvm.pow.f64(double 2.0, double 2.0)
+ ret double %1
+}
diff --git a/test/CodeGen/SPARC/float.ll b/test/CodeGen/SPARC/float.ll
index d7a79cb05a82..c4cc04420ad7 100644
--- a/test/CodeGen/SPARC/float.ll
+++ b/test/CodeGen/SPARC/float.ll
@@ -53,20 +53,18 @@ declare double @get_double()
declare double @llvm.fabs.f64(double) nounwind readonly
; V8-LABEL: test_v9_floatreg:
-; V8: fsubd {{.+}}, {{.+}}, {{.+}}
-; V8: faddd {{.+}}, {{.+}}, [[R:%f(((1|2)?(0|2|4|6|8))|30)]]
+; V8: fsubd {{.+}}, {{.+}}, [[R:%f(((1|2)?(0|2|4|6|8))|30)]]
; V8: std [[R]], [%{{.+}}]
; V8: ldd [%{{.+}}], %f0
+; V8: faddd {{.+}}, {{.+}}, {{.+}}
; V9-LABEL: test_v9_floatreg:
; V9: fsubd {{.+}}, {{.+}}, {{.+}}
-; V9: faddd {{.+}}, {{.+}}, [[R:%f((3(2|4|6|8))|((4|5)(0|2|4|6|8))|(60|62))]]
-; V9: fmovd [[R]], %f0
+; V9: faddd {{.+}}, {{.+}}, %f0
; SPARC64-LABEL: test_v9_floatreg:
; SPARC64: fsubd {{.+}}, {{.+}}, {{.+}}
-; SPARC64: faddd {{.+}}, {{.+}}, [[R:%f((3(2|4|6|8))|((4|5)(0|2|4|6|8))|(60|62))]]
-; SPARC64: fmovd [[R]], %f0
+; SPARC64: faddd {{.+}}, {{.+}}, %f0
define double @test_v9_floatreg() {
entry:
diff --git a/test/CodeGen/SPARC/fp128.ll b/test/CodeGen/SPARC/fp128.ll
index c864cb7d599b..e0eaf93a733e 100644
--- a/test/CodeGen/SPARC/fp128.ll
+++ b/test/CodeGen/SPARC/fp128.ll
@@ -45,14 +45,14 @@ entry:
; HARD: std %f{{.+}}, [%[[S1:.+]]]
; HARD-DAG: ldd [%[[S0]]], %f{{.+}}
; HARD-DAG: ldd [%[[S1]]], %f{{.+}}
-; HARD: jmp %o7+12
+; HARD: jmp {{%[oi]7}}+12
; SOFT-LABEL: f128_spill
; SOFT: std %f{{.+}}, [%[[S0:.+]]]
; SOFT: std %f{{.+}}, [%[[S1:.+]]]
; SOFT-DAG: ldd [%[[S0]]], %f{{.+}}
; SOFT-DAG: ldd [%[[S1]]], %f{{.+}}
-; SOFT: jmp %o7+12
+; SOFT: jmp {{%[oi]7}}+12
define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) {
entry:
diff --git a/test/CodeGen/SPARC/inlineasm.ll b/test/CodeGen/SPARC/inlineasm.ll
index 526cde8de8b4..d54c5c6bc780 100644
--- a/test/CodeGen/SPARC/inlineasm.ll
+++ b/test/CodeGen/SPARC/inlineasm.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=sparc -no-integrated-as <%s | FileCheck %s
+; RUN: llc -march=sparc <%s | FileCheck %s
; CHECK-LABEL: test_constraint_r
; CHECK: add %o1, %o0, %o0
@@ -8,7 +8,7 @@ entry:
ret i32 %0
}
-; CHECK-LABEL: test_constraint_I
+; CHECK-LABEL: test_constraint_I:
; CHECK: add %o0, 1023, %o0
define i32 @test_constraint_I(i32 %a) {
entry:
@@ -16,7 +16,7 @@ entry:
ret i32 %0
}
-; CHECK-LABEL: test_constraint_I_neg
+; CHECK-LABEL: test_constraint_I_neg:
; CHECK: add %o0, -4096, %o0
define i32 @test_constraint_I_neg(i32 %a) {
entry:
@@ -24,7 +24,7 @@ entry:
ret i32 %0
}
-; CHECK-LABEL: test_constraint_I_largeimm
+; CHECK-LABEL: test_constraint_I_largeimm:
; CHECK: sethi 9, [[R0:%[gilo][0-7]]]
; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]]
; CHECK: add %o0, [[R1]], %o0
@@ -34,12 +34,51 @@ entry:
ret i32 %0
}
-; CHECK-LABEL: test_constraint_reg
+; CHECK-LABEL: test_constraint_reg:
; CHECK: ldda [%o1] 43, %g2
-; CHECK: ldda [%o1] 43, %g3
+; CHECK: ldda [%o1] 43, %g4
define void @test_constraint_reg(i32 %s, i32* %ptr) {
entry:
%0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
- %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g3},r,n"(i32* %ptr, i32 43)
+ %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g4},r,n"(i32* %ptr, i32 43)
ret void
}
+
+;; Ensure that i64 args to asm are allocated to the IntPair register class.
+;; Also checks that register renaming for leaf proc works.
+; CHECK-LABEL: test_constraint_r_i64:
+; CHECK: mov %o0, %o5
+; CHECK: sra %o5, 31, %o4
+; CHECK: std %o4, [%o1]
+define i32 @test_constraint_r_i64(i32 %foo, i64* %out, i32 %o) {
+entry:
+ %conv = sext i32 %foo to i64
+ tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
+ ret i32 %o
+}
+
+;; Same test without leaf-proc opt
+; CHECK-LABEL: test_constraint_r_i64_noleaf:
+; CHECK: mov %i0, %i5
+; CHECK: sra %i5, 31, %i4
+; CHECK: std %i4, [%i1]
+define i32 @test_constraint_r_i64_noleaf(i32 %foo, i64* %out, i32 %o) #0 {
+entry:
+ %conv = sext i32 %foo to i64
+ tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
+ ret i32 %o
+}
+attributes #0 = { "no-frame-pointer-elim"="true" }
+
+;; Ensures that tied in and out gets allocated properly.
+; CHECK-LABEL: test_i64_inout:
+; CHECK: sethi 0, %o2
+; CHECK: mov 5, %o3
+; CHECK: xor %o2, %g0, %o2
+; CHECK: mov %o2, %o0
+; CHECK: ret
+define i64 @test_i64_inout() {
+entry:
+ %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);
+ ret i64 %0
+}
diff --git a/test/CodeGen/SPARC/missing-sret.ll b/test/CodeGen/SPARC/missing-sret.ll
new file mode 100644
index 000000000000..683d840bd250
--- /dev/null
+++ b/test/CodeGen/SPARC/missing-sret.ll
@@ -0,0 +1,9 @@
+; RUN: llc -march=sparc -filetype=obj < %s > /dev/null 2> %t2
+
+define void @mul_double_cc({ double, double }* noalias sret %agg.result, double %a, double %b, double %c, double %d) {
+entry:
+ call void @__muldc3({ double, double }* sret %agg.result, double %a, double %b, double %c, double %d)
+ ret void
+}
+
+declare void @__muldc3({ double, double }*, double, double, double, double)
diff --git a/test/CodeGen/SPARC/reserved-regs.ll b/test/CodeGen/SPARC/reserved-regs.ll
new file mode 100644
index 000000000000..fe208015827b
--- /dev/null
+++ b/test/CodeGen/SPARC/reserved-regs.ll
@@ -0,0 +1,135 @@
+; RUN: llc -march=sparc < %s | FileCheck %s
+
+@g = common global [32 x i32] zeroinitializer, align 16
+@h = common global [16 x i64] zeroinitializer, align 16
+
+;; Ensures that we don't use registers which are supposed to be reserved.
+
+; CHECK-LABEL: use_all_i32_regs:
+; CHECK-NOT: %g0
+; CHECK-NOT: %g1
+; CHECK-NOT: %g5
+; CHECK-NOT: %g6
+; CHECK-NOT: %g7
+; CHECK-NOT: %o6
+; CHECK-NOT: %i6
+; CHECK-NOT: %i7
+; CHECK: ret
+define void @use_all_i32_regs() {
+entry:
+ %0 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 0), align 16
+ %1 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 1), align 4
+ %2 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 2), align 8
+ %3 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 3), align 4
+ %4 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 4), align 16
+ %5 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 5), align 4
+ %6 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 6), align 8
+ %7 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 7), align 4
+ %8 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 8), align 16
+ %9 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 9), align 4
+ %10 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 10), align 8
+ %11 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 11), align 4
+ %12 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 12), align 16
+ %13 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 13), align 4
+ %14 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 14), align 8
+ %15 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 15), align 4
+ %16 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 16), align 16
+ %17 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 17), align 4
+ %18 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 18), align 8
+ %19 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 19), align 4
+ %20 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 20), align 16
+ %21 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 21), align 4
+ %22 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 22), align 8
+ %23 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 23), align 4
+ %24 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 24), align 16
+ %25 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 25), align 4
+ %26 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 26), align 8
+ %27 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 27), align 4
+ %28 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 28), align 16
+ %29 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 29), align 4
+ %30 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 30), align 8
+ %31 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 31), align 4
+ store volatile i32 %1, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 0), align 16
+ store volatile i32 %2, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 1), align 4
+ store volatile i32 %3, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 2), align 8
+ store volatile i32 %4, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 3), align 4
+ store volatile i32 %5, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 4), align 16
+ store volatile i32 %6, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 5), align 4
+ store volatile i32 %7, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 6), align 8
+ store volatile i32 %8, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 7), align 4
+ store volatile i32 %9, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 8), align 16
+ store volatile i32 %10, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 9), align 4
+ store volatile i32 %11, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 10), align 8
+ store volatile i32 %12, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 11), align 4
+ store volatile i32 %13, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 12), align 16
+ store volatile i32 %14, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 13), align 4
+ store volatile i32 %15, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 14), align 8
+ store volatile i32 %16, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 15), align 4
+ store volatile i32 %17, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 16), align 16
+ store volatile i32 %18, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 17), align 4
+ store volatile i32 %19, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 18), align 8
+ store volatile i32 %20, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 19), align 4
+ store volatile i32 %21, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 20), align 16
+ store volatile i32 %22, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 21), align 4
+ store volatile i32 %23, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 22), align 8
+ store volatile i32 %24, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 23), align 4
+ store volatile i32 %25, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 24), align 16
+ store volatile i32 %26, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 25), align 4
+ store volatile i32 %27, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 26), align 8
+ store volatile i32 %28, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 27), align 4
+ store volatile i32 %29, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 28), align 16
+ store volatile i32 %30, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 29), align 4
+ store volatile i32 %31, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 30), align 8
+ store volatile i32 %0, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 31), align 4
+ ret void
+}
+
+
+; CHECK-LABEL: use_all_i64_regs:
+; CHECK-NOT: %g0
+; CHECK-NOT: %g1
+; CHECK-NOT: %g4
+; CHECK-NOT: %g5
+; CHECK-NOT: %g6
+; CHECK-NOT: %g7
+; CHECK-NOT: %o6
+; CHECK-NOT: %o7
+; CHECK-NOT: %i6
+; CHECK-NOT: %i7
+; CHECK: ret
+define void @use_all_i64_regs() {
+entry:
+ %0 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 0), align 16
+ %1 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 1), align 4
+ %2 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 2), align 8
+ %3 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 3), align 4
+ %4 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 4), align 16
+ %5 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 5), align 4
+ %6 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 6), align 8
+ %7 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 7), align 4
+ %8 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 8), align 16
+ %9 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 9), align 4
+ %10 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 10), align 8
+ %11 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 11), align 4
+ %12 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 12), align 16
+ %13 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 13), align 4
+ %14 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 14), align 8
+ %15 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 15), align 4
+ store volatile i64 %1, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 0), align 16
+ store volatile i64 %2, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 1), align 4
+ store volatile i64 %3, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 2), align 8
+ store volatile i64 %4, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 3), align 4
+ store volatile i64 %5, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 4), align 16
+ store volatile i64 %6, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 5), align 4
+ store volatile i64 %7, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 6), align 8
+ store volatile i64 %8, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 7), align 4
+ store volatile i64 %9, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 8), align 16
+ store volatile i64 %10, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 9), align 4
+ store volatile i64 %11, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 10), align 8
+ store volatile i64 %12, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 11), align 4
+ store volatile i64 %13, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 12), align 16
+ store volatile i64 %14, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 13), align 4
+ store volatile i64 %15, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 14), align 8
+ store volatile i64 %0, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 15), align 4
+ ret void
+}
diff --git a/test/CodeGen/SPARC/select-mask.ll b/test/CodeGen/SPARC/select-mask.ll
new file mode 100644
index 000000000000..2e69a3b9be53
--- /dev/null
+++ b/test/CodeGen/SPARC/select-mask.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=sparc < %s
+
+;; getBooleanContents on Sparc used to claim that no bits mattered
+;; other than the first for SELECT. Thus, the 'trunc' got eliminated
+;; as redundant. But, cmp does NOT ignore the other bits!
+
+; CHECK-LABEL: select_mask:
+; CHECK: ldub [%o0], [[R:%[goli][0-7]]]
+; CHECK: and [[R]], 1, [[V:%[goli][0-7]]]
+; CHECK: cmp [[V]], 0
+define i32 @select_mask(i8* %this) {
+entry:
+ %bf.load2 = load i8, i8* %this, align 4
+ %bf.cast5 = trunc i8 %bf.load2 to i1
+ %cond = select i1 %bf.cast5, i32 2, i32 0
+ ret i32 %cond
+}
diff --git a/test/CodeGen/SPARC/spill.ll b/test/CodeGen/SPARC/spill.ll
new file mode 100644
index 000000000000..a461de9640bd
--- /dev/null
+++ b/test/CodeGen/SPARC/spill.ll
@@ -0,0 +1,64 @@
+; RUN: llc -march=sparc < %s | FileCheck %s
+
+;; Ensure that spills and reloads work for various types on
+;; sparcv8.
+
+;; For i32/i64 tests, use an asm statement which clobbers most
+;; registers to ensure the spill will happen.
+
+; CHECK-LABEL: test_i32_spill:
+; CHECK: and %i0, %i1, %o0
+; CHECK: st %o0, [%fp+{{.+}}]
+; CHECK: add %o0, %o0, %g0
+; CHECK: ld [%fp+{{.+}}, %i0
+define i32 @test_i32_spill(i32 %a, i32 %b) {
+entry:
+ %r0 = and i32 %a, %b
+ ; The clobber list has all registers except g0/o0. (Only o0 is usable.)
+ %0 = call i32 asm sideeffect "add $0,$1,%g0", "=r,0,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6},~{o7}"(i32 %r0)
+ ret i32 %r0
+}
+
+; CHECK-LABEL: test_i64_spill:
+; CHECK: and %i0, %i2, %o0
+; CHECK: and %i1, %i3, %o1
+; CHECK: std %o0, [%fp+{{.+}}]
+; CHECK: add %o0, %o0, %g0
+; CHECK: ldd [%fp+{{.+}}, %i0
+define i64 @test_i64_spill(i64 %a, i64 %b) {
+entry:
+ %r0 = and i64 %a, %b
+ ; The clobber list has all registers except g0,g1,o0,o1. (Only o0/o1 are a usable pair)
+ ; So, o0/o1 must be used.
+ %0 = call i64 asm sideeffect "add $0,$1,%g0", "=r,0,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o2},~{o3},~{o4},~{o5},~{o7}"(i64 %r0)
+ ret i64 %r0
+}
+
+;; For float/double tests, a call is a suitable clobber as *all* FPU
+;; registers are caller-save on sparcv8.
+
+; CHECK-LABEL: test_float_spill:
+; CHECK: fadds %f1, %f0, [[R:%[f][0-31]]]
+; CHECK: st [[R]], [%fp+{{.+}}]
+; CHECK: call
+; CHECK: ld [%fp+{{.+}}, %f0
+declare float @foo_float(float)
+define float @test_float_spill(float %a, float %b) {
+entry:
+ %r0 = fadd float %a, %b
+ %0 = call float @foo_float(float %r0)
+ ret float %r0
+}
+
+; CHECK-LABEL: test_double_spill:
+; CHECK: faddd %f2, %f0, [[R:%[f][0-31]]]
+; CHECK: std [[R]], [%fp+{{.+}}]
+; CHECK: call
+; CHECK: ldd [%fp+{{.+}}, %f0
+declare double @foo_double(double)
+define double @test_double_spill(double %a, double %b) {
+entry:
+ %r0 = fadd double %a, %b
+ %0 = call double @foo_double(double %r0)
+ ret double %r0
+}
diff --git a/test/CodeGen/SPARC/stack-align.ll b/test/CodeGen/SPARC/stack-align.ll
new file mode 100644
index 000000000000..2554ee821fcd
--- /dev/null
+++ b/test/CodeGen/SPARC/stack-align.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=sparc < %s | FileCheck %s
+declare void @stack_realign_helper(i32 %a, i32* %b)
+
+@foo = global i32 1
+
+;; This is a function where we have a local variable of 64-byte
+;; alignment. We want to see that the stack is aligned (the initial
+;; andn), that the local var is accessed via stack pointer (to %o0), and that
+;; the argument is accessed via frame pointer not stack pointer (to %o1).
+
+;; CHECK-LABEL: stack_realign:
+;; CHECK: andn %sp, 63, %sp
+;; CHECK-NEXT: ld [%fp+92], %o0
+;; CHECK-NEXT: call stack_realign_helper
+;; CHECK-NEXT: add %sp, 128, %o1
+
+define void @stack_realign(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
+entry:
+ %aligned = alloca i32, align 64
+ call void @stack_realign_helper(i32 %g, i32* %aligned)
+ ret void
+}
diff --git a/test/CodeGen/SPARC/tls.ll b/test/CodeGen/SPARC/tls.ll
index a70637b283f5..8ebd36833ba1 100644
--- a/test/CodeGen/SPARC/tls.ll
+++ b/test/CodeGen/SPARC/tls.ll
@@ -103,10 +103,10 @@ entry:
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0x4
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0x8
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_HIX22 local_symbol 0x0
-; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_LOX10 local_symbol 0x0
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_HI22 local_symbol 0x0
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_LO10 local_symbol 0x0
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_ADD local_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_LOX10 local_symbol 0x0
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_CALL local_symbol 0x0
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_ADD local_symbol 0x0
; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0x4
diff --git a/test/CodeGen/SPARC/varargs.ll b/test/CodeGen/SPARC/varargs.ll
index c2d1e98b698b..576acc284fb9 100644
--- a/test/CodeGen/SPARC/varargs.ll
+++ b/test/CodeGen/SPARC/varargs.ll
@@ -67,8 +67,8 @@ declare void @llvm.va_start(i8*)
; CHECK: call_1d
; The fixed-arg double goes in %d2, the second goes in %o2.
; CHECK: sethi 1048576
-; CHECK: , %o2
; CHECK: , %f2
+; CHECK: , %o2
define i32 @call_1d() #0 {
entry:
%call = call double (i8*, double, ...) @varargsfunc(i8* undef, double 1.000000e+00, double 2.000000e+00)
generated by cgit v1.3 (git 2.53.0) at 2026-07-29 11:31:40 +0000