diff options
Diffstat (limited to 'test/CodeGen/Thumb2')
26 files changed, 376 insertions, 123 deletions
diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll index f26c6d114b8e..550b3efae998 100644 --- a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll +++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll @@ -5,8 +5,13 @@ define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { entry: ; CHECK: __gcov_execlp: -; CHECK: mov sp, r7 -; CHECK: sub sp, #4 +; CHECK: sub sp, #8 +; CHECK: push +; CHECK: add r7, sp, #4 +; CHECK: subs r4, r7, #4 +; CHECK: mov sp, r4 +; CHECK-NOT: mov sp, r7 +; CHECK: add sp, #8 call void @__gcov_flush() nounwind br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/Thumb2/2009-08-21-PostRAKill4.ll b/test/CodeGen/Thumb2/2009-08-21-PostRAKill4.ll new file mode 100644 index 000000000000..5cfc68d09408 --- /dev/null +++ b/test/CodeGen/Thumb2/2009-08-21-PostRAKill4.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler + +; ModuleID = '<stdin>' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" +target triple = "armv7-apple-darwin9" + +@.str = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=0] +@.str1 = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1] +@.str2 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] + +declare i32 @getUnknown(i32, ...) nounwind + +declare void @llvm.va_start(i8*) nounwind + +declare void @llvm.va_end(i8*) nounwind + +declare i32 @printf(i8* nocapture, ...) nounwind + +define i32 @main() nounwind { +entry: + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0] + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0] + %2 = tail call i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1] + %3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0] + ret i32 0 +} diff --git a/test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll b/test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll new file mode 100644 index 000000000000..06a152d56e4d --- /dev/null +++ b/test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll @@ -0,0 +1,106 @@ +; RUN: llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" +target triple = "thumbv7-apple-darwin9" + +@history = internal global [2 x [56 x i32]] [[56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0], [56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0]] ; <[2 x [56 x i32]]*> [#uses=3] +@nodes = internal global i64 0 ; <i64*> [#uses=4] +@.str = private constant [9 x i8] c"##-<=>+#\00", align 1 ; <[9 x i8]*> [#uses=2] +@.str1 = private constant [6 x i8] c"%c%d\0A\00", align 1 ; <[6 x i8]*> [#uses=1] +@.str2 = private constant [16 x i8] c"Fhourstones 2.0\00", align 1 ; <[16 x i8]*> [#uses=1] +@.str3 = private constant [54 x i8] c"Using %d transposition table entries with %d probes.\0A\00", align 1 ; <[54 x i8]*> [#uses=1] +@.str4 = private constant [31 x i8] c"Solving %d-ply position after \00", align 1 ; <[31 x i8]*> [#uses=1] +@.str5 = private constant [7 x i8] c" . . .\00", align 1 ; <[7 x i8]*> [#uses=1] +@.str6 = private constant [28 x i8] c"score = %d (%c) work = %d\0A\00", align 1 ; <[28 x i8]*> [#uses=1] +@.str7 = private constant [36 x i8] c"%lu pos / %lu msec = %.1f Kpos/sec\0A\00", align 1 ; <[36 x i8]*> [#uses=1] +@plycnt = internal global i32 0 ; <i32*> [#uses=21] +@dias = internal global [19 x i32] zeroinitializer ; <[19 x i32]*> [#uses=43] +@columns = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=18] +@height = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=21] +@rows = internal global [8 x i32] zeroinitializer ; <[8 x i32]*> [#uses=20] +@colthr = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=5] +@moves = internal global [44 x i32] zeroinitializer ; <[44 x i32]*> [#uses=9] +@.str8 = private constant [3 x i8] c"%d\00", align 1 ; <[3 x i8]*> [#uses=1] +@he = internal global i8* null ; <i8**> [#uses=9] +@hits = internal global i64 0 ; <i64*> [#uses=8] +@posed = internal global i64 0 ; <i64*> [#uses=7] +@ht = internal global i32* null ; <i32**> [#uses=5] +@.str16 = private constant [19 x i8] c"store rate = %.3f\0A\00", align 1 ; <[19 x i8]*> [#uses=1] +@.str117 = private constant [45 x i8] c"- %5.3f < %5.3f = %5.3f > %5.3f + %5.3f\0A\00", align 1 ; <[45 x i8]*> [#uses=1] +@.str218 = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1] +@.str319 = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1] + +declare i32 @puts(i8* nocapture) nounwind + +declare i32 @getchar() nounwind + +define internal i32 @transpose() nounwind readonly { +; CHECK: push +entry: + %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; <i32> [#uses=1] + %1 = shl i32 %0, 7 ; <i32> [#uses=1] + %2 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 2), align 4 ; <i32> [#uses=1] + %3 = or i32 %1, %2 ; <i32> [#uses=1] + %4 = shl i32 %3, 7 ; <i32> [#uses=1] + %5 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 3), align 4 ; <i32> [#uses=1] + %6 = or i32 %4, %5 ; <i32> [#uses=3] + %7 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 7), align 4 ; <i32> [#uses=1] + %8 = shl i32 %7, 7 ; <i32> [#uses=1] + %9 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 6), align 4 ; <i32> [#uses=1] + %10 = or i32 %8, %9 ; <i32> [#uses=1] + %11 = shl i32 %10, 7 ; <i32> [#uses=1] + %12 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 5), align 4 ; <i32> [#uses=1] + %13 = or i32 %11, %12 ; <i32> [#uses=3] + %14 = icmp ugt i32 %6, %13 ; <i1> [#uses=2] + %.pn2.in.i = select i1 %14, i32 %6, i32 %13 ; <i32> [#uses=1] + %.pn1.in.i = select i1 %14, i32 %13, i32 %6 ; <i32> [#uses=1] + %.pn2.i = shl i32 %.pn2.in.i, 7 ; <i32> [#uses=1] + %.pn3.i = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 4) ; <i32> [#uses=1] + %.pn.in.in.i = or i32 %.pn2.i, %.pn3.i ; <i32> [#uses=1] + %.pn.in.i = zext i32 %.pn.in.in.i to i64 ; <i64> [#uses=1] + %.pn.i = shl i64 %.pn.in.i, 21 ; <i64> [#uses=1] + %.pn1.i = zext i32 %.pn1.in.i to i64 ; <i64> [#uses=1] + %iftmp.22.0.i = or i64 %.pn.i, %.pn1.i ; <i64> [#uses=2] + %15 = lshr i64 %iftmp.22.0.i, 17 ; <i64> [#uses=1] + %16 = trunc i64 %15 to i32 ; <i32> [#uses=2] + %17 = urem i64 %iftmp.22.0.i, 1050011 ; <i64> [#uses=1] + %18 = trunc i64 %17 to i32 ; <i32> [#uses=1] + %19 = urem i32 %16, 179 ; <i32> [#uses=1] + %20 = or i32 %19, 131072 ; <i32> [#uses=1] + %21 = load i32** @ht, align 4 ; <i32*> [#uses=1] + br label %bb5 + +bb: ; preds = %bb5 + %22 = getelementptr inbounds i32* %21, i32 %x.0 ; <i32*> [#uses=1] + %23 = load i32* %22, align 4 ; <i32> [#uses=1] + %24 = icmp eq i32 %23, %16 ; <i1> [#uses=1] + br i1 %24, label %bb1, label %bb2 + +bb1: ; preds = %bb + %25 = load i8** @he, align 4 ; <i8*> [#uses=1] + %26 = getelementptr inbounds i8* %25, i32 %x.0 ; <i8*> [#uses=1] + %27 = load i8* %26, align 1 ; <i8> [#uses=1] + %28 = sext i8 %27 to i32 ; <i32> [#uses=1] + ret i32 %28 + +bb2: ; preds = %bb + %29 = add nsw i32 %20, %x.0 ; <i32> [#uses=3] + %30 = add i32 %29, -1050011 ; <i32> [#uses=1] + %31 = icmp sgt i32 %29, 1050010 ; <i1> [#uses=1] + %. = select i1 %31, i32 %30, i32 %29 ; <i32> [#uses=1] + %32 = add i32 %33, 1 ; <i32> [#uses=1] + br label %bb5 + +bb5: ; preds = %bb2, %entry + %33 = phi i32 [ 0, %entry ], [ %32, %bb2 ] ; <i32> [#uses=2] + %x.0 = phi i32 [ %18, %entry ], [ %., %bb2 ] ; <i32> [#uses=3] + %34 = icmp sgt i32 %33, 7 ; <i1> [#uses=1] + br i1 %34, label %bb7, label %bb + +bb7: ; preds = %bb5 + ret i32 -128 +} + +declare noalias i8* @calloc(i32, i32) nounwind + +declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind diff --git a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll index 7ee19863de19..458569ec93b5 100644 --- a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll +++ b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 \ +; RUN: -pre-RA-sched=source | FileCheck -check-prefix=SOURCE %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 \ +; RUN: -pre-RA-sched=list-hybrid | FileCheck -check-prefix=HYBRID %s ; Radar 7459078 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" @@ -10,9 +13,11 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- %s5 = type { i32 } ; Make sure the cmp is not scheduled before the InlineAsm that clobbers cc. -; CHECK: InlineAsm End -; CHECK: cmp -; CHECK: beq +; SOURCE: InlineAsm End +; SOURCE: cmp +; SOURCE: beq +; HYBRID: InlineAsm End +; HYBRID: cbz define void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { entry: %tmp1 = getelementptr inbounds %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0 diff --git a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll index 26750065af3f..9ed6a01255f8 100644 --- a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll +++ b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll @@ -23,8 +23,9 @@ entry: %4 = insertelement <2 x double> %2, double %V.0.ph, i32 1 ; <<2 x double>> [#uses=2] ; Constant pool load followed by add. ; Then clobber the loaded register, not the sum. -; CHECK: vldr.64 [[LDR:d.]] -; CHECK: vadd.f64 [[ADD:d.]], [[LDR]], [[LDR]] +; CHECK: vldr.64 [[LDR:d.*]], +; CHECK: LPC0_0: +; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]] ; CHECK: vmov.f64 [[LDR]] %5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2] %6 = fadd <2 x double> %4, %4 ; <<2 x double>> [#uses=2] diff --git a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll index c5fc5098cd46..f91e1c9febe2 100644 --- a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll +++ b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic | FileCheck %s ; rdar://8115404 ; Tail merging must not split an IT block. diff --git a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll index abcf13a3e38f..41f7f299555d 100644 --- a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll +++ b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll @@ -5,6 +5,10 @@ define internal fastcc i32 @Callee(i32 %i) nounwind { entry: ; CHECK: Callee: +; CHECK: push +; CHECK: mov r4, sp +; CHECK: sub.w r12, r4, #1000 +; CHECK: mov sp, r12 %0 = icmp eq i32 %i, 0 ; <i1> [#uses=1] br i1 %0, label %bb2, label %bb @@ -17,9 +21,11 @@ bb: ; preds = %entry ret i32 %4 bb2: ; preds = %entry -; Must restore sp from fp here -; CHECK: mov sp, r7 -; CHECK: sub sp, #8 +; Must restore sp from fp here. Make sure not to leave sp in a temporarily invalid +; state though. rdar://8465407 +; CHECK-NOT: mov sp, r7 +; CHECK: sub.w r4, r7, #8 +; CHECK: mov sp, r4 ; CHECK: pop ret i32 0 } diff --git a/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll b/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll new file mode 100644 index 000000000000..313728c1b56a --- /dev/null +++ b/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll @@ -0,0 +1,34 @@ +; rdar://8465407 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s + +%struct.buf = type opaque + +declare void @bar() nounwind optsize + +define void @foo() nounwind optsize { +; CHECK: foo: +; CHECK: push +; CHECK: add r7, sp, #4 +; CHECK: sub sp, #4 +entry: + %m.i = alloca %struct.buf*, align 4 + br label %bb + +bb: + br i1 undef, label %bb3, label %bb2 + +bb2: + call void @bar() nounwind optsize + br i1 undef, label %bb, label %bb3 + +bb3: + br i1 undef, label %return, label %bb + +return: +; CHECK: %return +; 'mov sp, r7' would have left sp in an invalid state +; CHECK-NOT: mov sp, r7 +; CHECK-NOT: sub, sp, #4 +; CHECK: add sp, #4 + ret void +} diff --git a/test/CodeGen/Thumb2/2010-12-03-AddSPNarrowing.ll b/test/CodeGen/Thumb2/2010-12-03-AddSPNarrowing.ll new file mode 100644 index 000000000000..5b91a5f65aee --- /dev/null +++ b/test/CodeGen/Thumb2/2010-12-03-AddSPNarrowing.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s +; Radar 8724703: Make sure that a t2ADDrSPi instruction with SP as the +; destination register is narrowed to tADDspi instead of tADDrSPi. + +define void @test() nounwind { +entry: +; CHECK: sub.w +; CHECK: add.w + %Buffer.i = alloca [512 x i8], align 4 + ret void +} diff --git a/test/CodeGen/Thumb2/bfi.ll b/test/CodeGen/Thumb2/bfi.ll index 22473bb35a0a..6fb2fc888d9f 100644 --- a/test/CodeGen/Thumb2/bfi.ll +++ b/test/CodeGen/Thumb2/bfi.ll @@ -38,3 +38,14 @@ entry: %or = or i32 %and2, %and ; <i32> [#uses=1] ret i32 %or } + +; rdar://8752056 +define i32 @f4(i32 %a) nounwind { +; CHECK: f4 +; CHECK: movw r1, #3137 +; CHECK: bfi r1, r0, #15, #5 + %1 = shl i32 %a, 15 + %ins7 = and i32 %1, 1015808 + %ins12 = or i32 %ins7, 3137 + ret i32 %ins12 +} diff --git a/test/CodeGen/Thumb2/buildvector-crash.ll b/test/CodeGen/Thumb2/buildvector-crash.ll new file mode 100644 index 000000000000..01ef472d3104 --- /dev/null +++ b/test/CodeGen/Thumb2/buildvector-crash.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -O3 -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 | FileCheck %s +; Formerly crashed, 3573915. + +define void @RotateStarsFP_Vec() nounwind { +bb.nph372: + br label %bb8 + +bb8: ; preds = %bb8, %bb.nph372 + %0 = fadd <4 x float> undef, <float 0xBFEE353F80000000, float 0xBFEE353F80000000, float 0xBFEE353F80000000, float 0xBFEE353F80000000> + %1 = fmul <4 x float> %0, undef + %2 = fmul <4 x float> %1, undef + %3 = fadd <4 x float> undef, %2 + store <4 x float> %3, <4 x float>* undef, align 4 + br label %bb8 +; CHECK: RotateStarsFP_Vec: +; CHECK: vldmia +} diff --git a/test/CodeGen/Thumb2/cortex-fp.ll b/test/CodeGen/Thumb2/cortex-fp.ll index f7ec5a3b577c..d06f8a7beeb0 100644 --- a/test/CodeGen/Thumb2/cortex-fp.ll +++ b/test/CodeGen/Thumb2/cortex-fp.ll @@ -19,6 +19,6 @@ entry: %0 = fmul double %a, %b ; CORTEXM3: blx ___muldf3 ; CORTEXM4: blx ___muldf3 -; CORTEXA8: vmul.f64 d0, d1, d0 +; CORTEXA8: vmul.f64 d16, d17, d16 ret double %0 } diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index 583f4057bcd9..b8c8cb122a19 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -1,15 +1,20 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 1 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s define void @fht(float* nocapture %fz, i16 signext %n) nounwind { +; CHECK: fht: entry: br label %bb5 bb5: ; preds = %bb5, %entry +; CHECK: %bb5 +; CHECK: bne br i1 undef, label %bb5, label %bb.nph bb.nph: ; preds = %bb5 br label %bb7 +; Loop preheader +; CHECK: vmov.f32 bb7: ; preds = %bb9, %bb.nph %s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3] %tmp79 = add i32 undef, undef ; <i32> [#uses=1] @@ -19,6 +24,9 @@ bb7: ; preds = %bb9, %bb.nph br label %bb8 bb8: ; preds = %bb8, %bb7 +; CHECK: %bb8 +; CHECK-NOT: vmov.f32 +; CHECK: blt %tmp54 = add i32 0, %tmp53 ; <i32> [#uses=0] %fi.1 = getelementptr float* %fz, i32 undef ; <float*> [#uses=2] %tmp80 = add i32 0, %tmp79 ; <i32> [#uses=1] diff --git a/test/CodeGen/Thumb2/div.ll b/test/CodeGen/Thumb2/div.ll index e63a115273ff..2c00c70c0db6 100644 --- a/test/CodeGen/Thumb2/div.ll +++ b/test/CodeGen/Thumb2/div.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 \ +; RUN: llc < %s -mtriple=thumb-apple-darwin -mattr=+thumb2 \ ; RUN: | FileCheck %s -check-prefix=CHECK-THUMB ; RUN: llc < %s -march=thumb -mcpu=cortex-m3 -mattr=+thumb2 \ ; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll index 97295341858c..68b5d1cc94fb 100644 --- a/test/CodeGen/Thumb2/large-stack.ll +++ b/test/CodeGen/Thumb2/large-stack.ll @@ -27,7 +27,7 @@ define i32 @test3() { ; DARWIN: sub.w sp, sp, #805306368 ; DARWIN: sub sp, #20 ; LINUX: test3: -; LINUX: stmdb sp!, {r4, r7, r11, lr} +; LINUX: push.w {r4, r7, r11, lr} ; LINUX: sub.w sp, sp, #805306368 ; LINUX: sub sp, #16 %retval = alloca i32, align 4 diff --git a/test/CodeGen/Thumb2/load-global.ll b/test/CodeGen/Thumb2/load-global.ll deleted file mode 100644 index 46e053ca4ea5..000000000000 --- a/test/CodeGen/Thumb2/load-global.ll +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC -; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX - -@G = external global i32 - -define i32 @test1() { -; STATIC: _test1: -; STATIC: .long _G - -; DYNAMIC: _test1: -; DYNAMIC: .long L_G$non_lazy_ptr - -; PIC: _test1 -; PIC: add r0, pc -; PIC: .long L_G$non_lazy_ptr-(LPC0_0+4) - -; LINUX: test1 -; LINUX: .long G(GOT) - %tmp = load i32* @G - ret i32 %tmp -} diff --git a/test/CodeGen/Thumb2/machine-licm-vdup.ll b/test/CodeGen/Thumb2/machine-licm-vdup.ll deleted file mode 100644 index fde2ee0ab0c9..000000000000 --- a/test/CodeGen/Thumb2/machine-licm-vdup.ll +++ /dev/null @@ -1,38 +0,0 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim -arm-vdup-splat | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -arm-vdup-splat | FileCheck %s -; Modified version of machine-licm.ll with -arm-vdup-splat turned on, 8003375. -; Eventually this should become the default and be moved into machine-licm.ll. -; FIXME: the vdup should be hoisted out of the loop, 8248029. - -define void @t2(i8* %ptr1, i8* %ptr2) nounwind { -entry: -; CHECK: t2: -; CHECK: mov.w r3, #1065353216 - br i1 undef, label %bb1, label %bb2 - -bb1: -; CHECK-NEXT: %bb1 -; CHECK: vdup.32 q1, r3 - %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ] - %tmp1 = shl i32 %indvar, 2 - %gep1 = getelementptr i8* %ptr1, i32 %tmp1 - %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1) - %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2) - %gep2 = getelementptr i8* %ptr2, i32 %tmp1 - call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1) - %indvar.next = add i32 %indvar, 1 - %cond = icmp eq i32 %indvar.next, 10 - br i1 %cond, label %bb2, label %bb1 - -bb2: - ret void -} - -; CHECK-NOT: LCPI1_0: -; CHECK: .subsections_via_symbols - -declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly - -declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind - -declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index b949b2f30506..5e776dd8937c 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -3,9 +3,6 @@ ; rdar://7353541 ; rdar://7354376 -; The generated code is no where near ideal. It's not recognizing the two -; constantpool entries being loaded can be merged into one. - @GV = external global i32 ; <i32*> [#uses=2] define void @t1(i32* nocapture %vals, i32 %c) nounwind { @@ -17,21 +14,21 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 -; CHECK: ldr.n r2, LCPI0_0 +; CHECK: movw r2, :lower16:L_GV$non_lazy_ptr +; CHECK: movt r2, :upper16:L_GV$non_lazy_ptr ; CHECK: ldr r2, [r2] ; CHECK: ldr r3, [r2] ; CHECK: LBB0_2 -; CHECK: LCPI0_0: -; CHECK-NOT: LCPI0_1: +; CHECK-NOT: LCPI0_0: ; PIC: BB#1 -; PIC: ldr.n r2, LCPI0_0 +; PIC: movw r2, :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) +; PIC: movt r2, :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) ; PIC: add r2, pc ; PIC: ldr r2, [r2] ; PIC: ldr r3, [r2] ; PIC: LBB0_2 -; PIC: LCPI0_0: -; PIC-NOT: LCPI0_1: +; PIC-NOT: LCPI0_0: ; PIC: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] br label %bb @@ -55,8 +52,8 @@ return: ; preds = %bb, %entry define void @t2(i8* %ptr1, i8* %ptr2) nounwind { entry: ; CHECK: t2: -; CHECK: adr r{{.}}, #LCPI1_0 -; CHECK: vldmia r3, {d0, d1} +; CHECK: mov.w r3, #1065353216 +; CHECK: vdup.32 q{{.*}}, r3 br i1 undef, label %bb1, label %bb2 bb1: @@ -76,11 +73,50 @@ bb2: ret void } -; CHECK: LCPI1_0: -; CHECK: .section +; CHECK-NOT: LCPI1_0: declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone + +; rdar://8241368 +; isel should not fold immediate into eor's which would have prevented LICM. +define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone { +; CHECK: t3: +bb.nph: +; CHECK: bb.nph +; CHECK: movw {{(r[0-9])|(lr)}}, #32768 +; CHECK: movs {{(r[0-9])|(lr)}}, #8 +; CHECK: movw [[REGISTER:(r[0-9])|(lr)]], #16386 +; CHECK: movw {{(r[0-9])|(lr)}}, #65534 +; CHECK: movt {{(r[0-9])|(lr)}}, #65535 + br label %bb + +bb: ; preds = %bb, %bb.nph +; CHECK: bb +; CHECK: eor.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]] +; CHECK: eor.w +; CHECK-NOT: eor +; CHECK: and + %data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; <i8> [#uses=2] + %crc_addr.112 = phi i16 [ %crc, %bb.nph ], [ %crc_addr.2, %bb ] ; <i16> [#uses=3] + %i.011 = phi i8 [ 0, %bb.nph ], [ %7, %bb ] ; <i8> [#uses=1] + %0 = trunc i16 %crc_addr.112 to i8 ; <i8> [#uses=1] + %1 = xor i8 %data_addr.013, %0 ; <i8> [#uses=1] + %2 = and i8 %1, 1 ; <i8> [#uses=1] + %3 = icmp eq i8 %2, 0 ; <i1> [#uses=2] + %4 = xor i16 %crc_addr.112, 16386 ; <i16> [#uses=1] + %crc_addr.0 = select i1 %3, i16 %crc_addr.112, i16 %4 ; <i16> [#uses=1] + %5 = lshr i16 %crc_addr.0, 1 ; <i16> [#uses=2] + %6 = or i16 %5, -32768 ; <i16> [#uses=1] + %crc_addr.2 = select i1 %3, i16 %5, i16 %6 ; <i16> [#uses=2] + %7 = add i8 %i.011, 1 ; <i8> [#uses=2] + %8 = lshr i8 %data_addr.013, 1 ; <i8> [#uses=1] + %exitcond = icmp eq i8 %7, 8 ; <i1> [#uses=1] + br i1 %exitcond, label %bb8, label %bb + +bb8: ; preds = %bb + ret i16 %crc_addr.2 +} diff --git a/test/CodeGen/Thumb2/thumb2-badreg-operands.ll b/test/CodeGen/Thumb2/thumb2-badreg-operands.ll deleted file mode 100644 index 4df06b836fc5..000000000000 --- a/test/CodeGen/Thumb2/thumb2-badreg-operands.ll +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s - -define void @b(i32 %x) nounwind optsize { -entry: -; CHECK: b -; CHECK: mov r2, sp -; CHECK: mls r0, r0, r1, r2 -; CHECK: mov sp, r0 - %0 = mul i32 %x, 24 ; <i32> [#uses=1] - %vla = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1] - call arm_aapcscc void @a(i8* %vla) nounwind optsize - ret void -} - -declare void @a(i8*) optsize diff --git a/test/CodeGen/Thumb2/thumb2-barrier.ll b/test/CodeGen/Thumb2/thumb2-barrier.ll index a54d09e62919..93ae7c428bdf 100644 --- a/test/CodeGen/Thumb2/thumb2-barrier.ll +++ b/test/CodeGen/Thumb2/thumb2-barrier.ll @@ -1,17 +1,31 @@ ; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 ) +declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1) -define void @t1() { -; CHECK: t1: -; CHECK: dsb - call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true ) +define void @t_st() { +; CHECK: t_st: +; CHECK: dmb st + call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 true) ret void } -define void @t2() { -; CHECK: t2: -; CHECK: dmb - call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false ) +define void @t_sy() { +; CHECK: t_sy: +; CHECK: dmb sy + call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 true) + ret void +} + +define void @t_ishst() { +; CHECK: t_ishst: +; CHECK: dmb ishst + call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 false) + ret void +} + +define void @t_ish() { +; CHECK: t_ish: +; CHECK: dmb ish + call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 false) ret void } diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll index cc2ef140d113..bcf10eff729b 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll @@ -23,7 +23,6 @@ bb52: ; preds = %newFuncRoot ; CHECK: movne ; CHECK: moveq ; CHECK: pop -; CHECK-NEXT: @ BB#1: %0 = load i64* @posed, align 4 ; <i64> [#uses=3] %1 = sub i64 %0, %.reload78 ; <i64> [#uses=1] %2 = ashr i64 %1, 1 ; <i64> [#uses=3] diff --git a/test/CodeGen/Thumb2/thumb2-ldrd.ll b/test/CodeGen/Thumb2/thumb2-ldrd.ll index 22d4e88ed17d..a747d5f75697 100644 --- a/test/CodeGen/Thumb2/thumb2-ldrd.ll +++ b/test/CodeGen/Thumb2/thumb2-ldrd.ll @@ -4,7 +4,7 @@ define i64 @t(i64 %a) nounwind readonly { entry: -;CHECK: ldrd r2, [r2] +;CHECK: ldrd r2, r3, [r2] %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 %2 = mul i64 %1, %a diff --git a/test/CodeGen/Thumb2/thumb2-mov.ll b/test/CodeGen/Thumb2/thumb2-mov.ll index 1dc3614993bd..adb6dde2c788 100644 --- a/test/CodeGen/Thumb2/thumb2-mov.ll +++ b/test/CodeGen/Thumb2/thumb2-mov.ll @@ -53,7 +53,7 @@ define i32 @t2_const_var2_2_ok_1(i32 %lhs) { define i32 @t2_const_var2_2_ok_2(i32 %lhs) { ;CHECK: t2_const_var2_2_ok_2: -;CHECK: add.w r0, r0, #-1426063360 +;CHECK: add.w r0, r0, #2868903936 ;CHECK: add.w r0, r0, #47616 %ret = add i32 %lhs, 2868951552 ; 0xab00ba00 ret i32 %ret @@ -61,7 +61,7 @@ define i32 @t2_const_var2_2_ok_2(i32 %lhs) { define i32 @t2_const_var2_2_ok_3(i32 %lhs) { ;CHECK: t2_const_var2_2_ok_3: -;CHECK: add.w r0, r0, #-1426019584 +;CHECK: add.w r0, r0, #2868947712 ;CHECK: adds r0, #16 %ret = add i32 %lhs, 2868947728 ; 0xab00ab10 ret i32 %ret @@ -69,7 +69,7 @@ define i32 @t2_const_var2_2_ok_3(i32 %lhs) { define i32 @t2_const_var2_2_ok_4(i32 %lhs) { ;CHECK: t2_const_var2_2_ok_4: -;CHECK: add.w r0, r0, #-1426019584 +;CHECK: add.w r0, r0, #2868947712 ;CHECK: add.w r0, r0, #1048592 %ret = add i32 %lhs, 2869996304 ; 0xab10ab10 ret i32 %ret diff --git a/test/CodeGen/Thumb2/thumb2-mul.ll b/test/CodeGen/Thumb2/thumb2-mul.ll index b1515b514820..8d1de55b4dc6 100644 --- a/test/CodeGen/Thumb2/thumb2-mul.ll +++ b/test/CodeGen/Thumb2/thumb2-mul.ll @@ -6,3 +6,21 @@ define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp = mul i32 %a, %b ret i32 %tmp } + +%struct.CMPoint = type { %struct.Point, float, float, [5 x float] } +%struct.Point = type { float, float } + +define %struct.CMPoint* @t1(i32 %i, i32 %j, i32 %n, %struct.CMPoint* %thePoints) nounwind readnone ssp { +entry: +; CHECK: t1: +; CHECK: mla r0, r2, r0, r1 +; CHECK: add.w r0, r0, r0, lsl #3 +; CHECL: add.w r0, r3, r0, lsl #2 + %mul = mul i32 %n, %i + %add = add i32 %mul, %j + %0 = ptrtoint %struct.CMPoint* %thePoints to i32 + %mul5 = mul i32 %add, 36 + %add6 = add i32 %mul5, %0 + %1 = inttoptr i32 %add6 to %struct.CMPoint* + ret %struct.CMPoint* %1 +} diff --git a/test/CodeGen/Thumb2/thumb2-select_xform.ll b/test/CodeGen/Thumb2/thumb2-select_xform.ll index 56cb1f6fb409..ceefabbbfa21 100644 --- a/test/CodeGen/Thumb2/thumb2-select_xform.ll +++ b/test/CodeGen/Thumb2/thumb2-select_xform.ll @@ -2,8 +2,8 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK: t1 -; CHECK: sub.w r0, r1, #-2147483648 -; CHECK: subs r0, #1 +; CHECK: mvn r0, #-2147483648 +; CHECK: add r0, r1 ; CHECK: cmp r2, #10 ; CHECK: it gt ; CHECK: movgt r0, r1 diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll index 4f92c9333806..d9a0617f5a46 100644 --- a/test/CodeGen/Thumb2/thumb2-spill-q.ll +++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll @@ -15,11 +15,34 @@ define void @aaa(%quuz* %this, i8* %block) { ; CHECK: vst1.64 {{.*}}[{{.*}}, :128] ; CHECK: vld1.64 {{.*}}[{{.*}}, :128] entry: - %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] + %aligned_vec = alloca <4 x float>, align 16 + %"alloca point" = bitcast i32 0 to i32 + %vecptr = bitcast <4 x float>* %aligned_vec to i8* + %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind store float 6.300000e+01, float* undef, align 4 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] store float 0.000000e+00, float* undef, align 4 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] + %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 %val173 = load <4 x float>* undef ; <<4 x float>> [#uses=1] br label %bb4 @@ -44,7 +67,16 @@ bb4: ; preds = %bb193, %entry %18 = fmul <4 x float> %17, %val173 ; <<4 x float>> [#uses=1] %19 = shufflevector <4 x float> %18, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1] %20 = shufflevector <2 x float> %19, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] - %21 = fadd <4 x float> zeroinitializer, %20 ; <<4 x float>> [#uses=2] + %tmp1 = fadd <4 x float> %20, %ld3 + %tmp2 = fadd <4 x float> %tmp1, %ld4 + %tmp3 = fadd <4 x float> %tmp2, %ld5 + %tmp4 = fadd <4 x float> %tmp3, %ld6 + %tmp5 = fadd <4 x float> %tmp4, %ld7 + %tmp6 = fadd <4 x float> %tmp5, %ld8 + %tmp7 = fadd <4 x float> %tmp6, %ld9 + %tmp8 = fadd <4 x float> %tmp7, %ld10 + %tmp9 = fadd <4 x float> %tmp8, %ld11 + %21 = fadd <4 x float> %tmp9, %ld12 %22 = fcmp ogt <4 x float> %besterror.0.2264, %21 ; <<4 x i1>> [#uses=0] %tmp = extractelement <4 x i1> %22, i32 0 br i1 %tmp, label %bb193, label %bb186 |