1 files changed, 235 insertions, 0 deletions
diff --git a/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
index 7bcc57aef4ac..3658bc9af957 100644
--- a/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
+++ b/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
@@ -35,6 +35,25 @@
     %ret = fadd double %arg1, %arg2
     ret double %ret
   }
+  
+  define void @test_fsub_float() {
+    %ret1 = fsub float undef, undef
+    %ret2 = fsub double undef, undef
+    ret void
+  }
+
+  define void @test_fmul_float() {
+    %ret1 = fmul float undef, undef
+    %ret2 = fmul double undef, undef
+    ret void
+  }
+
+  define void @test_fdiv_float() {
+    %ret1 = fdiv float undef, undef
+    %ret2 = fdiv double undef, undef
+    ret void
+  }
+  
 
   define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
     %ret = add <4 x i32> %arg1, %arg2
@@ -135,6 +154,26 @@
     ret i1 %r
   }
 
+  define i8 @test_xor_i8() {
+    %ret = xor i8 undef, undef
+    ret i8 %ret
+  }
+
+  define i16 @test_or_i16() {
+    %ret = or i16 undef, undef
+    ret i16 %ret
+  }
+
+  define i32 @test_and_i32() {
+    %ret = and i32 undef, undef
+    ret i32 %ret
+  }
+
+  define i64 @test_and_i64() {
+    %ret = and i64 undef, undef
+    ret i64 %ret
+  }
+
 ...
 ---
 name:            test_add_i8
@@ -338,6 +377,105 @@ body:             |
 
 ...
 ---
+name:            test_fsub_float
+# CHECK-LABEL: name:  test_fsub_float
+alignment:       4
+legalized:       true
+regBankSelected: false
+# CHECK:       registers:
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 3, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 4, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 5, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 6, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 7, class: vecr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s32) = IMPLICIT_DEF
+    %2(s64) = IMPLICIT_DEF
+    %1(s32) = G_FSUB %0, %0
+    %3(s64) = G_FSUB %2, %2
+    RET 0
+
+...
+---
+name:            test_fmul_float
+# CHECK-LABEL: name:  test_fmul_float
+alignment:       4
+legalized:       true
+regBankSelected: false
+# CHECK:       registers:
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 3, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 4, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 5, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 6, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 7, class: vecr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s32) = IMPLICIT_DEF
+    %2(s64) = IMPLICIT_DEF
+    %1(s32) = G_FMUL %0, %0
+    %3(s64) = G_FMUL %2, %2
+    RET 0
+
+...
+---
+name:            test_fdiv_float
+# CHECK-LABEL: name:  test_fdiv_float
+alignment:       4
+legalized:       true
+regBankSelected: false
+# CHECK:       registers:
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 3, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 4, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 5, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 6, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 7, class: vecr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s32) = IMPLICIT_DEF
+    %2(s64) = IMPLICIT_DEF
+    %1(s32) = G_FDIV %0, %0
+    %3(s64) = G_FDIV %2, %2
+    RET 0
+
+...
+---
 name:            test_add_v4i32
 alignment:       4
 legalized:       true
@@ -850,3 +988,100 @@ body:             |
     RET 0, implicit %al
 
 ...
+---
+name:            test_xor_i8
+# CHECK-LABEL: name:  test_xor_i8
+alignment:       4
+legalized:       true
+regBankSelected: false
+# CHECK:       registers:
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s8) = IMPLICIT_DEF
+    %1(s8) = G_XOR %0, %0
+    %al = COPY %1(s8)
+    RET 0, implicit %al
+
+...
+---
+name:            test_or_i16
+# CHECK-LABEL: name:  test_or_i16
+alignment:       4
+legalized:       true
+regBankSelected: false
+# CHECK:       registers:
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s16) = IMPLICIT_DEF
+    %1(s16) = G_OR %0, %0
+    %ax = COPY %1(s16)
+    RET 0, implicit %ax
+
+...
+---
+name:            test_and_i32
+# CHECK-LABEL: name:  test_and_i32
+alignment:       4
+legalized:       true
+regBankSelected: false
+# CHECK:       registers:
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s32) = IMPLICIT_DEF
+    %1(s32) = G_AND %0, %0
+    %eax = COPY %1(s32)
+    RET 0, implicit %eax
+
+...
+---
+name:            test_and_i64
+# CHECK-LABEL: name:  test_and_i64
+alignment:       4
+legalized:       true
+regBankSelected: false
+# CHECK:       registers:
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.1 (%ir-block.0):
+    %0(s64) = IMPLICIT_DEF
+    %1(s64) = G_AND %0, %0
+    %rax = COPY %1(s64)
+    RET 0, implicit %rax
+
+...
+