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-rw-r--r--test/CodeGen/X86/i486-fence-loop.ll27
1 files changed, 27 insertions, 0 deletions
diff --git a/test/CodeGen/X86/i486-fence-loop.ll b/test/CodeGen/X86/i486-fence-loop.ll
new file mode 100644
index 000000000000..d8096197b0df
--- /dev/null
+++ b/test/CodeGen/X86/i486-fence-loop.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=x86 -mcpu=i486 -o - %s | FileCheck %s
+
+; Main test here was that ISelDAG could cope with a MachineNode in the chain
+; from the first load to the "X86ISD::SUB". Previously it thought that meant no
+; cycle could be formed so it tried to use "sub (%eax), [[RHS]]".
+
+define void @gst_atomic_queue_push(i32* %addr) {
+; CHECK-LABEL: gst_atomic_queue_push:
+; CHECK: movl (%eax), [[LHS:%e[a-z]+]]
+; CHECK: lock
+; CHECK-NEXT: orl
+; CHECK: movl (%eax), [[RHS:%e[a-z]+]]
+; CHECK: cmpl [[LHS]], [[RHS]]
+
+entry:
+ br label %while.body
+
+while.body:
+ %0 = load volatile i32* %addr, align 4
+ fence seq_cst
+ %1 = load volatile i32* %addr, align 4
+ %cmp = icmp sgt i32 %1, %0
+ br i1 %cmp, label %while.body, label %if.then
+
+if.then:
+ ret void
+} \ No newline at end of file