diff options
Diffstat (limited to 'test/CodeGen/X86/implicit-null-checks.mir')
| -rw-r--r-- | test/CodeGen/X86/implicit-null-checks.mir | 902 |
1 files changed, 884 insertions, 18 deletions
diff --git a/test/CodeGen/X86/implicit-null-checks.mir b/test/CodeGen/X86/implicit-null-checks.mir index 81351511374c..39bfedaa7814 100644 --- a/test/CodeGen/X86/implicit-null-checks.mir +++ b/test/CodeGen/X86/implicit-null-checks.mir @@ -131,6 +131,240 @@ ret i32 0 } + define i32 @use_alternate_load_op(i32* %ptr, i32* %ptr2) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret i32 undef + + is_null: + ret i32 0 + } + + define i32 @imp_null_check_gep_load_with_use_dep(i32* %x, i32 %a) { + entry: + %c = icmp eq i32* %x, null + br i1 %c, label %is_null, label %not_null, !make.implicit !0 + + is_null: ; preds = %entry + ret i32 42 + + not_null: ; preds = %entry + %x.loc = getelementptr i32, i32* %x, i32 1 + %y = ptrtoint i32* %x.loc to i32 + %b = add i32 %a, %y + %t = load i32, i32* %x + %z = add i32 %t, %b + ret i32 %z + } + + define i32 @imp_null_check_load_with_base_sep(i32* %x, i32 %a) { + entry: + %c = icmp eq i32* %x, null + br i1 %c, label %is_null, label %not_null, !make.implicit !0 + + is_null: ; preds = %entry + ret i32 42 + + not_null: ; preds = %entry + ret i32 undef + } + + define void @inc_store(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret void + + is_null: + ret void + } + + define void @inc_store_plus_offset(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret void + + is_null: + ret void + } + + define void @inc_store_with_dep(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret void + + is_null: + ret void + } + + define i32 @inc_store_with_dep_in_null(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret i32 undef + + is_null: + ret i32 undef + } + + define void @inc_store_with_volatile(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret void + + is_null: + ret void + } + + define void @inc_store_with_two_dep(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret void + + is_null: + ret void + } + + define void @inc_store_with_redefined_base(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret void + + is_null: + ret void + } + + define i32 @inc_store_with_reused_base(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret i32 undef + + is_null: + ret i32 undef + } + + define i32 @inc_store_across_call(i32* %ptr) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + call void @f() + ret i32 undef + + is_null: + ret i32 undef + } + + define i32 @inc_store_with_dep_in_dep(i32* %ptr, i32 %val) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret i32 undef + + is_null: + ret i32 undef + } + + define i32 @inc_store_with_load_over_store(i32* %ptr, i32* %ptr2) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret i32 undef + + is_null: + ret i32 undef + } + + define i32 @inc_store_with_store_over_load(i32* %ptr, i32* %ptr2) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret i32 undef + + is_null: + ret i32 undef + } + + define void @inc_store_with_store_over_store(i32* %ptr, i32* %ptr2) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret void + + is_null: + ret void + } + + define void @inc_store_with_load_and_store(i32* %ptr, i32* %ptr2) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret void + + is_null: + ret void + } + + define i32 @inc_store_and_load_no_alias(i32* noalias %ptr, i32* noalias %ptr2) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret i32 undef + + is_null: + ret i32 undef + } + + define i32 @inc_store_and_load_alias(i32* %ptr, i32* %ptr2) { + entry: + %ptr_is_null = icmp eq i32* %ptr, null + br i1 %ptr_is_null, label %is_null, label %not_null, !make.implicit !0 + + not_null: + ret i32 undef + + is_null: + ret i32 undef + } + attributes #0 = { "target-features"="+bmi,+bmi2" } !0 = !{} @@ -145,7 +379,7 @@ liveins: - { reg: '%esi' } # CHECK: bb.0.entry: # CHECK: %eax = MOV32ri 2200000 -# CHECK-NEXT: %eax = FAULTING_LOAD_OP %bb.3.is_null, {{[0-9]+}}, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) +# CHECK-NEXT: %eax = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) # CHECK-NEXT: JMP_1 %bb.1.not_null body: | @@ -167,15 +401,15 @@ body: | bb.2.ret_200: %eax = MOV32ri 200 - RET 0, %eax + RETQ %eax bb.3.is_null: %eax = MOV32ri 42 - RET 0, %eax + RETQ %eax bb.4.ret_100: %eax = MOV32ri 100 - RET 0, %eax + RETQ %eax ... --- @@ -217,11 +451,11 @@ body: | bb.3.is_null: liveins: %eax, %ah, %al, %ax, %bh, %bl, %bp, %bpl, %bx, %eax, %ebp, %ebx, %rax, %rbp, %rbx, %r12, %r13, %r14, %r15, %r12b, %r13b, %r14b, %r15b, %r12d, %r13d, %r14d, %r15d, %r12w, %r13w, %r14w, %r15w - RET 0, %eax + RETQ %eax bb.4.ret_100: %eax = MOV32ri 100 - RET 0, %eax + RETQ %eax ... --- @@ -256,15 +490,15 @@ body: | bb.2.ret_200: %eax = MOV32ri 200 - RET 0, %eax + RETQ %eax bb.3.is_null: %eax = MOV32ri 42 - RET 0, %eax + RETQ %eax bb.4.ret_100: %eax = MOV32ri 100 - RET 0, %eax + RETQ %eax ... --- @@ -298,15 +532,15 @@ body: | bb.2.ret_200: %eax = MOV32ri 200 - RET 0, %eax + RETQ %eax bb.3.is_null: %eax = MOV32ri 42 - RET 0, %eax + RETQ %eax bb.4.ret_100: %eax = MOV32ri 100 - RET 0, %eax + RETQ %eax ... --- @@ -319,7 +553,7 @@ liveins: - { reg: '%rsi' } # CHECK: bb.0.entry: # CHECK: %rbx = MOV64rr %rdx -# CHECK-NEXT: %rdi = FAULTING_LOAD_OP %bb.3.is_null, {{[0-9]+}}, killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) +# CHECK-NEXT: %rdi = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) body: | bb.0.entry: @@ -341,15 +575,15 @@ body: | bb.2.ret_200: %eax = MOV32ri 200 - RET 0, %eax + RETQ %eax bb.3.is_null: %eax = MOV32ri 42 - RET 0, %eax + RETQ %eax bb.4.ret_100: %eax = MOV32ri 100 - RET 0, %eax + RETQ %eax ... --- @@ -364,7 +598,7 @@ calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] # CHECK: body: -# CHECK-NOT: FAULTING_LOAD_OP +# CHECK-NOT: FAULTING_OP # CHECK: bb.1.stay: # CHECK: CALL64pcrel32 body: | @@ -397,7 +631,7 @@ body: | name: dependency_live_in_hazard # CHECK-LABEL: name: dependency_live_in_hazard # CHECK: bb.0.entry: -# CHECK-NOT: FAULTING_LOAD_OP +# CHECK-NOT: FAULTING_OP # CHECK: bb.1.not_null: # Make sure that the BEXTR32rm instruction below is not used to emit @@ -431,3 +665,635 @@ body: | RETQ %eax ... +--- +name: use_alternate_load_op +# CHECK-LABEL: name: use_alternate_load_op +# CHECK: bb.0.entry: +# CHECK: %rax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _ +# CHECK-NEXT: JMP_1 %bb.1.not_null +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %rcx = MOV64rm killed %rsi, 1, _, 0, _ + %rcx = AND64rm killed %rcx, %rdi, 1, _, 0, _, implicit-def dead %eflags + %rax = MOV64rm killed %rdi, 1, _, 0, _ + RETQ %eax + + bb.2.is_null: + %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags + RETQ %eax + +... +--- +name: imp_null_check_gep_load_with_use_dep +# CHECK-LABEL: name: imp_null_check_gep_load_with_use_dep +# CHECK: bb.0.entry: +# CHECK: %eax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _, implicit-def %rax :: (load 4 from %ir.x) +# CHECK-NEXT: JMP_1 %bb.1.not_null +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.1.is_null(0x30000000), %bb.2.not_null(0x50000000) + liveins: %rsi, %rdi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.1.is_null, implicit %eflags + + bb.2.not_null: + liveins: %rdi, %rsi + + %rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags + %eax = MOV32rm killed %rdi, 1, _, 0, _, implicit-def %rax :: (load 4 from %ir.x) + %eax = LEA64_32r killed %rax, 1, killed %rsi, 4, _ + RETQ %eax + + bb.1.is_null: + %eax = MOV32ri 42 + RETQ %eax + +... +--- +name: imp_null_check_load_with_base_sep +# CHECK-LABEL: name: imp_null_check_load_with_base_sep +# CHECK: bb.0.entry: +# CHECK: %rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags +# CHECK-NEXT: %esi = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, killed %esi, %rdi, 1, _, 0, _, implicit-def dead %eflags +# CHECK-NEXT: JMP_1 %bb.1.not_null +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.1.is_null(0x30000000), %bb.2.not_null(0x50000000) + liveins: %rsi, %rdi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.1.is_null, implicit %eflags + + bb.2.not_null: + liveins: %rdi, %rsi + + %rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags + %esi = AND32rm killed %esi, %rdi, 1, _, 0, _, implicit-def dead %eflags + %eax = MOV32rr %esi + RETQ %eax + + bb.1.is_null: + %eax = MOV32ri 42 + RETQ %eax + +... +--- +name: inc_store +# CHECK-LABEL: name: inc_store +# CHECK: bb.0.entry: +# CHECK: _ = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _, killed %rsi +# CHECK-NEXT: JMP_1 %bb.1.not_null +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + MOV64mr killed %rdi, 1, _, 0, _, killed %rsi + RETQ + + bb.2.is_null: + RETQ + +... +--- +name: inc_store_plus_offset +# CHECK-LABEL: inc_store_plus_offset +# CHECK: bb.0.entry: +# CHECK: _ = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 16, _, killed %rsi +# CHECK-NEXT: JMP_1 %bb.1.not_null +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + MOV64mr killed %rdi, 1, _, 16, _, killed %rsi + RETQ + + bb.2.is_null: + RETQ + +... +--- +name: inc_store_with_dep +# CHECK-LABEL: inc_store_with_dep +# CHECK: bb.0.entry: +# CHECK: %esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags +# CHECK-NEXT: _ = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 16, _, killed %esi +# CHECK-NEXT: JMP_1 %bb.1.not_null +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags + MOV32mr killed %rdi, 1, _, 16, _, killed %esi + RETQ + + bb.2.is_null: + RETQ + +... +--- +name: inc_store_with_dep_in_null +# CHECK-LABEL: inc_store_with_dep_in_null +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %esi = ADD32rr %esi, %esi, implicit-def dead %eflags + MOV32mr killed %rdi, 1, _, 0, _, %esi + %eax = MOV32rr killed %esi + RETQ %eax + + bb.2.is_null: + liveins: %rsi + + %eax = MOV32rr killed %esi + RETQ %eax + +... +--- +name: inc_store_with_volatile +# CHECK-LABEL: inc_store_with_volatile +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + MOV32mr killed %rdi, 1, _, 0, _, killed %esi :: (volatile store 4 into %ir.ptr) + RETQ + + bb.2.is_null: + RETQ + +... +--- +name: inc_store_with_two_dep +# CHECK-LABEL: inc_store_with_two_dep +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags + %esi = ADD32ri killed %esi, 15, implicit-def dead %eflags + MOV32mr killed %rdi, 1, _, 16, _, killed %esi + RETQ + + bb.2.is_null: + RETQ + +... +--- +name: inc_store_with_redefined_base +# CHECK-LABEL: inc_store_with_redefined_base +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %rdi = ADD64rr killed %rdi, killed %rdi, implicit-def dead %eflags + MOV32mr killed %rdi, 1, _, 16, _, killed %esi + RETQ + + bb.2.is_null: + RETQ + +... +--- +name: inc_store_with_reused_base +# CHECK-LABEL: inc_store_with_reused_base +# CHECK: bb.0.entry: +# CHECK: _ = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 16, _, killed %esi +# CHECK-NEXT: JMP_1 %bb.1.not_null +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %rax = MOV64rr %rdi + MOV32mr killed %rdi, 1, _, 16, _, killed %esi + RETQ %eax + + bb.2.is_null: + %rax = XOR64rr undef %rax, undef %rax, implicit-def dead %eflags + RETQ %eax + +... +--- +name: inc_store_across_call +# CHECK-LABEL: inc_store_across_call +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rbx, %rbx, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } +calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', + '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', + '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', + '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rbx + + frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp + CFI_INSTRUCTION def_cfa_offset 16 + CFI_INSTRUCTION offset %rbx, -16 + %rbx = MOV64rr killed %rdi + TEST64rr %rbx, %rbx, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rbx + + CALL64pcrel32 @f, csr_64, implicit %rsp, implicit-def %rsp + MOV32mi %rbx, 1, _, 0, _, 20 + %rax = MOV64rr killed %rbx + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax + + bb.2.is_null: + %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags + %rbx = POP64r implicit-def %rsp, implicit %rsp + RETQ %eax + +... +--- +name: inc_store_with_dep_in_dep +# CHECK-LABEL: inc_store_with_dep_in_dep +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %eax = MOV32rr %esi + %esi = ADD32ri killed %esi, 15, implicit-def dead %eflags + MOV32mr killed %rdi, 1, _, 0, _, killed %esi + RETQ %eax + + bb.2.is_null: + %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags + RETQ %eax + +... +--- +name: inc_store_with_load_over_store +# CHECK-LABEL: inc_store_with_load_over_store +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + MOV32mi killed %rsi, 1, _, 0, _, 2 + %eax = MOV32rm killed %rdi, 1, _, 0, _ + RETQ %eax + + bb.2.is_null: + %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags + RETQ %eax + +... +--- +name: inc_store_with_store_over_load +# CHECK-LABEL: inc_store_with_store_over_load +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %eax = MOV32rm killed %rsi, 1, _, 0, _ + MOV32mi killed %rdi, 1, _, 0, _, 2 + RETQ %eax + + bb.2.is_null: + %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags + RETQ %eax + +... +--- +name: inc_store_with_store_over_store +# CHECK-LABEL: inc_store_with_store_over_store +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + MOV32mi killed %rsi, 1, _, 0, _, 3 + MOV32mi killed %rdi, 1, _, 0, _, 2 + RETQ + + bb.2.is_null: + RETQ + +... +--- +name: inc_store_with_load_and_store +# CHECK-LABEL: inc_store_with_load_and_store +# CHECK: bb.0.entry: +# CHECK: _ = FAULTING_OP 2, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _, killed %esi, implicit-def dead %eflags +# CHECK-NEXT: JMP_1 %bb.1.not_null +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + %esi = ADD32rr %esi, %esi, implicit-def dead %eflags + ADD32mr killed %rdi, 1, _, 0, _, killed %esi, implicit-def dead %eflags + RETQ + + bb.2.is_null: + RETQ + +... +--- +name: inc_store_and_load_no_alias +# CHECK-LABEL: inc_store_and_load_no_alias +# CHECK: bb.0.entry: +# CHECK: %eax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr) +# CHECK-NEXT: JMP_1 %bb.1.not_null +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + MOV32mi killed %rsi, 1, _, 0, _, 3 :: (store 4 into %ir.ptr2) + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr) + RETQ %eax + + bb.2.is_null: + %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags + RETQ %eax + +... +--- +name: inc_store_and_load_alias +# CHECK-LABEL: inc_store_and_load_alias +# CHECK: bb.0.entry: +# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags +# CHECK-NEXT: JE_1 %bb.2.is_null, implicit killed %eflags +# CHECK: bb.1.not_null + +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '%rdi' } + - { reg: '%rsi' } +body: | + bb.0.entry: + successors: %bb.2.is_null, %bb.1.not_null + liveins: %rdi, %rsi + + TEST64rr %rdi, %rdi, implicit-def %eflags + JE_1 %bb.2.is_null, implicit killed %eflags + + bb.1.not_null: + liveins: %rdi, %rsi + + MOV32mi killed %rsi, 1, _, 0, _, 3 :: (store 4 into %ir.ptr2) + %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr) + RETQ %eax + + bb.2.is_null: + %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags + RETQ %eax + +... |