1 files changed, 26 insertions, 14 deletions
diff --git a/test/CodeGen/X86/vec_set-B.ll b/test/CodeGen/X86/vec_set-B.ll
index 0580a3376656..ecd9b57cfd0c 100644
--- a/test/CodeGen/X86/vec_set-B.ll
+++ b/test/CodeGen/X86/vec_set-B.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
 
 ; These should both generate something like this:
 ;_test3:
@@ -9,26 +10,37 @@
 ;	ret
 
 define <2 x i64> @test3(i64 %arg) nounwind {
-; CHECK-LABEL: test3:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    movl $1234567, %eax # imm = 0x12D687
-; CHECK-NEXT:    andl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movd %eax, %xmm0
-; CHECK-NEXT:    retl
+; X86-LABEL: test3:
+; X86:       # BB#0:
+; X86-NEXT:    movl $1234567, %eax # imm = 0x12D687
+; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movd %eax, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: test3:
+; X64:       # BB#0:
+; X64-NEXT:    andl $1234567, %edi # imm = 0x12D687
+; X64-NEXT:    movq %rdi, %xmm0
+; X64-NEXT:    retq
   %A = and i64 %arg, 1234567
   %B = insertelement <2 x i64> zeroinitializer, i64 %A, i32 0
   ret <2 x i64> %B
 }
 
 define <2 x i64> @test2(i64 %arg) nounwind {
-; CHECK-LABEL: test2:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    movl $1234567, %eax # imm = 0x12D687
-; CHECK-NEXT:    andl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movd %eax, %xmm0
-; CHECK-NEXT:    retl
+; X86-LABEL: test2:
+; X86:       # BB#0:
+; X86-NEXT:    movl $1234567, %eax # imm = 0x12D687
+; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movd %eax, %xmm0
+; X86-NEXT:    retl
+;
+; X64-LABEL: test2:
+; X64:       # BB#0:
+; X64-NEXT:    andl $1234567, %edi # imm = 0x12D687
+; X64-NEXT:    movq %rdi, %xmm0
+; X64-NEXT:    retq
   %A = and i64 %arg, 1234567
   %B = insertelement <2 x i64> undef, i64 %A, i32 0
   ret <2 x i64> %B
 }
-